drivers/fpga/zynqpl.c

   1 /*
   2  * (C) Copyright 2012-2013, Xilinx, Michal Simek
   3  *
   4  * (C) Copyright 2012
   5  * Joe Hershberger <joe.hershberger@ni.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <zynqpl.h>
  13 #include <linux/sizes.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 #define DEVCFG_CTRL_PCFG_PROG_B         0x40000000
  18 #define DEVCFG_ISR_FATAL_ERROR_MASK     0x00740040
  19 #define DEVCFG_ISR_ERROR_FLAGS_MASK     0x00340840
  20 #define DEVCFG_ISR_RX_FIFO_OV           0x00040000
  21 #define DEVCFG_ISR_DMA_DONE             0x00002000
  22 #define DEVCFG_ISR_PCFG_DONE            0x00000004
  23 #define DEVCFG_STATUS_DMA_CMD_Q_F       0x80000000
  24 #define DEVCFG_STATUS_DMA_CMD_Q_E       0x40000000
  25 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
  26 #define DEVCFG_STATUS_PCFG_INIT         0x00000010
  27 #define DEVCFG_MCTRL_PCAP_LPBK          0x00000010
  28 #define DEVCFG_MCTRL_RFIFO_FLUSH        0x00000002
  29 #define DEVCFG_MCTRL_WFIFO_FLUSH        0x00000001
  30
  31 #ifndef CONFIG_SYS_FPGA_WAIT
  32 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100  /* 10 ms */
  33 #endif
  34
  35 #ifndef CONFIG_SYS_FPGA_PROG_TIME
  36 #define CONFIG_SYS_FPGA_PROG_TIME       (CONFIG_SYS_HZ * 4) /* 4 s */
  37 #endif
  38
  39 static int zynq_info(xilinx_desc *desc)
  40 {
  41         return FPGA_SUCCESS;
  42 }
  43
  44 #define DUMMY_WORD      0xffffffff
  45
  46 /* Xilinx binary format header */
  47 static const u32 bin_format[] = {
  48         DUMMY_WORD, /* Dummy words */
  49         DUMMY_WORD,
  50         DUMMY_WORD,
  51         DUMMY_WORD,
  52         DUMMY_WORD,
  53         DUMMY_WORD,
  54         DUMMY_WORD,
  55         DUMMY_WORD,
  56         0x000000bb, /* Sync word */
  57         0x11220044, /* Sync word */
  58         DUMMY_WORD,
  59         DUMMY_WORD,
  60         0xaa995566, /* Sync word */
  61 };
  62
  63 #define SWAP_NO         1
  64 #define SWAP_DONE       2
  65
  66 /*
  67  * Load the whole word from unaligned buffer
  68  * Keep in your mind that it is byte loading on little-endian system
  69  */
  70 static u32 load_word(const void *buf, u32 swap)
  71 {
  72         u32 word = 0;
  73         u8 *bitc = (u8 *)buf;
  74         int p;
  75
  76         if (swap == SWAP_NO) {
  77                 for (p = 0; p < 4; p++) {
  78                         word <<= 8;
  79                         word |= bitc[p];
  80                 }
  81         } else {
  82                 for (p = 3; p >= 0; p--) {
  83                         word <<= 8;
  84                         word |= bitc[p];
  85                 }
  86         }
  87
  88         return word;
  89 }
  90
  91 static u32 check_header(const void *buf)
  92 {
  93         u32 i, pattern;
  94         int swap = SWAP_NO;
  95         u32 *test = (u32 *)buf;
  96
  97         debug("%s: Let's check bitstream header\n", __func__);
  98
  99         /* Checking that passing bin is not a bitstream */
 100         for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
 101                 pattern = load_word(&test[i], swap);
 102
 103                 /*
 104                  * Bitstreams in binary format are swapped
 105                  * compare to regular bistream.
 106                  * Do not swap dummy word but if swap is done assume
 107                  * that parsing buffer is binary format
 108                  */
 109                 if ((__swab32(pattern) != DUMMY_WORD) &&
 110                     (__swab32(pattern) == bin_format[i])) {
 111                         pattern = __swab32(pattern);
 112                         swap = SWAP_DONE;
 113                         debug("%s: data swapped - let's swap\n", __func__);
 114                 }
 115
 116                 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
 117                       (u32)&test[i], pattern, bin_format[i]);
 118                 if (pattern != bin_format[i]) {
 119                         debug("%s: Bitstream is not recognized\n", __func__);
 120                         return 0;
 121                 }
 122         }
 123         debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
 124               (u32)buf, swap == SWAP_NO ? "without" : "with");
 125
 126         return swap;
 127 }
 128
 129 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
 130 {
 131         u32 word, p = 0; /* possition */
 132
 133         /* Because buf doesn't need to be aligned let's read it by chars */
 134         for (p = 0; p < bsize; p++) {
 135                 word = load_word(&buf[p], SWAP_NO);
 136                 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
 137
 138                 /* Find the first bitstream dummy word */
 139                 if (word == DUMMY_WORD) {
 140                         debug("%s: Found dummy word at position %x/%x\n",
 141                               __func__, p, (u32)&buf[p]);
 142                         *swap = check_header(&buf[p]);
 143                         if (*swap) {
 144                                 /* FIXME add full bitstream checking here */
 145                                 return &buf[p];
 146                         }
 147                 }
 148                 /* Loop can be huge - support CTRL + C */
 149                 if (ctrlc())
 150                         return 0;
 151         }
 152         return 0;
 153 }
 154
 155 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
 156 {
 157         unsigned long ts; /* Timestamp */
 158         u32 partialbit = 0;
 159         u32 i, control, isr_status, status, swap, diff;
 160         u32 *buf_start;
 161
 162         /* Detect if we are going working with partial or full bitstream */
 163         if (bsize != desc->size) {
 164                 printf("%s: Working with partial bitstream\n", __func__);
 165                 partialbit = 1;
 166         }
 167
 168         buf_start = check_data((u8 *)buf, bsize, &swap);
 169         if (!buf_start)
 170                 return FPGA_FAIL;
 171
 172         /* Check if data is postpone from start */
 173         diff = (u32)buf_start - (u32)buf;
 174         if (diff) {
 175                 printf("%s: Bitstream is not validated yet (diff %x)\n",
 176                        __func__, diff);
 177                 return FPGA_FAIL;
 178         }
 179
 180         if ((u32)buf < SZ_1M) {
 181                 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
 182                        __func__, (u32)buf);
 183                 return FPGA_FAIL;
 184         }
 185
 186         if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
 187                 u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
 188
 189                 /*
 190                  * This might be dangerous but permits to flash if
 191                  * ARCH_DMA_MINALIGN is greater than header size
 192                  */
 193                 if (new_buf > buf_start) {
 194                         debug("%s: Aligned buffer is after buffer start\n",
 195                               __func__);
 196                         new_buf -= ARCH_DMA_MINALIGN;
 197                 }
 198
 199                 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
 200                        (u32)buf_start, (u32)new_buf, swap);
 201
 202                 for (i = 0; i < (bsize/4); i++)
 203                         new_buf[i] = load_word(&buf_start[i], swap);
 204
 205                 swap = SWAP_DONE;
 206                 buf = new_buf;
 207         } else if (swap != SWAP_DONE) {
 208                 /* For bitstream which are aligned */
 209                 u32 *new_buf = (u32 *)buf;
 210
 211                 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
 212                        swap);
 213
 214                 for (i = 0; i < (bsize/4); i++)
 215                         new_buf[i] = load_word(&buf_start[i], swap);
 216
 217                 swap = SWAP_DONE;
 218         }
 219
 220         /* Clear loopback bit */
 221         clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
 222
 223         if (!partialbit) {
 224                 zynq_slcr_devcfg_disable();
 225
 226                 /* Setting PCFG_PROG_B signal to high */
 227                 control = readl(&devcfg_base->ctrl);
 228                 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 229                 /* Setting PCFG_PROG_B signal to low */
 230                 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 231
 232                 /* Polling the PCAP_INIT status for Reset */
 233                 ts = get_timer(0);
 234                 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
 235                         if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 236                                 printf("%s: Timeout wait for INIT to clear\n",
 237                                        __func__);
 238                                 return FPGA_FAIL;
 239                         }
 240                 }
 241
 242                 /* Setting PCFG_PROG_B signal to high */
 243                 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 244
 245                 /* Polling the PCAP_INIT status for Set */
 246                 ts = get_timer(0);
 247                 while (!(readl(&devcfg_base->status) &
 248                         DEVCFG_STATUS_PCFG_INIT)) {
 249                         if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 250                                 printf("%s: Timeout wait for INIT to set\n",
 251                                        __func__);
 252                                 return FPGA_FAIL;
 253                         }
 254                 }
 255         }
 256
 257         isr_status = readl(&devcfg_base->int_sts);
 258
 259         /* Clear it all, so if Boot ROM comes back, it can proceed */
 260         writel(0xFFFFFFFF, &devcfg_base->int_sts);
 261
 262         if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
 263                 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
 264
 265                 /* If RX FIFO overflow, need to flush RX FIFO first */
 266                 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
 267                         writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
 268                         writel(0xFFFFFFFF, &devcfg_base->int_sts);
 269                 }
 270                 return FPGA_FAIL;
 271         }
 272
 273         status = readl(&devcfg_base->status);
 274
 275         debug("%s: Status = 0x%08X\n", __func__, status);
 276
 277         if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
 278                 debug("%s: Error: device busy\n", __func__);
 279                 return FPGA_FAIL;
 280         }
 281
 282         debug("%s: Device ready\n", __func__);
 283
 284         if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
 285                 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
 286                         /* Error state, transfer cannot occur */
 287                         debug("%s: ISR indicates error\n", __func__);
 288                         return FPGA_FAIL;
 289                 } else {
 290                         /* Clear out the status */
 291                         writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
 292                 }
 293         }
 294
 295         if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
 296                 /* Clear the count of completed DMA transfers */
 297                 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
 298         }
 299
 300         debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
 301         debug("%s: Size = %zu\n", __func__, bsize);
 302
 303         /* flush(clean & invalidate) d-cache range buf */
 304         flush_dcache_range((u32)buf, (u32)buf +
 305                            roundup(bsize, ARCH_DMA_MINALIGN));
 306
 307         /* Set up the transfer */
 308         writel((u32)buf | 1, &devcfg_base->dma_src_addr);
 309         writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
 310         writel(bsize >> 2, &devcfg_base->dma_src_len);
 311         writel(0, &devcfg_base->dma_dst_len);
 312
 313         isr_status = readl(&devcfg_base->int_sts);
 314
 315         /* Polling the PCAP_INIT status for Set */
 316         ts = get_timer(0);
 317         while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
 318                 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
 319                         debug("%s: Error: isr = 0x%08X\n", __func__,
 320                               isr_status);
 321                         debug("%s: Write count = 0x%08X\n", __func__,
 322                               readl(&devcfg_base->write_count));
 323                         debug("%s: Read count = 0x%08X\n", __func__,
 324                               readl(&devcfg_base->read_count));
 325
 326                         return FPGA_FAIL;
 327                 }
 328                 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
 329                         printf("%s: Timeout wait for DMA to complete\n",
 330                                __func__);
 331                         return FPGA_FAIL;
 332                 }
 333                 isr_status = readl(&devcfg_base->int_sts);
 334         }
 335
 336         debug("%s: DMA transfer is done\n", __func__);
 337
 338         /* Check FPGA configuration completion */
 339         ts = get_timer(0);
 340         while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
 341                 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 342                         printf("%s: Timeout wait for FPGA to config\n",
 343                                __func__);
 344                         return FPGA_FAIL;
 345                 }
 346                 isr_status = readl(&devcfg_base->int_sts);
 347         }
 348
 349         debug("%s: FPGA config done\n", __func__);
 350
 351         /* Clear out the DMA status */
 352         writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
 353
 354         if (!partialbit)
 355                 zynq_slcr_devcfg_enable();
 356
 357         return FPGA_SUCCESS;
 358 }
 359
 360 static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 361 {
 362         return FPGA_FAIL;
 363 }
 364
 365 struct xilinx_fpga_op zynq_op = {
 366         .load = zynq_load,
 367         .dump = zynq_dump,
 368         .info = zynq_info,
 369 };