]>
git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/gpio/at91_gpio.c
2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
6 * Copyright (C) 2005 HP Labs
8 * SPDX-License-Identifier: GPL-2.0+
14 * As the code is right now, it expects all PIO ports A,B,C,...
15 * to be evenly spaced in the memory map:
16 * ATMEL_BASE_PIOA + port * sizeof at91pio_t
17 * This might not necessaryly be true in future Atmel SoCs.
18 * This code should be fixed to use a pointer array to the ports.
24 #include <asm/sizes.h>
25 #include <asm/arch/hardware.h>
26 #include <asm/arch/at91_pio.h>
28 int at91_set_pio_pullup(unsigned port
, unsigned pin
, int use_pullup
)
30 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
33 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
36 writel(1 << pin
, &pio
->port
[port
].puer
);
38 writel(1 << pin
, &pio
->port
[port
].pudr
);
39 writel(mask
, &pio
->port
[port
].per
);
45 * mux the pin to the "GPIO" peripheral role.
47 int at91_set_pio_periph(unsigned port
, unsigned pin
, int use_pullup
)
49 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
52 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
54 writel(mask
, &pio
->port
[port
].idr
);
55 at91_set_pio_pullup(port
, pin
, use_pullup
);
56 writel(mask
, &pio
->port
[port
].per
);
62 * mux the pin to the "A" internal peripheral role.
64 int at91_set_a_periph(unsigned port
, unsigned pin
, int use_pullup
)
66 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
69 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
71 writel(mask
, &pio
->port
[port
].idr
);
72 at91_set_pio_pullup(port
, pin
, use_pullup
);
73 #if defined(CPU_HAS_PIO3)
74 writel(readl(&pio
->port
[port
].abcdsr1
) & ~mask
,
75 &pio
->port
[port
].abcdsr1
);
76 writel(readl(&pio
->port
[port
].abcdsr2
) & ~mask
,
77 &pio
->port
[port
].abcdsr2
);
79 writel(mask
, &pio
->port
[port
].asr
);
81 writel(mask
, &pio
->port
[port
].pdr
);
87 * mux the pin to the "B" internal peripheral role.
89 int at91_set_b_periph(unsigned port
, unsigned pin
, int use_pullup
)
91 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
94 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
96 writel(mask
, &pio
->port
[port
].idr
);
97 at91_set_pio_pullup(port
, pin
, use_pullup
);
98 #if defined(CPU_HAS_PIO3)
99 writel(readl(&pio
->port
[port
].abcdsr1
) | mask
,
100 &pio
->port
[port
].abcdsr1
);
101 writel(readl(&pio
->port
[port
].abcdsr2
) & ~mask
,
102 &pio
->port
[port
].abcdsr2
);
104 writel(mask
, &pio
->port
[port
].bsr
);
106 writel(mask
, &pio
->port
[port
].pdr
);
111 #if defined(CPU_HAS_PIO3)
113 * mux the pin to the "C" internal peripheral role.
115 int at91_set_c_periph(unsigned port
, unsigned pin
, int use_pullup
)
117 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
120 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
122 writel(mask
, &pio
->port
[port
].idr
);
123 at91_set_pio_pullup(port
, pin
, use_pullup
);
124 writel(readl(&pio
->port
[port
].abcdsr1
) & ~mask
,
125 &pio
->port
[port
].abcdsr1
);
126 writel(readl(&pio
->port
[port
].abcdsr2
) | mask
,
127 &pio
->port
[port
].abcdsr2
);
128 writel(mask
, &pio
->port
[port
].pdr
);
134 * mux the pin to the "D" internal peripheral role.
136 int at91_set_d_periph(unsigned port
, unsigned pin
, int use_pullup
)
138 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
141 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
143 writel(mask
, &pio
->port
[port
].idr
);
144 at91_set_pio_pullup(port
, pin
, use_pullup
);
145 writel(readl(&pio
->port
[port
].abcdsr1
) | mask
,
146 &pio
->port
[port
].abcdsr1
);
147 writel(readl(&pio
->port
[port
].abcdsr2
) | mask
,
148 &pio
->port
[port
].abcdsr2
);
149 writel(mask
, &pio
->port
[port
].pdr
);
156 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
157 * configure it for an input.
159 int at91_set_pio_input(unsigned port
, u32 pin
, int use_pullup
)
161 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
164 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
166 writel(mask
, &pio
->port
[port
].idr
);
167 at91_set_pio_pullup(port
, pin
, use_pullup
);
168 writel(mask
, &pio
->port
[port
].odr
);
169 writel(mask
, &pio
->port
[port
].per
);
175 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
176 * and configure it for an output.
178 int at91_set_pio_output(unsigned port
, u32 pin
, int value
)
180 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
183 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
185 writel(mask
, &pio
->port
[port
].idr
);
186 writel(mask
, &pio
->port
[port
].pudr
);
188 writel(mask
, &pio
->port
[port
].sodr
);
190 writel(mask
, &pio
->port
[port
].codr
);
191 writel(mask
, &pio
->port
[port
].oer
);
192 writel(mask
, &pio
->port
[port
].per
);
198 * enable/disable the glitch filter. mostly used with IRQ handling.
200 int at91_set_pio_deglitch(unsigned port
, unsigned pin
, int is_on
)
202 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
205 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
208 #if defined(CPU_HAS_PIO3)
209 writel(mask
, &pio
->port
[port
].ifscdr
);
211 writel(mask
, &pio
->port
[port
].ifer
);
213 writel(mask
, &pio
->port
[port
].ifdr
);
219 #if defined(CPU_HAS_PIO3)
221 * enable/disable the debounce filter.
223 int at91_set_pio_debounce(unsigned port
, unsigned pin
, int is_on
, int div
)
225 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
228 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
231 writel(mask
, &pio
->port
[port
].ifscer
);
232 writel(div
& PIO_SCDR_DIV
, &pio
->port
[port
].scdr
);
233 writel(mask
, &pio
->port
[port
].ifer
);
235 writel(mask
, &pio
->port
[port
].ifdr
);
242 * enable/disable the pull-down.
243 * If pull-up already enabled while calling the function, we disable it.
245 int at91_set_pio_pulldown(unsigned port
, unsigned pin
, int is_on
)
247 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
250 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
252 writel(mask
, &pio
->port
[port
].pudr
);
254 writel(mask
, &pio
->port
[port
].ppder
);
256 writel(mask
, &pio
->port
[port
].ppddr
);
262 * disable Schmitt trigger
264 int at91_set_pio_disable_schmitt_trig(unsigned port
, unsigned pin
)
266 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
269 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
271 writel(readl(&pio
->port
[port
].schmitt
) | mask
,
272 &pio
->port
[port
].schmitt
);
279 * enable/disable the multi-driver. This is only valid for output and
280 * allows the output pin to run as an open collector output.
282 int at91_set_pio_multi_drive(unsigned port
, unsigned pin
, int is_on
)
284 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
287 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
290 writel(mask
, &pio
->port
[port
].mder
);
292 writel(mask
, &pio
->port
[port
].mddr
);
298 * assuming the pin is muxed as a gpio output, set its value.
300 int at91_set_pio_value(unsigned port
, unsigned pin
, int value
)
302 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
305 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
308 writel(mask
, &pio
->port
[port
].sodr
);
310 writel(mask
, &pio
->port
[port
].codr
);
316 * read the pin's value (works even if it's not muxed as a gpio).
318 int at91_get_pio_value(unsigned port
, unsigned pin
)
321 at91_pio_t
*pio
= (at91_pio_t
*) ATMEL_BASE_PIOA
;
324 if ((port
< ATMEL_PIO_PORTS
) && (pin
< 32)) {
326 pdsr
= readl(&pio
->port
[port
].pdsr
) & mask
;