2 * Atmel PIO4 device driver
4 * Copyright (C) 2015 Atmel Corporation
5 * Wenyou.Yang <wenyou.yang@atmel.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/hardware.h>
16 #include <mach/gpio.h>
17 #include <mach/atmel_pio4.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 static struct atmel_pio4_port
*atmel_pio4_port_base(u32 port
)
23 struct atmel_pio4_port
*base
= NULL
;
27 base
= (struct atmel_pio4_port
*)ATMEL_BASE_PIOA
;
30 base
= (struct atmel_pio4_port
*)ATMEL_BASE_PIOB
;
33 base
= (struct atmel_pio4_port
*)ATMEL_BASE_PIOC
;
36 base
= (struct atmel_pio4_port
*)ATMEL_BASE_PIOD
;
39 printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
47 static int atmel_pio4_config_io_func(u32 port
, u32 pin
,
48 u32 func
, u32 use_pullup
)
50 struct atmel_pio4_port
*port_base
;
53 if (pin
>= ATMEL_PIO_NPINS_PER_BANK
)
56 port_base
= atmel_pio4_port_base(port
);
62 reg
|= use_pullup
? ATMEL_PIO_PUEN_MASK
: 0;
64 writel(mask
, &port_base
->mskr
);
65 writel(reg
, &port_base
->cfgr
);
70 int atmel_pio4_set_gpio(u32 port
, u32 pin
, u32 use_pullup
)
72 return atmel_pio4_config_io_func(port
, pin
,
73 ATMEL_PIO_CFGR_FUNC_GPIO
,
77 int atmel_pio4_set_a_periph(u32 port
, u32 pin
, u32 use_pullup
)
79 return atmel_pio4_config_io_func(port
, pin
,
80 ATMEL_PIO_CFGR_FUNC_PERIPH_A
,
84 int atmel_pio4_set_b_periph(u32 port
, u32 pin
, u32 use_pullup
)
86 return atmel_pio4_config_io_func(port
, pin
,
87 ATMEL_PIO_CFGR_FUNC_PERIPH_B
,
91 int atmel_pio4_set_c_periph(u32 port
, u32 pin
, u32 use_pullup
)
93 return atmel_pio4_config_io_func(port
, pin
,
94 ATMEL_PIO_CFGR_FUNC_PERIPH_C
,
98 int atmel_pio4_set_d_periph(u32 port
, u32 pin
, u32 use_pullup
)
100 return atmel_pio4_config_io_func(port
, pin
,
101 ATMEL_PIO_CFGR_FUNC_PERIPH_D
,
105 int atmel_pio4_set_e_periph(u32 port
, u32 pin
, u32 use_pullup
)
107 return atmel_pio4_config_io_func(port
, pin
,
108 ATMEL_PIO_CFGR_FUNC_PERIPH_E
,
112 int atmel_pio4_set_f_periph(u32 port
, u32 pin
, u32 use_pullup
)
114 return atmel_pio4_config_io_func(port
, pin
,
115 ATMEL_PIO_CFGR_FUNC_PERIPH_F
,
119 int atmel_pio4_set_g_periph(u32 port
, u32 pin
, u32 use_pullup
)
121 return atmel_pio4_config_io_func(port
, pin
,
122 ATMEL_PIO_CFGR_FUNC_PERIPH_G
,
126 int atmel_pio4_set_pio_output(u32 port
, u32 pin
, u32 value
)
128 struct atmel_pio4_port
*port_base
;
131 if (pin
>= ATMEL_PIO_NPINS_PER_BANK
)
134 port_base
= atmel_pio4_port_base(port
);
139 reg
= ATMEL_PIO_CFGR_FUNC_GPIO
| ATMEL_PIO_DIR_MASK
;
141 writel(mask
, &port_base
->mskr
);
142 writel(reg
, &port_base
->cfgr
);
145 writel(mask
, &port_base
->sodr
);
147 writel(mask
, &port_base
->codr
);
152 int atmel_pio4_get_pio_input(u32 port
, u32 pin
)
154 struct atmel_pio4_port
*port_base
;
157 if (pin
>= ATMEL_PIO_NPINS_PER_BANK
)
160 port_base
= atmel_pio4_port_base(port
);
165 reg
= ATMEL_PIO_CFGR_FUNC_GPIO
;
167 writel(mask
, &port_base
->mskr
);
168 writel(reg
, &port_base
->cfgr
);
170 return (readl(&port_base
->pdsr
) & mask
) ? 1 : 0;
173 #ifdef CONFIG_DM_GPIO
175 struct atmel_pioctrl_data
{
179 struct atmel_pio4_platdata
{
180 struct atmel_pio4_port
*reg_base
;
183 static struct atmel_pio4_port
*atmel_pio4_bank_base(struct udevice
*dev
,
186 struct atmel_pio4_platdata
*plat
= dev_get_platdata(dev
);
187 struct atmel_pio4_port
*port_base
=
188 (struct atmel_pio4_port
*)((u32
)plat
->reg_base
+
189 ATMEL_PIO_BANK_OFFSET
* bank
);
194 static int atmel_pio4_direction_input(struct udevice
*dev
, unsigned offset
)
196 u32 bank
= ATMEL_PIO_BANK(offset
);
197 u32 line
= ATMEL_PIO_LINE(offset
);
198 struct atmel_pio4_port
*port_base
= atmel_pio4_bank_base(dev
, bank
);
199 u32 mask
= BIT(line
);
201 writel(mask
, &port_base
->mskr
);
203 clrbits_le32(&port_base
->cfgr
,
204 ATMEL_PIO_CFGR_FUNC_MASK
| ATMEL_PIO_DIR_MASK
);
209 static int atmel_pio4_direction_output(struct udevice
*dev
,
210 unsigned offset
, int value
)
212 u32 bank
= ATMEL_PIO_BANK(offset
);
213 u32 line
= ATMEL_PIO_LINE(offset
);
214 struct atmel_pio4_port
*port_base
= atmel_pio4_bank_base(dev
, bank
);
215 u32 mask
= BIT(line
);
217 writel(mask
, &port_base
->mskr
);
219 clrsetbits_le32(&port_base
->cfgr
,
220 ATMEL_PIO_CFGR_FUNC_MASK
, ATMEL_PIO_DIR_MASK
);
223 writel(mask
, &port_base
->sodr
);
225 writel(mask
, &port_base
->codr
);
230 static int atmel_pio4_get_value(struct udevice
*dev
, unsigned offset
)
232 u32 bank
= ATMEL_PIO_BANK(offset
);
233 u32 line
= ATMEL_PIO_LINE(offset
);
234 struct atmel_pio4_port
*port_base
= atmel_pio4_bank_base(dev
, bank
);
235 u32 mask
= BIT(line
);
237 return (readl(&port_base
->pdsr
) & mask
) ? 1 : 0;
240 static int atmel_pio4_set_value(struct udevice
*dev
,
241 unsigned offset
, int value
)
243 u32 bank
= ATMEL_PIO_BANK(offset
);
244 u32 line
= ATMEL_PIO_LINE(offset
);
245 struct atmel_pio4_port
*port_base
= atmel_pio4_bank_base(dev
, bank
);
246 u32 mask
= BIT(line
);
249 writel(mask
, &port_base
->sodr
);
251 writel(mask
, &port_base
->codr
);
256 static int atmel_pio4_get_function(struct udevice
*dev
, unsigned offset
)
258 u32 bank
= ATMEL_PIO_BANK(offset
);
259 u32 line
= ATMEL_PIO_LINE(offset
);
260 struct atmel_pio4_port
*port_base
= atmel_pio4_bank_base(dev
, bank
);
261 u32 mask
= BIT(line
);
263 writel(mask
, &port_base
->mskr
);
265 return (readl(&port_base
->cfgr
) &
266 ATMEL_PIO_DIR_MASK
) ? GPIOF_OUTPUT
: GPIOF_INPUT
;
269 static const struct dm_gpio_ops atmel_pio4_ops
= {
270 .direction_input
= atmel_pio4_direction_input
,
271 .direction_output
= atmel_pio4_direction_output
,
272 .get_value
= atmel_pio4_get_value
,
273 .set_value
= atmel_pio4_set_value
,
274 .get_function
= atmel_pio4_get_function
,
277 static int atmel_pio4_bind(struct udevice
*dev
)
279 return dm_scan_fdt_node(dev
, gd
->fdt_blob
, dev
->of_offset
, false);
282 static int atmel_pio4_probe(struct udevice
*dev
)
284 struct atmel_pio4_platdata
*plat
= dev_get_platdata(dev
);
285 struct gpio_dev_priv
*uc_priv
= dev_get_uclass_priv(dev
);
286 struct atmel_pioctrl_data
*pioctrl_data
;
287 struct udevice
*dev_clk
;
289 fdt_addr_t addr_base
;
294 ret
= clk_get_by_index(dev
, 0, &clk
);
298 periph
= fdtdec_get_uint(gd
->fdt_blob
, clk
.dev
->of_offset
, "reg", -1);
302 dev_clk
= dev_get_parent(clk
.dev
);
303 ret
= clk_request(dev_clk
, &clk
);
308 ret
= clk_enable(&clk
);
314 addr_base
= dev_get_addr(dev
);
315 if (addr_base
== FDT_ADDR_T_NONE
)
318 plat
->reg_base
= (struct atmel_pio4_port
*)addr_base
;
320 pioctrl_data
= (struct atmel_pioctrl_data
*)dev_get_driver_data(dev
);
321 nbanks
= pioctrl_data
->nbanks
;
323 uc_priv
->bank_name
= fdt_get_name(gd
->fdt_blob
, dev
->of_offset
, NULL
);
324 uc_priv
->gpio_count
= nbanks
* ATMEL_PIO_NPINS_PER_BANK
;
330 * The number of banks can be different from a SoC to another one.
331 * We can have up to 16 banks.
333 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data
= {
337 static const struct udevice_id atmel_pio4_ids
[] = {
339 .compatible
= "atmel,sama5d2-gpio",
340 .data
= (ulong
)&atmel_sama5d2_pioctrl_data
,
345 U_BOOT_DRIVER(gpio_atmel_pio4
) = {
346 .name
= "gpio_atmel_pio4",
348 .ops
= &atmel_pio4_ops
,
349 .probe
= atmel_pio4_probe
,
350 .bind
= atmel_pio4_bind
,
351 .of_match
= atmel_pio4_ids
,
352 .platdata_auto_alloc_size
= sizeof(struct atmel_pio4_platdata
),