1 // SPDX-License-Identifier: GPL-2.0+
3 * GPIO driver for TI DaVinci DA8xx SOCs.
5 * (C) Copyright 2011 Guralp Systems Ltd.
6 * Laurence Withers <lwithers@guralp.com>
14 #include <dt-bindings/gpio/gpio.h>
16 #include "da8xx_gpio.h"
18 #ifndef CONFIG_DM_GPIO
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/davinci_misc.h>
22 static struct gpio_registry
{
24 char name
[GPIO_NAME_SIZE
];
25 } gpio_registry
[MAX_NUM_GPIOS
];
27 #if defined(CONFIG_SOC_DA8XX)
28 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
30 #if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
31 static const struct pinmux_config gpio_pinmux
[] = {
32 { pinmux(13), 8, 6 }, /* GP0[0] */
48 { pinmux(15), 8, 6 }, /* GP1[0] */
64 { pinmux(17), 8, 6 }, /* GP2[0] */
80 { pinmux(10), 8, 1 }, /* GP3[0] */
96 { pinmux(12), 8, 4 }, /* GP4[0] */
100 { pinmux(13), 8, 0 },
101 { pinmux(13), 8, 1 },
102 { pinmux(13), 8, 2 },
103 { pinmux(13), 8, 3 },
104 { pinmux(13), 8, 4 },
105 { pinmux(13), 8, 5 },
106 { pinmux(11), 8, 7 },
107 { pinmux(12), 8, 0 },
108 { pinmux(12), 8, 1 },
109 { pinmux(12), 8, 2 },
110 { pinmux(12), 8, 3 },
112 { pinmux(7), 8, 3 }, /* GP5[0] */
128 { pinmux(5), 8, 1 }, /* GP6[0] */
144 { pinmux(1), 8, 0 }, /* GP7[0] */
161 #else /* CONFIG_SOC_DA8XX && CONFIG_SOC_DA850 */
162 static const struct pinmux_config gpio_pinmux
[] = {
163 { pinmux(1), 8, 7 }, /* GP0[0] */
179 { pinmux(4), 8, 7 }, /* GP1[0] */
195 { pinmux(6), 8, 7 }, /* GP2[0] */
211 { pinmux(8), 8, 7 }, /* GP3[0] */
227 { pinmux(10), 8, 7 }, /* GP4[0] */
228 { pinmux(10), 8, 6 },
229 { pinmux(10), 8, 5 },
230 { pinmux(10), 8, 4 },
231 { pinmux(10), 8, 3 },
232 { pinmux(10), 8, 2 },
233 { pinmux(10), 8, 1 },
234 { pinmux(10), 8, 0 },
243 { pinmux(12), 8, 7 }, /* GP5[0] */
244 { pinmux(12), 8, 6 },
245 { pinmux(12), 8, 5 },
246 { pinmux(12), 8, 4 },
247 { pinmux(12), 8, 3 },
248 { pinmux(12), 8, 2 },
249 { pinmux(12), 8, 1 },
250 { pinmux(12), 8, 0 },
251 { pinmux(11), 8, 7 },
252 { pinmux(11), 8, 6 },
253 { pinmux(11), 8, 5 },
254 { pinmux(11), 8, 4 },
255 { pinmux(11), 8, 3 },
256 { pinmux(11), 8, 2 },
257 { pinmux(11), 8, 1 },
258 { pinmux(11), 8, 0 },
259 { pinmux(19), 8, 6 }, /* GP6[0] */
260 { pinmux(19), 8, 5 },
261 { pinmux(19), 8, 4 },
262 { pinmux(19), 8, 3 },
263 { pinmux(19), 8, 2 },
264 { pinmux(16), 8, 1 },
265 { pinmux(14), 8, 1 },
266 { pinmux(14), 8, 0 },
267 { pinmux(13), 8, 7 },
268 { pinmux(13), 8, 6 },
269 { pinmux(13), 8, 5 },
270 { pinmux(13), 8, 4 },
271 { pinmux(13), 8, 3 },
272 { pinmux(13), 8, 2 },
273 { pinmux(13), 8, 1 },
274 { pinmux(13), 8, 0 },
275 { pinmux(18), 8, 1 }, /* GP7[0] */
276 { pinmux(18), 8, 0 },
277 { pinmux(17), 8, 7 },
278 { pinmux(17), 8, 6 },
279 { pinmux(17), 8, 5 },
280 { pinmux(17), 8, 4 },
281 { pinmux(17), 8, 3 },
282 { pinmux(17), 8, 2 },
283 { pinmux(17), 8, 1 },
284 { pinmux(17), 8, 0 },
285 { pinmux(16), 8, 7 },
286 { pinmux(16), 8, 6 },
287 { pinmux(16), 8, 5 },
288 { pinmux(16), 8, 4 },
289 { pinmux(16), 8, 3 },
290 { pinmux(16), 8, 2 },
291 { pinmux(19), 8, 0 }, /* GP8[0] */
299 { pinmux(19), 8, 1 },
300 { pinmux(19), 8, 0 },
301 { pinmux(18), 8, 7 },
302 { pinmux(18), 8, 6 },
303 { pinmux(18), 8, 5 },
304 { pinmux(18), 8, 4 },
305 { pinmux(18), 8, 3 },
306 { pinmux(18), 8, 2 },
308 #endif /* CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850 */
309 #else /* !CONFIG_SOC_DA8XX */
310 #define davinci_configure_pin_mux(a, b)
311 #endif /* CONFIG_SOC_DA8XX */
313 int gpio_request(unsigned int gpio
, const char *label
)
315 if (gpio
>= MAX_NUM_GPIOS
)
318 if (gpio_registry
[gpio
].is_registered
)
321 gpio_registry
[gpio
].is_registered
= 1;
322 strncpy(gpio_registry
[gpio
].name
, label
, GPIO_NAME_SIZE
);
323 gpio_registry
[gpio
].name
[GPIO_NAME_SIZE
- 1] = 0;
325 davinci_configure_pin_mux(&gpio_pinmux
[gpio
], 1);
330 int gpio_free(unsigned int gpio
)
332 if (gpio
>= MAX_NUM_GPIOS
)
335 if (!gpio_registry
[gpio
].is_registered
)
338 gpio_registry
[gpio
].is_registered
= 0;
339 gpio_registry
[gpio
].name
[0] = '\0';
340 /* Do not configure as input or change pin mux here */
345 static int _gpio_direction_output(struct davinci_gpio
*bank
, unsigned int gpio
, int value
)
347 clrbits_le32(&bank
->dir
, 1U << GPIO_BIT(gpio
));
348 gpio_set_value(gpio
, value
);
352 static int _gpio_direction_input(struct davinci_gpio
*bank
, unsigned int gpio
)
354 setbits_le32(&bank
->dir
, 1U << GPIO_BIT(gpio
));
358 static int _gpio_get_value(struct davinci_gpio
*bank
, unsigned int gpio
)
361 ip
= in_le32(&bank
->in_data
) & (1U << GPIO_BIT(gpio
));
365 static int _gpio_set_value(struct davinci_gpio
*bank
, unsigned int gpio
, int value
)
368 bank
->set_data
= 1U << GPIO_BIT(gpio
);
370 bank
->clr_data
= 1U << GPIO_BIT(gpio
);
375 static int _gpio_get_dir(struct davinci_gpio
*bank
, unsigned int gpio
)
377 return in_le32(&bank
->dir
) & (1U << GPIO_BIT(gpio
));
380 #ifndef CONFIG_DM_GPIO
384 unsigned int gpio
, dir
, val
;
385 struct davinci_gpio
*bank
;
387 for (gpio
= 0; gpio
< MAX_NUM_GPIOS
; ++gpio
) {
388 bank
= GPIO_BANK(gpio
);
389 dir
= _gpio_get_dir(bank
, gpio
);
390 val
= gpio_get_value(gpio
);
392 printf("% 4d: %s: %d [%c] %s\n",
393 gpio
, dir
? " in" : "out", val
,
394 gpio_registry
[gpio
].is_registered
? 'x' : ' ',
395 gpio_registry
[gpio
].name
);
399 int gpio_direction_input(unsigned int gpio
)
401 struct davinci_gpio
*bank
;
403 bank
= GPIO_BANK(gpio
);
404 return _gpio_direction_input(bank
, gpio
);
407 int gpio_direction_output(unsigned int gpio
, int value
)
409 struct davinci_gpio
*bank
;
411 bank
= GPIO_BANK(gpio
);
412 return _gpio_direction_output(bank
, gpio
, value
);
415 int gpio_get_value(unsigned int gpio
)
417 struct davinci_gpio
*bank
;
419 bank
= GPIO_BANK(gpio
);
420 return _gpio_get_value(bank
, gpio
);
423 int gpio_set_value(unsigned int gpio
, int value
)
425 struct davinci_gpio
*bank
;
427 bank
= GPIO_BANK(gpio
);
428 return _gpio_set_value(bank
, gpio
, value
);
431 #else /* CONFIG_DM_GPIO */
433 static struct davinci_gpio
*davinci_get_gpio_bank(struct udevice
*dev
, unsigned int offset
)
435 struct davinci_gpio_bank
*bank
= dev_get_priv(dev
);
439 * The device tree is not broken into banks but the infrastructure is
440 * expecting it this way, so we'll first include the 0x10 offset, then
441 * calculate the bank manually based on the offset.
442 * Casting 'addr' as Unsigned long is needed to make the math work.
444 addr
= ((unsigned long)(struct davinci_gpio
*)bank
->base
) +
445 0x10 + (0x28 * (offset
>> 5));
446 return (struct davinci_gpio
*)addr
;
449 static int davinci_gpio_direction_input(struct udevice
*dev
, unsigned int offset
)
451 struct davinci_gpio
*base
= davinci_get_gpio_bank(dev
, offset
);
454 * Fetch the address based on GPIO, but only pass the masked low 32-bits
456 _gpio_direction_input(base
, (offset
& 0x1f));
460 static int davinci_gpio_direction_output(struct udevice
*dev
, unsigned int offset
,
463 struct davinci_gpio
*base
= davinci_get_gpio_bank(dev
, offset
);
465 _gpio_direction_output(base
, (offset
& 0x1f), value
);
469 static int davinci_gpio_get_value(struct udevice
*dev
, unsigned int offset
)
471 struct davinci_gpio
*base
= davinci_get_gpio_bank(dev
, offset
);
473 return _gpio_get_value(base
, (offset
& 0x1f));
476 static int davinci_gpio_set_value(struct udevice
*dev
, unsigned int offset
,
479 struct davinci_gpio
*base
= davinci_get_gpio_bank(dev
, offset
);
481 _gpio_set_value(base
, (offset
& 0x1f), value
);
486 static int davinci_gpio_get_function(struct udevice
*dev
, unsigned int offset
)
489 struct davinci_gpio
*base
= davinci_get_gpio_bank(dev
, offset
);
491 dir
= _gpio_get_dir(base
, offset
);
499 static int davinci_gpio_xlate(struct udevice
*dev
, struct gpio_desc
*desc
,
500 struct ofnode_phandle_args
*args
)
502 desc
->offset
= args
->args
[0];
504 if (args
->args
[1] & GPIO_ACTIVE_LOW
)
505 desc
->flags
= GPIOD_ACTIVE_LOW
;
511 static const struct dm_gpio_ops gpio_davinci_ops
= {
512 .direction_input
= davinci_gpio_direction_input
,
513 .direction_output
= davinci_gpio_direction_output
,
514 .get_value
= davinci_gpio_get_value
,
515 .set_value
= davinci_gpio_set_value
,
516 .get_function
= davinci_gpio_get_function
,
517 .xlate
= davinci_gpio_xlate
,
520 static int davinci_gpio_probe(struct udevice
*dev
)
522 struct davinci_gpio_bank
*bank
= dev_get_priv(dev
);
523 struct davinci_gpio_platdata
*plat
= dev_get_platdata(dev
);
524 struct gpio_dev_priv
*uc_priv
= dev_get_uclass_priv(dev
);
525 const void *fdt
= gd
->fdt_blob
;
526 int node
= dev_of_offset(dev
);
528 uc_priv
->bank_name
= plat
->port_name
;
529 uc_priv
->gpio_count
= fdtdec_get_int(fdt
, node
, "ti,ngpio", -1);
530 bank
->base
= (struct davinci_gpio
*)plat
->base
;
534 static const struct udevice_id davinci_gpio_ids
[] = {
535 { .compatible
= "ti,dm6441-gpio" },
536 { .compatible
= "ti,k2g-gpio" },
540 static int davinci_gpio_ofdata_to_platdata(struct udevice
*dev
)
542 struct davinci_gpio_platdata
*plat
= dev_get_platdata(dev
);
545 addr
= devfdt_get_addr(dev
);
546 if (addr
== FDT_ADDR_T_NONE
)
553 U_BOOT_DRIVER(gpio_davinci
) = {
554 .name
= "gpio_davinci",
556 .ops
= &gpio_davinci_ops
,
557 .ofdata_to_platdata
= of_match_ptr(davinci_gpio_ofdata_to_platdata
),
558 .of_match
= davinci_gpio_ids
,
559 .bind
= dm_scan_fdt_dev
,
560 .platdata_auto_alloc_size
= sizeof(struct davinci_gpio_platdata
),
561 .probe
= davinci_gpio_probe
,
562 .priv_auto_alloc_size
= sizeof(struct davinci_gpio_bank
),