drivers/gpio/gpio-rcar.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas R-Car GPIO Support
   4  *
   5  *  Copyright (C) 2014 Renesas Electronics Corporation
   6  *  Copyright (C) 2013 Magnus Damm
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/gpio/driver.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/ioport.h>
  15 #include <linux/irq.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pinctrl/consumer.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/slab.h>
  24
  25 struct gpio_rcar_bank_info {
  26         u32 iointsel;
  27         u32 inoutsel;
  28         u32 outdt;
  29         u32 posneg;
  30         u32 edglevel;
  31         u32 bothedge;
  32         u32 intmsk;
  33 };
  34
  35 struct gpio_rcar_priv {
  36         void __iomem *base;
  37         spinlock_t lock;
  38         struct device *dev;
  39         struct gpio_chip gpio_chip;
  40         struct irq_chip irq_chip;
  41         unsigned int irq_parent;
  42         atomic_t wakeup_path;
  43         bool has_outdtsel;
  44         bool has_both_edge_trigger;
  45         struct gpio_rcar_bank_info bank_info;
  46 };
  47
  48 #define IOINTSEL 0x00   /* General IO/Interrupt Switching Register */
  49 #define INOUTSEL 0x04   /* General Input/Output Switching Register */
  50 #define OUTDT 0x08      /* General Output Register */
  51 #define INDT 0x0c       /* General Input Register */
  52 #define INTDT 0x10      /* Interrupt Display Register */
  53 #define INTCLR 0x14     /* Interrupt Clear Register */
  54 #define INTMSK 0x18     /* Interrupt Mask Register */
  55 #define MSKCLR 0x1c     /* Interrupt Mask Clear Register */
  56 #define POSNEG 0x20     /* Positive/Negative Logic Select Register */
  57 #define EDGLEVEL 0x24   /* Edge/level Select Register */
  58 #define FILONOFF 0x28   /* Chattering Prevention On/Off Register */
  59 #define OUTDTSEL 0x40   /* Output Data Select Register */
  60 #define BOTHEDGE 0x4c   /* One Edge/Both Edge Select Register */
  61
  62 #define RCAR_MAX_GPIO_PER_BANK          32
  63
  64 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  65 {
  66         return ioread32(p->base + offs);
  67 }
  68
  69 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  70                                    u32 value)
  71 {
  72         iowrite32(value, p->base + offs);
  73 }
  74
  75 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  76                                  int bit, bool value)
  77 {
  78         u32 tmp = gpio_rcar_read(p, offs);
  79
  80         if (value)
  81                 tmp |= BIT(bit);
  82         else
  83                 tmp &= ~BIT(bit);
  84
  85         gpio_rcar_write(p, offs, tmp);
  86 }
  87
  88 static void gpio_rcar_irq_disable(struct irq_data *d)
  89 {
  90         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  91         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
  92
  93         gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
  94 }
  95
  96 static void gpio_rcar_irq_enable(struct irq_data *d)
  97 {
  98         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  99         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 100
 101         gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
 102 }
 103
 104 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 105                                                   unsigned int hwirq,
 106                                                   bool active_high_rising_edge,
 107                                                   bool level_trigger,
 108                                                   bool both)
 109 {
 110         unsigned long flags;
 111
 112         /* follow steps in the GPIO documentation for
 113          * "Setting Edge-Sensitive Interrupt Input Mode" and
 114          * "Setting Level-Sensitive Interrupt Input Mode"
 115          */
 116
 117         spin_lock_irqsave(&p->lock, flags);
 118
 119         /* Configure postive or negative logic in POSNEG */
 120         gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
 121
 122         /* Configure edge or level trigger in EDGLEVEL */
 123         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 124
 125         /* Select one edge or both edges in BOTHEDGE */
 126         if (p->has_both_edge_trigger)
 127                 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
 128
 129         /* Select "Interrupt Input Mode" in IOINTSEL */
 130         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 131
 132         /* Write INTCLR in case of edge trigger */
 133         if (!level_trigger)
 134                 gpio_rcar_write(p, INTCLR, BIT(hwirq));
 135
 136         spin_unlock_irqrestore(&p->lock, flags);
 137 }
 138
 139 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 140 {
 141         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 142         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 143         unsigned int hwirq = irqd_to_hwirq(d);
 144
 145         dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
 146
 147         switch (type & IRQ_TYPE_SENSE_MASK) {
 148         case IRQ_TYPE_LEVEL_HIGH:
 149                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
 150                                                       false);
 151                 break;
 152         case IRQ_TYPE_LEVEL_LOW:
 153                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
 154                                                       false);
 155                 break;
 156         case IRQ_TYPE_EDGE_RISING:
 157                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 158                                                       false);
 159                 break;
 160         case IRQ_TYPE_EDGE_FALLING:
 161                 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
 162                                                       false);
 163                 break;
 164         case IRQ_TYPE_EDGE_BOTH:
 165                 if (!p->has_both_edge_trigger)
 166                         return -EINVAL;
 167                 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
 168                                                       true);
 169                 break;
 170         default:
 171                 return -EINVAL;
 172         }
 173         return 0;
 174 }
 175
 176 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
 177 {
 178         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 179         struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 180         int error;
 181
 182         if (p->irq_parent) {
 183                 error = irq_set_irq_wake(p->irq_parent, on);
 184                 if (error) {
 185                         dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
 186                                 p->irq_parent);
 187                         p->irq_parent = 0;
 188                 }
 189         }
 190
 191         if (on)
 192                 atomic_inc(&p->wakeup_path);
 193         else
 194                 atomic_dec(&p->wakeup_path);
 195
 196         return 0;
 197 }
 198
 199 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
 200 {
 201         struct gpio_rcar_priv *p = dev_id;
 202         u32 pending;
 203         unsigned int offset, irqs_handled = 0;
 204
 205         while ((pending = gpio_rcar_read(p, INTDT) &
 206                           gpio_rcar_read(p, INTMSK))) {
 207                 offset = __ffs(pending);
 208                 gpio_rcar_write(p, INTCLR, BIT(offset));
 209                 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
 210                                                     offset));
 211                 irqs_handled++;
 212         }
 213
 214         return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 215 }
 216
 217 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 218                                                        unsigned int gpio,
 219                                                        bool output)
 220 {
 221         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 222         unsigned long flags;
 223
 224         /* follow steps in the GPIO documentation for
 225          * "Setting General Output Mode" and
 226          * "Setting General Input Mode"
 227          */
 228
 229         spin_lock_irqsave(&p->lock, flags);
 230
 231         /* Configure postive logic in POSNEG */
 232         gpio_rcar_modify_bit(p, POSNEG, gpio, false);
 233
 234         /* Select "General Input/Output Mode" in IOINTSEL */
 235         gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
 236
 237         /* Select Input Mode or Output Mode in INOUTSEL */
 238         gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
 239
 240         /* Select General Output Register to output data in OUTDTSEL */
 241         if (p->has_outdtsel && output)
 242                 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
 243
 244         spin_unlock_irqrestore(&p->lock, flags);
 245 }
 246
 247 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
 248 {
 249         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 250         int error;
 251
 252         error = pm_runtime_get_sync(p->dev);
 253         if (error < 0)
 254                 return error;
 255
 256         error = pinctrl_gpio_request(chip->base + offset);
 257         if (error)
 258                 pm_runtime_put(p->dev);
 259
 260         return error;
 261 }
 262
 263 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
 264 {
 265         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 266
 267         pinctrl_gpio_free(chip->base + offset);
 268
 269         /*
 270          * Set the GPIO as an input to ensure that the next GPIO request won't
 271          * drive the GPIO pin as an output.
 272          */
 273         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 274
 275         pm_runtime_put(p->dev);
 276 }
 277
 278 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
 279 {
 280         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 281
 282         return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
 283 }
 284
 285 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
 286 {
 287         gpio_rcar_config_general_input_output_mode(chip, offset, false);
 288         return 0;
 289 }
 290
 291 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
 292 {
 293         u32 bit = BIT(offset);
 294
 295         /* testing on r8a7790 shows that INDT does not show correct pin state
 296          * when configured as output, so use OUTDT in case of output pins */
 297         if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
 298                 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
 299         else
 300                 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
 301 }
 302
 303 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
 304 {
 305         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 306         unsigned long flags;
 307
 308         spin_lock_irqsave(&p->lock, flags);
 309         gpio_rcar_modify_bit(p, OUTDT, offset, value);
 310         spin_unlock_irqrestore(&p->lock, flags);
 311 }
 312
 313 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
 314                                    unsigned long *bits)
 315 {
 316         struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 317         unsigned long flags;
 318         u32 val, bankmask;
 319
 320         bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
 321         if (chip->valid_mask)
 322                 bankmask &= chip->valid_mask[0];
 323
 324         if (!bankmask)
 325                 return;
 326
 327         spin_lock_irqsave(&p->lock, flags);
 328         val = gpio_rcar_read(p, OUTDT);
 329         val &= ~bankmask;
 330         val |= (bankmask & bits[0]);
 331         gpio_rcar_write(p, OUTDT, val);
 332         spin_unlock_irqrestore(&p->lock, flags);
 333 }
 334
 335 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
 336                                       int value)
 337 {
 338         /* write GPIO value to output before selecting output mode of pin */
 339         gpio_rcar_set(chip, offset, value);
 340         gpio_rcar_config_general_input_output_mode(chip, offset, true);
 341         return 0;
 342 }
 343
 344 struct gpio_rcar_info {
 345         bool has_outdtsel;
 346         bool has_both_edge_trigger;
 347 };
 348
 349 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
 350         .has_outdtsel = false,
 351         .has_both_edge_trigger = false,
 352 };
 353
 354 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
 355         .has_outdtsel = true,
 356         .has_both_edge_trigger = true,
 357 };
 358
 359 static const struct of_device_id gpio_rcar_of_table[] = {
 360         {
 361                 .compatible = "renesas,gpio-r8a7743",
 362                 /* RZ/G1 GPIO is identical to R-Car Gen2. */
 363                 .data = &gpio_rcar_info_gen2,
 364         }, {
 365                 .compatible = "renesas,gpio-r8a7790",
 366                 .data = &gpio_rcar_info_gen2,
 367         }, {
 368                 .compatible = "renesas,gpio-r8a7791",
 369                 .data = &gpio_rcar_info_gen2,
 370         }, {
 371                 .compatible = "renesas,gpio-r8a7792",
 372                 .data = &gpio_rcar_info_gen2,
 373         }, {
 374                 .compatible = "renesas,gpio-r8a7793",
 375                 .data = &gpio_rcar_info_gen2,
 376         }, {
 377                 .compatible = "renesas,gpio-r8a7794",
 378                 .data = &gpio_rcar_info_gen2,
 379         }, {
 380                 .compatible = "renesas,gpio-r8a7795",
 381                 /* Gen3 GPIO is identical to Gen2. */
 382                 .data = &gpio_rcar_info_gen2,
 383         }, {
 384                 .compatible = "renesas,gpio-r8a7796",
 385                 /* Gen3 GPIO is identical to Gen2. */
 386                 .data = &gpio_rcar_info_gen2,
 387         }, {
 388                 .compatible = "renesas,rcar-gen1-gpio",
 389                 .data = &gpio_rcar_info_gen1,
 390         }, {
 391                 .compatible = "renesas,rcar-gen2-gpio",
 392                 .data = &gpio_rcar_info_gen2,
 393         }, {
 394                 .compatible = "renesas,rcar-gen3-gpio",
 395                 /* Gen3 GPIO is identical to Gen2. */
 396                 .data = &gpio_rcar_info_gen2,
 397         }, {
 398                 .compatible = "renesas,gpio-rcar",
 399                 .data = &gpio_rcar_info_gen1,
 400         }, {
 401                 /* Terminator */
 402         },
 403 };
 404
 405 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
 406
 407 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
 408 {
 409         struct device_node *np = p->dev->of_node;
 410         const struct gpio_rcar_info *info;
 411         struct of_phandle_args args;
 412         int ret;
 413
 414         info = of_device_get_match_data(p->dev);
 415         p->has_outdtsel = info->has_outdtsel;
 416         p->has_both_edge_trigger = info->has_both_edge_trigger;
 417
 418         ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
 419         *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
 420
 421         if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
 422                 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
 423                          *npins, RCAR_MAX_GPIO_PER_BANK);
 424                 *npins = RCAR_MAX_GPIO_PER_BANK;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int gpio_rcar_probe(struct platform_device *pdev)
 431 {
 432         struct gpio_rcar_priv *p;
 433         struct resource *io, *irq;
 434         struct gpio_chip *gpio_chip;
 435         struct irq_chip *irq_chip;
 436         struct device *dev = &pdev->dev;
 437         const char *name = dev_name(dev);
 438         unsigned int npins;
 439         int ret;
 440
 441         p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
 442         if (!p)
 443                 return -ENOMEM;
 444
 445         p->dev = dev;
 446         spin_lock_init(&p->lock);
 447
 448         /* Get device configuration from DT node */
 449         ret = gpio_rcar_parse_dt(p, &npins);
 450         if (ret < 0)
 451                 return ret;
 452
 453         platform_set_drvdata(pdev, p);
 454
 455         pm_runtime_enable(dev);
 456
 457         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 458         if (!irq) {
 459                 dev_err(dev, "missing IRQ\n");
 460                 ret = -EINVAL;
 461                 goto err0;
 462         }
 463
 464         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 465         p->base = devm_ioremap_resource(dev, io);
 466         if (IS_ERR(p->base)) {
 467                 ret = PTR_ERR(p->base);
 468                 goto err0;
 469         }
 470
 471         gpio_chip = &p->gpio_chip;
 472         gpio_chip->request = gpio_rcar_request;
 473         gpio_chip->free = gpio_rcar_free;
 474         gpio_chip->get_direction = gpio_rcar_get_direction;
 475         gpio_chip->direction_input = gpio_rcar_direction_input;
 476         gpio_chip->get = gpio_rcar_get;
 477         gpio_chip->direction_output = gpio_rcar_direction_output;
 478         gpio_chip->set = gpio_rcar_set;
 479         gpio_chip->set_multiple = gpio_rcar_set_multiple;
 480         gpio_chip->label = name;
 481         gpio_chip->parent = dev;
 482         gpio_chip->owner = THIS_MODULE;
 483         gpio_chip->base = -1;
 484         gpio_chip->ngpio = npins;
 485
 486         irq_chip = &p->irq_chip;
 487         irq_chip->name = name;
 488         irq_chip->parent_device = dev;
 489         irq_chip->irq_mask = gpio_rcar_irq_disable;
 490         irq_chip->irq_unmask = gpio_rcar_irq_enable;
 491         irq_chip->irq_set_type = gpio_rcar_irq_set_type;
 492         irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
 493         irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
 494
 495         ret = gpiochip_add_data(gpio_chip, p);
 496         if (ret) {
 497                 dev_err(dev, "failed to add GPIO controller\n");
 498                 goto err0;
 499         }
 500
 501         ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
 502                                    IRQ_TYPE_NONE);
 503         if (ret) {
 504                 dev_err(dev, "cannot add irqchip\n");
 505                 goto err1;
 506         }
 507
 508         p->irq_parent = irq->start;
 509         if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
 510                              IRQF_SHARED, name, p)) {
 511                 dev_err(dev, "failed to request IRQ\n");
 512                 ret = -ENOENT;
 513                 goto err1;
 514         }
 515
 516         dev_info(dev, "driving %d GPIOs\n", npins);
 517
 518         return 0;
 519
 520 err1:
 521         gpiochip_remove(gpio_chip);
 522 err0:
 523         pm_runtime_disable(dev);
 524         return ret;
 525 }
 526
 527 static int gpio_rcar_remove(struct platform_device *pdev)
 528 {
 529         struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
 530
 531         gpiochip_remove(&p->gpio_chip);
 532
 533         pm_runtime_disable(&pdev->dev);
 534         return 0;
 535 }
 536
 537 #ifdef CONFIG_PM_SLEEP
 538 static int gpio_rcar_suspend(struct device *dev)
 539 {
 540         struct gpio_rcar_priv *p = dev_get_drvdata(dev);
 541
 542         p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
 543         p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
 544         p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
 545         p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
 546         p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
 547         p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
 548         if (p->has_both_edge_trigger)
 549                 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
 550
 551         if (atomic_read(&p->wakeup_path))
 552                 device_set_wakeup_path(dev);
 553
 554         return 0;
 555 }
 556
 557 static int gpio_rcar_resume(struct device *dev)
 558 {
 559         struct gpio_rcar_priv *p = dev_get_drvdata(dev);
 560         unsigned int offset;
 561         u32 mask;
 562
 563         for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
 564                 if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
 565                         continue;
 566
 567                 mask = BIT(offset);
 568                 /* I/O pin */
 569                 if (!(p->bank_info.iointsel & mask)) {
 570                         if (p->bank_info.inoutsel & mask)
 571                                 gpio_rcar_direction_output(
 572                                         &p->gpio_chip, offset,
 573                                         !!(p->bank_info.outdt & mask));
 574                         else
 575                                 gpio_rcar_direction_input(&p->gpio_chip,
 576                                                           offset);
 577                 } else {
 578                         /* Interrupt pin */
 579                         gpio_rcar_config_interrupt_input_mode(
 580                                 p,
 581                                 offset,
 582                                 !(p->bank_info.posneg & mask),
 583                                 !(p->bank_info.edglevel & mask),
 584                                 !!(p->bank_info.bothedge & mask));
 585
 586                         if (p->bank_info.intmsk & mask)
 587                                 gpio_rcar_write(p, MSKCLR, mask);
 588                 }
 589         }
 590
 591         return 0;
 592 }
 593 #endif /* CONFIG_PM_SLEEP*/
 594
 595 static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
 596
 597 static struct platform_driver gpio_rcar_device_driver = {
 598         .probe          = gpio_rcar_probe,
 599         .remove         = gpio_rcar_remove,
 600         .driver         = {
 601                 .name   = "gpio_rcar",
 602                 .pm     = &gpio_rcar_pm_ops,
 603                 .of_match_table = of_match_ptr(gpio_rcar_of_table),
 604         }
 605 };
 606
 607 module_platform_driver(gpio_rcar_device_driver);
 608
 609 MODULE_AUTHOR("Magnus Damm");
 610 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
 611 MODULE_LICENSE("GPL v2");