drivers/gpio/gpio-uniphier.c

   1 /*
   2  * Copyright (C) 2016-2017 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <linux/bitops.h>
  11 #include <linux/io.h>
  12 #include <linux/sizes.h>
  13 #include <linux/errno.h>
  14 #include <asm/global_data.h>
  15 #include <asm/gpio.h>
  16
  17 #define UNIPHIER_GPIO_LINES_PER_BANK    8
  18
  19 #define UNIPHIER_GPIO_PORT_DATA         0x0     /* data */
  20 #define UNIPHIER_GPIO_PORT_DIR          0x4     /* direction (1:in, 0:out) */
  21 #define UNIPHIER_GPIO_IRQ_EN            0x90    /* irq enable */
  22
  23 struct uniphier_gpio_priv {
  24         void __iomem *regs;
  25 };
  26
  27 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
  28 {
  29         unsigned int reg;
  30
  31         reg = (bank + 1) * 8;
  32
  33         /*
  34          * Unfortunately, the GPIO port registers are not contiguous because
  35          * offset 0x90-0x9f is used for IRQ.  Add 0x10 when crossing the region.
  36          */
  37         if (reg >= UNIPHIER_GPIO_IRQ_EN)
  38                 reg += 0x10;
  39
  40         return reg;
  41 }
  42
  43 static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
  44                                             unsigned int *bank, u32 *mask)
  45 {
  46         *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
  47         *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
  48 }
  49
  50 static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
  51                                      unsigned int reg, u32 mask, u32 val)
  52 {
  53         u32 tmp;
  54
  55         tmp = readl(priv->regs + reg);
  56         tmp &= ~mask;
  57         tmp |= mask & val;
  58         writel(tmp, priv->regs + reg);
  59 }
  60
  61 static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
  62                                      unsigned int reg, u32 mask, u32 val)
  63 {
  64         struct uniphier_gpio_priv *priv = dev_get_priv(dev);
  65
  66         if (!mask)
  67                 return;
  68
  69         uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
  70                                  mask, val);
  71 }
  72
  73 static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
  74                                        unsigned int reg, int val)
  75 {
  76         unsigned int bank;
  77         u32 mask;
  78
  79         uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
  80
  81         uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
  82 }
  83
  84 static int uniphier_gpio_offset_read(struct udevice *dev,
  85                                      unsigned int offset, unsigned int reg)
  86 {
  87         struct uniphier_gpio_priv *priv = dev_get_priv(dev);
  88         unsigned int bank, reg_offset;
  89         u32 mask;
  90
  91         uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
  92         reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
  93
  94         return !!(readl(priv->regs + reg_offset) & mask);
  95 }
  96
  97 static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
  98 {
  99         return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
 100                                                 GPIOF_INPUT : GPIOF_OUTPUT;
 101 }
 102
 103 static int uniphier_gpio_direction_input(struct udevice *dev,
 104                                          unsigned int offset)
 105 {
 106         uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
 107
 108         return 0;
 109 }
 110
 111 static int uniphier_gpio_direction_output(struct udevice *dev,
 112                                           unsigned int offset, int value)
 113 {
 114         uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
 115         uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);
 116
 117         return 0;
 118 }
 119
 120 static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
 121 {
 122         return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
 123 }
 124
 125 static int uniphier_gpio_set_value(struct udevice *dev,
 126                                    unsigned int offset, int value)
 127 {
 128         uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
 129
 130         return 0;
 131 }
 132
 133 static const struct dm_gpio_ops uniphier_gpio_ops = {
 134         .direction_input        = uniphier_gpio_direction_input,
 135         .direction_output       = uniphier_gpio_direction_output,
 136         .get_value              = uniphier_gpio_get_value,
 137         .set_value              = uniphier_gpio_set_value,
 138         .get_function           = uniphier_gpio_get_function,
 139 };
 140
 141 static int uniphier_gpio_probe(struct udevice *dev)
 142 {
 143         struct uniphier_gpio_priv *priv = dev_get_priv(dev);
 144         struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 145         fdt_addr_t addr;
 146
 147         addr = devfdt_get_addr(dev);
 148         if (addr == FDT_ADDR_T_NONE)
 149                 return -EINVAL;
 150
 151         priv->regs = devm_ioremap(dev, addr, SZ_512);
 152         if (!priv->regs)
 153                 return -ENOMEM;
 154
 155         uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 156                                               "ngpios", 0);
 157
 158         return 0;
 159 }
 160
 161 static const struct udevice_id uniphier_gpio_match[] = {
 162         { .compatible = "socionext,uniphier-gpio" },
 163         { /* sentinel */ }
 164 };
 165
 166 U_BOOT_DRIVER(uniphier_gpio) = {
 167         .name   = "uniphier-gpio",
 168         .id     = UCLASS_GPIO,
 169         .of_match = uniphier_gpio_match,
 170         .probe  = uniphier_gpio_probe,
 171         .priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
 172         .ops    = &uniphier_gpio_ops,
 173 };