2 * Copyright (c) 2012 The Chromium OS Authors.
3 * SPDX-License-Identifier: GPL-2.0+
7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8 * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9 * consisting of a standard header and a device-specific set of registers. PCI
10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11 * other things). Within the PCI configuration space, the GPIOBASE register
12 * tells us where in the device's I/O region we can find more registers to
13 * actually access the GPIOs.
15 * PCI bus/device/function 0:1f:0 => PCI config registers
16 * PCI config register "GPIOBASE"
17 * PCI I/O space + [GPIOBASE] => start of GPIO registers
18 * GPIO registers => gpio pin function, direction, value
21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22 * ICH versions have more, but the decoding the matrix that describes them is
23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24 * but they will ONLY work for certain unspecified chipsets because the offset
25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26 * reserved or subject to arcane restrictions.
39 DECLARE_GLOBAL_DATA_PTR
;
41 #define GPIO_PER_BANK 32
43 struct ich6_bank_priv
{
44 /* These are I/O addresses */
50 #define GPIO_USESEL_OFFSET(x) (x)
51 #define GPIO_IOSEL_OFFSET(x) (x + 4)
52 #define GPIO_LVL_OFFSET(x) (x + 8)
54 #define IOPAD_MODE_MASK 0x7
55 #define IOPAD_PULL_ASSIGN_SHIFT 7
56 #define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT)
57 #define IOPAD_PULL_STRENGTH_SHIFT 9
58 #define IOPAD_PULL_STRENGTH_MASK (0x3 << IOPAD_PULL_STRENGTH_SHIFT)
60 /* TODO: Move this to device tree, or platform data */
61 void ich_gpio_set_gpio_map(const struct pch_gpio_map
*map
)
63 gd
->arch
.gpio_map
= map
;
66 static int _ich6_gpio_set_value(uint16_t base
, unsigned offset
, int value
)
72 val
|= (1UL << offset
);
74 val
&= ~(1UL << offset
);
80 static int _ich6_gpio_set_function(uint16_t base
, unsigned offset
, int func
)
86 val
|= (1UL << offset
);
90 val
&= ~(1UL << offset
);
97 static int _ich6_gpio_set_direction(uint16_t base
, unsigned offset
, int dir
)
103 val
|= (1UL << offset
);
107 val
&= ~(1UL << offset
);
114 static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase
, s32 iobase
, int pin_node
)
123 * GPIO node is not mandatory, so we only do the
124 * pinmuxing if the node exist.
126 ret
= fdtdec_get_int_array(gd
->fdt_blob
, pin_node
, "gpio-offset",
129 /* Do we want to force the GPIO mode? */
130 prop
= fdt_getprop(gd
->fdt_blob
, pin_node
, "mode-gpio",
133 _ich6_gpio_set_function(GPIO_USESEL_OFFSET
139 fdtdec_get_int(gd
->fdt_blob
, pin_node
, "direction", -1);
141 _ich6_gpio_set_direction(GPIO_IOSEL_OFFSET
144 gpio_offset
[1], val
);
147 fdtdec_get_int(gd
->fdt_blob
, pin_node
, "output-value", -1);
149 _ich6_gpio_set_value(GPIO_LVL_OFFSET(gpiobase
)
151 gpio_offset
[1], val
);
154 /* if iobase is present, let's configure the pad */
159 * The offset for the same pin for the IOBASE and GPIOBASE are
160 * different, so instead of maintaining a lookup table,
161 * the device tree should provide directly the correct
162 * value for both mapping.
165 fdtdec_get_int(gd
->fdt_blob
, pin_node
, "pad-offset", -1);
166 if (pad_offset
== -1) {
167 debug("%s: Invalid register io offset %d\n",
168 __func__
, pad_offset
);
172 /* compute the absolute pad address */
173 iobase_addr
= iobase
+ pad_offset
;
176 * Do we need to set a specific function mode?
177 * If someone put also 'mode-gpio', this option will
178 * be just ignored by the controller
180 val
= fdtdec_get_int(gd
->fdt_blob
, pin_node
, "mode-func", -1);
182 clrsetbits_le32(iobase_addr
, IOPAD_MODE_MASK
, val
);
184 /* Configure the pull-up/down if needed */
185 val
= fdtdec_get_int(gd
->fdt_blob
, pin_node
, "pull-assign", -1);
187 clrsetbits_le32(iobase_addr
,
188 IOPAD_PULL_ASSIGN_MASK
,
189 val
<< IOPAD_PULL_ASSIGN_SHIFT
);
192 fdtdec_get_int(gd
->fdt_blob
, pin_node
, "pull-strength", -1);
194 clrsetbits_le32(iobase_addr
,
195 IOPAD_PULL_STRENGTH_MASK
,
196 val
<< IOPAD_PULL_STRENGTH_SHIFT
);
198 debug("%s: pad cfg [0x%x]: %08x\n", __func__
, pad_offset
,
205 int gpio_ich6_pinctrl_init(void)
214 ret
= uclass_first_device(UCLASS_PCH
, &pch
);
221 * Get the memory/io base address to configure every pins.
222 * IOBASE is used to configure the mode/pads
223 * GPIOBASE is used to configure the direction and default value
225 ret
= pch_get_gpio_base(pch
, &gpiobase
);
227 debug("%s: invalid GPIOBASE address (%08x)\n", __func__
,
232 /* This is not an error to not have a pinctrl node */
234 fdtdec_next_compatible(gd
->fdt_blob
, 0, COMPAT_INTEL_X86_PINCTRL
);
236 debug("%s: no pinctrl node\n", __func__
);
241 * Get the IOBASE, this is not mandatory as this is not
242 * supported by all the CPU
244 ret
= pch_get_io_base(pch
, &iobase
);
245 if (ret
&& ret
!= -ENOSYS
) {
246 debug("%s: invalid IOBASE address (%08x)\n", __func__
,
251 for (pin_node
= fdt_first_subnode(gd
->fdt_blob
, node
);
253 pin_node
= fdt_next_subnode(gd
->fdt_blob
, pin_node
)) {
254 /* Configure the pin */
255 ret
= _gpio_ich6_pinctrl_cfg_pin(gpiobase
, iobase
, pin_node
);
257 debug("%s: invalid configuration for the pin %d\n",
266 static int gpio_ich6_ofdata_to_platdata(struct udevice
*dev
)
268 struct ich6_bank_platdata
*plat
= dev_get_platdata(dev
);
273 ret
= pch_get_gpio_base(dev
->parent
, &gpiobase
);
277 offset
= fdtdec_get_int(gd
->fdt_blob
, dev
->of_offset
, "reg", -1);
279 debug("%s: Invalid register offset %d\n", __func__
, offset
);
282 plat
->base_addr
= gpiobase
+ offset
;
283 plat
->bank_name
= fdt_getprop(gd
->fdt_blob
, dev
->of_offset
,
289 static int ich6_gpio_probe(struct udevice
*dev
)
291 struct ich6_bank_platdata
*plat
= dev_get_platdata(dev
);
292 struct gpio_dev_priv
*uc_priv
= dev_get_uclass_priv(dev
);
293 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
295 if (gd
->arch
.gpio_map
) {
296 setup_pch_gpios(plat
->base_addr
, gd
->arch
.gpio_map
);
297 gd
->arch
.gpio_map
= NULL
;
300 uc_priv
->gpio_count
= GPIO_PER_BANK
;
301 uc_priv
->bank_name
= plat
->bank_name
;
302 bank
->use_sel
= plat
->base_addr
;
303 bank
->io_sel
= plat
->base_addr
+ 4;
304 bank
->lvl
= plat
->base_addr
+ 8;
309 static int ich6_gpio_request(struct udevice
*dev
, unsigned offset
,
312 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
316 * Make sure that the GPIO pin we want isn't already in use for some
317 * built-in hardware function. We have to check this for every
320 tmplong
= inl(bank
->use_sel
);
321 if (!(tmplong
& (1UL << offset
))) {
322 debug("%s: gpio %d is reserved for internal use\n", __func__
,
330 static int ich6_gpio_direction_input(struct udevice
*dev
, unsigned offset
)
332 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
334 return _ich6_gpio_set_direction(bank
->io_sel
, offset
, 0);
337 static int ich6_gpio_direction_output(struct udevice
*dev
, unsigned offset
,
341 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
343 ret
= _ich6_gpio_set_direction(bank
->io_sel
, offset
, 1);
347 return _ich6_gpio_set_value(bank
->lvl
, offset
, value
);
350 static int ich6_gpio_get_value(struct udevice
*dev
, unsigned offset
)
352 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
356 tmplong
= inl(bank
->lvl
);
357 r
= (tmplong
& (1UL << offset
)) ? 1 : 0;
361 static int ich6_gpio_set_value(struct udevice
*dev
, unsigned offset
,
364 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
365 return _ich6_gpio_set_value(bank
->lvl
, offset
, value
);
368 static int ich6_gpio_get_function(struct udevice
*dev
, unsigned offset
)
370 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
371 u32 mask
= 1UL << offset
;
373 if (!(inl(bank
->use_sel
) & mask
))
375 if (inl(bank
->io_sel
) & mask
)
381 static const struct dm_gpio_ops gpio_ich6_ops
= {
382 .request
= ich6_gpio_request
,
383 .direction_input
= ich6_gpio_direction_input
,
384 .direction_output
= ich6_gpio_direction_output
,
385 .get_value
= ich6_gpio_get_value
,
386 .set_value
= ich6_gpio_set_value
,
387 .get_function
= ich6_gpio_get_function
,
390 static const struct udevice_id intel_ich6_gpio_ids
[] = {
391 { .compatible
= "intel,ich6-gpio" },
395 U_BOOT_DRIVER(gpio_ich6
) = {
398 .of_match
= intel_ich6_gpio_ids
,
399 .ops
= &gpio_ich6_ops
,
400 .ofdata_to_platdata
= gpio_ich6_ofdata_to_platdata
,
401 .probe
= ich6_gpio_probe
,
402 .priv_auto_alloc_size
= sizeof(struct ich6_bank_priv
),
403 .platdata_auto_alloc_size
= sizeof(struct ich6_bank_platdata
),