2 * Copyright (c) 2012 The Chromium OS Authors.
3 * SPDX-License-Identifier: GPL-2.0+
7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8 * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9 * consisting of a standard header and a device-specific set of registers. PCI
10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11 * other things). Within the PCI configuration space, the GPIOBASE register
12 * tells us where in the device's I/O region we can find more registers to
13 * actually access the GPIOs.
15 * PCI bus/device/function 0:1f:0 => PCI config registers
16 * PCI config register "GPIOBASE"
17 * PCI I/O space + [GPIOBASE] => start of GPIO registers
18 * GPIO registers => gpio pin function, direction, value
21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22 * ICH versions have more, but the decoding the matrix that describes them is
23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24 * but they will ONLY work for certain unspecified chipsets because the offset
25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26 * reserved or subject to arcane restrictions.
40 DECLARE_GLOBAL_DATA_PTR
;
42 #define GPIO_PER_BANK 32
44 struct ich6_bank_priv
{
45 /* These are I/O addresses */
50 bool use_lvl_write_cache
;
53 #define GPIO_USESEL_OFFSET(x) (x)
54 #define GPIO_IOSEL_OFFSET(x) (x + 4)
55 #define GPIO_LVL_OFFSET(x) (x + 8)
57 static int _ich6_gpio_set_value(struct ich6_bank_priv
*bank
, unsigned offset
,
62 if (bank
->use_lvl_write_cache
)
63 val
= bank
->lvl_write_cache
;
68 val
|= (1UL << offset
);
70 val
&= ~(1UL << offset
);
72 if (bank
->use_lvl_write_cache
)
73 bank
->lvl_write_cache
= val
;
78 static int _ich6_gpio_set_direction(uint16_t base
, unsigned offset
, int dir
)
84 val
|= (1UL << offset
);
88 val
&= ~(1UL << offset
);
95 static int gpio_ich6_ofdata_to_platdata(struct udevice
*dev
)
97 struct ich6_bank_platdata
*plat
= dev_get_platdata(dev
);
102 ret
= pch_get_gpio_base(dev
->parent
, &gpiobase
);
106 offset
= fdtdec_get_int(gd
->fdt_blob
, dev_of_offset(dev
), "reg", -1);
108 debug("%s: Invalid register offset %d\n", __func__
, offset
);
111 plat
->offset
= offset
;
112 plat
->base_addr
= gpiobase
+ offset
;
113 plat
->bank_name
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
),
119 static int ich6_gpio_probe(struct udevice
*dev
)
121 struct ich6_bank_platdata
*plat
= dev_get_platdata(dev
);
122 struct gpio_dev_priv
*uc_priv
= dev_get_uclass_priv(dev
);
123 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
126 uc_priv
->gpio_count
= GPIO_PER_BANK
;
127 uc_priv
->bank_name
= plat
->bank_name
;
128 bank
->use_sel
= plat
->base_addr
;
129 bank
->io_sel
= plat
->base_addr
+ 4;
130 bank
->lvl
= plat
->base_addr
+ 8;
132 prop
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
),
133 "use-lvl-write-cache", NULL
);
135 bank
->use_lvl_write_cache
= true;
137 bank
->use_lvl_write_cache
= false;
138 bank
->lvl_write_cache
= 0;
143 static int ich6_gpio_request(struct udevice
*dev
, unsigned offset
,
146 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
150 * Make sure that the GPIO pin we want isn't already in use for some
151 * built-in hardware function. We have to check this for every
154 tmplong
= inl(bank
->use_sel
);
155 if (!(tmplong
& (1UL << offset
))) {
156 debug("%s: gpio %d is reserved for internal use\n", __func__
,
164 static int ich6_gpio_direction_input(struct udevice
*dev
, unsigned offset
)
166 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
168 return _ich6_gpio_set_direction(bank
->io_sel
, offset
, 0);
171 static int ich6_gpio_direction_output(struct udevice
*dev
, unsigned offset
,
175 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
177 ret
= _ich6_gpio_set_direction(bank
->io_sel
, offset
, 1);
181 return _ich6_gpio_set_value(bank
, offset
, value
);
184 static int ich6_gpio_get_value(struct udevice
*dev
, unsigned offset
)
186 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
190 tmplong
= inl(bank
->lvl
);
191 if (bank
->use_lvl_write_cache
)
192 tmplong
|= bank
->lvl_write_cache
;
193 r
= (tmplong
& (1UL << offset
)) ? 1 : 0;
197 static int ich6_gpio_set_value(struct udevice
*dev
, unsigned offset
,
200 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
201 return _ich6_gpio_set_value(bank
, offset
, value
);
204 static int ich6_gpio_get_function(struct udevice
*dev
, unsigned offset
)
206 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
207 u32 mask
= 1UL << offset
;
209 if (!(inl(bank
->use_sel
) & mask
))
211 if (inl(bank
->io_sel
) & mask
)
217 static const struct dm_gpio_ops gpio_ich6_ops
= {
218 .request
= ich6_gpio_request
,
219 .direction_input
= ich6_gpio_direction_input
,
220 .direction_output
= ich6_gpio_direction_output
,
221 .get_value
= ich6_gpio_get_value
,
222 .set_value
= ich6_gpio_set_value
,
223 .get_function
= ich6_gpio_get_function
,
226 static const struct udevice_id intel_ich6_gpio_ids
[] = {
227 { .compatible
= "intel,ich6-gpio" },
231 U_BOOT_DRIVER(gpio_ich6
) = {
234 .of_match
= intel_ich6_gpio_ids
,
235 .ops
= &gpio_ich6_ops
,
236 .ofdata_to_platdata
= gpio_ich6_ofdata_to_platdata
,
237 .probe
= ich6_gpio_probe
,
238 .priv_auto_alloc_size
= sizeof(struct ich6_bank_priv
),
239 .platdata_auto_alloc_size
= sizeof(struct ich6_bank_platdata
),