2 * Copyright (c) 2012 The Chromium OS Authors.
3 * SPDX-License-Identifier: GPL-2.0+
7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8 * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9 * consisting of a standard header and a device-specific set of registers. PCI
10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11 * other things). Within the PCI configuration space, the GPIOBASE register
12 * tells us where in the device's I/O region we can find more registers to
13 * actually access the GPIOs.
15 * PCI bus/device/function 0:1f:0 => PCI config registers
16 * PCI config register "GPIOBASE"
17 * PCI I/O space + [GPIOBASE] => start of GPIO registers
18 * GPIO registers => gpio pin function, direction, value
21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22 * ICH versions have more, but the decoding the matrix that describes them is
23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24 * but they will ONLY work for certain unspecified chipsets because the offset
25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26 * reserved or subject to arcane restrictions.
38 #define GPIO_PER_BANK 32
40 struct ich6_bank_priv
{
41 /* These are I/O addresses */
47 /* TODO: Move this to device tree, or platform data */
48 void ich_gpio_set_gpio_map(const struct pch_gpio_map
*map
)
50 gd
->arch
.gpio_map
= map
;
53 static int gpio_ich6_ofdata_to_platdata(struct udevice
*dev
)
55 struct ich6_bank_platdata
*plat
= dev_get_platdata(dev
);
56 pci_dev_t pci_dev
; /* handle for 0:1f:0 */
63 /* Where should it be? */
64 pci_dev
= PCI_BDF(0, 0x1f, 0);
66 /* Is the device present? */
67 tmpword
= pci_read_config16(pci_dev
, PCI_VENDOR_ID
);
68 if (tmpword
!= PCI_VENDOR_ID_INTEL
) {
69 debug("%s: wrong VendorID\n", __func__
);
73 tmpword
= pci_read_config16(pci_dev
, PCI_DEVICE_ID
);
74 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL
, tmpword
);
76 * We'd like to validate the Device ID too, but pretty much any
77 * value is either a) correct with slight differences, or b)
78 * correct but undocumented. We'll have to check a bunch of other
82 /* I/O should already be enabled (it's a RO bit). */
83 tmpword
= pci_read_config16(pci_dev
, PCI_COMMAND
);
84 if (!(tmpword
& PCI_COMMAND_IO
)) {
85 debug("%s: device IO not enabled\n", __func__
);
89 /* Header Type must be normal (bits 6-0 only; see spec.) */
90 tmpbyte
= pci_read_config8(pci_dev
, PCI_HEADER_TYPE
);
91 if ((tmpbyte
& 0x7f) != PCI_HEADER_TYPE_NORMAL
) {
92 debug("%s: invalid Header type\n", __func__
);
96 /* Base Class must be a bridge device */
97 tmpbyte
= pci_read_config8(pci_dev
, PCI_CLASS_CODE
);
98 if (tmpbyte
!= PCI_CLASS_CODE_BRIDGE
) {
99 debug("%s: invalid class\n", __func__
);
102 /* Sub Class must be ISA */
103 tmpbyte
= pci_read_config8(pci_dev
, PCI_CLASS_SUB_CODE
);
104 if (tmpbyte
!= PCI_CLASS_SUB_CODE_BRIDGE_ISA
) {
105 debug("%s: invalid subclass\n", __func__
);
109 /* Programming Interface must be 0x00 (no others exist) */
110 tmpbyte
= pci_read_config8(pci_dev
, PCI_CLASS_PROG
);
111 if (tmpbyte
!= 0x00) {
112 debug("%s: invalid interface type\n", __func__
);
117 * GPIOBASE moved to its current offset with ICH6, but prior to
118 * that it was unused (or undocumented). Check that it looks
119 * okay: not all ones or zeros.
121 * Note we don't need check bit0 here, because the Tunnel Creek
122 * GPIO base address register bit0 is reserved (read returns 0),
123 * while on the Ivybridge the bit0 is used to indicate it is an
126 tmplong
= pci_read_config32(pci_dev
, PCI_CFG_GPIOBASE
);
127 if (tmplong
== 0x00000000 || tmplong
== 0xffffffff) {
128 debug("%s: unexpected GPIOBASE value\n", __func__
);
133 * Okay, I guess we're looking at the right device. The actual
134 * GPIO registers are in the PCI device's I/O space, starting
135 * at the offset that we just read. Bit 0 indicates that it's
136 * an I/O address, not a memory address, so mask that off.
138 gpiobase
= tmplong
& 0xfffe;
139 offset
= fdtdec_get_int(gd
->fdt_blob
, dev
->of_offset
, "reg", -1);
141 debug("%s: Invalid register offset %d\n", __func__
, offset
);
144 plat
->base_addr
= gpiobase
+ offset
;
145 plat
->bank_name
= fdt_getprop(gd
->fdt_blob
, dev
->of_offset
,
151 static int ich6_gpio_probe(struct udevice
*dev
)
153 struct ich6_bank_platdata
*plat
= dev_get_platdata(dev
);
154 struct gpio_dev_priv
*uc_priv
= dev
->uclass_priv
;
155 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
157 if (gd
->arch
.gpio_map
) {
158 setup_pch_gpios(plat
->base_addr
, gd
->arch
.gpio_map
);
159 gd
->arch
.gpio_map
= NULL
;
162 uc_priv
->gpio_count
= GPIO_PER_BANK
;
163 uc_priv
->bank_name
= plat
->bank_name
;
164 bank
->use_sel
= plat
->base_addr
;
165 bank
->io_sel
= plat
->base_addr
+ 4;
166 bank
->lvl
= plat
->base_addr
+ 8;
171 static int ich6_gpio_request(struct udevice
*dev
, unsigned offset
,
174 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
178 * Make sure that the GPIO pin we want isn't already in use for some
179 * built-in hardware function. We have to check this for every
182 tmplong
= inl(bank
->use_sel
);
183 if (!(tmplong
& (1UL << offset
))) {
184 debug("%s: gpio %d is reserved for internal use\n", __func__
,
192 static int ich6_gpio_direction_input(struct udevice
*dev
, unsigned offset
)
194 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
197 tmplong
= inl(bank
->io_sel
);
198 tmplong
|= (1UL << offset
);
199 outl(bank
->io_sel
, tmplong
);
203 static int ich6_gpio_direction_output(struct udevice
*dev
, unsigned offset
,
206 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
209 gpio_set_value(offset
, value
);
211 tmplong
= inl(bank
->io_sel
);
212 tmplong
&= ~(1UL << offset
);
213 outl(bank
->io_sel
, tmplong
);
217 static int ich6_gpio_get_value(struct udevice
*dev
, unsigned offset
)
220 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
224 tmplong
= inl(bank
->lvl
);
225 r
= (tmplong
& (1UL << offset
)) ? 1 : 0;
229 static int ich6_gpio_set_value(struct udevice
*dev
, unsigned offset
,
232 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
235 tmplong
= inl(bank
->lvl
);
237 tmplong
|= (1UL << offset
);
239 tmplong
&= ~(1UL << offset
);
240 outl(bank
->lvl
, tmplong
);
244 static int ich6_gpio_get_function(struct udevice
*dev
, unsigned offset
)
246 struct ich6_bank_priv
*bank
= dev_get_priv(dev
);
247 u32 mask
= 1UL << offset
;
249 if (!(inl(bank
->use_sel
) & mask
))
251 if (inl(bank
->io_sel
) & mask
)
257 static const struct dm_gpio_ops gpio_ich6_ops
= {
258 .request
= ich6_gpio_request
,
259 .direction_input
= ich6_gpio_direction_input
,
260 .direction_output
= ich6_gpio_direction_output
,
261 .get_value
= ich6_gpio_get_value
,
262 .set_value
= ich6_gpio_set_value
,
263 .get_function
= ich6_gpio_get_function
,
266 static const struct udevice_id intel_ich6_gpio_ids
[] = {
267 { .compatible
= "intel,ich6-gpio" },
271 U_BOOT_DRIVER(gpio_ich6
) = {
274 .of_match
= intel_ich6_gpio_ids
,
275 .ops
= &gpio_ich6_ops
,
276 .ofdata_to_platdata
= gpio_ich6_ofdata_to_platdata
,
277 .probe
= ich6_gpio_probe
,
278 .priv_auto_alloc_size
= sizeof(struct ich6_bank_priv
),
279 .platdata_auto_alloc_size
= sizeof(struct ich6_bank_platdata
),