drivers/gpio/mxc_gpio.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2009
   4  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
   5  *
   6  * Copyright (C) 2011
   7  * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
   8  */
   9 #include <common.h>
  10 #include <errno.h>
  11 #include <dm.h>
  12 #include <malloc.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16
  17 enum mxc_gpio_direction {
  18         MXC_GPIO_DIRECTION_IN,
  19         MXC_GPIO_DIRECTION_OUT,
  20 };
  21
  22 #define GPIO_PER_BANK                   32
  23
  24 struct mxc_gpio_plat {
  25         int bank_index;
  26         struct gpio_regs *regs;
  27 };
  28
  29 struct mxc_bank_info {
  30         struct gpio_regs *regs;
  31 };
  32
  33 #if !CONFIG_IS_ENABLED(DM_GPIO)
  34 #define GPIO_TO_PORT(n)         ((n) / 32)
  35
  36 /* GPIO port description */
  37 static unsigned long gpio_ports[] = {
  38         [0] = GPIO1_BASE_ADDR,
  39         [1] = GPIO2_BASE_ADDR,
  40         [2] = GPIO3_BASE_ADDR,
  41 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  42                 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  43                 defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
  44                 defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
  45         [3] = GPIO4_BASE_ADDR,
  46 #endif
  47 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  48                 defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
  49                 defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
  50         [4] = GPIO5_BASE_ADDR,
  51 #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
  52                 defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
  53         [5] = GPIO6_BASE_ADDR,
  54 #endif
  55 #endif
  56 #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  57                 defined(CONFIG_ARCH_IMX8)
  58 #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  59         [6] = GPIO7_BASE_ADDR,
  60 #endif
  61 #endif
  62 #if defined(CONFIG_ARCH_IMX8)
  63         [7] = GPIO8_BASE_ADDR,
  64 #endif
  65 };
  66
  67 static int mxc_gpio_direction(unsigned int gpio,
  68         enum mxc_gpio_direction direction)
  69 {
  70         unsigned int port = GPIO_TO_PORT(gpio);
  71         struct gpio_regs *regs;
  72         u32 l;
  73
  74         if (port >= ARRAY_SIZE(gpio_ports))
  75                 return -1;
  76
  77         gpio &= 0x1f;
  78
  79         regs = (struct gpio_regs *)gpio_ports[port];
  80
  81         l = readl(&regs->gpio_dir);
  82
  83         switch (direction) {
  84         case MXC_GPIO_DIRECTION_OUT:
  85                 l |= 1 << gpio;
  86                 break;
  87         case MXC_GPIO_DIRECTION_IN:
  88                 l &= ~(1 << gpio);
  89         }
  90         writel(l, &regs->gpio_dir);
  91
  92         return 0;
  93 }
  94
  95 int gpio_set_value(unsigned gpio, int value)
  96 {
  97         unsigned int port = GPIO_TO_PORT(gpio);
  98         struct gpio_regs *regs;
  99         u32 l;
 100
 101         if (port >= ARRAY_SIZE(gpio_ports))
 102                 return -1;
 103
 104         gpio &= 0x1f;
 105
 106         regs = (struct gpio_regs *)gpio_ports[port];
 107
 108         l = readl(&regs->gpio_dr);
 109         if (value)
 110                 l |= 1 << gpio;
 111         else
 112                 l &= ~(1 << gpio);
 113         writel(l, &regs->gpio_dr);
 114
 115         return 0;
 116 }
 117
 118 int gpio_get_value(unsigned gpio)
 119 {
 120         unsigned int port = GPIO_TO_PORT(gpio);
 121         struct gpio_regs *regs;
 122         u32 val;
 123
 124         if (port >= ARRAY_SIZE(gpio_ports))
 125                 return -1;
 126
 127         gpio &= 0x1f;
 128
 129         regs = (struct gpio_regs *)gpio_ports[port];
 130
 131         val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
 132
 133         return val;
 134 }
 135
 136 int gpio_request(unsigned gpio, const char *label)
 137 {
 138         unsigned int port = GPIO_TO_PORT(gpio);
 139         if (port >= ARRAY_SIZE(gpio_ports))
 140                 return -1;
 141         return 0;
 142 }
 143
 144 int gpio_free(unsigned gpio)
 145 {
 146         return 0;
 147 }
 148
 149 int gpio_direction_input(unsigned gpio)
 150 {
 151         return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
 152 }
 153
 154 int gpio_direction_output(unsigned gpio, int value)
 155 {
 156         int ret = gpio_set_value(gpio, value);
 157
 158         if (ret < 0)
 159                 return ret;
 160
 161         return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
 162 }
 163 #endif
 164
 165 #if CONFIG_IS_ENABLED(DM_GPIO)
 166 #include <fdtdec.h>
 167 static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
 168 {
 169         u32 val;
 170
 171         val = readl(&regs->gpio_dir);
 172
 173         return val & (1 << offset) ? 1 : 0;
 174 }
 175
 176 static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
 177                                     enum mxc_gpio_direction direction)
 178 {
 179         u32 l;
 180
 181         l = readl(&regs->gpio_dir);
 182
 183         switch (direction) {
 184         case MXC_GPIO_DIRECTION_OUT:
 185                 l |= 1 << offset;
 186                 break;
 187         case MXC_GPIO_DIRECTION_IN:
 188                 l &= ~(1 << offset);
 189         }
 190         writel(l, &regs->gpio_dir);
 191 }
 192
 193 static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
 194                                     int value)
 195 {
 196         u32 l;
 197
 198         l = readl(&regs->gpio_dr);
 199         if (value)
 200                 l |= 1 << offset;
 201         else
 202                 l &= ~(1 << offset);
 203         writel(l, &regs->gpio_dr);
 204 }
 205
 206 static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
 207 {
 208         return (readl(&regs->gpio_psr) >> offset) & 0x01;
 209 }
 210
 211 /* set GPIO pin 'gpio' as an input */
 212 static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
 213 {
 214         struct mxc_bank_info *bank = dev_get_priv(dev);
 215
 216         /* Configure GPIO direction as input. */
 217         mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
 218
 219         return 0;
 220 }
 221
 222 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
 223 static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
 224                                        int value)
 225 {
 226         struct mxc_bank_info *bank = dev_get_priv(dev);
 227
 228         /* Configure GPIO output value. */
 229         mxc_gpio_bank_set_value(bank->regs, offset, value);
 230
 231         /* Configure GPIO direction as output. */
 232         mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
 233
 234         return 0;
 235 }
 236
 237 /* read GPIO IN value of pin 'gpio' */
 238 static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
 239 {
 240         struct mxc_bank_info *bank = dev_get_priv(dev);
 241
 242         return mxc_gpio_bank_get_value(bank->regs, offset);
 243 }
 244
 245 /* write GPIO OUT value to pin 'gpio' */
 246 static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
 247                                  int value)
 248 {
 249         struct mxc_bank_info *bank = dev_get_priv(dev);
 250
 251         mxc_gpio_bank_set_value(bank->regs, offset, value);
 252
 253         return 0;
 254 }
 255
 256 static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
 257 {
 258         struct mxc_bank_info *bank = dev_get_priv(dev);
 259
 260         /* GPIOF_FUNC is not implemented yet */
 261         if (mxc_gpio_is_output(bank->regs, offset))
 262                 return GPIOF_OUTPUT;
 263         else
 264                 return GPIOF_INPUT;
 265 }
 266
 267 static const struct dm_gpio_ops gpio_mxc_ops = {
 268         .direction_input        = mxc_gpio_direction_input,
 269         .direction_output       = mxc_gpio_direction_output,
 270         .get_value              = mxc_gpio_get_value,
 271         .set_value              = mxc_gpio_set_value,
 272         .get_function           = mxc_gpio_get_function,
 273 };
 274
 275 static int mxc_gpio_probe(struct udevice *dev)
 276 {
 277         struct mxc_bank_info *bank = dev_get_priv(dev);
 278         struct mxc_gpio_plat *plat = dev_get_platdata(dev);
 279         struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 280         int banknum;
 281         char name[18], *str;
 282
 283         banknum = plat->bank_index;
 284         sprintf(name, "GPIO%d_", banknum + 1);
 285         str = strdup(name);
 286         if (!str)
 287                 return -ENOMEM;
 288         uc_priv->bank_name = str;
 289         uc_priv->gpio_count = GPIO_PER_BANK;
 290         bank->regs = plat->regs;
 291
 292         return 0;
 293 }
 294
 295 static int mxc_gpio_bind(struct udevice *dev)
 296 {
 297         struct mxc_gpio_plat *plat = dev->platdata;
 298         fdt_addr_t addr;
 299
 300         /*
 301          * If platdata already exsits, directly return.
 302          * Actually only when DT is not supported, platdata
 303          * is statically initialized in U_BOOT_DEVICES.Here
 304          * will return.
 305          */
 306         if (plat)
 307                 return 0;
 308
 309         addr = devfdt_get_addr(dev);
 310         if (addr == FDT_ADDR_T_NONE)
 311                 return -EINVAL;
 312
 313         /*
 314          * TODO:
 315          * When every board is converted to driver model and DT is supported,
 316          * this can be done by auto-alloc feature, but not using calloc
 317          * to alloc memory for platdata.
 318          *
 319          * For example mxc_plat below uses platform data rather than device
 320          * tree.
 321          *
 322          * NOTE: DO NOT COPY this code if you are using device tree.
 323          */
 324         plat = calloc(1, sizeof(*plat));
 325         if (!plat)
 326                 return -ENOMEM;
 327
 328         plat->regs = (struct gpio_regs *)addr;
 329         plat->bank_index = dev->req_seq;
 330         dev->platdata = plat;
 331
 332         return 0;
 333 }
 334
 335 static const struct udevice_id mxc_gpio_ids[] = {
 336         { .compatible = "fsl,imx35-gpio" },
 337         { }
 338 };
 339
 340 U_BOOT_DRIVER(gpio_mxc) = {
 341         .name   = "gpio_mxc",
 342         .id     = UCLASS_GPIO,
 343         .ops    = &gpio_mxc_ops,
 344         .probe  = mxc_gpio_probe,
 345         .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
 346         .of_match = mxc_gpio_ids,
 347         .bind   = mxc_gpio_bind,
 348 };
 349
 350 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 351 static const struct mxc_gpio_plat mxc_plat[] = {
 352         { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
 353         { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
 354         { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
 355 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 356                 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 357                 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 358         { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
 359 #endif
 360 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 361                 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 362         { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
 363 #ifndef CONFIG_IMX8M
 364         { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
 365 #endif
 366 #endif
 367 #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
 368         { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
 369 #endif
 370 #if defined(CONFIG_ARCH_IMX8)
 371         { 7, (struct gpio_regs *)GPIO8_BASE_ADDR },
 372 #endif
 373 };
 374
 375 U_BOOT_DEVICES(mxc_gpios) = {
 376         { "gpio_mxc", &mxc_plat[0] },
 377         { "gpio_mxc", &mxc_plat[1] },
 378         { "gpio_mxc", &mxc_plat[2] },
 379 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 380                 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 381                 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 382         { "gpio_mxc", &mxc_plat[3] },
 383 #endif
 384 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 385                 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 386         { "gpio_mxc", &mxc_plat[4] },
 387 #ifndef CONFIG_IMX8M
 388         { "gpio_mxc", &mxc_plat[5] },
 389 #endif
 390 #endif
 391 #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
 392         { "gpio_mxc", &mxc_plat[6] },
 393 #endif
 394 #if defined(CONFIG_ARCH_IMX8)
 395         { "gpio_mxc", &mxc_plat[7] },
 396 #endif
 397 };
 398 #endif
 399 #endif