drivers/gpio/mxs_gpio.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale i.MX28 GPIO control code
   4  *
   5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   6  * on behalf of DENX Software Engineering GmbH
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <linux/errno.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/imx-regs.h>
  15
  16 #if     defined(CONFIG_MX23)
  17 #define PINCTRL_BANKS           3
  18 #define PINCTRL_DOUT(n)         (0x0500 + ((n) * 0x10))
  19 #define PINCTRL_DIN(n)          (0x0600 + ((n) * 0x10))
  20 #define PINCTRL_DOE(n)          (0x0700 + ((n) * 0x10))
  21 #define PINCTRL_PIN2IRQ(n)      (0x0800 + ((n) * 0x10))
  22 #define PINCTRL_IRQEN(n)        (0x0900 + ((n) * 0x10))
  23 #define PINCTRL_IRQSTAT(n)      (0x0c00 + ((n) * 0x10))
  24 #elif   defined(CONFIG_MX28)
  25 #define PINCTRL_BANKS           5
  26 #define PINCTRL_DOUT(n)         (0x0700 + ((n) * 0x10))
  27 #define PINCTRL_DIN(n)          (0x0900 + ((n) * 0x10))
  28 #define PINCTRL_DOE(n)          (0x0b00 + ((n) * 0x10))
  29 #define PINCTRL_PIN2IRQ(n)      (0x1000 + ((n) * 0x10))
  30 #define PINCTRL_IRQEN(n)        (0x1100 + ((n) * 0x10))
  31 #define PINCTRL_IRQSTAT(n)      (0x1400 + ((n) * 0x10))
  32 #else
  33 #error "Please select CONFIG_MX23 or CONFIG_MX28"
  34 #endif
  35
  36 #define GPIO_INT_FALL_EDGE      0x0
  37 #define GPIO_INT_LOW_LEV        0x1
  38 #define GPIO_INT_RISE_EDGE      0x2
  39 #define GPIO_INT_HIGH_LEV       0x3
  40 #define GPIO_INT_LEV_MASK       (1 << 0)
  41 #define GPIO_INT_POL_MASK       (1 << 1)
  42
  43 void mxs_gpio_init(void)
  44 {
  45         int i;
  46
  47         for (i = 0; i < PINCTRL_BANKS; i++) {
  48                 writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
  49                 writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
  50                 /* Use SCT address here to clear the IRQSTAT bits */
  51                 writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
  52         }
  53 }
  54
  55 #if !CONFIG_IS_ENABLED(DM_GPIO)
  56 int gpio_get_value(unsigned gpio)
  57 {
  58         uint32_t bank = PAD_BANK(gpio);
  59         uint32_t offset = PINCTRL_DIN(bank);
  60         struct mxs_register_32 *reg =
  61                 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  62
  63         return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
  64 }
  65
  66 void gpio_set_value(unsigned gpio, int value)
  67 {
  68         uint32_t bank = PAD_BANK(gpio);
  69         uint32_t offset = PINCTRL_DOUT(bank);
  70         struct mxs_register_32 *reg =
  71                 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  72
  73         if (value)
  74                 writel(1 << PAD_PIN(gpio), &reg->reg_set);
  75         else
  76                 writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  77 }
  78
  79 int gpio_direction_input(unsigned gpio)
  80 {
  81         uint32_t bank = PAD_BANK(gpio);
  82         uint32_t offset = PINCTRL_DOE(bank);
  83         struct mxs_register_32 *reg =
  84                 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  85
  86         writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  87
  88         return 0;
  89 }
  90
  91 int gpio_direction_output(unsigned gpio, int value)
  92 {
  93         uint32_t bank = PAD_BANK(gpio);
  94         uint32_t offset = PINCTRL_DOE(bank);
  95         struct mxs_register_32 *reg =
  96                 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  97
  98         gpio_set_value(gpio, value);
  99
 100         writel(1 << PAD_PIN(gpio), &reg->reg_set);
 101
 102         return 0;
 103 }
 104
 105 int gpio_request(unsigned gpio, const char *label)
 106 {
 107         if (PAD_BANK(gpio) >= PINCTRL_BANKS)
 108                 return -1;
 109
 110         return 0;
 111 }
 112
 113 int gpio_free(unsigned gpio)
 114 {
 115         return 0;
 116 }
 117
 118 int name_to_gpio(const char *name)
 119 {
 120         unsigned bank, pin;
 121         char *end;
 122
 123         bank = simple_strtoul(name, &end, 10);
 124
 125         if (!*end || *end != ':')
 126                 return bank;
 127
 128         pin = simple_strtoul(end + 1, NULL, 10);
 129
 130         return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
 131 }
 132 #else /* DM_GPIO */
 133 #include <dm.h>
 134 #include <asm/gpio.h>
 135 #include <dt-structs.h>
 136 #include <asm/arch/gpio.h>
 137 #define MXS_MAX_GPIO_PER_BANK           32
 138
 139 #ifdef CONFIG_MX28
 140 #define dtd_fsl_imx_gpio dtd_fsl_imx28_gpio
 141 #else /* CONFIG_MX23 */
 142 #define dtd_fsl_imx_gpio dtd_fsl_imx23_gpio
 143 #endif
 144
 145 DECLARE_GLOBAL_DATA_PTR;
 146 /*
 147  * According to i.MX28 Reference Manual:
 148  * 'i.MX28 Applications Processor Reference Manual, Rev. 1, 2010'
 149  * The i.MX28 has following number of GPIOs available:
 150  * Bank 0: 0-28 -> 29 PINS
 151  * Bank 1: 0-31 -> 32 PINS
 152  * Bank 2: 0-27 -> 28 PINS
 153  * Bank 3: 0-30 -> 31 PINS
 154  * Bank 4: 0-20 -> 21 PINS
 155  */
 156
 157 struct mxs_gpio_platdata {
 158 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 159         struct dtd_fsl_imx_gpio dtplat;
 160 #endif
 161         unsigned int bank;
 162         int gpio_ranges;
 163 };
 164
 165 struct mxs_gpio_priv {
 166         unsigned int bank;
 167 };
 168
 169 static int mxs_gpio_get_value(struct udevice *dev, unsigned offset)
 170 {
 171         struct mxs_gpio_priv *priv = dev_get_priv(dev);
 172         struct mxs_register_32 *reg =
 173                 (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
 174                                            PINCTRL_DIN(priv->bank));
 175
 176         return (readl(&reg->reg) >> offset) & 1;
 177 }
 178
 179 static int mxs_gpio_set_value(struct udevice *dev, unsigned offset,
 180                               int value)
 181 {
 182         struct mxs_gpio_priv *priv = dev_get_priv(dev);
 183         struct mxs_register_32 *reg =
 184                 (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
 185                                            PINCTRL_DOUT(priv->bank));
 186         if (value)
 187                 writel(BIT(offset), &reg->reg_set);
 188         else
 189                 writel(BIT(offset), &reg->reg_clr);
 190
 191         return 0;
 192 }
 193
 194 static int mxs_gpio_direction_input(struct udevice *dev, unsigned offset)
 195 {
 196         struct mxs_gpio_priv *priv = dev_get_priv(dev);
 197         struct mxs_register_32 *reg =
 198                 (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
 199                                            PINCTRL_DOE(priv->bank));
 200
 201         writel(BIT(offset), &reg->reg_clr);
 202
 203         return 0;
 204 }
 205
 206 static int mxs_gpio_direction_output(struct udevice *dev, unsigned offset,
 207                                      int value)
 208 {
 209         struct mxs_gpio_priv *priv = dev_get_priv(dev);
 210         struct mxs_register_32 *reg =
 211                 (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
 212                                            PINCTRL_DOE(priv->bank));
 213
 214         mxs_gpio_set_value(dev, offset, value);
 215
 216         writel(BIT(offset), &reg->reg_set);
 217
 218         return 0;
 219 }
 220
 221 static int mxs_gpio_get_function(struct udevice *dev, unsigned offset)
 222 {
 223         struct mxs_gpio_priv *priv = dev_get_priv(dev);
 224         struct mxs_register_32 *reg =
 225                 (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
 226                                            PINCTRL_DOE(priv->bank));
 227         bool is_output = !!(readl(&reg->reg) >> offset);
 228
 229         return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
 230 }
 231
 232 static const struct dm_gpio_ops gpio_mxs_ops = {
 233         .direction_input        = mxs_gpio_direction_input,
 234         .direction_output       = mxs_gpio_direction_output,
 235         .get_value              = mxs_gpio_get_value,
 236         .set_value              = mxs_gpio_set_value,
 237         .get_function           = mxs_gpio_get_function,
 238 };
 239
 240 static int mxs_gpio_probe(struct udevice *dev)
 241 {
 242         struct mxs_gpio_platdata *plat = dev_get_platdata(dev);
 243         struct mxs_gpio_priv *priv = dev_get_priv(dev);
 244         struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 245         char name[16], *str;
 246
 247 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 248         struct dtd_fsl_imx_gpio *dtplat = &plat->dtplat;
 249         priv->bank = (unsigned int)dtplat->reg[0];
 250         uc_priv->gpio_count = dtplat->gpio_ranges[3];
 251 #else
 252         priv->bank = (unsigned int)plat->bank;
 253         uc_priv->gpio_count = plat->gpio_ranges;
 254 #endif
 255         snprintf(name, sizeof(name), "GPIO%d_", priv->bank);
 256         str = strdup(name);
 257         if (!str)
 258                 return -ENOMEM;
 259
 260         uc_priv->bank_name = str;
 261
 262         debug("%s: %s: %d pins base: 0x%x\n", __func__, uc_priv->bank_name,
 263               uc_priv->gpio_count, priv->bank);
 264
 265         return 0;
 266 }
 267
 268 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 269 static int mxs_ofdata_to_platdata(struct udevice *dev)
 270 {
 271         struct mxs_gpio_platdata *plat = dev->platdata;
 272         struct fdtdec_phandle_args args;
 273         int node = dev_of_offset(dev);
 274         int ret;
 275
 276         plat->bank = devfdt_get_addr(dev);
 277         if (plat->bank == FDT_ADDR_T_NONE) {
 278                 printf("%s: No 'reg' property defined!\n", __func__);
 279                 return -EINVAL;
 280         }
 281
 282         ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
 283                                              NULL, 3, 0, &args);
 284         if (ret)
 285                 printf("%s: 'gpio-ranges' not defined - using default!\n",
 286                        __func__);
 287
 288         plat->gpio_ranges = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK;
 289
 290         return 0;
 291 }
 292
 293 static const struct udevice_id mxs_gpio_ids[] = {
 294         { .compatible = "fsl,imx23-gpio" },
 295         { .compatible = "fsl,imx28-gpio" },
 296         { }
 297 };
 298 #endif
 299
 300 U_BOOT_DRIVER(gpio_mxs) = {
 301 #ifdef CONFIG_MX28
 302         .name = "fsl_imx28_gpio",
 303 #else /* CONFIG_MX23 */
 304         .name = "fsl_imx23_gpio",
 305 #endif
 306         .id     = UCLASS_GPIO,
 307         .ops    = &gpio_mxs_ops,
 308         .probe  = mxs_gpio_probe,
 309         .priv_auto_alloc_size = sizeof(struct mxs_gpio_priv),
 310         .platdata_auto_alloc_size = sizeof(struct mxs_gpio_platdata),
 311 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 312         .of_match = mxs_gpio_ids,
 313         .ofdata_to_platdata = mxs_ofdata_to_platdata,
 314 #endif
 315 };
 316 #endif /* DM_GPIO */