drivers/gpio/s5p_gpio.c

   1 /*
   2  * (C) Copyright 2009 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <fdtdec.h>
  12 #include <malloc.h>
  13 #include <asm/io.h>
  14 #include <asm/gpio.h>
  15 #include <dm/device-internal.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #define S5P_GPIO_GET_PIN(x)     (x % GPIO_PER_BANK)
  20
  21 #define CON_MASK(val)                   (0xf << ((val) << 2))
  22 #define CON_SFR(gpio, cfg)              ((cfg) << ((gpio) << 2))
  23 #define CON_SFR_UNSHIFT(val, gpio)      ((val) >> ((gpio) << 2))
  24
  25 #define DAT_MASK(gpio)                  (0x1 << (gpio))
  26 #define DAT_SET(gpio)                   (0x1 << (gpio))
  27
  28 #define PULL_MASK(gpio)         (0x3 << ((gpio) << 1))
  29 #define PULL_MODE(gpio, pull)           ((pull) << ((gpio) << 1))
  30
  31 #define DRV_MASK(gpio)                  (0x3 << ((gpio) << 1))
  32 #define DRV_SET(gpio, mode)             ((mode) << ((gpio) << 1))
  33 #define RATE_MASK(gpio)         (0x1 << (gpio + 16))
  34 #define RATE_SET(gpio)                  (0x1 << (gpio + 16))
  35
  36 /* Platform data for each bank */
  37 struct exynos_gpio_platdata {
  38         struct s5p_gpio_bank *bank;
  39         const char *bank_name;  /* Name of port, e.g. 'gpa0" */
  40 };
  41
  42 /* Information about each bank at run-time */
  43 struct exynos_bank_info {
  44         struct s5p_gpio_bank *bank;
  45 };
  46
  47 static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
  48 {
  49         const struct gpio_info *data;
  50         unsigned int upto;
  51         int i, count;
  52
  53         data = get_gpio_data();
  54         count = get_bank_num();
  55         upto = 0;
  56
  57         for (i = 0; i < count; i++) {
  58                 debug("i=%d, upto=%d\n", i, upto);
  59                 if (gpio < data->max_gpio) {
  60                         struct s5p_gpio_bank *bank;
  61                         bank = (struct s5p_gpio_bank *)data->reg_addr;
  62                         bank += (gpio - upto) / GPIO_PER_BANK;
  63                         debug("gpio=%d, bank=%p\n", gpio, bank);
  64                         return bank;
  65                 }
  66
  67                 upto = data->max_gpio;
  68                 data++;
  69         }
  70
  71         return NULL;
  72 }
  73
  74 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
  75 {
  76         unsigned int value;
  77
  78         value = readl(&bank->con);
  79         value &= ~CON_MASK(gpio);
  80         value |= CON_SFR(gpio, cfg);
  81         writel(value, &bank->con);
  82 }
  83
  84 static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
  85 {
  86         unsigned int value;
  87
  88         value = readl(&bank->dat);
  89         value &= ~DAT_MASK(gpio);
  90         if (en)
  91                 value |= DAT_SET(gpio);
  92         writel(value, &bank->dat);
  93 }
  94
  95 #ifdef CONFIG_SPL_BUILD
  96 /* Common GPIO API - SPL does not support driver model yet */
  97 int gpio_set_value(unsigned gpio, int value)
  98 {
  99         s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
 100                            s5p_gpio_get_pin(gpio), value);
 101
 102         return 0;
 103 }
 104 #else
 105 static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio)
 106 {
 107         unsigned int value;
 108
 109         value = readl(&bank->con);
 110         value &= CON_MASK(gpio);
 111         return CON_SFR_UNSHIFT(value, gpio);
 112 }
 113
 114 static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
 115 {
 116         unsigned int value;
 117
 118         value = readl(&bank->dat);
 119         return !!(value & DAT_MASK(gpio));
 120 }
 121 #endif /* CONFIG_SPL_BUILD */
 122
 123 static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
 124 {
 125         unsigned int value;
 126
 127         value = readl(&bank->pull);
 128         value &= ~PULL_MASK(gpio);
 129
 130         switch (mode) {
 131         case S5P_GPIO_PULL_DOWN:
 132         case S5P_GPIO_PULL_UP:
 133                 value |= PULL_MODE(gpio, mode);
 134                 break;
 135         default:
 136                 break;
 137         }
 138
 139         writel(value, &bank->pull);
 140 }
 141
 142 static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
 143 {
 144         unsigned int value;
 145
 146         value = readl(&bank->drv);
 147         value &= ~DRV_MASK(gpio);
 148
 149         switch (mode) {
 150         case S5P_GPIO_DRV_1X:
 151         case S5P_GPIO_DRV_2X:
 152         case S5P_GPIO_DRV_3X:
 153         case S5P_GPIO_DRV_4X:
 154                 value |= DRV_SET(gpio, mode);
 155                 break;
 156         default:
 157                 return;
 158         }
 159
 160         writel(value, &bank->drv);
 161 }
 162
 163 static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 164 {
 165         unsigned int value;
 166
 167         value = readl(&bank->drv);
 168         value &= ~RATE_MASK(gpio);
 169
 170         switch (mode) {
 171         case S5P_GPIO_DRV_FAST:
 172         case S5P_GPIO_DRV_SLOW:
 173                 value |= RATE_SET(gpio);
 174                 break;
 175         default:
 176                 return;
 177         }
 178
 179         writel(value, &bank->drv);
 180 }
 181
 182 int s5p_gpio_get_pin(unsigned gpio)
 183 {
 184         return S5P_GPIO_GET_PIN(gpio);
 185 }
 186
 187 /* Driver model interface */
 188 #ifndef CONFIG_SPL_BUILD
 189 /* set GPIO pin 'gpio' as an input */
 190 static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
 191 {
 192         struct exynos_bank_info *state = dev_get_priv(dev);
 193
 194         /* Configure GPIO direction as input. */
 195         s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT);
 196
 197         return 0;
 198 }
 199
 200 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
 201 static int exynos_gpio_direction_output(struct udevice *dev, unsigned offset,
 202                                        int value)
 203 {
 204         struct exynos_bank_info *state = dev_get_priv(dev);
 205
 206         /* Configure GPIO output value. */
 207         s5p_gpio_set_value(state->bank, offset, value);
 208
 209         /* Configure GPIO direction as output. */
 210         s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT);
 211
 212         return 0;
 213 }
 214
 215 /* read GPIO IN value of pin 'gpio' */
 216 static int exynos_gpio_get_value(struct udevice *dev, unsigned offset)
 217 {
 218         struct exynos_bank_info *state = dev_get_priv(dev);
 219
 220         return s5p_gpio_get_value(state->bank, offset);
 221 }
 222
 223 /* write GPIO OUT value to pin 'gpio' */
 224 static int exynos_gpio_set_value(struct udevice *dev, unsigned offset,
 225                                  int value)
 226 {
 227         struct exynos_bank_info *state = dev_get_priv(dev);
 228
 229         s5p_gpio_set_value(state->bank, offset, value);
 230
 231         return 0;
 232 }
 233 #endif /* nCONFIG_SPL_BUILD */
 234
 235 /*
 236  * There is no common GPIO API for pull, drv, pin, rate (yet). These
 237  * functions are kept here to preserve function ordering for review.
 238  */
 239 void gpio_set_pull(int gpio, int mode)
 240 {
 241         s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
 242                           s5p_gpio_get_pin(gpio), mode);
 243 }
 244
 245 void gpio_set_drv(int gpio, int mode)
 246 {
 247         s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
 248                          s5p_gpio_get_pin(gpio), mode);
 249 }
 250
 251 void gpio_cfg_pin(int gpio, int cfg)
 252 {
 253         s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
 254                          s5p_gpio_get_pin(gpio), cfg);
 255 }
 256
 257 void gpio_set_rate(int gpio, int mode)
 258 {
 259         s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
 260                           s5p_gpio_get_pin(gpio), mode);
 261 }
 262
 263 #ifndef CONFIG_SPL_BUILD
 264 static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
 265 {
 266         struct exynos_bank_info *state = dev_get_priv(dev);
 267         int cfg;
 268
 269         cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
 270         if (cfg == S5P_GPIO_OUTPUT)
 271                 return GPIOF_OUTPUT;
 272         else if (cfg == S5P_GPIO_INPUT)
 273                 return GPIOF_INPUT;
 274         else
 275                 return GPIOF_FUNC;
 276 }
 277
 278 static const struct dm_gpio_ops gpio_exynos_ops = {
 279         .direction_input        = exynos_gpio_direction_input,
 280         .direction_output       = exynos_gpio_direction_output,
 281         .get_value              = exynos_gpio_get_value,
 282         .set_value              = exynos_gpio_set_value,
 283         .get_function           = exynos_gpio_get_function,
 284 };
 285
 286 static int gpio_exynos_probe(struct udevice *dev)
 287 {
 288         struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 289         struct exynos_bank_info *priv = dev->priv;
 290         struct exynos_gpio_platdata *plat = dev->platdata;
 291
 292         /* Only child devices have ports */
 293         if (!plat)
 294                 return 0;
 295
 296         priv->bank = plat->bank;
 297
 298         uc_priv->gpio_count = GPIO_PER_BANK;
 299         uc_priv->bank_name = plat->bank_name;
 300
 301         return 0;
 302 }
 303
 304 /**
 305  * We have a top-level GPIO device with no actual GPIOs. It has a child
 306  * device for each Exynos GPIO bank.
 307  */
 308 static int gpio_exynos_bind(struct udevice *parent)
 309 {
 310         struct exynos_gpio_platdata *plat = parent->platdata;
 311         struct s5p_gpio_bank *bank, *base;
 312         const void *blob = gd->fdt_blob;
 313         int node;
 314
 315         /* If this is a child device, there is nothing to do here */
 316         if (plat)
 317                 return 0;
 318
 319         base = (struct s5p_gpio_bank *)devfdt_get_addr(parent);
 320         for (node = fdt_first_subnode(blob, dev_of_offset(parent)), bank = base;
 321              node > 0;
 322              node = fdt_next_subnode(blob, node), bank++) {
 323                 struct exynos_gpio_platdata *plat;
 324                 struct udevice *dev;
 325                 fdt_addr_t reg;
 326                 int ret;
 327
 328                 if (!fdtdec_get_bool(blob, node, "gpio-controller"))
 329                         continue;
 330                 plat = calloc(1, sizeof(*plat));
 331                 if (!plat)
 332                         return -ENOMEM;
 333
 334                 plat->bank_name = fdt_get_name(blob, node, NULL);
 335                 ret = device_bind(parent, parent->driver,
 336                                   plat->bank_name, plat, -1, &dev);
 337                 if (ret)
 338                         return ret;
 339
 340                 dev_set_of_offset(dev, node);
 341
 342                 reg = devfdt_get_addr(dev);
 343                 if (reg != FDT_ADDR_T_NONE)
 344                         bank = (struct s5p_gpio_bank *)((ulong)base + reg);
 345
 346                 plat->bank = bank;
 347
 348                 debug("dev at %p: %s\n", bank, plat->bank_name);
 349         }
 350
 351         return 0;
 352 }
 353
 354 static const struct udevice_id exynos_gpio_ids[] = {
 355         { .compatible = "samsung,s5pc100-pinctrl" },
 356         { .compatible = "samsung,s5pc110-pinctrl" },
 357         { .compatible = "samsung,exynos4210-pinctrl" },
 358         { .compatible = "samsung,exynos4x12-pinctrl" },
 359         { .compatible = "samsung,exynos5250-pinctrl" },
 360         { .compatible = "samsung,exynos5420-pinctrl" },
 361         { }
 362 };
 363
 364 U_BOOT_DRIVER(gpio_exynos) = {
 365         .name   = "gpio_exynos",
 366         .id     = UCLASS_GPIO,
 367         .of_match = exynos_gpio_ids,
 368         .bind   = gpio_exynos_bind,
 369         .probe = gpio_exynos_probe,
 370         .priv_auto_alloc_size = sizeof(struct exynos_bank_info),
 371         .ops    = &gpio_exynos_ops,
 372 };
 373 #endif