1 // SPDX-License-Identifier: GPL-2.0+
3 * NVIDIA Tegra20 GPIO handling.
4 * (C) Copyright 2010-2012,2015
5 * NVIDIA Corporation <www.nvidia.com>
9 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
10 * Tom Warren (twarren@nvidia.com)
19 #include <asm/bitops.h>
20 #include <asm/arch/tegra.h>
22 #include <dm/device-internal.h>
23 #include <dt-bindings/gpio/gpio.h>
25 static const int CONFIG_SFIO
= 0;
26 static const int CONFIG_GPIO
= 1;
27 static const int DIRECTION_INPUT
= 0;
28 static const int DIRECTION_OUTPUT
= 1;
30 struct tegra_gpio_platdata
{
31 struct gpio_ctlr_bank
*bank
;
32 const char *port_name
; /* Name of port, e.g. "B" */
33 int base_gpio
; /* Port number for this port (0, 1,.., n-1) */
36 /* Information about each port at run-time */
37 struct tegra_port_info
{
38 struct gpio_ctlr_bank
*bank
;
39 int base_gpio
; /* Port number for this port (0, 1,.., n-1) */
42 /* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
43 static int get_config(unsigned gpio
)
45 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
46 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
50 u
= readl(&bank
->gpio_config
[GPIO_PORT(gpio
)]);
51 type
= (u
>> GPIO_BIT(gpio
)) & 1;
53 debug("get_config: port = %d, bit = %d is %s\n",
54 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), type
? "GPIO" : "SFPIO");
56 return type
? CONFIG_GPIO
: CONFIG_SFIO
;
59 /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
60 static void set_config(unsigned gpio
, int type
)
62 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
63 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
66 debug("set_config: port = %d, bit = %d, %s\n",
67 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), type
? "GPIO" : "SFPIO");
69 u
= readl(&bank
->gpio_config
[GPIO_PORT(gpio
)]);
70 if (type
!= CONFIG_SFIO
)
71 u
|= 1 << GPIO_BIT(gpio
);
73 u
&= ~(1 << GPIO_BIT(gpio
));
74 writel(u
, &bank
->gpio_config
[GPIO_PORT(gpio
)]);
77 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
78 static int get_direction(unsigned gpio
)
80 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
81 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
85 u
= readl(&bank
->gpio_dir_out
[GPIO_PORT(gpio
)]);
86 dir
= (u
>> GPIO_BIT(gpio
)) & 1;
88 debug("get_direction: port = %d, bit = %d, %s\n",
89 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), dir
? "OUT" : "IN");
91 return dir
? DIRECTION_OUTPUT
: DIRECTION_INPUT
;
94 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
95 static void set_direction(unsigned gpio
, int output
)
97 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
98 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
101 debug("set_direction: port = %d, bit = %d, %s\n",
102 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), output
? "OUT" : "IN");
104 u
= readl(&bank
->gpio_dir_out
[GPIO_PORT(gpio
)]);
105 if (output
!= DIRECTION_INPUT
)
106 u
|= 1 << GPIO_BIT(gpio
);
108 u
&= ~(1 << GPIO_BIT(gpio
));
109 writel(u
, &bank
->gpio_dir_out
[GPIO_PORT(gpio
)]);
112 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
113 static void set_level(unsigned gpio
, int high
)
115 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
116 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
119 debug("set_level: port = %d, bit %d == %d\n",
120 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), high
);
122 u
= readl(&bank
->gpio_out
[GPIO_PORT(gpio
)]);
124 u
|= 1 << GPIO_BIT(gpio
);
126 u
&= ~(1 << GPIO_BIT(gpio
));
127 writel(u
, &bank
->gpio_out
[GPIO_PORT(gpio
)]);
131 * Generic_GPIO primitives.
134 /* set GPIO pin 'gpio' as an input */
135 static int tegra_gpio_direction_input(struct udevice
*dev
, unsigned offset
)
137 struct tegra_port_info
*state
= dev_get_priv(dev
);
139 /* Configure GPIO direction as input. */
140 set_direction(state
->base_gpio
+ offset
, DIRECTION_INPUT
);
142 /* Enable the pin as a GPIO */
143 set_config(state
->base_gpio
+ offset
, 1);
148 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
149 static int tegra_gpio_direction_output(struct udevice
*dev
, unsigned offset
,
152 struct tegra_port_info
*state
= dev_get_priv(dev
);
153 int gpio
= state
->base_gpio
+ offset
;
155 /* Configure GPIO output value. */
156 set_level(gpio
, value
);
158 /* Configure GPIO direction as output. */
159 set_direction(gpio
, DIRECTION_OUTPUT
);
161 /* Enable the pin as a GPIO */
162 set_config(state
->base_gpio
+ offset
, 1);
167 /* read GPIO IN value of pin 'gpio' */
168 static int tegra_gpio_get_value(struct udevice
*dev
, unsigned offset
)
170 struct tegra_port_info
*state
= dev_get_priv(dev
);
171 int gpio
= state
->base_gpio
+ offset
;
174 debug("%s: pin = %d (port %d:bit %d)\n", __func__
,
175 gpio
, GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
));
177 if (get_direction(gpio
) == DIRECTION_INPUT
)
178 val
= readl(&state
->bank
->gpio_in
[GPIO_PORT(gpio
)]);
180 val
= readl(&state
->bank
->gpio_out
[GPIO_PORT(gpio
)]);
182 return (val
>> GPIO_BIT(gpio
)) & 1;
185 /* write GPIO OUT value to pin 'gpio' */
186 static int tegra_gpio_set_value(struct udevice
*dev
, unsigned offset
, int value
)
188 struct tegra_port_info
*state
= dev_get_priv(dev
);
189 int gpio
= state
->base_gpio
+ offset
;
191 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
192 gpio
, GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), value
);
194 /* Configure GPIO output value. */
195 set_level(gpio
, value
);
200 void gpio_config_table(const struct tegra_gpio_config
*config
, int len
)
204 for (i
= 0; i
< len
; i
++) {
205 switch (config
[i
].init
) {
206 case TEGRA_GPIO_INIT_IN
:
207 set_direction(config
[i
].gpio
, DIRECTION_INPUT
);
209 case TEGRA_GPIO_INIT_OUT0
:
210 set_level(config
[i
].gpio
, 0);
211 set_direction(config
[i
].gpio
, DIRECTION_OUTPUT
);
213 case TEGRA_GPIO_INIT_OUT1
:
214 set_level(config
[i
].gpio
, 1);
215 set_direction(config
[i
].gpio
, DIRECTION_OUTPUT
);
218 set_config(config
[i
].gpio
, CONFIG_GPIO
);
222 static int tegra_gpio_get_function(struct udevice
*dev
, unsigned offset
)
224 struct tegra_port_info
*state
= dev_get_priv(dev
);
225 int gpio
= state
->base_gpio
+ offset
;
227 if (!get_config(gpio
))
229 else if (get_direction(gpio
))
235 static int tegra_gpio_xlate(struct udevice
*dev
, struct gpio_desc
*desc
,
236 struct ofnode_phandle_args
*args
)
240 gpio
= args
->args
[0];
241 port
= gpio
/ TEGRA_GPIOS_PER_PORT
;
242 ret
= device_get_child(dev
, port
, &desc
->dev
);
245 desc
->offset
= gpio
% TEGRA_GPIOS_PER_PORT
;
246 desc
->flags
= args
->args
[1] & GPIO_ACTIVE_LOW
? GPIOD_ACTIVE_LOW
: 0;
251 static const struct dm_gpio_ops gpio_tegra_ops
= {
252 .direction_input
= tegra_gpio_direction_input
,
253 .direction_output
= tegra_gpio_direction_output
,
254 .get_value
= tegra_gpio_get_value
,
255 .set_value
= tegra_gpio_set_value
,
256 .get_function
= tegra_gpio_get_function
,
257 .xlate
= tegra_gpio_xlate
,
261 * Returns the name of a GPIO port
263 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
265 * @base_port: Base port number (0, 1..n-1)
266 * @return allocated string containing the name
268 static char *gpio_port_name(int base_port
)
275 *s
++ = 'A' + (base_port
% 26);
284 static const struct udevice_id tegra_gpio_ids
[] = {
285 { .compatible
= "nvidia,tegra30-gpio" },
286 { .compatible
= "nvidia,tegra20-gpio" },
290 static int gpio_tegra_probe(struct udevice
*dev
)
292 struct gpio_dev_priv
*uc_priv
= dev_get_uclass_priv(dev
);
293 struct tegra_port_info
*priv
= dev
->priv
;
294 struct tegra_gpio_platdata
*plat
= dev
->platdata
;
296 /* Only child devices have ports */
300 priv
->bank
= plat
->bank
;
301 priv
->base_gpio
= plat
->base_gpio
;
303 uc_priv
->gpio_count
= TEGRA_GPIOS_PER_PORT
;
304 uc_priv
->bank_name
= plat
->port_name
;
310 * We have a top-level GPIO device with no actual GPIOs. It has a child
311 * device for each Tegra port.
313 static int gpio_tegra_bind(struct udevice
*parent
)
315 struct tegra_gpio_platdata
*plat
= parent
->platdata
;
316 struct gpio_ctlr
*ctlr
;
321 /* If this is a child device, there is nothing to do here */
325 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
326 #ifdef CONFIG_SPL_BUILD
327 ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
328 bank_count
= TEGRA_GPIO_BANKS
;
334 * This driver does not make use of interrupts, other than to figure
335 * out the number of GPIO banks
337 len
= dev_read_size(parent
, "interrupts");
340 bank_count
= len
/ 3 / sizeof(u32
);
341 ctlr
= (struct gpio_ctlr
*)dev_read_addr(parent
);
342 if ((ulong
)ctlr
== FDT_ADDR_T_NONE
)
346 for (bank
= 0; bank
< bank_count
; bank
++) {
349 for (port
= 0; port
< TEGRA_PORTS_PER_BANK
; port
++) {
350 struct tegra_gpio_platdata
*plat
;
354 plat
= calloc(1, sizeof(*plat
));
357 plat
->bank
= &ctlr
->gpio_bank
[bank
];
358 base_port
= bank
* TEGRA_PORTS_PER_BANK
+ port
;
359 plat
->base_gpio
= TEGRA_GPIOS_PER_PORT
* base_port
;
360 plat
->port_name
= gpio_port_name(base_port
);
362 ret
= device_bind(parent
, parent
->driver
,
363 plat
->port_name
, plat
, -1, &dev
);
366 dev_set_of_offset(dev
, dev_of_offset(parent
));
373 U_BOOT_DRIVER(gpio_tegra
) = {
374 .name
= "gpio_tegra",
376 .of_match
= tegra_gpio_ids
,
377 .bind
= gpio_tegra_bind
,
378 .probe
= gpio_tegra_probe
,
379 .priv_auto_alloc_size
= sizeof(struct tegra_port_info
),
380 .ops
= &gpio_tegra_ops
,