drivers/gpio/tegra_gpio.c

   1 /*
   2  * NVIDIA Tegra20 GPIO handling.
   3  *  (C) Copyright 2010-2012
   4  *  NVIDIA Corporation <www.nvidia.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
  11  * Tom Warren (twarren@nvidia.com)
  12  */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <malloc.h>
  17 #include <errno.h>
  18 #include <fdtdec.h>
  19 #include <asm/io.h>
  20 #include <asm/bitops.h>
  21 #include <asm/arch/tegra.h>
  22 #include <asm/gpio.h>
  23 #include <dm/device-internal.h>
  24 #include <dt-bindings/gpio/gpio.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 enum {
  29         TEGRA_CMD_INFO,
  30         TEGRA_CMD_PORT,
  31         TEGRA_CMD_OUTPUT,
  32         TEGRA_CMD_INPUT,
  33 };
  34
  35 struct tegra_gpio_platdata {
  36         struct gpio_ctlr_bank *bank;
  37         const char *port_name;  /* Name of port, e.g. "B" */
  38         int base_gpio;          /* Port number for this port (0, 1,.., n-1) */
  39 };
  40
  41 /* Information about each port at run-time */
  42 struct tegra_port_info {
  43         struct gpio_ctlr_bank *bank;
  44         int base_gpio;          /* Port number for this port (0, 1,.., n-1) */
  45 };
  46
  47 /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
  48 static int get_config(unsigned gpio)
  49 {
  50         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  51         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  52         u32 u;
  53         int type;
  54
  55         u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
  56         type =  (u >> GPIO_BIT(gpio)) & 1;
  57
  58         debug("get_config: port = %d, bit = %d is %s\n",
  59                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
  60
  61         return type;
  62 }
  63
  64 /* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
  65 static void set_config(unsigned gpio, int type)
  66 {
  67         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  68         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  69         u32 u;
  70
  71         debug("set_config: port = %d, bit = %d, %s\n",
  72                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
  73
  74         u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
  75         if (type)                               /* GPIO */
  76                 u |= 1 << GPIO_BIT(gpio);
  77         else
  78                 u &= ~(1 << GPIO_BIT(gpio));
  79         writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
  80 }
  81
  82 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
  83 static int get_direction(unsigned gpio)
  84 {
  85         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  86         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  87         u32 u;
  88         int dir;
  89
  90         u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
  91         dir =  (u >> GPIO_BIT(gpio)) & 1;
  92
  93         debug("get_direction: port = %d, bit = %d, %s\n",
  94                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
  95
  96         return dir;
  97 }
  98
  99 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
 100 static void set_direction(unsigned gpio, int output)
 101 {
 102         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
 103         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
 104         u32 u;
 105
 106         debug("set_direction: port = %d, bit = %d, %s\n",
 107                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
 108
 109         u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
 110         if (output)
 111                 u |= 1 << GPIO_BIT(gpio);
 112         else
 113                 u &= ~(1 << GPIO_BIT(gpio));
 114         writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
 115 }
 116
 117 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
 118 static void set_level(unsigned gpio, int high)
 119 {
 120         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
 121         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
 122         u32 u;
 123
 124         debug("set_level: port = %d, bit %d == %d\n",
 125                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
 126
 127         u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
 128         if (high)
 129                 u |= 1 << GPIO_BIT(gpio);
 130         else
 131                 u &= ~(1 << GPIO_BIT(gpio));
 132         writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
 133 }
 134
 135 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
 136 int tegra_spl_gpio_direction_output(int gpio, int value)
 137 {
 138         /* Configure as a GPIO */
 139         set_config(gpio, 1);
 140
 141         /* Configure GPIO output value. */
 142         set_level(gpio, value);
 143
 144         /* Configure GPIO direction as output. */
 145         set_direction(gpio, 1);
 146
 147         return 0;
 148 }
 149
 150 /*
 151  * Generic_GPIO primitives.
 152  */
 153
 154 static int tegra_gpio_request(struct udevice *dev, unsigned offset,
 155                               const char *label)
 156 {
 157         struct tegra_port_info *state = dev_get_priv(dev);
 158
 159         /* Configure as a GPIO */
 160         set_config(state->base_gpio + offset, 1);
 161
 162         return 0;
 163 }
 164
 165 /* set GPIO pin 'gpio' as an input */
 166 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
 167 {
 168         struct tegra_port_info *state = dev_get_priv(dev);
 169
 170         /* Configure GPIO direction as input. */
 171         set_direction(state->base_gpio + offset, 0);
 172
 173         return 0;
 174 }
 175
 176 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
 177 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
 178                                        int value)
 179 {
 180         struct tegra_port_info *state = dev_get_priv(dev);
 181         int gpio = state->base_gpio + offset;
 182
 183         /* Configure GPIO output value. */
 184         set_level(gpio, value);
 185
 186         /* Configure GPIO direction as output. */
 187         set_direction(gpio, 1);
 188
 189         return 0;
 190 }
 191
 192 /* read GPIO IN value of pin 'gpio' */
 193 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
 194 {
 195         struct tegra_port_info *state = dev_get_priv(dev);
 196         int gpio = state->base_gpio + offset;
 197         int val;
 198
 199         debug("%s: pin = %d (port %d:bit %d)\n", __func__,
 200               gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
 201
 202         val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
 203
 204         return (val >> GPIO_BIT(gpio)) & 1;
 205 }
 206
 207 /* write GPIO OUT value to pin 'gpio' */
 208 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 209 {
 210         struct tegra_port_info *state = dev_get_priv(dev);
 211         int gpio = state->base_gpio + offset;
 212
 213         debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
 214               gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
 215
 216         /* Configure GPIO output value. */
 217         set_level(gpio, value);
 218
 219         return 0;
 220 }
 221
 222 void gpio_config_table(const struct tegra_gpio_config *config, int len)
 223 {
 224         int i;
 225
 226         for (i = 0; i < len; i++) {
 227                 switch (config[i].init) {
 228                 case TEGRA_GPIO_INIT_IN:
 229                         gpio_direction_input(config[i].gpio);
 230                         break;
 231                 case TEGRA_GPIO_INIT_OUT0:
 232                         gpio_direction_output(config[i].gpio, 0);
 233                         break;
 234                 case TEGRA_GPIO_INIT_OUT1:
 235                         gpio_direction_output(config[i].gpio, 1);
 236                         break;
 237                 }
 238                 set_config(config[i].gpio, 1);
 239         }
 240 }
 241
 242 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
 243 {
 244         struct tegra_port_info *state = dev_get_priv(dev);
 245         int gpio = state->base_gpio + offset;
 246
 247         if (!get_config(gpio))
 248                 return GPIOF_FUNC;
 249         else if (get_direction(gpio))
 250                 return GPIOF_OUTPUT;
 251         else
 252                 return GPIOF_INPUT;
 253 }
 254
 255 static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
 256                             struct fdtdec_phandle_args *args)
 257 {
 258         int gpio, port, ret;
 259
 260         gpio = args->args[0];
 261         port = gpio / TEGRA_GPIOS_PER_PORT;
 262         ret = device_get_child(dev, port, &desc->dev);
 263         if (ret)
 264                 return ret;
 265         desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
 266         desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
 267
 268         return 0;
 269 }
 270
 271 static const struct dm_gpio_ops gpio_tegra_ops = {
 272         .request                = tegra_gpio_request,
 273         .direction_input        = tegra_gpio_direction_input,
 274         .direction_output       = tegra_gpio_direction_output,
 275         .get_value              = tegra_gpio_get_value,
 276         .set_value              = tegra_gpio_set_value,
 277         .get_function           = tegra_gpio_get_function,
 278         .xlate                  = tegra_gpio_xlate,
 279 };
 280
 281 /**
 282  * Returns the name of a GPIO port
 283  *
 284  * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
 285  *
 286  * @base_port: Base port number (0, 1..n-1)
 287  * @return allocated string containing the name
 288  */
 289 static char *gpio_port_name(int base_port)
 290 {
 291         char *name, *s;
 292
 293         name = malloc(3);
 294         if (name) {
 295                 s = name;
 296                 *s++ = 'A' + (base_port % 26);
 297                 if (base_port >= 26)
 298                         *s++ = *name;
 299                 *s = '\0';
 300         }
 301
 302         return name;
 303 }
 304
 305 static const struct udevice_id tegra_gpio_ids[] = {
 306         { .compatible = "nvidia,tegra30-gpio" },
 307         { .compatible = "nvidia,tegra20-gpio" },
 308         { }
 309 };
 310
 311 static int gpio_tegra_probe(struct udevice *dev)
 312 {
 313         struct gpio_dev_priv *uc_priv = dev->uclass_priv;
 314         struct tegra_port_info *priv = dev->priv;
 315         struct tegra_gpio_platdata *plat = dev->platdata;
 316
 317         /* Only child devices have ports */
 318         if (!plat)
 319                 return 0;
 320
 321         priv->bank = plat->bank;
 322         priv->base_gpio = plat->base_gpio;
 323
 324         uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
 325         uc_priv->bank_name = plat->port_name;
 326
 327         return 0;
 328 }
 329
 330 /**
 331  * We have a top-level GPIO device with no actual GPIOs. It has a child
 332  * device for each Tegra port.
 333  */
 334 static int gpio_tegra_bind(struct udevice *parent)
 335 {
 336         struct tegra_gpio_platdata *plat = parent->platdata;
 337         struct gpio_ctlr *ctlr;
 338         int bank_count;
 339         int bank;
 340         int ret;
 341         int len;
 342
 343         /* If this is a child device, there is nothing to do here */
 344         if (plat)
 345                 return 0;
 346
 347         /*
 348          * This driver does not make use of interrupts, other than to figure
 349          * out the number of GPIO banks
 350          */
 351         if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
 352                 return -EINVAL;
 353         bank_count = len / 3 / sizeof(u32);
 354         ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob,
 355                                                    parent->of_offset, "reg");
 356         for (bank = 0; bank < bank_count; bank++) {
 357                 int port;
 358
 359                 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
 360                         struct tegra_gpio_platdata *plat;
 361                         struct udevice *dev;
 362                         int base_port;
 363
 364                         plat = calloc(1, sizeof(*plat));
 365                         if (!plat)
 366                                 return -ENOMEM;
 367                         plat->bank = &ctlr->gpio_bank[bank];
 368                         base_port = bank * TEGRA_PORTS_PER_BANK + port;
 369                         plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
 370                         plat->port_name = gpio_port_name(base_port);
 371
 372                         ret = device_bind(parent, parent->driver,
 373                                           plat->port_name, plat, -1, &dev);
 374                         if (ret)
 375                                 return ret;
 376                         dev->of_offset = parent->of_offset;
 377                 }
 378         }
 379
 380         return 0;
 381 }
 382
 383 U_BOOT_DRIVER(gpio_tegra) = {
 384         .name   = "gpio_tegra",
 385         .id     = UCLASS_GPIO,
 386         .of_match = tegra_gpio_ids,
 387         .bind   = gpio_tegra_bind,
 388         .probe = gpio_tegra_probe,
 389         .priv_auto_alloc_size = sizeof(struct tegra_port_info),
 390         .ops    = &gpio_tegra_ops,
 391 };