2 * NVIDIA Tegra20 GPIO handling.
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
11 * Tom Warren (twarren@nvidia.com)
20 #include <asm/bitops.h>
21 #include <asm/arch/tegra.h>
23 #include <dm/device-internal.h>
24 #include <dt-bindings/gpio/gpio.h>
26 DECLARE_GLOBAL_DATA_PTR
;
35 struct tegra_gpio_platdata
{
36 struct gpio_ctlr_bank
*bank
;
37 const char *port_name
; /* Name of port, e.g. "B" */
38 int base_gpio
; /* Port number for this port (0, 1,.., n-1) */
41 /* Information about each port at run-time */
42 struct tegra_port_info
{
43 struct gpio_ctlr_bank
*bank
;
44 int base_gpio
; /* Port number for this port (0, 1,.., n-1) */
47 /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
48 static int get_config(unsigned gpio
)
50 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
51 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
55 u
= readl(&bank
->gpio_config
[GPIO_PORT(gpio
)]);
56 type
= (u
>> GPIO_BIT(gpio
)) & 1;
58 debug("get_config: port = %d, bit = %d is %s\n",
59 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), type
? "GPIO" : "SFPIO");
64 /* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
65 static void set_config(unsigned gpio
, int type
)
67 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
68 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
71 debug("set_config: port = %d, bit = %d, %s\n",
72 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), type
? "GPIO" : "SFPIO");
74 u
= readl(&bank
->gpio_config
[GPIO_PORT(gpio
)]);
76 u
|= 1 << GPIO_BIT(gpio
);
78 u
&= ~(1 << GPIO_BIT(gpio
));
79 writel(u
, &bank
->gpio_config
[GPIO_PORT(gpio
)]);
82 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
83 static int get_direction(unsigned gpio
)
85 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
86 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
90 u
= readl(&bank
->gpio_dir_out
[GPIO_PORT(gpio
)]);
91 dir
= (u
>> GPIO_BIT(gpio
)) & 1;
93 debug("get_direction: port = %d, bit = %d, %s\n",
94 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), dir
? "OUT" : "IN");
99 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
100 static void set_direction(unsigned gpio
, int output
)
102 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
103 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
106 debug("set_direction: port = %d, bit = %d, %s\n",
107 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), output
? "OUT" : "IN");
109 u
= readl(&bank
->gpio_dir_out
[GPIO_PORT(gpio
)]);
111 u
|= 1 << GPIO_BIT(gpio
);
113 u
&= ~(1 << GPIO_BIT(gpio
));
114 writel(u
, &bank
->gpio_dir_out
[GPIO_PORT(gpio
)]);
117 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
118 static void set_level(unsigned gpio
, int high
)
120 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
121 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
124 debug("set_level: port = %d, bit %d == %d\n",
125 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), high
);
127 u
= readl(&bank
->gpio_out
[GPIO_PORT(gpio
)]);
129 u
|= 1 << GPIO_BIT(gpio
);
131 u
&= ~(1 << GPIO_BIT(gpio
));
132 writel(u
, &bank
->gpio_out
[GPIO_PORT(gpio
)]);
136 * Generic_GPIO primitives.
139 static int tegra_gpio_request(struct udevice
*dev
, unsigned offset
,
142 struct tegra_port_info
*state
= dev_get_priv(dev
);
144 /* Configure as a GPIO */
145 set_config(state
->base_gpio
+ offset
, 1);
150 /* set GPIO pin 'gpio' as an input */
151 static int tegra_gpio_direction_input(struct udevice
*dev
, unsigned offset
)
153 struct tegra_port_info
*state
= dev_get_priv(dev
);
155 /* Configure GPIO direction as input. */
156 set_direction(state
->base_gpio
+ offset
, 0);
161 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
162 static int tegra_gpio_direction_output(struct udevice
*dev
, unsigned offset
,
165 struct tegra_port_info
*state
= dev_get_priv(dev
);
166 int gpio
= state
->base_gpio
+ offset
;
168 /* Configure GPIO output value. */
169 set_level(gpio
, value
);
171 /* Configure GPIO direction as output. */
172 set_direction(gpio
, 1);
177 /* read GPIO IN value of pin 'gpio' */
178 static int tegra_gpio_get_value(struct udevice
*dev
, unsigned offset
)
180 struct tegra_port_info
*state
= dev_get_priv(dev
);
181 int gpio
= state
->base_gpio
+ offset
;
184 debug("%s: pin = %d (port %d:bit %d)\n", __func__
,
185 gpio
, GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
));
187 val
= readl(&state
->bank
->gpio_in
[GPIO_PORT(gpio
)]);
189 return (val
>> GPIO_BIT(gpio
)) & 1;
192 /* write GPIO OUT value to pin 'gpio' */
193 static int tegra_gpio_set_value(struct udevice
*dev
, unsigned offset
, int value
)
195 struct tegra_port_info
*state
= dev_get_priv(dev
);
196 int gpio
= state
->base_gpio
+ offset
;
198 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
199 gpio
, GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), value
);
201 /* Configure GPIO output value. */
202 set_level(gpio
, value
);
207 void gpio_config_table(const struct tegra_gpio_config
*config
, int len
)
211 for (i
= 0; i
< len
; i
++) {
212 switch (config
[i
].init
) {
213 case TEGRA_GPIO_INIT_IN
:
214 gpio_direction_input(config
[i
].gpio
);
216 case TEGRA_GPIO_INIT_OUT0
:
217 gpio_direction_output(config
[i
].gpio
, 0);
219 case TEGRA_GPIO_INIT_OUT1
:
220 gpio_direction_output(config
[i
].gpio
, 1);
223 set_config(config
[i
].gpio
, 1);
227 static int tegra_gpio_get_function(struct udevice
*dev
, unsigned offset
)
229 struct tegra_port_info
*state
= dev_get_priv(dev
);
230 int gpio
= state
->base_gpio
+ offset
;
232 if (!get_config(gpio
))
234 else if (get_direction(gpio
))
240 static int tegra_gpio_xlate(struct udevice
*dev
, struct gpio_desc
*desc
,
241 struct fdtdec_phandle_args
*args
)
245 gpio
= args
->args
[0];
246 port
= gpio
/ TEGRA_GPIOS_PER_PORT
;
247 ret
= device_get_child(dev
, port
, &desc
->dev
);
250 desc
->offset
= gpio
% TEGRA_GPIOS_PER_PORT
;
251 desc
->flags
= args
->args
[1] & GPIO_ACTIVE_LOW
? GPIOD_ACTIVE_LOW
: 0;
256 static const struct dm_gpio_ops gpio_tegra_ops
= {
257 .request
= tegra_gpio_request
,
258 .direction_input
= tegra_gpio_direction_input
,
259 .direction_output
= tegra_gpio_direction_output
,
260 .get_value
= tegra_gpio_get_value
,
261 .set_value
= tegra_gpio_set_value
,
262 .get_function
= tegra_gpio_get_function
,
263 .xlate
= tegra_gpio_xlate
,
267 * Returns the name of a GPIO port
269 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
271 * @base_port: Base port number (0, 1..n-1)
272 * @return allocated string containing the name
274 static char *gpio_port_name(int base_port
)
281 *s
++ = 'A' + (base_port
% 26);
290 static const struct udevice_id tegra_gpio_ids
[] = {
291 { .compatible
= "nvidia,tegra30-gpio" },
292 { .compatible
= "nvidia,tegra20-gpio" },
296 static int gpio_tegra_probe(struct udevice
*dev
)
298 struct gpio_dev_priv
*uc_priv
= dev
->uclass_priv
;
299 struct tegra_port_info
*priv
= dev
->priv
;
300 struct tegra_gpio_platdata
*plat
= dev
->platdata
;
302 /* Only child devices have ports */
306 priv
->bank
= plat
->bank
;
307 priv
->base_gpio
= plat
->base_gpio
;
309 uc_priv
->gpio_count
= TEGRA_GPIOS_PER_PORT
;
310 uc_priv
->bank_name
= plat
->port_name
;
316 * We have a top-level GPIO device with no actual GPIOs. It has a child
317 * device for each Tegra port.
319 static int gpio_tegra_bind(struct udevice
*parent
)
321 struct tegra_gpio_platdata
*plat
= parent
->platdata
;
322 struct gpio_ctlr
*ctlr
;
327 /* If this is a child device, there is nothing to do here */
331 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
332 #ifdef CONFIG_SPL_BUILD
333 ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
334 bank_count
= TEGRA_GPIO_BANKS
;
340 * This driver does not make use of interrupts, other than to figure
341 * out the number of GPIO banks
343 if (!fdt_getprop(gd
->fdt_blob
, parent
->of_offset
, "interrupts", &len
))
345 bank_count
= len
/ 3 / sizeof(u32
);
346 ctlr
= (struct gpio_ctlr
*)fdtdec_get_addr(gd
->fdt_blob
,
347 parent
->of_offset
, "reg");
350 for (bank
= 0; bank
< bank_count
; bank
++) {
353 for (port
= 0; port
< TEGRA_PORTS_PER_BANK
; port
++) {
354 struct tegra_gpio_platdata
*plat
;
358 plat
= calloc(1, sizeof(*plat
));
361 plat
->bank
= &ctlr
->gpio_bank
[bank
];
362 base_port
= bank
* TEGRA_PORTS_PER_BANK
+ port
;
363 plat
->base_gpio
= TEGRA_GPIOS_PER_PORT
* base_port
;
364 plat
->port_name
= gpio_port_name(base_port
);
366 ret
= device_bind(parent
, parent
->driver
,
367 plat
->port_name
, plat
, -1, &dev
);
370 dev
->of_offset
= parent
->of_offset
;
377 U_BOOT_DRIVER(gpio_tegra
) = {
378 .name
= "gpio_tegra",
380 .of_match
= tegra_gpio_ids
,
381 .bind
= gpio_tegra_bind
,
382 .probe
= gpio_tegra_probe
,
383 .priv_auto_alloc_size
= sizeof(struct tegra_port_info
),
384 .ops
= &gpio_tegra_ops
,
385 .flags
= DM_FLAG_PRE_RELOC
,