drivers/gpu/drm/amd/amdgpu/amdgpu.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __AMDGPU_H__
  29 #define __AMDGPU_H__
  30
  31 #include "amdgpu_ctx.h"
  32
  33 #include <linux/atomic.h>
  34 #include <linux/wait.h>
  35 #include <linux/list.h>
  36 #include <linux/kref.h>
  37 #include <linux/rbtree.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/dma-fence.h>
  40
  41 #include <drm/ttm/ttm_bo_api.h>
  42 #include <drm/ttm/ttm_bo_driver.h>
  43 #include <drm/ttm/ttm_placement.h>
  44 #include <drm/ttm/ttm_module.h>
  45 #include <drm/ttm/ttm_execbuf_util.h>
  46
  47 #include <drm/amdgpu_drm.h>
  48 #include <drm/drm_gem.h>
  49 #include <drm/drm_ioctl.h>
  50 #include <drm/gpu_scheduler.h>
  51
  52 #include <kgd_kfd_interface.h>
  53 #include "dm_pp_interface.h"
  54 #include "kgd_pp_interface.h"
  55
  56 #include "amd_shared.h"
  57 #include "amdgpu_mode.h"
  58 #include "amdgpu_ih.h"
  59 #include "amdgpu_irq.h"
  60 #include "amdgpu_ucode.h"
  61 #include "amdgpu_ttm.h"
  62 #include "amdgpu_psp.h"
  63 #include "amdgpu_gds.h"
  64 #include "amdgpu_sync.h"
  65 #include "amdgpu_ring.h"
  66 #include "amdgpu_vm.h"
  67 #include "amdgpu_dpm.h"
  68 #include "amdgpu_acp.h"
  69 #include "amdgpu_uvd.h"
  70 #include "amdgpu_vce.h"
  71 #include "amdgpu_vcn.h"
  72 #include "amdgpu_jpeg.h"
  73 #include "amdgpu_mn.h"
  74 #include "amdgpu_gmc.h"
  75 #include "amdgpu_gfx.h"
  76 #include "amdgpu_sdma.h"
  77 #include "amdgpu_nbio.h"
  78 #include "amdgpu_dm.h"
  79 #include "amdgpu_virt.h"
  80 #include "amdgpu_csa.h"
  81 #include "amdgpu_gart.h"
  82 #include "amdgpu_debugfs.h"
  83 #include "amdgpu_job.h"
  84 #include "amdgpu_bo_list.h"
  85 #include "amdgpu_gem.h"
  86 #include "amdgpu_doorbell.h"
  87 #include "amdgpu_amdkfd.h"
  88 #include "amdgpu_smu.h"
  89 #include "amdgpu_discovery.h"
  90 #include "amdgpu_mes.h"
  91 #include "amdgpu_umc.h"
  92 #include "amdgpu_mmhub.h"
  93
  94 #define MAX_GPU_INSTANCE                16
  95
  96 struct amdgpu_gpu_instance
  97 {
  98         struct amdgpu_device            *adev;
  99         int                             mgpu_fan_enabled;
 100 };
 101
 102 struct amdgpu_mgpu_info
 103 {
 104         struct amdgpu_gpu_instance      gpu_ins[MAX_GPU_INSTANCE];
 105         struct mutex                    mutex;
 106         uint32_t                        num_gpu;
 107         uint32_t                        num_dgpu;
 108         uint32_t                        num_apu;
 109 };
 110
 111 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
 112
 113 /*
 114  * Modules parameters.
 115  */
 116 extern int amdgpu_modeset;
 117 extern int amdgpu_vram_limit;
 118 extern int amdgpu_vis_vram_limit;
 119 extern int amdgpu_gart_size;
 120 extern int amdgpu_gtt_size;
 121 extern int amdgpu_moverate;
 122 extern int amdgpu_benchmarking;
 123 extern int amdgpu_testing;
 124 extern int amdgpu_audio;
 125 extern int amdgpu_disp_priority;
 126 extern int amdgpu_hw_i2c;
 127 extern int amdgpu_pcie_gen2;
 128 extern int amdgpu_msi;
 129 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
 130 extern int amdgpu_dpm;
 131 extern int amdgpu_fw_load_type;
 132 extern int amdgpu_aspm;
 133 extern int amdgpu_runtime_pm;
 134 extern uint amdgpu_ip_block_mask;
 135 extern int amdgpu_bapm;
 136 extern int amdgpu_deep_color;
 137 extern int amdgpu_vm_size;
 138 extern int amdgpu_vm_block_size;
 139 extern int amdgpu_vm_fragment_size;
 140 extern int amdgpu_vm_fault_stop;
 141 extern int amdgpu_vm_debug;
 142 extern int amdgpu_vm_update_mode;
 143 extern int amdgpu_exp_hw_support;
 144 extern int amdgpu_dc;
 145 extern int amdgpu_sched_jobs;
 146 extern int amdgpu_sched_hw_submission;
 147 extern uint amdgpu_pcie_gen_cap;
 148 extern uint amdgpu_pcie_lane_cap;
 149 extern uint amdgpu_cg_mask;
 150 extern uint amdgpu_pg_mask;
 151 extern uint amdgpu_sdma_phase_quantum;
 152 extern char *amdgpu_disable_cu;
 153 extern char *amdgpu_virtual_display;
 154 extern uint amdgpu_pp_feature_mask;
 155 extern uint amdgpu_force_long_training;
 156 extern int amdgpu_job_hang_limit;
 157 extern int amdgpu_lbpw;
 158 extern int amdgpu_compute_multipipe;
 159 extern int amdgpu_gpu_recovery;
 160 extern int amdgpu_emu_mode;
 161 extern uint amdgpu_smu_memory_pool_size;
 162 extern uint amdgpu_dc_feature_mask;
 163 extern uint amdgpu_dm_abm_level;
 164 extern struct amdgpu_mgpu_info mgpu_info;
 165 extern int amdgpu_ras_enable;
 166 extern uint amdgpu_ras_mask;
 167 extern int amdgpu_async_gfx_ring;
 168 extern int amdgpu_mcbp;
 169 extern int amdgpu_discovery;
 170 extern int amdgpu_mes;
 171 extern int amdgpu_noretry;
 172 extern int amdgpu_force_asic_type;
 173 #ifdef CONFIG_HSA_AMD
 174 extern int sched_policy;
 175 #else
 176 static const int sched_policy = KFD_SCHED_POLICY_HWS;
 177 #endif
 178
 179 #ifdef CONFIG_DRM_AMDGPU_SI
 180 extern int amdgpu_si_support;
 181 #endif
 182 #ifdef CONFIG_DRM_AMDGPU_CIK
 183 extern int amdgpu_cik_support;
 184 #endif
 185
 186 #define AMDGPU_VM_MAX_NUM_CTX                   4096
 187 #define AMDGPU_SG_THRESHOLD                     (256*1024*1024)
 188 #define AMDGPU_DEFAULT_GTT_SIZE_MB              3072ULL /* 3GB by default */
 189 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS          3000
 190 #define AMDGPU_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 191 #define AMDGPU_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 192 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
 193 #define AMDGPU_IB_POOL_SIZE                     16
 194 #define AMDGPU_DEBUGFS_MAX_COMPONENTS           32
 195 #define AMDGPUFB_CONN_LIMIT                     4
 196 #define AMDGPU_BIOS_NUM_SCRATCH                 16
 197
 198 /* hard reset data */
 199 #define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
 200
 201 /* reset flags */
 202 #define AMDGPU_RESET_GFX                        (1 << 0)
 203 #define AMDGPU_RESET_COMPUTE                    (1 << 1)
 204 #define AMDGPU_RESET_DMA                        (1 << 2)
 205 #define AMDGPU_RESET_CP                         (1 << 3)
 206 #define AMDGPU_RESET_GRBM                       (1 << 4)
 207 #define AMDGPU_RESET_DMA1                       (1 << 5)
 208 #define AMDGPU_RESET_RLC                        (1 << 6)
 209 #define AMDGPU_RESET_SEM                        (1 << 7)
 210 #define AMDGPU_RESET_IH                         (1 << 8)
 211 #define AMDGPU_RESET_VMC                        (1 << 9)
 212 #define AMDGPU_RESET_MC                         (1 << 10)
 213 #define AMDGPU_RESET_DISPLAY                    (1 << 11)
 214 #define AMDGPU_RESET_UVD                        (1 << 12)
 215 #define AMDGPU_RESET_VCE                        (1 << 13)
 216 #define AMDGPU_RESET_VCE1                       (1 << 14)
 217
 218 /* max cursor sizes (in pixels) */
 219 #define CIK_CURSOR_WIDTH 128
 220 #define CIK_CURSOR_HEIGHT 128
 221
 222 struct amdgpu_device;
 223 struct amdgpu_ib;
 224 struct amdgpu_cs_parser;
 225 struct amdgpu_job;
 226 struct amdgpu_irq_src;
 227 struct amdgpu_fpriv;
 228 struct amdgpu_bo_va_mapping;
 229 struct amdgpu_atif;
 230 struct kfd_vm_fault_info;
 231
 232 enum amdgpu_cp_irq {
 233         AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
 234         AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
 235         AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
 236         AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
 237         AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
 238         AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
 239         AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
 240         AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
 241         AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
 242         AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
 243
 244         AMDGPU_CP_IRQ_LAST
 245 };
 246
 247 enum amdgpu_thermal_irq {
 248         AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
 249         AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
 250
 251         AMDGPU_THERMAL_IRQ_LAST
 252 };
 253
 254 enum amdgpu_kiq_irq {
 255         AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
 256         AMDGPU_CP_KIQ_IRQ_LAST
 257 };
 258
 259 #define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */
 260 #define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */
 261 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
 262
 263 int amdgpu_device_ip_set_clockgating_state(void *dev,
 264                                            enum amd_ip_block_type block_type,
 265                                            enum amd_clockgating_state state);
 266 int amdgpu_device_ip_set_powergating_state(void *dev,
 267                                            enum amd_ip_block_type block_type,
 268                                            enum amd_powergating_state state);
 269 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
 270                                             u32 *flags);
 271 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
 272                                    enum amd_ip_block_type block_type);
 273 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
 274                               enum amd_ip_block_type block_type);
 275
 276 #define AMDGPU_MAX_IP_NUM 16
 277
 278 struct amdgpu_ip_block_status {
 279         bool valid;
 280         bool sw;
 281         bool hw;
 282         bool late_initialized;
 283         bool hang;
 284 };
 285
 286 struct amdgpu_ip_block_version {
 287         const enum amd_ip_block_type type;
 288         const u32 major;
 289         const u32 minor;
 290         const u32 rev;
 291         const struct amd_ip_funcs *funcs;
 292 };
 293
 294 #define HW_REV(_Major, _Minor, _Rev) \
 295         ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
 296
 297 struct amdgpu_ip_block {
 298         struct amdgpu_ip_block_status status;
 299         const struct amdgpu_ip_block_version *version;
 300 };
 301
 302 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
 303                                        enum amd_ip_block_type type,
 304                                        u32 major, u32 minor);
 305
 306 struct amdgpu_ip_block *
 307 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
 308                               enum amd_ip_block_type type);
 309
 310 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
 311                                const struct amdgpu_ip_block_version *ip_block_version);
 312
 313 /*
 314  * BIOS.
 315  */
 316 bool amdgpu_get_bios(struct amdgpu_device *adev);
 317 bool amdgpu_read_bios(struct amdgpu_device *adev);
 318
 319 /*
 320  * Clocks
 321  */
 322
 323 #define AMDGPU_MAX_PPLL 3
 324
 325 struct amdgpu_clock {
 326         struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
 327         struct amdgpu_pll spll;
 328         struct amdgpu_pll mpll;
 329         /* 10 Khz units */
 330         uint32_t default_mclk;
 331         uint32_t default_sclk;
 332         uint32_t default_dispclk;
 333         uint32_t current_dispclk;
 334         uint32_t dp_extclk;
 335         uint32_t max_pixel_clock;
 336 };
 337
 338 /* sub-allocation manager, it has to be protected by another lock.
 339  * By conception this is an helper for other part of the driver
 340  * like the indirect buffer or semaphore, which both have their
 341  * locking.
 342  *
 343  * Principe is simple, we keep a list of sub allocation in offset
 344  * order (first entry has offset == 0, last entry has the highest
 345  * offset).
 346  *
 347  * When allocating new object we first check if there is room at
 348  * the end total_size - (last_object_offset + last_object_size) >=
 349  * alloc_size. If so we allocate new object there.
 350  *
 351  * When there is not enough room at the end, we start waiting for
 352  * each sub object until we reach object_offset+object_size >=
 353  * alloc_size, this object then become the sub object we return.
 354  *
 355  * Alignment can't be bigger than page size.
 356  *
 357  * Hole are not considered for allocation to keep things simple.
 358  * Assumption is that there won't be hole (all object on same
 359  * alignment).
 360  */
 361
 362 #define AMDGPU_SA_NUM_FENCE_LISTS       32
 363
 364 struct amdgpu_sa_manager {
 365         wait_queue_head_t       wq;
 366         struct amdgpu_bo        *bo;
 367         struct list_head        *hole;
 368         struct list_head        flist[AMDGPU_SA_NUM_FENCE_LISTS];
 369         struct list_head        olist;
 370         unsigned                size;
 371         uint64_t                gpu_addr;
 372         void                    *cpu_ptr;
 373         uint32_t                domain;
 374         uint32_t                align;
 375 };
 376
 377 /* sub-allocation buffer */
 378 struct amdgpu_sa_bo {
 379         struct list_head                olist;
 380         struct list_head                flist;
 381         struct amdgpu_sa_manager        *manager;
 382         unsigned                        soffset;
 383         unsigned                        eoffset;
 384         struct dma_fence                *fence;
 385 };
 386
 387 int amdgpu_fence_slab_init(void);
 388 void amdgpu_fence_slab_fini(void);
 389
 390 /*
 391  * IRQS.
 392  */
 393
 394 struct amdgpu_flip_work {
 395         struct delayed_work             flip_work;
 396         struct work_struct              unpin_work;
 397         struct amdgpu_device            *adev;
 398         int                             crtc_id;
 399         u32                             target_vblank;
 400         uint64_t                        base;
 401         struct drm_pending_vblank_event *event;
 402         struct amdgpu_bo                *old_abo;
 403         struct dma_fence                *excl;
 404         unsigned                        shared_count;
 405         struct dma_fence                **shared;
 406         struct dma_fence_cb             cb;
 407         bool                            async;
 408 };
 409
 410
 411 /*
 412  * CP & rings.
 413  */
 414
 415 struct amdgpu_ib {
 416         struct amdgpu_sa_bo             *sa_bo;
 417         uint32_t                        length_dw;
 418         uint64_t                        gpu_addr;
 419         uint32_t                        *ptr;
 420         uint32_t                        flags;
 421 };
 422
 423 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
 424
 425 /*
 426  * file private structure
 427  */
 428
 429 struct amdgpu_fpriv {
 430         struct amdgpu_vm        vm;
 431         struct amdgpu_bo_va     *prt_va;
 432         struct amdgpu_bo_va     *csa_va;
 433         struct mutex            bo_list_lock;
 434         struct idr              bo_list_handles;
 435         struct amdgpu_ctx_mgr   ctx_mgr;
 436 };
 437
 438 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
 439
 440 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 441                   unsigned size, struct amdgpu_ib *ib);
 442 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
 443                     struct dma_fence *f);
 444 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 445                        struct amdgpu_ib *ibs, struct amdgpu_job *job,
 446                        struct dma_fence **f);
 447 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
 448 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
 449 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
 450
 451 /*
 452  * CS.
 453  */
 454 struct amdgpu_cs_chunk {
 455         uint32_t                chunk_id;
 456         uint32_t                length_dw;
 457         void                    *kdata;
 458 };
 459
 460 struct amdgpu_cs_post_dep {
 461         struct drm_syncobj *syncobj;
 462         struct dma_fence_chain *chain;
 463         u64 point;
 464 };
 465
 466 struct amdgpu_cs_parser {
 467         struct amdgpu_device    *adev;
 468         struct drm_file         *filp;
 469         struct amdgpu_ctx       *ctx;
 470
 471         /* chunks */
 472         unsigned                nchunks;
 473         struct amdgpu_cs_chunk  *chunks;
 474
 475         /* scheduler job object */
 476         struct amdgpu_job       *job;
 477         struct drm_sched_entity *entity;
 478
 479         /* buffer objects */
 480         struct ww_acquire_ctx           ticket;
 481         struct amdgpu_bo_list           *bo_list;
 482         struct amdgpu_mn                *mn;
 483         struct amdgpu_bo_list_entry     vm_pd;
 484         struct list_head                validated;
 485         struct dma_fence                *fence;
 486         uint64_t                        bytes_moved_threshold;
 487         uint64_t                        bytes_moved_vis_threshold;
 488         uint64_t                        bytes_moved;
 489         uint64_t                        bytes_moved_vis;
 490
 491         /* user fence */
 492         struct amdgpu_bo_list_entry     uf_entry;
 493
 494         unsigned                        num_post_deps;
 495         struct amdgpu_cs_post_dep       *post_deps;
 496 };
 497
 498 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
 499                                       uint32_t ib_idx, int idx)
 500 {
 501         return p->job->ibs[ib_idx].ptr[idx];
 502 }
 503
 504 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
 505                                        uint32_t ib_idx, int idx,
 506                                        uint32_t value)
 507 {
 508         p->job->ibs[ib_idx].ptr[idx] = value;
 509 }
 510
 511 /*
 512  * Writeback
 513  */
 514 #define AMDGPU_MAX_WB 128       /* Reserve at most 128 WB slots for amdgpu-owned rings. */
 515
 516 struct amdgpu_wb {
 517         struct amdgpu_bo        *wb_obj;
 518         volatile uint32_t       *wb;
 519         uint64_t                gpu_addr;
 520         u32                     num_wb; /* Number of wb slots actually reserved for amdgpu. */
 521         unsigned long           used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
 522 };
 523
 524 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
 525 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
 526
 527 /*
 528  * Benchmarking
 529  */
 530 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
 531
 532
 533 /*
 534  * Testing
 535  */
 536 void amdgpu_test_moves(struct amdgpu_device *adev);
 537
 538 /*
 539  * ASIC specific register table accessible by UMD
 540  */
 541 struct amdgpu_allowed_register_entry {
 542         uint32_t reg_offset;
 543         bool grbm_indexed;
 544 };
 545
 546 enum amd_reset_method {
 547         AMD_RESET_METHOD_LEGACY = 0,
 548         AMD_RESET_METHOD_MODE0,
 549         AMD_RESET_METHOD_MODE1,
 550         AMD_RESET_METHOD_MODE2,
 551         AMD_RESET_METHOD_BACO
 552 };
 553
 554 /*
 555  * ASIC specific functions.
 556  */
 557 struct amdgpu_asic_funcs {
 558         bool (*read_disabled_bios)(struct amdgpu_device *adev);
 559         bool (*read_bios_from_rom)(struct amdgpu_device *adev,
 560                                    u8 *bios, u32 length_bytes);
 561         int (*read_register)(struct amdgpu_device *adev, u32 se_num,
 562                              u32 sh_num, u32 reg_offset, u32 *value);
 563         void (*set_vga_state)(struct amdgpu_device *adev, bool state);
 564         int (*reset)(struct amdgpu_device *adev);
 565         enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
 566         /* get the reference clock */
 567         u32 (*get_xclk)(struct amdgpu_device *adev);
 568         /* MM block clocks */
 569         int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
 570         int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
 571         /* static power management */
 572         int (*get_pcie_lanes)(struct amdgpu_device *adev);
 573         void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
 574         /* get config memsize register */
 575         u32 (*get_config_memsize)(struct amdgpu_device *adev);
 576         /* flush hdp write queue */
 577         void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 578         /* invalidate hdp read cache */
 579         void (*invalidate_hdp)(struct amdgpu_device *adev,
 580                                struct amdgpu_ring *ring);
 581         /* check if the asic needs a full reset of if soft reset will work */
 582         bool (*need_full_reset)(struct amdgpu_device *adev);
 583         /* initialize doorbell layout for specific asic*/
 584         void (*init_doorbell_index)(struct amdgpu_device *adev);
 585         /* PCIe bandwidth usage */
 586         void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
 587                                uint64_t *count1);
 588         /* do we need to reset the asic at init time (e.g., kexec) */
 589         bool (*need_reset_on_init)(struct amdgpu_device *adev);
 590         /* PCIe replay counter */
 591         uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
 592         /* device supports BACO */
 593         bool (*supports_baco)(struct amdgpu_device *adev);
 594 };
 595
 596 /*
 597  * IOCTL.
 598  */
 599 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
 600                                 struct drm_file *filp);
 601
 602 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 603 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
 604                                     struct drm_file *filp);
 605 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 606 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
 607                                 struct drm_file *filp);
 608
 609 /* VRAM scratch page for HDP bug, default vram page */
 610 struct amdgpu_vram_scratch {
 611         struct amdgpu_bo                *robj;
 612         volatile uint32_t               *ptr;
 613         u64                             gpu_addr;
 614 };
 615
 616 /*
 617  * ACPI
 618  */
 619 struct amdgpu_atcs_functions {
 620         bool get_ext_state;
 621         bool pcie_perf_req;
 622         bool pcie_dev_rdy;
 623         bool pcie_bus_width;
 624 };
 625
 626 struct amdgpu_atcs {
 627         struct amdgpu_atcs_functions functions;
 628 };
 629
 630 /*
 631  * Firmware VRAM reservation
 632  */
 633 struct amdgpu_fw_vram_usage {
 634         u64 start_offset;
 635         u64 size;
 636         struct amdgpu_bo *reserved_bo;
 637         void *va;
 638
 639         /* Offset on the top of VRAM, used as c2p write buffer.
 640         */
 641         u64 mem_train_fb_loc;
 642         bool mem_train_support;
 643 };
 644
 645 /*
 646  * CGS
 647  */
 648 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
 649 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
 650
 651 /*
 652  * Core structure, functions and helpers.
 653  */
 654 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
 655 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
 656
 657 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
 658 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
 659
 660 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
 661 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
 662
 663 struct amdgpu_mmio_remap {
 664         u32 reg_offset;
 665         resource_size_t bus_addr;
 666 };
 667
 668 struct amdgpu_df_funcs {
 669         void (*sw_init)(struct amdgpu_device *adev);
 670         void (*sw_fini)(struct amdgpu_device *adev);
 671         void (*enable_broadcast_mode)(struct amdgpu_device *adev,
 672                                       bool enable);
 673         u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
 674         u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
 675         void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
 676                                                  bool enable);
 677         void (*get_clockgating_state)(struct amdgpu_device *adev,
 678                                       u32 *flags);
 679         void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
 680                                             bool enable);
 681         int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
 682                                          int is_enable);
 683         int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
 684                                          int is_disable);
 685         void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
 686                                          uint64_t *count);
 687         uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
 688         void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
 689                          uint32_t ficadl_val, uint32_t ficadh_val);
 690 };
 691 /* Define the HW IP blocks will be used in driver , add more if necessary */
 692 enum amd_hw_ip_block_type {
 693         GC_HWIP = 1,
 694         HDP_HWIP,
 695         SDMA0_HWIP,
 696         SDMA1_HWIP,
 697         SDMA2_HWIP,
 698         SDMA3_HWIP,
 699         SDMA4_HWIP,
 700         SDMA5_HWIP,
 701         SDMA6_HWIP,
 702         SDMA7_HWIP,
 703         MMHUB_HWIP,
 704         ATHUB_HWIP,
 705         NBIO_HWIP,
 706         MP0_HWIP,
 707         MP1_HWIP,
 708         UVD_HWIP,
 709         VCN_HWIP = UVD_HWIP,
 710         JPEG_HWIP = VCN_HWIP,
 711         VCE_HWIP,
 712         DF_HWIP,
 713         DCE_HWIP,
 714         OSSSYS_HWIP,
 715         SMUIO_HWIP,
 716         PWR_HWIP,
 717         NBIF_HWIP,
 718         THM_HWIP,
 719         CLK_HWIP,
 720         UMC_HWIP,
 721         RSMU_HWIP,
 722         MAX_HWIP
 723 };
 724
 725 #define HWIP_MAX_INSTANCE       8
 726
 727 struct amd_powerplay {
 728         void *pp_handle;
 729         const struct amd_pm_funcs *pp_funcs;
 730 };
 731
 732 #define AMDGPU_RESET_MAGIC_NUM 64
 733 #define AMDGPU_MAX_DF_PERFMONS 4
 734 struct amdgpu_device {
 735         struct device                   *dev;
 736         struct drm_device               *ddev;
 737         struct pci_dev                  *pdev;
 738
 739 #ifdef CONFIG_DRM_AMD_ACP
 740         struct amdgpu_acp               acp;
 741 #endif
 742
 743         /* ASIC */
 744         enum amd_asic_type              asic_type;
 745         uint32_t                        family;
 746         uint32_t                        rev_id;
 747         uint32_t                        external_rev_id;
 748         unsigned long                   flags;
 749         int                             usec_timeout;
 750         const struct amdgpu_asic_funcs  *asic_funcs;
 751         bool                            shutdown;
 752         bool                            need_swiotlb;
 753         bool                            accel_working;
 754         struct notifier_block           acpi_nb;
 755         struct amdgpu_i2c_chan          *i2c_bus[AMDGPU_MAX_I2C_BUS];
 756         struct amdgpu_debugfs           debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
 757         unsigned                        debugfs_count;
 758 #if defined(CONFIG_DEBUG_FS)
 759         struct dentry                   *debugfs_preempt;
 760         struct dentry                   *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
 761 #endif
 762         struct amdgpu_atif              *atif;
 763         struct amdgpu_atcs              atcs;
 764         struct mutex                    srbm_mutex;
 765         /* GRBM index mutex. Protects concurrent access to GRBM index */
 766         struct mutex                    grbm_idx_mutex;
 767         struct dev_pm_domain            vga_pm_domain;
 768         bool                            have_disp_power_ref;
 769         bool                            have_atomics_support;
 770
 771         /* BIOS */
 772         bool                            is_atom_fw;
 773         uint8_t                         *bios;
 774         uint32_t                        bios_size;
 775         struct amdgpu_bo                *stolen_vga_memory;
 776         struct amdgpu_bo                *discovery_memory;
 777         uint32_t                        bios_scratch_reg_offset;
 778         uint32_t                        bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
 779
 780         /* Register/doorbell mmio */
 781         resource_size_t                 rmmio_base;
 782         resource_size_t                 rmmio_size;
 783         void __iomem                    *rmmio;
 784         /* protects concurrent MM_INDEX/DATA based register access */
 785         spinlock_t mmio_idx_lock;
 786         struct amdgpu_mmio_remap        rmmio_remap;
 787         /* protects concurrent SMC based register access */
 788         spinlock_t smc_idx_lock;
 789         amdgpu_rreg_t                   smc_rreg;
 790         amdgpu_wreg_t                   smc_wreg;
 791         /* protects concurrent PCIE register access */
 792         spinlock_t pcie_idx_lock;
 793         amdgpu_rreg_t                   pcie_rreg;
 794         amdgpu_wreg_t                   pcie_wreg;
 795         amdgpu_rreg_t                   pciep_rreg;
 796         amdgpu_wreg_t                   pciep_wreg;
 797         amdgpu_rreg64_t                 pcie_rreg64;
 798         amdgpu_wreg64_t                 pcie_wreg64;
 799         /* protects concurrent UVD register access */
 800         spinlock_t uvd_ctx_idx_lock;
 801         amdgpu_rreg_t                   uvd_ctx_rreg;
 802         amdgpu_wreg_t                   uvd_ctx_wreg;
 803         /* protects concurrent DIDT register access */
 804         spinlock_t didt_idx_lock;
 805         amdgpu_rreg_t                   didt_rreg;
 806         amdgpu_wreg_t                   didt_wreg;
 807         /* protects concurrent gc_cac register access */
 808         spinlock_t gc_cac_idx_lock;
 809         amdgpu_rreg_t                   gc_cac_rreg;
 810         amdgpu_wreg_t                   gc_cac_wreg;
 811         /* protects concurrent se_cac register access */
 812         spinlock_t se_cac_idx_lock;
 813         amdgpu_rreg_t                   se_cac_rreg;
 814         amdgpu_wreg_t                   se_cac_wreg;
 815         /* protects concurrent ENDPOINT (audio) register access */
 816         spinlock_t audio_endpt_idx_lock;
 817         amdgpu_block_rreg_t             audio_endpt_rreg;
 818         amdgpu_block_wreg_t             audio_endpt_wreg;
 819         void __iomem                    *rio_mem;
 820         resource_size_t                 rio_mem_size;
 821         struct amdgpu_doorbell          doorbell;
 822
 823         /* clock/pll info */
 824         struct amdgpu_clock            clock;
 825
 826         /* MC */
 827         struct amdgpu_gmc               gmc;
 828         struct amdgpu_gart              gart;
 829         dma_addr_t                      dummy_page_addr;
 830         struct amdgpu_vm_manager        vm_manager;
 831         struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
 832         unsigned                        num_vmhubs;
 833
 834         /* memory management */
 835         struct amdgpu_mman              mman;
 836         struct amdgpu_vram_scratch      vram_scratch;
 837         struct amdgpu_wb                wb;
 838         atomic64_t                      num_bytes_moved;
 839         atomic64_t                      num_evictions;
 840         atomic64_t                      num_vram_cpu_page_faults;
 841         atomic_t                        gpu_reset_counter;
 842         atomic_t                        vram_lost_counter;
 843
 844         /* data for buffer migration throttling */
 845         struct {
 846                 spinlock_t              lock;
 847                 s64                     last_update_us;
 848                 s64                     accum_us; /* accumulated microseconds */
 849                 s64                     accum_us_vis; /* for visible VRAM */
 850                 u32                     log2_max_MBps;
 851         } mm_stats;
 852
 853         /* display */
 854         bool                            enable_virtual_display;
 855         struct amdgpu_mode_info         mode_info;
 856         /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
 857         struct work_struct              hotplug_work;
 858         struct amdgpu_irq_src           crtc_irq;
 859         struct amdgpu_irq_src           vupdate_irq;
 860         struct amdgpu_irq_src           pageflip_irq;
 861         struct amdgpu_irq_src           hpd_irq;
 862
 863         /* rings */
 864         u64                             fence_context;
 865         unsigned                        num_rings;
 866         struct amdgpu_ring              *rings[AMDGPU_MAX_RINGS];
 867         bool                            ib_pool_ready;
 868         struct amdgpu_sa_manager        ring_tmp_bo;
 869
 870         /* interrupts */
 871         struct amdgpu_irq               irq;
 872
 873         /* powerplay */
 874         struct amd_powerplay            powerplay;
 875         bool                            pp_force_state_enabled;
 876
 877         /* smu */
 878         struct smu_context              smu;
 879
 880         /* dpm */
 881         struct amdgpu_pm                pm;
 882         u32                             cg_flags;
 883         u32                             pg_flags;
 884
 885         /* nbio */
 886         struct amdgpu_nbio              nbio;
 887
 888         /* mmhub */
 889         struct amdgpu_mmhub             mmhub;
 890
 891         /* gfx */
 892         struct amdgpu_gfx               gfx;
 893
 894         /* sdma */
 895         struct amdgpu_sdma              sdma;
 896
 897         /* uvd */
 898         struct amdgpu_uvd               uvd;
 899
 900         /* vce */
 901         struct amdgpu_vce               vce;
 902
 903         /* vcn */
 904         struct amdgpu_vcn               vcn;
 905
 906         /* jpeg */
 907         struct amdgpu_jpeg              jpeg;
 908
 909         /* firmwares */
 910         struct amdgpu_firmware          firmware;
 911
 912         /* PSP */
 913         struct psp_context              psp;
 914
 915         /* GDS */
 916         struct amdgpu_gds               gds;
 917
 918         /* KFD */
 919         struct amdgpu_kfd_dev           kfd;
 920
 921         /* UMC */
 922         struct amdgpu_umc               umc;
 923
 924         /* display related functionality */
 925         struct amdgpu_display_manager dm;
 926
 927         /* discovery */
 928         uint8_t                         *discovery;
 929
 930         /* mes */
 931         bool                            enable_mes;
 932         struct amdgpu_mes               mes;
 933
 934         struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
 935         int                             num_ip_blocks;
 936         struct mutex    mn_lock;
 937         DECLARE_HASHTABLE(mn_hash, 7);
 938
 939         /* tracking pinned memory */
 940         atomic64_t vram_pin_size;
 941         atomic64_t visible_pin_size;
 942         atomic64_t gart_pin_size;
 943
 944         /* soc15 register offset based on ip, instance and  segment */
 945         uint32_t                *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
 946
 947         const struct amdgpu_df_funcs    *df_funcs;
 948
 949         /* delayed work_func for deferring clockgating during resume */
 950         struct delayed_work     delayed_init_work;
 951
 952         struct amdgpu_virt      virt;
 953         /* firmware VRAM reservation */
 954         struct amdgpu_fw_vram_usage fw_vram_usage;
 955
 956         /* link all shadow bo */
 957         struct list_head                shadow_list;
 958         struct mutex                    shadow_list_lock;
 959         /* keep an lru list of rings by HW IP */
 960         struct list_head                ring_lru_list;
 961         spinlock_t                      ring_lru_list_lock;
 962
 963         /* record hw reset is performed */
 964         bool has_hw_reset;
 965         u8                              reset_magic[AMDGPU_RESET_MAGIC_NUM];
 966
 967         /* s3/s4 mask */
 968         bool                            in_suspend;
 969
 970         /* record last mm index being written through WREG32*/
 971         unsigned long last_mm_index;
 972         bool                            in_gpu_reset;
 973         enum pp_mp1_state               mp1_state;
 974         struct mutex  lock_reset;
 975         struct amdgpu_doorbell_index doorbell_index;
 976
 977         struct mutex                    notifier_lock;
 978
 979         int asic_reset_res;
 980         struct work_struct              xgmi_reset_work;
 981
 982         long                            gfx_timeout;
 983         long                            sdma_timeout;
 984         long                            video_timeout;
 985         long                            compute_timeout;
 986
 987         uint64_t                        unique_id;
 988         uint64_t        df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
 989
 990         /* device pstate */
 991         int                             pstate;
 992         /* enable runtime pm on the device */
 993         bool                            runpm;
 994
 995         bool                            pm_sysfs_en;
 996         bool                            ucode_sysfs_en;
 997
 998         bool                            in_baco;
 999 };
1000
1001 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1002 {
1003         return container_of(bdev, struct amdgpu_device, mman.bdev);
1004 }
1005
1006 int amdgpu_device_init(struct amdgpu_device *adev,
1007                        struct drm_device *ddev,
1008                        struct pci_dev *pdev,
1009                        uint32_t flags);
1010 void amdgpu_device_fini(struct amdgpu_device *adev);
1011 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1012
1013 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1014                                uint32_t *buf, size_t size, bool write);
1015 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1016                         uint32_t acc_flags);
1017 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1018                     uint32_t acc_flags);
1019 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1020 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1021
1022 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1023 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1024
1025 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1026 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1027
1028 int emu_soc_asic_init(struct amdgpu_device *adev);
1029
1030 /*
1031  * Registers read & write functions.
1032  */
1033
1034 #define AMDGPU_REGS_IDX       (1<<0)
1035 #define AMDGPU_REGS_NO_KIQ    (1<<1)
1036
1037 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1038 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1039
1040 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1041 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1042
1043 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1044 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1045 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1046 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1047 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1048 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1049 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1050 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1051 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1052 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1053 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1054 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1055 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1056 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1057 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1058 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1059 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1060 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1061 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1062 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1063 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1064 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1065 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1066 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1067 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1068 #define WREG32_P(reg, val, mask)                                \
1069         do {                                                    \
1070                 uint32_t tmp_ = RREG32(reg);                    \
1071                 tmp_ &= (mask);                                 \
1072                 tmp_ |= ((val) & ~(mask));                      \
1073                 WREG32(reg, tmp_);                              \
1074         } while (0)
1075 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1076 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1077 #define WREG32_PLL_P(reg, val, mask)                            \
1078         do {                                                    \
1079                 uint32_t tmp_ = RREG32_PLL(reg);                \
1080                 tmp_ &= (mask);                                 \
1081                 tmp_ |= ((val) & ~(mask));                      \
1082                 WREG32_PLL(reg, tmp_);                          \
1083         } while (0)
1084 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1085 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1086 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1087
1088 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1089 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1090
1091 #define REG_SET_FIELD(orig_val, reg, field, field_val)                  \
1092         (((orig_val) & ~REG_FIELD_MASK(reg, field)) |                   \
1093          (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1094
1095 #define REG_GET_FIELD(value, reg, field)                                \
1096         (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1097
1098 #define WREG32_FIELD(reg, field, val)   \
1099         WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1100
1101 #define WREG32_FIELD_OFFSET(reg, offset, field, val)    \
1102         WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1103
1104 /*
1105  * BIOS helpers.
1106  */
1107 #define RBIOS8(i) (adev->bios[i])
1108 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1109 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1110
1111 /*
1112  * ASICs macro.
1113  */
1114 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1115 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1116 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1117 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1118 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1119 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1120 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1121 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1122 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1123 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1124 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1125 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1126 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1127 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1128 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1129 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1130 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1131 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1132 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1133 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1134 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1135
1136 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1137
1138 /* Common functions */
1139 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1140 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1141                               struct amdgpu_job* job);
1142 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1143 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1144
1145 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1146                                   u64 num_vis_bytes);
1147 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1148 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1149                                              const u32 *registers,
1150                                              const u32 array_size);
1151
1152 bool amdgpu_device_supports_boco(struct drm_device *dev);
1153 bool amdgpu_device_supports_baco(struct drm_device *dev);
1154 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1155                                       struct amdgpu_device *peer_adev);
1156 int amdgpu_device_baco_enter(struct drm_device *dev);
1157 int amdgpu_device_baco_exit(struct drm_device *dev);
1158
1159 /* atpx handler */
1160 #if defined(CONFIG_VGA_SWITCHEROO)
1161 void amdgpu_register_atpx_handler(void);
1162 void amdgpu_unregister_atpx_handler(void);
1163 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1164 bool amdgpu_is_atpx_hybrid(void);
1165 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1166 bool amdgpu_has_atpx(void);
1167 #else
1168 static inline void amdgpu_register_atpx_handler(void) {}
1169 static inline void amdgpu_unregister_atpx_handler(void) {}
1170 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1171 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1172 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1173 static inline bool amdgpu_has_atpx(void) { return false; }
1174 #endif
1175
1176 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1177 void *amdgpu_atpx_get_dhandle(void);
1178 #else
1179 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1180 #endif
1181
1182 /*
1183  * KMS
1184  */
1185 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1186 extern const int amdgpu_max_kms_ioctl;
1187
1188 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1189 void amdgpu_driver_unload_kms(struct drm_device *dev);
1190 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1191 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1192 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1193                                  struct drm_file *file_priv);
1194 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1195 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1196 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1197 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1198 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1199 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1200 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1201                              unsigned long arg);
1202
1203 /*
1204  * functions used by amdgpu_encoder.c
1205  */
1206 struct amdgpu_afmt_acr {
1207         u32 clock;
1208
1209         int n_32khz;
1210         int cts_32khz;
1211
1212         int n_44_1khz;
1213         int cts_44_1khz;
1214
1215         int n_48khz;
1216         int cts_48khz;
1217
1218 };
1219
1220 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1221
1222 /* amdgpu_acpi.c */
1223 #if defined(CONFIG_ACPI)
1224 int amdgpu_acpi_init(struct amdgpu_device *adev);
1225 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1226 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1227 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1228                                                 u8 perf_req, bool advertise);
1229 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1230
1231 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1232                 struct amdgpu_dm_backlight_caps *caps);
1233 #else
1234 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1235 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1236 #endif
1237
1238 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1239                            uint64_t addr, struct amdgpu_bo **bo,
1240                            struct amdgpu_bo_va_mapping **mapping);
1241
1242 #if defined(CONFIG_DRM_AMD_DC)
1243 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1244 #else
1245 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1246 #endif
1247
1248
1249 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1250 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1251
1252 #include "amdgpu_object.h"
1253
1254 /* used by df_v3_6.c and amdgpu_pmu.c */
1255 #define AMDGPU_PMU_ATTR(_name, _object)                                 \
1256 static ssize_t                                                          \
1257 _name##_show(struct device *dev,                                        \
1258                                struct device_attribute *attr,           \
1259                                char *page)                              \
1260 {                                                                       \
1261         BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1);                 \
1262         return sprintf(page, _object "\n");                             \
1263 }                                                                       \
1264                                                                         \
1265 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1266
1267 #endif
1268