drivers/gpu/drm/amd/amdgpu/amdgpu.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __AMDGPU_H__
  29 #define __AMDGPU_H__
  30
  31 #ifdef pr_fmt
  32 #undef pr_fmt
  33 #endif
  34
  35 #define pr_fmt(fmt) "amdgpu: " fmt
  36
  37 #ifdef dev_fmt
  38 #undef dev_fmt
  39 #endif
  40
  41 #define dev_fmt(fmt) "amdgpu: " fmt
  42
  43 #include "amdgpu_ctx.h"
  44
  45 #include <linux/atomic.h>
  46 #include <linux/wait.h>
  47 #include <linux/list.h>
  48 #include <linux/kref.h>
  49 #include <linux/rbtree.h>
  50 #include <linux/hashtable.h>
  51 #include <linux/dma-fence.h>
  52 #include <linux/pci.h>
  53
  54 #include <drm/ttm/ttm_bo.h>
  55 #include <drm/ttm/ttm_placement.h>
  56
  57 #include <drm/amdgpu_drm.h>
  58 #include <drm/drm_gem.h>
  59 #include <drm/drm_ioctl.h>
  60
  61 #include <kgd_kfd_interface.h>
  62 #include "dm_pp_interface.h"
  63 #include "kgd_pp_interface.h"
  64
  65 #include "amd_shared.h"
  66 #include "amdgpu_mode.h"
  67 #include "amdgpu_ih.h"
  68 #include "amdgpu_irq.h"
  69 #include "amdgpu_ucode.h"
  70 #include "amdgpu_ttm.h"
  71 #include "amdgpu_psp.h"
  72 #include "amdgpu_gds.h"
  73 #include "amdgpu_sync.h"
  74 #include "amdgpu_ring.h"
  75 #include "amdgpu_vm.h"
  76 #include "amdgpu_dpm.h"
  77 #include "amdgpu_acp.h"
  78 #include "amdgpu_uvd.h"
  79 #include "amdgpu_vce.h"
  80 #include "amdgpu_vcn.h"
  81 #include "amdgpu_jpeg.h"
  82 #include "amdgpu_vpe.h"
  83 #include "amdgpu_umsch_mm.h"
  84 #include "amdgpu_gmc.h"
  85 #include "amdgpu_gfx.h"
  86 #include "amdgpu_sdma.h"
  87 #include "amdgpu_lsdma.h"
  88 #include "amdgpu_nbio.h"
  89 #include "amdgpu_hdp.h"
  90 #include "amdgpu_dm.h"
  91 #include "amdgpu_virt.h"
  92 #include "amdgpu_csa.h"
  93 #include "amdgpu_mes_ctx.h"
  94 #include "amdgpu_gart.h"
  95 #include "amdgpu_debugfs.h"
  96 #include "amdgpu_job.h"
  97 #include "amdgpu_bo_list.h"
  98 #include "amdgpu_gem.h"
  99 #include "amdgpu_doorbell.h"
 100 #include "amdgpu_amdkfd.h"
 101 #include "amdgpu_discovery.h"
 102 #include "amdgpu_mes.h"
 103 #include "amdgpu_umc.h"
 104 #include "amdgpu_mmhub.h"
 105 #include "amdgpu_gfxhub.h"
 106 #include "amdgpu_df.h"
 107 #include "amdgpu_smuio.h"
 108 #include "amdgpu_fdinfo.h"
 109 #include "amdgpu_mca.h"
 110 #include "amdgpu_ras.h"
 111 #include "amdgpu_xcp.h"
 112
 113 #define MAX_GPU_INSTANCE                64
 114
 115 struct amdgpu_gpu_instance
 116 {
 117         struct amdgpu_device            *adev;
 118         int                             mgpu_fan_enabled;
 119 };
 120
 121 struct amdgpu_mgpu_info
 122 {
 123         struct amdgpu_gpu_instance      gpu_ins[MAX_GPU_INSTANCE];
 124         struct mutex                    mutex;
 125         uint32_t                        num_gpu;
 126         uint32_t                        num_dgpu;
 127         uint32_t                        num_apu;
 128
 129         /* delayed reset_func for XGMI configuration if necessary */
 130         struct delayed_work             delayed_reset_work;
 131         bool                            pending_reset;
 132 };
 133
 134 enum amdgpu_ss {
 135         AMDGPU_SS_DRV_LOAD,
 136         AMDGPU_SS_DEV_D0,
 137         AMDGPU_SS_DEV_D3,
 138         AMDGPU_SS_DRV_UNLOAD
 139 };
 140
 141 struct amdgpu_watchdog_timer
 142 {
 143         bool timeout_fatal_disable;
 144         uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
 145 };
 146
 147 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
 148
 149 /*
 150  * Modules parameters.
 151  */
 152 extern int amdgpu_modeset;
 153 extern unsigned int amdgpu_vram_limit;
 154 extern int amdgpu_vis_vram_limit;
 155 extern int amdgpu_gart_size;
 156 extern int amdgpu_gtt_size;
 157 extern int amdgpu_moverate;
 158 extern int amdgpu_audio;
 159 extern int amdgpu_disp_priority;
 160 extern int amdgpu_hw_i2c;
 161 extern int amdgpu_pcie_gen2;
 162 extern int amdgpu_msi;
 163 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
 164 extern int amdgpu_dpm;
 165 extern int amdgpu_fw_load_type;
 166 extern int amdgpu_aspm;
 167 extern int amdgpu_runtime_pm;
 168 extern uint amdgpu_ip_block_mask;
 169 extern int amdgpu_bapm;
 170 extern int amdgpu_deep_color;
 171 extern int amdgpu_vm_size;
 172 extern int amdgpu_vm_block_size;
 173 extern int amdgpu_vm_fragment_size;
 174 extern int amdgpu_vm_fault_stop;
 175 extern int amdgpu_vm_debug;
 176 extern int amdgpu_vm_update_mode;
 177 extern int amdgpu_exp_hw_support;
 178 extern int amdgpu_dc;
 179 extern int amdgpu_sched_jobs;
 180 extern int amdgpu_sched_hw_submission;
 181 extern uint amdgpu_pcie_gen_cap;
 182 extern uint amdgpu_pcie_lane_cap;
 183 extern u64 amdgpu_cg_mask;
 184 extern uint amdgpu_pg_mask;
 185 extern uint amdgpu_sdma_phase_quantum;
 186 extern char *amdgpu_disable_cu;
 187 extern char *amdgpu_virtual_display;
 188 extern uint amdgpu_pp_feature_mask;
 189 extern uint amdgpu_force_long_training;
 190 extern int amdgpu_lbpw;
 191 extern int amdgpu_compute_multipipe;
 192 extern int amdgpu_gpu_recovery;
 193 extern int amdgpu_emu_mode;
 194 extern uint amdgpu_smu_memory_pool_size;
 195 extern int amdgpu_smu_pptable_id;
 196 extern uint amdgpu_dc_feature_mask;
 197 extern uint amdgpu_dc_debug_mask;
 198 extern uint amdgpu_dc_visual_confirm;
 199 extern uint amdgpu_dm_abm_level;
 200 extern int amdgpu_backlight;
 201 extern struct amdgpu_mgpu_info mgpu_info;
 202 extern int amdgpu_ras_enable;
 203 extern uint amdgpu_ras_mask;
 204 extern int amdgpu_bad_page_threshold;
 205 extern bool amdgpu_ignore_bad_page_threshold;
 206 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
 207 extern int amdgpu_async_gfx_ring;
 208 extern int amdgpu_mcbp;
 209 extern int amdgpu_discovery;
 210 extern int amdgpu_mes;
 211 extern int amdgpu_mes_kiq;
 212 extern int amdgpu_noretry;
 213 extern int amdgpu_force_asic_type;
 214 extern int amdgpu_smartshift_bias;
 215 extern int amdgpu_use_xgmi_p2p;
 216 extern int amdgpu_mtype_local;
 217 extern bool enforce_isolation;
 218 #ifdef CONFIG_HSA_AMD
 219 extern int sched_policy;
 220 extern bool debug_evictions;
 221 extern bool no_system_mem_limit;
 222 extern int halt_if_hws_hang;
 223 #else
 224 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
 225 static const bool __maybe_unused debug_evictions; /* = false */
 226 static const bool __maybe_unused no_system_mem_limit;
 227 static const int __maybe_unused halt_if_hws_hang;
 228 #endif
 229 #ifdef CONFIG_HSA_AMD_P2P
 230 extern bool pcie_p2p;
 231 #endif
 232
 233 extern int amdgpu_tmz;
 234 extern int amdgpu_reset_method;
 235
 236 #ifdef CONFIG_DRM_AMDGPU_SI
 237 extern int amdgpu_si_support;
 238 #endif
 239 #ifdef CONFIG_DRM_AMDGPU_CIK
 240 extern int amdgpu_cik_support;
 241 #endif
 242 extern int amdgpu_num_kcq;
 243
 244 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
 245 extern int amdgpu_vcnfw_log;
 246 extern int amdgpu_sg_display;
 247 extern int amdgpu_umsch_mm;
 248 extern int amdgpu_seamless;
 249
 250 extern int amdgpu_user_partt_mode;
 251 extern int amdgpu_agp;
 252
 253 #define AMDGPU_VM_MAX_NUM_CTX                   4096
 254 #define AMDGPU_SG_THRESHOLD                     (256*1024*1024)
 255 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS          3000
 256 #define AMDGPU_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 257 #define AMDGPU_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 258 #define AMDGPU_DEBUGFS_MAX_COMPONENTS           32
 259 #define AMDGPUFB_CONN_LIMIT                     4
 260 #define AMDGPU_BIOS_NUM_SCRATCH                 16
 261
 262 #define AMDGPU_VBIOS_VGA_ALLOCATION             (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
 263
 264 /* hard reset data */
 265 #define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
 266
 267 /* reset flags */
 268 #define AMDGPU_RESET_GFX                        (1 << 0)
 269 #define AMDGPU_RESET_COMPUTE                    (1 << 1)
 270 #define AMDGPU_RESET_DMA                        (1 << 2)
 271 #define AMDGPU_RESET_CP                         (1 << 3)
 272 #define AMDGPU_RESET_GRBM                       (1 << 4)
 273 #define AMDGPU_RESET_DMA1                       (1 << 5)
 274 #define AMDGPU_RESET_RLC                        (1 << 6)
 275 #define AMDGPU_RESET_SEM                        (1 << 7)
 276 #define AMDGPU_RESET_IH                         (1 << 8)
 277 #define AMDGPU_RESET_VMC                        (1 << 9)
 278 #define AMDGPU_RESET_MC                         (1 << 10)
 279 #define AMDGPU_RESET_DISPLAY                    (1 << 11)
 280 #define AMDGPU_RESET_UVD                        (1 << 12)
 281 #define AMDGPU_RESET_VCE                        (1 << 13)
 282 #define AMDGPU_RESET_VCE1                       (1 << 14)
 283
 284 /* max cursor sizes (in pixels) */
 285 #define CIK_CURSOR_WIDTH 128
 286 #define CIK_CURSOR_HEIGHT 128
 287
 288 /* smart shift bias level limits */
 289 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
 290 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
 291
 292 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
 293 #define AMDGPU_SWCTF_EXTRA_DELAY                50
 294
 295 struct amdgpu_xcp_mgr;
 296 struct amdgpu_device;
 297 struct amdgpu_irq_src;
 298 struct amdgpu_fpriv;
 299 struct amdgpu_bo_va_mapping;
 300 struct kfd_vm_fault_info;
 301 struct amdgpu_hive_info;
 302 struct amdgpu_reset_context;
 303 struct amdgpu_reset_control;
 304
 305 enum amdgpu_cp_irq {
 306         AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
 307         AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
 308         AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
 309         AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
 310         AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
 311         AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
 312         AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
 313         AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
 314         AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
 315         AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
 316
 317         AMDGPU_CP_IRQ_LAST
 318 };
 319
 320 enum amdgpu_thermal_irq {
 321         AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
 322         AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
 323
 324         AMDGPU_THERMAL_IRQ_LAST
 325 };
 326
 327 enum amdgpu_kiq_irq {
 328         AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
 329         AMDGPU_CP_KIQ_IRQ_LAST
 330 };
 331 #define SRIOV_USEC_TIMEOUT  1200000 /* wait 12 * 100ms for SRIOV */
 332 #define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */
 333 #define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */
 334 #define MAX_KIQ_REG_TRY 1000
 335
 336 int amdgpu_device_ip_set_clockgating_state(void *dev,
 337                                            enum amd_ip_block_type block_type,
 338                                            enum amd_clockgating_state state);
 339 int amdgpu_device_ip_set_powergating_state(void *dev,
 340                                            enum amd_ip_block_type block_type,
 341                                            enum amd_powergating_state state);
 342 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
 343                                             u64 *flags);
 344 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
 345                                    enum amd_ip_block_type block_type);
 346 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
 347                               enum amd_ip_block_type block_type);
 348
 349 #define AMDGPU_MAX_IP_NUM 16
 350
 351 struct amdgpu_ip_block_status {
 352         bool valid;
 353         bool sw;
 354         bool hw;
 355         bool late_initialized;
 356         bool hang;
 357 };
 358
 359 struct amdgpu_ip_block_version {
 360         const enum amd_ip_block_type type;
 361         const u32 major;
 362         const u32 minor;
 363         const u32 rev;
 364         const struct amd_ip_funcs *funcs;
 365 };
 366
 367 struct amdgpu_ip_block {
 368         struct amdgpu_ip_block_status status;
 369         const struct amdgpu_ip_block_version *version;
 370 };
 371
 372 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
 373                                        enum amd_ip_block_type type,
 374                                        u32 major, u32 minor);
 375
 376 struct amdgpu_ip_block *
 377 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
 378                               enum amd_ip_block_type type);
 379
 380 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
 381                                const struct amdgpu_ip_block_version *ip_block_version);
 382
 383 /*
 384  * BIOS.
 385  */
 386 bool amdgpu_get_bios(struct amdgpu_device *adev);
 387 bool amdgpu_read_bios(struct amdgpu_device *adev);
 388 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
 389                                      u8 *bios, u32 length_bytes);
 390 /*
 391  * Clocks
 392  */
 393
 394 #define AMDGPU_MAX_PPLL 3
 395
 396 struct amdgpu_clock {
 397         struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
 398         struct amdgpu_pll spll;
 399         struct amdgpu_pll mpll;
 400         /* 10 Khz units */
 401         uint32_t default_mclk;
 402         uint32_t default_sclk;
 403         uint32_t default_dispclk;
 404         uint32_t current_dispclk;
 405         uint32_t dp_extclk;
 406         uint32_t max_pixel_clock;
 407 };
 408
 409 /* sub-allocation manager, it has to be protected by another lock.
 410  * By conception this is an helper for other part of the driver
 411  * like the indirect buffer or semaphore, which both have their
 412  * locking.
 413  *
 414  * Principe is simple, we keep a list of sub allocation in offset
 415  * order (first entry has offset == 0, last entry has the highest
 416  * offset).
 417  *
 418  * When allocating new object we first check if there is room at
 419  * the end total_size - (last_object_offset + last_object_size) >=
 420  * alloc_size. If so we allocate new object there.
 421  *
 422  * When there is not enough room at the end, we start waiting for
 423  * each sub object until we reach object_offset+object_size >=
 424  * alloc_size, this object then become the sub object we return.
 425  *
 426  * Alignment can't be bigger than page size.
 427  *
 428  * Hole are not considered for allocation to keep things simple.
 429  * Assumption is that there won't be hole (all object on same
 430  * alignment).
 431  */
 432
 433 struct amdgpu_sa_manager {
 434         struct drm_suballoc_manager     base;
 435         struct amdgpu_bo                *bo;
 436         uint64_t                        gpu_addr;
 437         void                            *cpu_ptr;
 438 };
 439
 440 int amdgpu_fence_slab_init(void);
 441 void amdgpu_fence_slab_fini(void);
 442
 443 /*
 444  * IRQS.
 445  */
 446
 447 struct amdgpu_flip_work {
 448         struct delayed_work             flip_work;
 449         struct work_struct              unpin_work;
 450         struct amdgpu_device            *adev;
 451         int                             crtc_id;
 452         u32                             target_vblank;
 453         uint64_t                        base;
 454         struct drm_pending_vblank_event *event;
 455         struct amdgpu_bo                *old_abo;
 456         unsigned                        shared_count;
 457         struct dma_fence                **shared;
 458         struct dma_fence_cb             cb;
 459         bool                            async;
 460 };
 461
 462
 463 /*
 464  * file private structure
 465  */
 466
 467 struct amdgpu_fpriv {
 468         struct amdgpu_vm        vm;
 469         struct amdgpu_bo_va     *prt_va;
 470         struct amdgpu_bo_va     *csa_va;
 471         struct mutex            bo_list_lock;
 472         struct idr              bo_list_handles;
 473         struct amdgpu_ctx_mgr   ctx_mgr;
 474         /** GPU partition selection */
 475         uint32_t                xcp_id;
 476 };
 477
 478 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
 479
 480 /*
 481  * Writeback
 482  */
 483 #define AMDGPU_MAX_WB 1024      /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
 484
 485 struct amdgpu_wb {
 486         struct amdgpu_bo        *wb_obj;
 487         volatile uint32_t       *wb;
 488         uint64_t                gpu_addr;
 489         u32                     num_wb; /* Number of wb slots actually reserved for amdgpu. */
 490         unsigned long           used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
 491 };
 492
 493 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
 494 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
 495
 496 /*
 497  * Benchmarking
 498  */
 499 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
 500
 501 /*
 502  * ASIC specific register table accessible by UMD
 503  */
 504 struct amdgpu_allowed_register_entry {
 505         uint32_t reg_offset;
 506         bool grbm_indexed;
 507 };
 508
 509 enum amd_reset_method {
 510         AMD_RESET_METHOD_NONE = -1,
 511         AMD_RESET_METHOD_LEGACY = 0,
 512         AMD_RESET_METHOD_MODE0,
 513         AMD_RESET_METHOD_MODE1,
 514         AMD_RESET_METHOD_MODE2,
 515         AMD_RESET_METHOD_BACO,
 516         AMD_RESET_METHOD_PCI,
 517 };
 518
 519 struct amdgpu_video_codec_info {
 520         u32 codec_type;
 521         u32 max_width;
 522         u32 max_height;
 523         u32 max_pixels_per_frame;
 524         u32 max_level;
 525 };
 526
 527 #define codec_info_build(type, width, height, level) \
 528                          .codec_type = type,\
 529                          .max_width = width,\
 530                          .max_height = height,\
 531                          .max_pixels_per_frame = height * width,\
 532                          .max_level = level,
 533
 534 struct amdgpu_video_codecs {
 535         const u32 codec_count;
 536         const struct amdgpu_video_codec_info *codec_array;
 537 };
 538
 539 /*
 540  * ASIC specific functions.
 541  */
 542 struct amdgpu_asic_funcs {
 543         bool (*read_disabled_bios)(struct amdgpu_device *adev);
 544         bool (*read_bios_from_rom)(struct amdgpu_device *adev,
 545                                    u8 *bios, u32 length_bytes);
 546         int (*read_register)(struct amdgpu_device *adev, u32 se_num,
 547                              u32 sh_num, u32 reg_offset, u32 *value);
 548         void (*set_vga_state)(struct amdgpu_device *adev, bool state);
 549         int (*reset)(struct amdgpu_device *adev);
 550         enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
 551         /* get the reference clock */
 552         u32 (*get_xclk)(struct amdgpu_device *adev);
 553         /* MM block clocks */
 554         int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
 555         int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
 556         /* static power management */
 557         int (*get_pcie_lanes)(struct amdgpu_device *adev);
 558         void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
 559         /* get config memsize register */
 560         u32 (*get_config_memsize)(struct amdgpu_device *adev);
 561         /* flush hdp write queue */
 562         void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 563         /* invalidate hdp read cache */
 564         void (*invalidate_hdp)(struct amdgpu_device *adev,
 565                                struct amdgpu_ring *ring);
 566         /* check if the asic needs a full reset of if soft reset will work */
 567         bool (*need_full_reset)(struct amdgpu_device *adev);
 568         /* initialize doorbell layout for specific asic*/
 569         void (*init_doorbell_index)(struct amdgpu_device *adev);
 570         /* PCIe bandwidth usage */
 571         void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
 572                                uint64_t *count1);
 573         /* do we need to reset the asic at init time (e.g., kexec) */
 574         bool (*need_reset_on_init)(struct amdgpu_device *adev);
 575         /* PCIe replay counter */
 576         uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
 577         /* device supports BACO */
 578         bool (*supports_baco)(struct amdgpu_device *adev);
 579         /* pre asic_init quirks */
 580         void (*pre_asic_init)(struct amdgpu_device *adev);
 581         /* enter/exit umd stable pstate */
 582         int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
 583         /* query video codecs */
 584         int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
 585                                   const struct amdgpu_video_codecs **codecs);
 586         /* encode "> 32bits" smn addressing */
 587         u64 (*encode_ext_smn_addressing)(int ext_id);
 588 };
 589
 590 /*
 591  * IOCTL.
 592  */
 593 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
 594                                 struct drm_file *filp);
 595
 596 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 597 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
 598                                     struct drm_file *filp);
 599 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 600 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
 601                                 struct drm_file *filp);
 602
 603 /* VRAM scratch page for HDP bug, default vram page */
 604 struct amdgpu_mem_scratch {
 605         struct amdgpu_bo                *robj;
 606         volatile uint32_t               *ptr;
 607         u64                             gpu_addr;
 608 };
 609
 610 /*
 611  * CGS
 612  */
 613 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
 614 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
 615
 616 /*
 617  * Core structure, functions and helpers.
 618  */
 619 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
 620 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
 621
 622 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
 623 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
 624
 625 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
 626 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
 627
 628 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
 629 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
 630
 631 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
 632 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
 633
 634 struct amdgpu_mmio_remap {
 635         u32 reg_offset;
 636         resource_size_t bus_addr;
 637 };
 638
 639 /* Define the HW IP blocks will be used in driver , add more if necessary */
 640 enum amd_hw_ip_block_type {
 641         GC_HWIP = 1,
 642         HDP_HWIP,
 643         SDMA0_HWIP,
 644         SDMA1_HWIP,
 645         SDMA2_HWIP,
 646         SDMA3_HWIP,
 647         SDMA4_HWIP,
 648         SDMA5_HWIP,
 649         SDMA6_HWIP,
 650         SDMA7_HWIP,
 651         LSDMA_HWIP,
 652         MMHUB_HWIP,
 653         ATHUB_HWIP,
 654         NBIO_HWIP,
 655         MP0_HWIP,
 656         MP1_HWIP,
 657         UVD_HWIP,
 658         VCN_HWIP = UVD_HWIP,
 659         JPEG_HWIP = VCN_HWIP,
 660         VCN1_HWIP,
 661         VCE_HWIP,
 662         VPE_HWIP,
 663         DF_HWIP,
 664         DCE_HWIP,
 665         OSSSYS_HWIP,
 666         SMUIO_HWIP,
 667         PWR_HWIP,
 668         NBIF_HWIP,
 669         THM_HWIP,
 670         CLK_HWIP,
 671         UMC_HWIP,
 672         RSMU_HWIP,
 673         XGMI_HWIP,
 674         DCI_HWIP,
 675         PCIE_HWIP,
 676         MAX_HWIP
 677 };
 678
 679 #define HWIP_MAX_INSTANCE       44
 680
 681 #define HW_ID_MAX               300
 682 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \
 683         (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
 684 #define IP_VERSION(mj, mn, rv)          IP_VERSION_FULL(mj, mn, rv, 0, 0)
 685 #define IP_VERSION_MAJ(ver)             ((ver) >> 24)
 686 #define IP_VERSION_MIN(ver)             (((ver) >> 16) & 0xFF)
 687 #define IP_VERSION_REV(ver)             (((ver) >> 8) & 0xFF)
 688 #define IP_VERSION_VARIANT(ver)         (((ver) >> 4) & 0xF)
 689 #define IP_VERSION_SUBREV(ver)          ((ver) & 0xF)
 690 #define IP_VERSION_MAJ_MIN_REV(ver)     ((ver) >> 8)
 691
 692 struct amdgpu_ip_map_info {
 693         /* Map of logical to actual dev instances/mask */
 694         uint32_t                dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
 695         int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
 696                                       enum amd_hw_ip_block_type block,
 697                                       int8_t inst);
 698         uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
 699                                         enum amd_hw_ip_block_type block,
 700                                         uint32_t mask);
 701 };
 702
 703 struct amd_powerplay {
 704         void *pp_handle;
 705         const struct amd_pm_funcs *pp_funcs;
 706 };
 707
 708 struct ip_discovery_top;
 709
 710 /* polaris10 kickers */
 711 #define ASICID_IS_P20(did, rid)         (((did == 0x67DF) && \
 712                                          ((rid == 0xE3) || \
 713                                           (rid == 0xE4) || \
 714                                           (rid == 0xE5) || \
 715                                           (rid == 0xE7) || \
 716                                           (rid == 0xEF))) || \
 717                                          ((did == 0x6FDF) && \
 718                                          ((rid == 0xE7) || \
 719                                           (rid == 0xEF) || \
 720                                           (rid == 0xFF))))
 721
 722 #define ASICID_IS_P30(did, rid)         ((did == 0x67DF) && \
 723                                         ((rid == 0xE1) || \
 724                                          (rid == 0xF7)))
 725
 726 /* polaris11 kickers */
 727 #define ASICID_IS_P21(did, rid)         (((did == 0x67EF) && \
 728                                          ((rid == 0xE0) || \
 729                                           (rid == 0xE5))) || \
 730                                          ((did == 0x67FF) && \
 731                                          ((rid == 0xCF) || \
 732                                           (rid == 0xEF) || \
 733                                           (rid == 0xFF))))
 734
 735 #define ASICID_IS_P31(did, rid)         ((did == 0x67EF) && \
 736                                         ((rid == 0xE2)))
 737
 738 /* polaris12 kickers */
 739 #define ASICID_IS_P23(did, rid)         (((did == 0x6987) && \
 740                                          ((rid == 0xC0) || \
 741                                           (rid == 0xC1) || \
 742                                           (rid == 0xC3) || \
 743                                           (rid == 0xC7))) || \
 744                                          ((did == 0x6981) && \
 745                                          ((rid == 0x00) || \
 746                                           (rid == 0x01) || \
 747                                           (rid == 0x10))))
 748
 749 struct amdgpu_mqd_prop {
 750         uint64_t mqd_gpu_addr;
 751         uint64_t hqd_base_gpu_addr;
 752         uint64_t rptr_gpu_addr;
 753         uint64_t wptr_gpu_addr;
 754         uint32_t queue_size;
 755         bool use_doorbell;
 756         uint32_t doorbell_index;
 757         uint64_t eop_gpu_addr;
 758         uint32_t hqd_pipe_priority;
 759         uint32_t hqd_queue_priority;
 760         bool hqd_active;
 761 };
 762
 763 struct amdgpu_mqd {
 764         unsigned mqd_size;
 765         int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
 766                         struct amdgpu_mqd_prop *p);
 767 };
 768
 769 #define AMDGPU_RESET_MAGIC_NUM 64
 770 #define AMDGPU_MAX_DF_PERFMONS 4
 771 struct amdgpu_reset_domain;
 772 struct amdgpu_fru_info;
 773
 774 struct amdgpu_reset_info {
 775         /* reset dump register */
 776         u32 *reset_dump_reg_list;
 777         u32 *reset_dump_reg_value;
 778         int num_regs;
 779
 780 #ifdef CONFIG_DEV_COREDUMP
 781         struct amdgpu_coredump_info *coredump_info;
 782 #endif
 783 };
 784
 785 /*
 786  * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
 787  */
 788 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
 789
 790 struct amdgpu_device {
 791         struct device                   *dev;
 792         struct pci_dev                  *pdev;
 793         struct drm_device               ddev;
 794
 795 #ifdef CONFIG_DRM_AMD_ACP
 796         struct amdgpu_acp               acp;
 797 #endif
 798         struct amdgpu_hive_info *hive;
 799         struct amdgpu_xcp_mgr *xcp_mgr;
 800         /* ASIC */
 801         enum amd_asic_type              asic_type;
 802         uint32_t                        family;
 803         uint32_t                        rev_id;
 804         uint32_t                        external_rev_id;
 805         unsigned long                   flags;
 806         unsigned long                   apu_flags;
 807         int                             usec_timeout;
 808         const struct amdgpu_asic_funcs  *asic_funcs;
 809         bool                            shutdown;
 810         bool                            need_swiotlb;
 811         bool                            accel_working;
 812         struct notifier_block           acpi_nb;
 813         struct amdgpu_i2c_chan          *i2c_bus[AMDGPU_MAX_I2C_BUS];
 814         struct debugfs_blob_wrapper     debugfs_vbios_blob;
 815         struct debugfs_blob_wrapper     debugfs_discovery_blob;
 816         struct mutex                    srbm_mutex;
 817         /* GRBM index mutex. Protects concurrent access to GRBM index */
 818         struct mutex                    grbm_idx_mutex;
 819         struct dev_pm_domain            vga_pm_domain;
 820         bool                            have_disp_power_ref;
 821         bool                            have_atomics_support;
 822
 823         /* BIOS */
 824         bool                            is_atom_fw;
 825         uint8_t                         *bios;
 826         uint32_t                        bios_size;
 827         uint32_t                        bios_scratch_reg_offset;
 828         uint32_t                        bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
 829
 830         /* Register/doorbell mmio */
 831         resource_size_t                 rmmio_base;
 832         resource_size_t                 rmmio_size;
 833         void __iomem                    *rmmio;
 834         /* protects concurrent MM_INDEX/DATA based register access */
 835         spinlock_t mmio_idx_lock;
 836         struct amdgpu_mmio_remap        rmmio_remap;
 837         /* protects concurrent SMC based register access */
 838         spinlock_t smc_idx_lock;
 839         amdgpu_rreg_t                   smc_rreg;
 840         amdgpu_wreg_t                   smc_wreg;
 841         /* protects concurrent PCIE register access */
 842         spinlock_t pcie_idx_lock;
 843         amdgpu_rreg_t                   pcie_rreg;
 844         amdgpu_wreg_t                   pcie_wreg;
 845         amdgpu_rreg_t                   pciep_rreg;
 846         amdgpu_wreg_t                   pciep_wreg;
 847         amdgpu_rreg_ext_t               pcie_rreg_ext;
 848         amdgpu_wreg_ext_t               pcie_wreg_ext;
 849         amdgpu_rreg64_t                 pcie_rreg64;
 850         amdgpu_wreg64_t                 pcie_wreg64;
 851         amdgpu_rreg64_ext_t                     pcie_rreg64_ext;
 852         amdgpu_wreg64_ext_t                     pcie_wreg64_ext;
 853         /* protects concurrent UVD register access */
 854         spinlock_t uvd_ctx_idx_lock;
 855         amdgpu_rreg_t                   uvd_ctx_rreg;
 856         amdgpu_wreg_t                   uvd_ctx_wreg;
 857         /* protects concurrent DIDT register access */
 858         spinlock_t didt_idx_lock;
 859         amdgpu_rreg_t                   didt_rreg;
 860         amdgpu_wreg_t                   didt_wreg;
 861         /* protects concurrent gc_cac register access */
 862         spinlock_t gc_cac_idx_lock;
 863         amdgpu_rreg_t                   gc_cac_rreg;
 864         amdgpu_wreg_t                   gc_cac_wreg;
 865         /* protects concurrent se_cac register access */
 866         spinlock_t se_cac_idx_lock;
 867         amdgpu_rreg_t                   se_cac_rreg;
 868         amdgpu_wreg_t                   se_cac_wreg;
 869         /* protects concurrent ENDPOINT (audio) register access */
 870         spinlock_t audio_endpt_idx_lock;
 871         amdgpu_block_rreg_t             audio_endpt_rreg;
 872         amdgpu_block_wreg_t             audio_endpt_wreg;
 873         struct amdgpu_doorbell          doorbell;
 874
 875         /* clock/pll info */
 876         struct amdgpu_clock            clock;
 877
 878         /* MC */
 879         struct amdgpu_gmc               gmc;
 880         struct amdgpu_gart              gart;
 881         dma_addr_t                      dummy_page_addr;
 882         struct amdgpu_vm_manager        vm_manager;
 883         struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
 884         DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
 885
 886         /* memory management */
 887         struct amdgpu_mman              mman;
 888         struct amdgpu_mem_scratch       mem_scratch;
 889         struct amdgpu_wb                wb;
 890         atomic64_t                      num_bytes_moved;
 891         atomic64_t                      num_evictions;
 892         atomic64_t                      num_vram_cpu_page_faults;
 893         atomic_t                        gpu_reset_counter;
 894         atomic_t                        vram_lost_counter;
 895
 896         /* data for buffer migration throttling */
 897         struct {
 898                 spinlock_t              lock;
 899                 s64                     last_update_us;
 900                 s64                     accum_us; /* accumulated microseconds */
 901                 s64                     accum_us_vis; /* for visible VRAM */
 902                 u32                     log2_max_MBps;
 903         } mm_stats;
 904
 905         /* display */
 906         bool                            enable_virtual_display;
 907         struct amdgpu_vkms_output       *amdgpu_vkms_output;
 908         struct amdgpu_mode_info         mode_info;
 909         /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
 910         struct delayed_work         hotplug_work;
 911         struct amdgpu_irq_src           crtc_irq;
 912         struct amdgpu_irq_src           vline0_irq;
 913         struct amdgpu_irq_src           vupdate_irq;
 914         struct amdgpu_irq_src           pageflip_irq;
 915         struct amdgpu_irq_src           hpd_irq;
 916         struct amdgpu_irq_src           dmub_trace_irq;
 917         struct amdgpu_irq_src           dmub_outbox_irq;
 918
 919         /* rings */
 920         u64                             fence_context;
 921         unsigned                        num_rings;
 922         struct amdgpu_ring              *rings[AMDGPU_MAX_RINGS];
 923         struct dma_fence __rcu          *gang_submit;
 924         bool                            ib_pool_ready;
 925         struct amdgpu_sa_manager        ib_pools[AMDGPU_IB_POOL_MAX];
 926         struct amdgpu_sched             gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
 927
 928         /* interrupts */
 929         struct amdgpu_irq               irq;
 930
 931         /* powerplay */
 932         struct amd_powerplay            powerplay;
 933         struct amdgpu_pm                pm;
 934         u64                             cg_flags;
 935         u32                             pg_flags;
 936
 937         /* nbio */
 938         struct amdgpu_nbio              nbio;
 939
 940         /* hdp */
 941         struct amdgpu_hdp               hdp;
 942
 943         /* smuio */
 944         struct amdgpu_smuio             smuio;
 945
 946         /* mmhub */
 947         struct amdgpu_mmhub             mmhub;
 948
 949         /* gfxhub */
 950         struct amdgpu_gfxhub            gfxhub;
 951
 952         /* gfx */
 953         struct amdgpu_gfx               gfx;
 954
 955         /* sdma */
 956         struct amdgpu_sdma              sdma;
 957
 958         /* lsdma */
 959         struct amdgpu_lsdma             lsdma;
 960
 961         /* uvd */
 962         struct amdgpu_uvd               uvd;
 963
 964         /* vce */
 965         struct amdgpu_vce               vce;
 966
 967         /* vcn */
 968         struct amdgpu_vcn               vcn;
 969
 970         /* jpeg */
 971         struct amdgpu_jpeg              jpeg;
 972
 973         /* vpe */
 974         struct amdgpu_vpe               vpe;
 975
 976         /* umsch */
 977         struct amdgpu_umsch_mm          umsch_mm;
 978         bool                            enable_umsch_mm;
 979
 980         /* firmwares */
 981         struct amdgpu_firmware          firmware;
 982
 983         /* PSP */
 984         struct psp_context              psp;
 985
 986         /* GDS */
 987         struct amdgpu_gds               gds;
 988
 989         /* KFD */
 990         struct amdgpu_kfd_dev           kfd;
 991
 992         /* UMC */
 993         struct amdgpu_umc               umc;
 994
 995         /* display related functionality */
 996         struct amdgpu_display_manager dm;
 997
 998         /* mes */
 999         bool                            enable_mes;
1000         bool                            enable_mes_kiq;
1001         struct amdgpu_mes               mes;
1002         struct amdgpu_mqd               mqds[AMDGPU_HW_IP_NUM];
1003
1004         /* df */
1005         struct amdgpu_df                df;
1006
1007         /* MCA */
1008         struct amdgpu_mca               mca;
1009
1010         struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
1011         uint32_t                        harvest_ip_mask;
1012         int                             num_ip_blocks;
1013         struct mutex    mn_lock;
1014         DECLARE_HASHTABLE(mn_hash, 7);
1015
1016         /* tracking pinned memory */
1017         atomic64_t vram_pin_size;
1018         atomic64_t visible_pin_size;
1019         atomic64_t gart_pin_size;
1020
1021         /* soc15 register offset based on ip, instance and  segment */
1022         uint32_t                *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1023         struct amdgpu_ip_map_info       ip_map;
1024
1025         /* delayed work_func for deferring clockgating during resume */
1026         struct delayed_work     delayed_init_work;
1027
1028         struct amdgpu_virt      virt;
1029
1030         /* link all shadow bo */
1031         struct list_head                shadow_list;
1032         struct mutex                    shadow_list_lock;
1033
1034         /* record hw reset is performed */
1035         bool has_hw_reset;
1036         u8                              reset_magic[AMDGPU_RESET_MAGIC_NUM];
1037
1038         /* s3/s4 mask */
1039         bool                            in_suspend;
1040         bool                            in_s3;
1041         bool                            in_s4;
1042         bool                            in_s0ix;
1043
1044         enum pp_mp1_state               mp1_state;
1045         struct amdgpu_doorbell_index doorbell_index;
1046
1047         struct mutex                    notifier_lock;
1048
1049         int asic_reset_res;
1050         struct work_struct              xgmi_reset_work;
1051         struct list_head                reset_list;
1052
1053         long                            gfx_timeout;
1054         long                            sdma_timeout;
1055         long                            video_timeout;
1056         long                            compute_timeout;
1057
1058         uint64_t                        unique_id;
1059         uint64_t        df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1060
1061         /* enable runtime pm on the device */
1062         bool                            in_runpm;
1063         bool                            has_pr3;
1064
1065         bool                            ucode_sysfs_en;
1066
1067         struct amdgpu_fru_info          *fru_info;
1068         atomic_t                        throttling_logging_enabled;
1069         struct ratelimit_state          throttling_logging_rs;
1070         uint32_t                        ras_hw_enabled;
1071         uint32_t                        ras_enabled;
1072
1073         bool                            no_hw_access;
1074         struct pci_saved_state          *pci_state;
1075         pci_channel_state_t             pci_channel_state;
1076
1077         /* Track auto wait count on s_barrier settings */
1078         bool                            barrier_has_auto_waitcnt;
1079
1080         struct amdgpu_reset_control     *reset_cntl;
1081         uint32_t                        ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1082
1083         bool                            ram_is_direct_mapped;
1084
1085         struct list_head                ras_list;
1086
1087         struct ip_discovery_top         *ip_top;
1088
1089         struct amdgpu_reset_domain      *reset_domain;
1090
1091         struct mutex                    benchmark_mutex;
1092
1093         struct amdgpu_reset_info        reset_info;
1094
1095         bool                            scpm_enabled;
1096         uint32_t                        scpm_status;
1097
1098         struct work_struct              reset_work;
1099
1100         bool                            job_hang;
1101         bool                            dc_enabled;
1102         /* Mask of active clusters */
1103         uint32_t                        aid_mask;
1104
1105         /* Debug */
1106         bool                            debug_vm;
1107         bool                            debug_largebar;
1108         bool                            debug_disable_soft_recovery;
1109 };
1110
1111 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1112                                          uint8_t ip, uint8_t inst)
1113 {
1114         /* This considers only major/minor/rev and ignores
1115          * subrevision/variant fields.
1116          */
1117         return adev->ip_versions[ip][inst] & ~0xFFU;
1118 }
1119
1120 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1121                                               uint8_t ip, uint8_t inst)
1122 {
1123         /* This returns full version - major/minor/rev/variant/subrevision */
1124         return adev->ip_versions[ip][inst];
1125 }
1126
1127 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1128 {
1129         return container_of(ddev, struct amdgpu_device, ddev);
1130 }
1131
1132 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1133 {
1134         return &adev->ddev;
1135 }
1136
1137 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1138 {
1139         return container_of(bdev, struct amdgpu_device, mman.bdev);
1140 }
1141
1142 int amdgpu_device_init(struct amdgpu_device *adev,
1143                        uint32_t flags);
1144 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1145 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1146
1147 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1148
1149 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1150                              void *buf, size_t size, bool write);
1151 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1152                                  void *buf, size_t size, bool write);
1153
1154 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1155                                void *buf, size_t size, bool write);
1156 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1157                             uint32_t inst, uint32_t reg_addr, char reg_name[],
1158                             uint32_t expected_value, uint32_t mask);
1159 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1160                             uint32_t reg, uint32_t acc_flags);
1161 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1162                                     u64 reg_addr);
1163 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1164                                 uint32_t reg, uint32_t acc_flags,
1165                                 uint32_t xcc_id);
1166 void amdgpu_device_wreg(struct amdgpu_device *adev,
1167                         uint32_t reg, uint32_t v,
1168                         uint32_t acc_flags);
1169 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1170                                      u64 reg_addr, u32 reg_data);
1171 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1172                             uint32_t reg, uint32_t v,
1173                             uint32_t acc_flags,
1174                             uint32_t xcc_id);
1175 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1176                              uint32_t reg, uint32_t v, uint32_t xcc_id);
1177 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1178 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1179
1180 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1181                                 u32 reg_addr);
1182 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1183                                   u32 reg_addr);
1184 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1185                                   u64 reg_addr);
1186 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1187                                  u32 reg_addr, u32 reg_data);
1188 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1189                                    u32 reg_addr, u64 reg_data);
1190 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1191                                    u64 reg_addr, u64 reg_data);
1192 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1193 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1194 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1195
1196 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1197
1198 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1199                                  struct amdgpu_reset_context *reset_context);
1200
1201 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1202                          struct amdgpu_reset_context *reset_context);
1203
1204 int emu_soc_asic_init(struct amdgpu_device *adev);
1205
1206 /*
1207  * Registers read & write functions.
1208  */
1209 #define AMDGPU_REGS_NO_KIQ    (1<<1)
1210 #define AMDGPU_REGS_RLC (1<<2)
1211
1212 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1213 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1214
1215 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1216 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
1217
1218 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1219 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1220
1221 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1222 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1223 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1224 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1225 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1226 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1227 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
1228 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1229 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1230 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1231 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1232 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1233 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1234 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1235 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1236 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1237 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1238 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1239 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1240 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1241 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1242 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1243 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1244 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1245 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1246 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1247 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1248 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1249 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1250 #define WREG32_P(reg, val, mask)                                \
1251         do {                                                    \
1252                 uint32_t tmp_ = RREG32(reg);                    \
1253                 tmp_ &= (mask);                                 \
1254                 tmp_ |= ((val) & ~(mask));                      \
1255                 WREG32(reg, tmp_);                              \
1256         } while (0)
1257 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1258 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1259 #define WREG32_PLL_P(reg, val, mask)                            \
1260         do {                                                    \
1261                 uint32_t tmp_ = RREG32_PLL(reg);                \
1262                 tmp_ &= (mask);                                 \
1263                 tmp_ |= ((val) & ~(mask));                      \
1264                 WREG32_PLL(reg, tmp_);                          \
1265         } while (0)
1266
1267 #define WREG32_SMC_P(_Reg, _Val, _Mask)                         \
1268         do {                                                    \
1269                 u32 tmp = RREG32_SMC(_Reg);                     \
1270                 tmp &= (_Mask);                                 \
1271                 tmp |= ((_Val) & ~(_Mask));                     \
1272                 WREG32_SMC(_Reg, tmp);                          \
1273         } while (0)
1274
1275 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1276
1277 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1278 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1279
1280 #define REG_SET_FIELD(orig_val, reg, field, field_val)                  \
1281         (((orig_val) & ~REG_FIELD_MASK(reg, field)) |                   \
1282          (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1283
1284 #define REG_GET_FIELD(value, reg, field)                                \
1285         (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1286
1287 #define WREG32_FIELD(reg, field, val)   \
1288         WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1289
1290 #define WREG32_FIELD_OFFSET(reg, offset, field, val)    \
1291         WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1292
1293 /*
1294  * BIOS helpers.
1295  */
1296 #define RBIOS8(i) (adev->bios[i])
1297 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1298 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1299
1300 /*
1301  * ASICs macro.
1302  */
1303 #define amdgpu_asic_set_vga_state(adev, state) \
1304     ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1305 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1306 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1307 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1308 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1309 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1310 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1311 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1312 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1313 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1314 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1315 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1316 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1317 #define amdgpu_asic_flush_hdp(adev, r) \
1318         ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1319 #define amdgpu_asic_invalidate_hdp(adev, r) \
1320         ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1321          ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1322 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1323 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1324 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1325 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1326 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1327 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1328 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1329 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1330         ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1331 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1332
1333 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1334
1335 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1336 #define for_each_inst(i, inst_mask)        \
1337         for (i = ffs(inst_mask); i-- != 0; \
1338              i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1339
1340 /* Common functions */
1341 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1342 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1343 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1344                               struct amdgpu_job *job,
1345                               struct amdgpu_reset_context *reset_context);
1346 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1347 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1348 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1349 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1350 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1351
1352 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1353                                   u64 num_vis_bytes);
1354 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1355 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1356                                              const u32 *registers,
1357                                              const u32 array_size);
1358
1359 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1360 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1361 bool amdgpu_device_supports_px(struct drm_device *dev);
1362 bool amdgpu_device_supports_boco(struct drm_device *dev);
1363 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1364 bool amdgpu_device_supports_baco(struct drm_device *dev);
1365 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1366                                       struct amdgpu_device *peer_adev);
1367 int amdgpu_device_baco_enter(struct drm_device *dev);
1368 int amdgpu_device_baco_exit(struct drm_device *dev);
1369
1370 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1371                 struct amdgpu_ring *ring);
1372 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1373                 struct amdgpu_ring *ring);
1374
1375 void amdgpu_device_halt(struct amdgpu_device *adev);
1376 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1377                                 u32 reg);
1378 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1379                                 u32 reg, u32 v);
1380 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1381                                             struct dma_fence *gang);
1382 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1383
1384 /* atpx handler */
1385 #if defined(CONFIG_VGA_SWITCHEROO)
1386 void amdgpu_register_atpx_handler(void);
1387 void amdgpu_unregister_atpx_handler(void);
1388 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1389 bool amdgpu_is_atpx_hybrid(void);
1390 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1391 bool amdgpu_has_atpx(void);
1392 #else
1393 static inline void amdgpu_register_atpx_handler(void) {}
1394 static inline void amdgpu_unregister_atpx_handler(void) {}
1395 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1396 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1397 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1398 static inline bool amdgpu_has_atpx(void) { return false; }
1399 #endif
1400
1401 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1402 void *amdgpu_atpx_get_dhandle(void);
1403 #else
1404 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1405 #endif
1406
1407 /*
1408  * KMS
1409  */
1410 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1411 extern const int amdgpu_max_kms_ioctl;
1412
1413 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1414 void amdgpu_driver_unload_kms(struct drm_device *dev);
1415 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1416 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1417 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1418                                  struct drm_file *file_priv);
1419 void amdgpu_driver_release_kms(struct drm_device *dev);
1420
1421 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1422 int amdgpu_device_prepare(struct drm_device *dev);
1423 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1424 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1425 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1426 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1427 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1428 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1429                       struct drm_file *filp);
1430
1431 /*
1432  * functions used by amdgpu_encoder.c
1433  */
1434 struct amdgpu_afmt_acr {
1435         u32 clock;
1436
1437         int n_32khz;
1438         int cts_32khz;
1439
1440         int n_44_1khz;
1441         int cts_44_1khz;
1442
1443         int n_48khz;
1444         int cts_48khz;
1445
1446 };
1447
1448 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1449
1450 /* amdgpu_acpi.c */
1451
1452 struct amdgpu_numa_info {
1453         uint64_t size;
1454         int pxm;
1455         int nid;
1456 };
1457
1458 /* ATCS Device/Driver State */
1459 #define AMDGPU_ATCS_PSC_DEV_STATE_D0            0
1460 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT        3
1461 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR           0
1462 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR       1
1463
1464 #if defined(CONFIG_ACPI)
1465 int amdgpu_acpi_init(struct amdgpu_device *adev);
1466 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1467 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1468 bool amdgpu_acpi_is_power_shift_control_supported(void);
1469 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1470                                                 u8 perf_req, bool advertise);
1471 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1472                                     u8 dev_state, bool drv_state);
1473 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1474 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1475 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1476                              u64 *tmr_size);
1477 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1478                              struct amdgpu_numa_info *numa_info);
1479
1480 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1481 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1482 void amdgpu_acpi_detect(void);
1483 void amdgpu_acpi_release(void);
1484 #else
1485 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1486 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1487                                            u64 *tmr_offset, u64 *tmr_size)
1488 {
1489         return -EINVAL;
1490 }
1491 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1492                                            int xcc_id,
1493                                            struct amdgpu_numa_info *numa_info)
1494 {
1495         return -EINVAL;
1496 }
1497 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1498 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1499 static inline void amdgpu_acpi_detect(void) { }
1500 static inline void amdgpu_acpi_release(void) { }
1501 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1502 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1503                                                   u8 dev_state, bool drv_state) { return 0; }
1504 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1505                                                  enum amdgpu_ss ss_state) { return 0; }
1506 #endif
1507
1508 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1509 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1510 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1511 #else
1512 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1513 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1514 #endif
1515
1516 #if defined(CONFIG_DRM_AMD_DC)
1517 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1518 #else
1519 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1520 #endif
1521
1522
1523 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1524 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1525
1526 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1527                                            pci_channel_state_t state);
1528 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1529 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1530 void amdgpu_pci_resume(struct pci_dev *pdev);
1531
1532 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1533 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1534
1535 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1536
1537 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1538                                enum amd_clockgating_state state);
1539 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1540                                enum amd_powergating_state state);
1541
1542 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1543 {
1544         return amdgpu_gpu_recovery != 0 &&
1545                 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1546                 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1547                 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1548                 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1549 }
1550
1551 #include "amdgpu_object.h"
1552
1553 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1554 {
1555        return adev->gmc.tmz_enabled;
1556 }
1557
1558 int amdgpu_in_reset(struct amdgpu_device *adev);
1559
1560 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1561 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1562 extern const struct attribute_group amdgpu_flash_attr_group;
1563
1564 #endif