2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 #include <linux/list_sort.h>
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
33 #define AMDGPU_CS_MAX_PRIORITY 32u
34 #define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1)
36 /* This is based on the bucket sort with O(n) time complexity.
37 * An item with priority "i" is added to bucket[i]. The lists are then
38 * concatenated in descending order.
40 struct amdgpu_cs_buckets
{
41 struct list_head bucket
[AMDGPU_CS_NUM_BUCKETS
];
44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets
*b
)
48 for (i
= 0; i
< AMDGPU_CS_NUM_BUCKETS
; i
++)
49 INIT_LIST_HEAD(&b
->bucket
[i
]);
52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets
*b
,
53 struct list_head
*item
, unsigned priority
)
55 /* Since buffers which appear sooner in the relocation list are
56 * likely to be used more often than buffers which appear later
57 * in the list, the sort mustn't change the ordering of buffers
58 * with the same priority, i.e. it must be stable.
60 list_add_tail(item
, &b
->bucket
[min(priority
, AMDGPU_CS_MAX_PRIORITY
)]);
63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets
*b
,
64 struct list_head
*out_list
)
68 /* Connect the sorted buckets in the output list. */
69 for (i
= 0; i
< AMDGPU_CS_NUM_BUCKETS
; i
++) {
70 list_splice(&b
->bucket
[i
], out_list
);
74 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
75 u32 ip_instance
, u32 ring
,
76 struct amdgpu_ring
**out_ring
)
78 /* Right now all IPs have only one instance - multiple rings. */
79 if (ip_instance
!= 0) {
80 DRM_ERROR("invalid ip instance: %d\n", ip_instance
);
86 DRM_ERROR("unknown ip type: %d\n", ip_type
);
88 case AMDGPU_HW_IP_GFX
:
89 if (ring
< adev
->gfx
.num_gfx_rings
) {
90 *out_ring
= &adev
->gfx
.gfx_ring
[ring
];
92 DRM_ERROR("only %d gfx rings are supported now\n",
93 adev
->gfx
.num_gfx_rings
);
97 case AMDGPU_HW_IP_COMPUTE
:
98 if (ring
< adev
->gfx
.num_compute_rings
) {
99 *out_ring
= &adev
->gfx
.compute_ring
[ring
];
101 DRM_ERROR("only %d compute rings are supported now\n",
102 adev
->gfx
.num_compute_rings
);
106 case AMDGPU_HW_IP_DMA
:
107 if (ring
< adev
->sdma
.num_instances
) {
108 *out_ring
= &adev
->sdma
.instance
[ring
].ring
;
110 DRM_ERROR("only %d SDMA rings are supported\n",
111 adev
->sdma
.num_instances
);
115 case AMDGPU_HW_IP_UVD
:
116 *out_ring
= &adev
->uvd
.ring
;
118 case AMDGPU_HW_IP_VCE
:
120 *out_ring
= &adev
->vce
.ring
[ring
];
122 DRM_ERROR("only two VCE rings are supported\n");
130 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
)
132 union drm_amdgpu_cs
*cs
= data
;
133 uint64_t *chunk_array_user
;
134 uint64_t *chunk_array
;
135 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
140 if (cs
->in
.num_chunks
== 0)
143 chunk_array
= kmalloc_array(cs
->in
.num_chunks
, sizeof(uint64_t), GFP_KERNEL
);
147 p
->ctx
= amdgpu_ctx_get(fpriv
, cs
->in
.ctx_id
);
153 p
->bo_list
= amdgpu_bo_list_get(fpriv
, cs
->in
.bo_list_handle
);
156 INIT_LIST_HEAD(&p
->validated
);
157 chunk_array_user
= (uint64_t __user
*)(unsigned long)(cs
->in
.chunks
);
158 if (copy_from_user(chunk_array
, chunk_array_user
,
159 sizeof(uint64_t)*cs
->in
.num_chunks
)) {
164 p
->nchunks
= cs
->in
.num_chunks
;
165 p
->chunks
= kmalloc_array(p
->nchunks
, sizeof(struct amdgpu_cs_chunk
),
172 for (i
= 0; i
< p
->nchunks
; i
++) {
173 struct drm_amdgpu_cs_chunk __user
**chunk_ptr
= NULL
;
174 struct drm_amdgpu_cs_chunk user_chunk
;
175 uint32_t __user
*cdata
;
177 chunk_ptr
= (void __user
*)(unsigned long)chunk_array
[i
];
178 if (copy_from_user(&user_chunk
, chunk_ptr
,
179 sizeof(struct drm_amdgpu_cs_chunk
))) {
182 goto free_partial_kdata
;
184 p
->chunks
[i
].chunk_id
= user_chunk
.chunk_id
;
185 p
->chunks
[i
].length_dw
= user_chunk
.length_dw
;
187 size
= p
->chunks
[i
].length_dw
;
188 cdata
= (void __user
*)(unsigned long)user_chunk
.chunk_data
;
189 p
->chunks
[i
].user_ptr
= cdata
;
191 p
->chunks
[i
].kdata
= drm_malloc_ab(size
, sizeof(uint32_t));
192 if (p
->chunks
[i
].kdata
== NULL
) {
195 goto free_partial_kdata
;
197 size
*= sizeof(uint32_t);
198 if (copy_from_user(p
->chunks
[i
].kdata
, cdata
, size
)) {
200 goto free_partial_kdata
;
203 switch (p
->chunks
[i
].chunk_id
) {
204 case AMDGPU_CHUNK_ID_IB
:
208 case AMDGPU_CHUNK_ID_FENCE
:
209 size
= sizeof(struct drm_amdgpu_cs_chunk_fence
);
210 if (p
->chunks
[i
].length_dw
* sizeof(uint32_t) >= size
) {
212 struct drm_gem_object
*gobj
;
213 struct drm_amdgpu_cs_chunk_fence
*fence_data
;
215 fence_data
= (void *)p
->chunks
[i
].kdata
;
216 handle
= fence_data
->handle
;
217 gobj
= drm_gem_object_lookup(p
->adev
->ddev
,
221 goto free_partial_kdata
;
224 p
->uf
.bo
= gem_to_amdgpu_bo(gobj
);
225 p
->uf
.offset
= fence_data
->offset
;
228 goto free_partial_kdata
;
232 case AMDGPU_CHUNK_ID_DEPENDENCIES
:
237 goto free_partial_kdata
;
242 p
->ibs
= kcalloc(p
->num_ibs
, sizeof(struct amdgpu_ib
), GFP_KERNEL
);
255 drm_free_large(p
->chunks
[i
].kdata
);
259 amdgpu_bo_list_put(p
->bo_list
);
260 amdgpu_ctx_put(p
->ctx
);
267 /* Returns how many bytes TTM can move per IB.
269 static u64
amdgpu_cs_get_threshold_for_moves(struct amdgpu_device
*adev
)
271 u64 real_vram_size
= adev
->mc
.real_vram_size
;
272 u64 vram_usage
= atomic64_read(&adev
->vram_usage
);
274 /* This function is based on the current VRAM usage.
276 * - If all of VRAM is free, allow relocating the number of bytes that
277 * is equal to 1/4 of the size of VRAM for this IB.
279 * - If more than one half of VRAM is occupied, only allow relocating
280 * 1 MB of data for this IB.
282 * - From 0 to one half of used VRAM, the threshold decreases
297 * Note: It's a threshold, not a limit. The threshold must be crossed
298 * for buffer relocations to stop, so any buffer of an arbitrary size
299 * can be moved as long as the threshold isn't crossed before
300 * the relocation takes place. We don't want to disable buffer
301 * relocations completely.
303 * The idea is that buffers should be placed in VRAM at creation time
304 * and TTM should only do a minimum number of relocations during
305 * command submission. In practice, you need to submit at least
306 * a dozen IBs to move all buffers to VRAM if they are in GTT.
308 * Also, things can get pretty crazy under memory pressure and actual
309 * VRAM usage can change a lot, so playing safe even at 50% does
310 * consistently increase performance.
313 u64 half_vram
= real_vram_size
>> 1;
314 u64 half_free_vram
= vram_usage
>= half_vram
? 0 : half_vram
- vram_usage
;
315 u64 bytes_moved_threshold
= half_free_vram
>> 1;
316 return max(bytes_moved_threshold
, 1024*1024ull);
319 int amdgpu_cs_list_validate(struct amdgpu_device
*adev
,
320 struct amdgpu_vm
*vm
,
321 struct list_head
*validated
)
323 struct amdgpu_bo_list_entry
*lobj
;
324 struct amdgpu_bo
*bo
;
325 u64 bytes_moved
= 0, initial_bytes_moved
;
326 u64 bytes_moved_threshold
= amdgpu_cs_get_threshold_for_moves(adev
);
329 list_for_each_entry(lobj
, validated
, tv
.head
) {
331 if (!bo
->pin_count
) {
332 u32 domain
= lobj
->prefered_domains
;
334 amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
336 /* Check if this buffer will be moved and don't move it
337 * if we have moved too many buffers for this IB already.
339 * Note that this allows moving at least one buffer of
340 * any size, because it doesn't take the current "bo"
341 * into account. We don't want to disallow buffer moves
344 if ((lobj
->allowed_domains
& current_domain
) != 0 &&
345 (domain
& current_domain
) == 0 && /* will be moved */
346 bytes_moved
> bytes_moved_threshold
) {
348 domain
= current_domain
;
352 amdgpu_ttm_placement_from_domain(bo
, domain
);
353 initial_bytes_moved
= atomic64_read(&adev
->num_bytes_moved
);
354 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
355 bytes_moved
+= atomic64_read(&adev
->num_bytes_moved
) -
359 if (r
!= -ERESTARTSYS
&& domain
!= lobj
->allowed_domains
) {
360 domain
= lobj
->allowed_domains
;
366 lobj
->bo_va
= amdgpu_vm_bo_find(vm
, bo
);
371 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser
*p
)
373 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
374 struct amdgpu_cs_buckets buckets
;
375 struct list_head duplicates
;
376 bool need_mmap_lock
= false;
380 need_mmap_lock
= p
->bo_list
->has_userptr
;
381 amdgpu_cs_buckets_init(&buckets
);
382 for (i
= 0; i
< p
->bo_list
->num_entries
; i
++)
383 amdgpu_cs_buckets_add(&buckets
, &p
->bo_list
->array
[i
].tv
.head
,
384 p
->bo_list
->array
[i
].priority
);
386 amdgpu_cs_buckets_get_list(&buckets
, &p
->validated
);
389 p
->vm_bos
= amdgpu_vm_get_bos(p
->adev
, &fpriv
->vm
,
393 down_read(¤t
->mm
->mmap_sem
);
395 INIT_LIST_HEAD(&duplicates
);
396 r
= ttm_eu_reserve_buffers(&p
->ticket
, &p
->validated
, true, &duplicates
);
397 if (unlikely(r
!= 0))
400 r
= amdgpu_cs_list_validate(p
->adev
, &fpriv
->vm
, &p
->validated
);
404 r
= amdgpu_cs_list_validate(p
->adev
, &fpriv
->vm
, &duplicates
);
408 ttm_eu_backoff_reservation(&p
->ticket
, &p
->validated
);
412 up_read(¤t
->mm
->mmap_sem
);
417 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser
*p
)
419 struct amdgpu_bo_list_entry
*e
;
422 list_for_each_entry(e
, &p
->validated
, tv
.head
) {
423 struct reservation_object
*resv
= e
->robj
->tbo
.resv
;
424 r
= amdgpu_sync_resv(p
->adev
, &p
->ibs
[0].sync
, resv
, p
->filp
);
432 static int cmp_size_smaller_first(void *priv
, struct list_head
*a
,
435 struct amdgpu_bo_list_entry
*la
= list_entry(a
, struct amdgpu_bo_list_entry
, tv
.head
);
436 struct amdgpu_bo_list_entry
*lb
= list_entry(b
, struct amdgpu_bo_list_entry
, tv
.head
);
438 /* Sort A before B if A is smaller. */
439 return (int)la
->robj
->tbo
.num_pages
- (int)lb
->robj
->tbo
.num_pages
;
443 * cs_parser_fini() - clean parser states
444 * @parser: parser structure holding parsing context.
445 * @error: error number
447 * If error is set than unvalidate buffer, otherwise just free memory
448 * used by parsing context.
450 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser
*parser
, int error
, bool backoff
)
455 /* Sort the buffer list from the smallest to largest buffer,
456 * which affects the order of buffers in the LRU list.
457 * This assures that the smallest buffers are added first
458 * to the LRU list, so they are likely to be later evicted
459 * first, instead of large buffers whose eviction is more
462 * This slightly lowers the number of bytes moved by TTM
463 * per frame under memory pressure.
465 list_sort(NULL
, &parser
->validated
, cmp_size_smaller_first
);
467 ttm_eu_fence_buffer_objects(&parser
->ticket
,
470 } else if (backoff
) {
471 ttm_eu_backoff_reservation(&parser
->ticket
,
474 fence_put(parser
->fence
);
477 amdgpu_ctx_put(parser
->ctx
);
479 amdgpu_bo_list_put(parser
->bo_list
);
481 drm_free_large(parser
->vm_bos
);
482 for (i
= 0; i
< parser
->nchunks
; i
++)
483 drm_free_large(parser
->chunks
[i
].kdata
);
484 kfree(parser
->chunks
);
486 for (i
= 0; i
< parser
->num_ibs
; i
++)
487 amdgpu_ib_free(parser
->adev
, &parser
->ibs
[i
]);
490 drm_gem_object_unreference_unlocked(&parser
->uf
.bo
->gem_base
);
493 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser
*p
,
494 struct amdgpu_vm
*vm
)
496 struct amdgpu_device
*adev
= p
->adev
;
497 struct amdgpu_bo_va
*bo_va
;
498 struct amdgpu_bo
*bo
;
501 r
= amdgpu_vm_update_page_directory(adev
, vm
);
505 r
= amdgpu_sync_fence(adev
, &p
->ibs
[0].sync
, vm
->page_directory_fence
);
509 r
= amdgpu_vm_clear_freed(adev
, vm
);
514 for (i
= 0; i
< p
->bo_list
->num_entries
; i
++) {
517 /* ignore duplicates */
518 bo
= p
->bo_list
->array
[i
].robj
;
522 bo_va
= p
->bo_list
->array
[i
].bo_va
;
526 r
= amdgpu_vm_bo_update(adev
, bo_va
, &bo
->tbo
.mem
);
530 f
= bo_va
->last_pt_update
;
531 r
= amdgpu_sync_fence(adev
, &p
->ibs
[0].sync
, f
);
538 r
= amdgpu_vm_clear_invalids(adev
, vm
, &p
->ibs
[0].sync
);
540 if (amdgpu_vm_debug
&& p
->bo_list
) {
541 /* Invalidate all BOs to test for userspace bugs */
542 for (i
= 0; i
< p
->bo_list
->num_entries
; i
++) {
543 /* ignore duplicates */
544 bo
= p
->bo_list
->array
[i
].robj
;
548 amdgpu_vm_bo_invalidate(adev
, bo
);
555 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device
*adev
,
556 struct amdgpu_cs_parser
*parser
)
558 struct amdgpu_fpriv
*fpriv
= parser
->filp
->driver_priv
;
559 struct amdgpu_vm
*vm
= &fpriv
->vm
;
560 struct amdgpu_ring
*ring
;
563 if (parser
->num_ibs
== 0)
566 /* Only for UVD/VCE VM emulation */
567 for (i
= 0; i
< parser
->num_ibs
; i
++) {
568 ring
= parser
->ibs
[i
].ring
;
569 if (ring
->funcs
->parse_cs
) {
570 r
= amdgpu_ring_parse_cs(ring
, parser
, i
);
576 r
= amdgpu_bo_vm_update_pte(parser
, vm
);
578 amdgpu_cs_sync_rings(parser
);
583 static int amdgpu_cs_handle_lockup(struct amdgpu_device
*adev
, int r
)
586 r
= amdgpu_gpu_reset(adev
);
593 static int amdgpu_cs_ib_fill(struct amdgpu_device
*adev
,
594 struct amdgpu_cs_parser
*parser
)
596 struct amdgpu_fpriv
*fpriv
= parser
->filp
->driver_priv
;
597 struct amdgpu_vm
*vm
= &fpriv
->vm
;
601 for (i
= 0, j
= 0; i
< parser
->nchunks
&& j
< parser
->num_ibs
; i
++) {
602 struct amdgpu_cs_chunk
*chunk
;
603 struct amdgpu_ib
*ib
;
604 struct drm_amdgpu_cs_chunk_ib
*chunk_ib
;
605 struct amdgpu_ring
*ring
;
607 chunk
= &parser
->chunks
[i
];
608 ib
= &parser
->ibs
[j
];
609 chunk_ib
= (struct drm_amdgpu_cs_chunk_ib
*)chunk
->kdata
;
611 if (chunk
->chunk_id
!= AMDGPU_CHUNK_ID_IB
)
614 r
= amdgpu_cs_get_ring(adev
, chunk_ib
->ip_type
,
615 chunk_ib
->ip_instance
, chunk_ib
->ring
,
620 if (ring
->funcs
->parse_cs
) {
621 struct amdgpu_bo_va_mapping
*m
;
622 struct amdgpu_bo
*aobj
= NULL
;
626 m
= amdgpu_cs_find_mapping(parser
, chunk_ib
->va_start
,
629 DRM_ERROR("IB va_start is invalid\n");
633 if ((chunk_ib
->va_start
+ chunk_ib
->ib_bytes
) >
634 (m
->it
.last
+ 1) * AMDGPU_GPU_PAGE_SIZE
) {
635 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
639 /* the IB should be reserved at this point */
640 r
= amdgpu_bo_kmap(aobj
, (void **)&kptr
);
645 offset
= ((uint64_t)m
->it
.start
) * AMDGPU_GPU_PAGE_SIZE
;
646 kptr
+= chunk_ib
->va_start
- offset
;
648 r
= amdgpu_ib_get(ring
, NULL
, chunk_ib
->ib_bytes
, ib
);
650 DRM_ERROR("Failed to get ib !\n");
654 memcpy(ib
->ptr
, kptr
, chunk_ib
->ib_bytes
);
655 amdgpu_bo_kunmap(aobj
);
657 r
= amdgpu_ib_get(ring
, vm
, 0, ib
);
659 DRM_ERROR("Failed to get ib !\n");
663 ib
->gpu_addr
= chunk_ib
->va_start
;
666 ib
->length_dw
= chunk_ib
->ib_bytes
/ 4;
667 ib
->flags
= chunk_ib
->flags
;
668 ib
->ctx
= parser
->ctx
;
672 if (!parser
->num_ibs
)
675 /* add GDS resources to first IB */
676 if (parser
->bo_list
) {
677 struct amdgpu_bo
*gds
= parser
->bo_list
->gds_obj
;
678 struct amdgpu_bo
*gws
= parser
->bo_list
->gws_obj
;
679 struct amdgpu_bo
*oa
= parser
->bo_list
->oa_obj
;
680 struct amdgpu_ib
*ib
= &parser
->ibs
[0];
683 ib
->gds_base
= amdgpu_bo_gpu_offset(gds
);
684 ib
->gds_size
= amdgpu_bo_size(gds
);
687 ib
->gws_base
= amdgpu_bo_gpu_offset(gws
);
688 ib
->gws_size
= amdgpu_bo_size(gws
);
691 ib
->oa_base
= amdgpu_bo_gpu_offset(oa
);
692 ib
->oa_size
= amdgpu_bo_size(oa
);
695 /* wrap the last IB with user fence */
697 struct amdgpu_ib
*ib
= &parser
->ibs
[parser
->num_ibs
- 1];
699 /* UVD & VCE fw doesn't support user fences */
700 if (ib
->ring
->type
== AMDGPU_RING_TYPE_UVD
||
701 ib
->ring
->type
== AMDGPU_RING_TYPE_VCE
)
704 ib
->user
= &parser
->uf
;
710 static int amdgpu_cs_dependencies(struct amdgpu_device
*adev
,
711 struct amdgpu_cs_parser
*p
)
713 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
714 struct amdgpu_ib
*ib
;
720 /* Add dependencies to first IB */
722 for (i
= 0; i
< p
->nchunks
; ++i
) {
723 struct drm_amdgpu_cs_chunk_dep
*deps
;
724 struct amdgpu_cs_chunk
*chunk
;
727 chunk
= &p
->chunks
[i
];
729 if (chunk
->chunk_id
!= AMDGPU_CHUNK_ID_DEPENDENCIES
)
732 deps
= (struct drm_amdgpu_cs_chunk_dep
*)chunk
->kdata
;
733 num_deps
= chunk
->length_dw
* 4 /
734 sizeof(struct drm_amdgpu_cs_chunk_dep
);
736 for (j
= 0; j
< num_deps
; ++j
) {
737 struct amdgpu_ring
*ring
;
738 struct amdgpu_ctx
*ctx
;
741 r
= amdgpu_cs_get_ring(adev
, deps
[j
].ip_type
,
743 deps
[j
].ring
, &ring
);
747 ctx
= amdgpu_ctx_get(fpriv
, deps
[j
].ctx_id
);
751 fence
= amdgpu_ctx_get_fence(ctx
, ring
,
759 r
= amdgpu_sync_fence(adev
, &ib
->sync
, fence
);
771 static int amdgpu_cs_free_job(struct amdgpu_job
*job
)
775 for (i
= 0; i
< job
->num_ibs
; i
++)
776 amdgpu_ib_free(job
->adev
, &job
->ibs
[i
]);
779 drm_gem_object_unreference_unlocked(&job
->uf
.bo
->gem_base
);
783 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
785 struct amdgpu_device
*adev
= dev
->dev_private
;
786 union drm_amdgpu_cs
*cs
= data
;
787 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
788 struct amdgpu_vm
*vm
= &fpriv
->vm
;
789 struct amdgpu_cs_parser parser
= {};
790 bool reserved_buffers
= false;
793 if (!adev
->accel_working
)
799 r
= amdgpu_cs_parser_init(&parser
, data
);
801 DRM_ERROR("Failed to initialize parser !\n");
802 amdgpu_cs_parser_fini(&parser
, r
, false);
803 r
= amdgpu_cs_handle_lockup(adev
, r
);
806 mutex_lock(&vm
->mutex
);
807 r
= amdgpu_cs_parser_relocs(&parser
);
809 DRM_ERROR("Not enough memory for command submission!\n");
810 else if (r
&& r
!= -ERESTARTSYS
)
811 DRM_ERROR("Failed to process the buffer list %d!\n", r
);
813 reserved_buffers
= true;
814 r
= amdgpu_cs_ib_fill(adev
, &parser
);
818 r
= amdgpu_cs_dependencies(adev
, &parser
);
820 DRM_ERROR("Failed in the dependencies handling %d!\n", r
);
826 for (i
= 0; i
< parser
.num_ibs
; i
++)
827 trace_amdgpu_cs(&parser
, i
);
829 r
= amdgpu_cs_ib_vm_chunk(adev
, &parser
);
833 if (amdgpu_enable_scheduler
&& parser
.num_ibs
) {
834 struct amdgpu_ring
* ring
= parser
.ibs
->ring
;
835 struct amd_sched_fence
*fence
;
836 struct amdgpu_job
*job
;
838 job
= kzalloc(sizeof(struct amdgpu_job
), GFP_KERNEL
);
844 job
->base
.sched
= &ring
->sched
;
845 job
->base
.s_entity
= &parser
.ctx
->rings
[ring
->idx
].entity
;
846 job
->adev
= parser
.adev
;
847 job
->owner
= parser
.filp
;
848 job
->free_job
= amdgpu_cs_free_job
;
850 job
->ibs
= parser
.ibs
;
851 job
->num_ibs
= parser
.num_ibs
;
855 if (job
->ibs
[job
->num_ibs
- 1].user
) {
857 job
->ibs
[job
->num_ibs
- 1].user
= &job
->uf
;
861 fence
= amd_sched_fence_create(job
->base
.s_entity
,
865 amdgpu_cs_free_job(job
);
869 job
->base
.s_fence
= fence
;
870 parser
.fence
= fence_get(&fence
->base
);
872 cs
->out
.handle
= amdgpu_ctx_add_fence(parser
.ctx
, ring
,
874 job
->ibs
[job
->num_ibs
- 1].sequence
= cs
->out
.handle
;
876 trace_amdgpu_cs_ioctl(job
);
877 amd_sched_entity_push_job(&job
->base
);
880 struct amdgpu_fence
*fence
;
882 r
= amdgpu_ib_schedule(adev
, parser
.num_ibs
, parser
.ibs
,
884 fence
= parser
.ibs
[parser
.num_ibs
- 1].fence
;
885 parser
.fence
= fence_get(&fence
->base
);
886 cs
->out
.handle
= parser
.ibs
[parser
.num_ibs
- 1].sequence
;
890 amdgpu_cs_parser_fini(&parser
, r
, reserved_buffers
);
891 mutex_unlock(&vm
->mutex
);
892 r
= amdgpu_cs_handle_lockup(adev
, r
);
897 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
900 * @data: data from userspace
901 * @filp: file private
903 * Wait for the command submission identified by handle to finish.
905 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
,
906 struct drm_file
*filp
)
908 union drm_amdgpu_wait_cs
*wait
= data
;
909 struct amdgpu_device
*adev
= dev
->dev_private
;
910 unsigned long timeout
= amdgpu_gem_timeout(wait
->in
.timeout
);
911 struct amdgpu_ring
*ring
= NULL
;
912 struct amdgpu_ctx
*ctx
;
916 r
= amdgpu_cs_get_ring(adev
, wait
->in
.ip_type
, wait
->in
.ip_instance
,
917 wait
->in
.ring
, &ring
);
921 ctx
= amdgpu_ctx_get(filp
->driver_priv
, wait
->in
.ctx_id
);
925 fence
= amdgpu_ctx_get_fence(ctx
, ring
, wait
->in
.handle
);
929 r
= fence_wait_timeout(fence
, true, timeout
);
938 memset(wait
, 0, sizeof(*wait
));
939 wait
->out
.status
= (r
== 0);
945 * amdgpu_cs_find_bo_va - find bo_va for VM address
947 * @parser: command submission parser context
949 * @bo: resulting BO of the mapping found
951 * Search the buffer objects in the command submission context for a certain
952 * virtual memory address. Returns allocation structure when found, NULL
955 struct amdgpu_bo_va_mapping
*
956 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
957 uint64_t addr
, struct amdgpu_bo
**bo
)
959 struct amdgpu_bo_list_entry
*reloc
;
960 struct amdgpu_bo_va_mapping
*mapping
;
962 addr
/= AMDGPU_GPU_PAGE_SIZE
;
964 list_for_each_entry(reloc
, &parser
->validated
, tv
.head
) {
968 list_for_each_entry(mapping
, &reloc
->bo_va
->valids
, list
) {
969 if (mapping
->it
.start
> addr
||
970 addr
> mapping
->it
.last
)
973 *bo
= reloc
->bo_va
->bo
;
977 list_for_each_entry(mapping
, &reloc
->bo_va
->invalids
, list
) {
978 if (mapping
->it
.start
> addr
||
979 addr
> mapping
->it
.last
)
982 *bo
= reloc
->bo_va
->bo
;