2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/kthread.h>
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/pm_runtime.h>
32 #include "amdgpu_pm.h"
33 #include "amdgpu_dm_debugfs.h"
34 #include "amdgpu_ras.h"
35 #include "amdgpu_rap.h"
36 #include "amdgpu_securedisplay.h"
37 #include "amdgpu_fw_attestation.h"
38 #include "amdgpu_umr.h"
40 #include "amdgpu_reset.h"
41 #include "amdgpu_psp_ta.h"
43 #if defined(CONFIG_DEBUG_FS)
46 * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
48 * @read: True if reading
49 * @f: open file handle
50 * @buf: User buffer to write/read to
51 * @size: Number of bytes to write/read
52 * @pos: Offset to seek to
54 * This debugfs entry has special meaning on the offset being sought.
55 * Various bits have different meanings:
57 * Bit 62: Indicates a GRBM bank switch is needed
58 * Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is
60 * Bits 24..33: The SE or ME selector if needed
61 * Bits 34..43: The SH (or SA) or PIPE selector if needed
62 * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
64 * Bit 23: Indicates that the PM power gating lock should be held
65 * This is necessary to read registers that might be
66 * unreliable during a power gating transistion.
68 * The lower bits are the BYTE offset of the register to read. This
69 * allows reading multiple registers in a single call and having
70 * the returned size reflect that.
72 static int amdgpu_debugfs_process_reg_op(bool read
, struct file
*f
,
73 char __user
*buf
, size_t size
, loff_t
*pos
)
75 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
78 bool pm_pg_lock
, use_bank
, use_ring
;
79 unsigned int instance_bank
, sh_bank
, se_bank
, me
, pipe
, queue
, vmid
;
81 pm_pg_lock
= use_bank
= use_ring
= false;
82 instance_bank
= sh_bank
= se_bank
= me
= pipe
= queue
= vmid
= 0;
84 if (size
& 0x3 || *pos
& 0x3 ||
85 ((*pos
& (1ULL << 62)) && (*pos
& (1ULL << 61))))
88 /* are we reading registers for which a PG lock is necessary? */
89 pm_pg_lock
= (*pos
>> 23) & 1;
91 if (*pos
& (1ULL << 62)) {
92 se_bank
= (*pos
& GENMASK_ULL(33, 24)) >> 24;
93 sh_bank
= (*pos
& GENMASK_ULL(43, 34)) >> 34;
94 instance_bank
= (*pos
& GENMASK_ULL(53, 44)) >> 44;
100 if (instance_bank
== 0x3FF)
101 instance_bank
= 0xFFFFFFFF;
103 } else if (*pos
& (1ULL << 61)) {
105 me
= (*pos
& GENMASK_ULL(33, 24)) >> 24;
106 pipe
= (*pos
& GENMASK_ULL(43, 34)) >> 34;
107 queue
= (*pos
& GENMASK_ULL(53, 44)) >> 44;
108 vmid
= (*pos
& GENMASK_ULL(58, 54)) >> 54;
112 use_bank
= use_ring
= false;
115 *pos
&= (1UL << 22) - 1;
117 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
119 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
123 r
= amdgpu_virt_enable_access_debugfs(adev
);
125 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
130 if ((sh_bank
!= 0xFFFFFFFF && sh_bank
>= adev
->gfx
.config
.max_sh_per_se
) ||
131 (se_bank
!= 0xFFFFFFFF && se_bank
>= adev
->gfx
.config
.max_shader_engines
)) {
132 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
133 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
134 amdgpu_virt_disable_access_debugfs(adev
);
137 mutex_lock(&adev
->grbm_idx_mutex
);
138 amdgpu_gfx_select_se_sh(adev
, se_bank
,
139 sh_bank
, instance_bank
, 0);
140 } else if (use_ring
) {
141 mutex_lock(&adev
->srbm_mutex
);
142 amdgpu_gfx_select_me_pipe_q(adev
, me
, pipe
, queue
, vmid
, 0);
146 mutex_lock(&adev
->pm
.mutex
);
152 value
= RREG32(*pos
>> 2);
153 r
= put_user(value
, (uint32_t *)buf
);
155 r
= get_user(value
, (uint32_t *)buf
);
157 amdgpu_mm_wreg_mmio_rlc(adev
, *pos
>> 2, value
, 0);
172 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff, 0);
173 mutex_unlock(&adev
->grbm_idx_mutex
);
174 } else if (use_ring
) {
175 amdgpu_gfx_select_me_pipe_q(adev
, 0, 0, 0, 0, 0);
176 mutex_unlock(&adev
->srbm_mutex
);
180 mutex_unlock(&adev
->pm
.mutex
);
182 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
183 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
185 amdgpu_virt_disable_access_debugfs(adev
);
190 * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
192 static ssize_t
amdgpu_debugfs_regs_read(struct file
*f
, char __user
*buf
,
193 size_t size
, loff_t
*pos
)
195 return amdgpu_debugfs_process_reg_op(true, f
, buf
, size
, pos
);
199 * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
201 static ssize_t
amdgpu_debugfs_regs_write(struct file
*f
, const char __user
*buf
,
202 size_t size
, loff_t
*pos
)
204 return amdgpu_debugfs_process_reg_op(false, f
, (char __user
*)buf
, size
, pos
);
207 static int amdgpu_debugfs_regs2_open(struct inode
*inode
, struct file
*file
)
209 struct amdgpu_debugfs_regs2_data
*rd
;
211 rd
= kzalloc(sizeof(*rd
), GFP_KERNEL
);
214 rd
->adev
= file_inode(file
)->i_private
;
215 file
->private_data
= rd
;
216 mutex_init(&rd
->lock
);
221 static int amdgpu_debugfs_regs2_release(struct inode
*inode
, struct file
*file
)
223 struct amdgpu_debugfs_regs2_data
*rd
= file
->private_data
;
225 mutex_destroy(&rd
->lock
);
226 kfree(file
->private_data
);
230 static ssize_t
amdgpu_debugfs_regs2_op(struct file
*f
, char __user
*buf
, u32 offset
, size_t size
, int write_en
)
232 struct amdgpu_debugfs_regs2_data
*rd
= f
->private_data
;
233 struct amdgpu_device
*adev
= rd
->adev
;
238 if (size
& 0x3 || offset
& 0x3)
241 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
243 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
247 r
= amdgpu_virt_enable_access_debugfs(adev
);
249 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
253 mutex_lock(&rd
->lock
);
255 if (rd
->id
.use_grbm
) {
256 if ((rd
->id
.grbm
.sh
!= 0xFFFFFFFF && rd
->id
.grbm
.sh
>= adev
->gfx
.config
.max_sh_per_se
) ||
257 (rd
->id
.grbm
.se
!= 0xFFFFFFFF && rd
->id
.grbm
.se
>= adev
->gfx
.config
.max_shader_engines
)) {
258 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
259 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
260 amdgpu_virt_disable_access_debugfs(adev
);
261 mutex_unlock(&rd
->lock
);
264 mutex_lock(&adev
->grbm_idx_mutex
);
265 amdgpu_gfx_select_se_sh(adev
, rd
->id
.grbm
.se
,
267 rd
->id
.grbm
.instance
, rd
->id
.xcc_id
);
270 if (rd
->id
.use_srbm
) {
271 mutex_lock(&adev
->srbm_mutex
);
272 amdgpu_gfx_select_me_pipe_q(adev
, rd
->id
.srbm
.me
, rd
->id
.srbm
.pipe
,
273 rd
->id
.srbm
.queue
, rd
->id
.srbm
.vmid
, rd
->id
.xcc_id
);
277 mutex_lock(&adev
->pm
.mutex
);
281 value
= RREG32(offset
>> 2);
282 r
= put_user(value
, (uint32_t *)buf
);
284 r
= get_user(value
, (uint32_t *)buf
);
286 amdgpu_mm_wreg_mmio_rlc(adev
, offset
>> 2, value
, rd
->id
.xcc_id
);
298 if (rd
->id
.use_grbm
) {
299 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff, rd
->id
.xcc_id
);
300 mutex_unlock(&adev
->grbm_idx_mutex
);
303 if (rd
->id
.use_srbm
) {
304 amdgpu_gfx_select_me_pipe_q(adev
, 0, 0, 0, 0, rd
->id
.xcc_id
);
305 mutex_unlock(&adev
->srbm_mutex
);
309 mutex_unlock(&adev
->pm
.mutex
);
311 mutex_unlock(&rd
->lock
);
313 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
314 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
316 amdgpu_virt_disable_access_debugfs(adev
);
320 static long amdgpu_debugfs_regs2_ioctl(struct file
*f
, unsigned int cmd
, unsigned long data
)
322 struct amdgpu_debugfs_regs2_data
*rd
= f
->private_data
;
323 struct amdgpu_debugfs_regs2_iocdata v1_data
;
326 mutex_lock(&rd
->lock
);
329 case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2
:
330 r
= copy_from_user(&rd
->id
, (struct amdgpu_debugfs_regs2_iocdata_v2
*)data
,
335 case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE
:
336 r
= copy_from_user(&v1_data
, (struct amdgpu_debugfs_regs2_iocdata
*)data
,
349 rd
->id
.use_srbm
= v1_data
.use_srbm
;
350 rd
->id
.use_grbm
= v1_data
.use_grbm
;
351 rd
->id
.pg_lock
= v1_data
.pg_lock
;
352 rd
->id
.grbm
.se
= v1_data
.grbm
.se
;
353 rd
->id
.grbm
.sh
= v1_data
.grbm
.sh
;
354 rd
->id
.grbm
.instance
= v1_data
.grbm
.instance
;
355 rd
->id
.srbm
.me
= v1_data
.srbm
.me
;
356 rd
->id
.srbm
.pipe
= v1_data
.srbm
.pipe
;
357 rd
->id
.srbm
.queue
= v1_data
.srbm
.queue
;
360 mutex_unlock(&rd
->lock
);
364 static ssize_t
amdgpu_debugfs_regs2_read(struct file
*f
, char __user
*buf
, size_t size
, loff_t
*pos
)
366 return amdgpu_debugfs_regs2_op(f
, buf
, *pos
, size
, 0);
369 static ssize_t
amdgpu_debugfs_regs2_write(struct file
*f
, const char __user
*buf
, size_t size
, loff_t
*pos
)
371 return amdgpu_debugfs_regs2_op(f
, (char __user
*)buf
, *pos
, size
, 1);
374 static int amdgpu_debugfs_gprwave_open(struct inode
*inode
, struct file
*file
)
376 struct amdgpu_debugfs_gprwave_data
*rd
;
378 rd
= kzalloc(sizeof(*rd
), GFP_KERNEL
);
381 rd
->adev
= file_inode(file
)->i_private
;
382 file
->private_data
= rd
;
383 mutex_init(&rd
->lock
);
388 static int amdgpu_debugfs_gprwave_release(struct inode
*inode
, struct file
*file
)
390 struct amdgpu_debugfs_gprwave_data
*rd
= file
->private_data
;
392 mutex_destroy(&rd
->lock
);
393 kfree(file
->private_data
);
397 static ssize_t
amdgpu_debugfs_gprwave_read(struct file
*f
, char __user
*buf
, size_t size
, loff_t
*pos
)
399 struct amdgpu_debugfs_gprwave_data
*rd
= f
->private_data
;
400 struct amdgpu_device
*adev
= rd
->adev
;
405 if (size
& 0x3 || *pos
& 0x3)
408 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
410 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
414 r
= amdgpu_virt_enable_access_debugfs(adev
);
416 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
420 data
= kcalloc(1024, sizeof(*data
), GFP_KERNEL
);
422 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
423 amdgpu_virt_disable_access_debugfs(adev
);
427 /* switch to the specific se/sh/cu */
428 mutex_lock(&adev
->grbm_idx_mutex
);
429 amdgpu_gfx_select_se_sh(adev
, rd
->id
.se
, rd
->id
.sh
, rd
->id
.cu
, rd
->id
.xcc_id
);
431 if (!rd
->id
.gpr_or_wave
) {
433 if (adev
->gfx
.funcs
->read_wave_data
)
434 adev
->gfx
.funcs
->read_wave_data(adev
, rd
->id
.xcc_id
, rd
->id
.simd
, rd
->id
.wave
, data
, &x
);
437 if (rd
->id
.gpr
.vpgr_or_sgpr
) {
438 if (adev
->gfx
.funcs
->read_wave_vgprs
)
439 adev
->gfx
.funcs
->read_wave_vgprs(adev
, rd
->id
.xcc_id
, rd
->id
.simd
, rd
->id
.wave
, rd
->id
.gpr
.thread
, *pos
, size
>>2, data
);
441 if (adev
->gfx
.funcs
->read_wave_sgprs
)
442 adev
->gfx
.funcs
->read_wave_sgprs(adev
, rd
->id
.xcc_id
, rd
->id
.simd
, rd
->id
.wave
, *pos
, size
>>2, data
);
446 amdgpu_gfx_select_se_sh(adev
, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, rd
->id
.xcc_id
);
447 mutex_unlock(&adev
->grbm_idx_mutex
);
449 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
450 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
457 while (size
&& (*pos
< x
* 4)) {
460 value
= data
[*pos
>> 2];
461 r
= put_user(value
, (uint32_t *)buf
);
474 amdgpu_virt_disable_access_debugfs(adev
);
479 static long amdgpu_debugfs_gprwave_ioctl(struct file
*f
, unsigned int cmd
, unsigned long data
)
481 struct amdgpu_debugfs_gprwave_data
*rd
= f
->private_data
;
484 mutex_lock(&rd
->lock
);
487 case AMDGPU_DEBUGFS_GPRWAVE_IOC_SET_STATE
:
488 if (copy_from_user(&rd
->id
,
489 (struct amdgpu_debugfs_gprwave_iocdata
*)data
,
499 mutex_unlock(&rd
->lock
);
507 * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
509 * @f: open file handle
510 * @buf: User buffer to store read data in
511 * @size: Number of bytes to read
512 * @pos: Offset to seek to
514 * The lower bits are the BYTE offset of the register to read. This
515 * allows reading multiple registers in a single call and having
516 * the returned size reflect that.
518 static ssize_t
amdgpu_debugfs_regs_pcie_read(struct file
*f
, char __user
*buf
,
519 size_t size
, loff_t
*pos
)
521 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
525 if (size
& 0x3 || *pos
& 0x3)
528 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
530 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
534 r
= amdgpu_virt_enable_access_debugfs(adev
);
536 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
543 value
= RREG32_PCIE(*pos
);
544 r
= put_user(value
, (uint32_t *)buf
);
556 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
557 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
558 amdgpu_virt_disable_access_debugfs(adev
);
563 * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
565 * @f: open file handle
566 * @buf: User buffer to write data from
567 * @size: Number of bytes to write
568 * @pos: Offset to seek to
570 * The lower bits are the BYTE offset of the register to write. This
571 * allows writing multiple registers in a single call and having
572 * the returned size reflect that.
574 static ssize_t
amdgpu_debugfs_regs_pcie_write(struct file
*f
, const char __user
*buf
,
575 size_t size
, loff_t
*pos
)
577 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
581 if (size
& 0x3 || *pos
& 0x3)
584 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
586 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
590 r
= amdgpu_virt_enable_access_debugfs(adev
);
592 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
599 r
= get_user(value
, (uint32_t *)buf
);
603 WREG32_PCIE(*pos
, value
);
613 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
614 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
615 amdgpu_virt_disable_access_debugfs(adev
);
620 * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
622 * @f: open file handle
623 * @buf: User buffer to store read data in
624 * @size: Number of bytes to read
625 * @pos: Offset to seek to
627 * The lower bits are the BYTE offset of the register to read. This
628 * allows reading multiple registers in a single call and having
629 * the returned size reflect that.
631 static ssize_t
amdgpu_debugfs_regs_didt_read(struct file
*f
, char __user
*buf
,
632 size_t size
, loff_t
*pos
)
634 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
638 if (size
& 0x3 || *pos
& 0x3)
641 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
643 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
647 r
= amdgpu_virt_enable_access_debugfs(adev
);
649 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
656 value
= RREG32_DIDT(*pos
>> 2);
657 r
= put_user(value
, (uint32_t *)buf
);
669 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
670 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
671 amdgpu_virt_disable_access_debugfs(adev
);
676 * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
678 * @f: open file handle
679 * @buf: User buffer to write data from
680 * @size: Number of bytes to write
681 * @pos: Offset to seek to
683 * The lower bits are the BYTE offset of the register to write. This
684 * allows writing multiple registers in a single call and having
685 * the returned size reflect that.
687 static ssize_t
amdgpu_debugfs_regs_didt_write(struct file
*f
, const char __user
*buf
,
688 size_t size
, loff_t
*pos
)
690 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
694 if (size
& 0x3 || *pos
& 0x3)
697 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
699 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
703 r
= amdgpu_virt_enable_access_debugfs(adev
);
705 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
712 r
= get_user(value
, (uint32_t *)buf
);
716 WREG32_DIDT(*pos
>> 2, value
);
726 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
727 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
728 amdgpu_virt_disable_access_debugfs(adev
);
733 * amdgpu_debugfs_regs_smc_read - Read from a SMC register
735 * @f: open file handle
736 * @buf: User buffer to store read data in
737 * @size: Number of bytes to read
738 * @pos: Offset to seek to
740 * The lower bits are the BYTE offset of the register to read. This
741 * allows reading multiple registers in a single call and having
742 * the returned size reflect that.
744 static ssize_t
amdgpu_debugfs_regs_smc_read(struct file
*f
, char __user
*buf
,
745 size_t size
, loff_t
*pos
)
747 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
754 if (size
& 0x3 || *pos
& 0x3)
757 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
759 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
763 r
= amdgpu_virt_enable_access_debugfs(adev
);
765 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
772 value
= RREG32_SMC(*pos
);
773 r
= put_user(value
, (uint32_t *)buf
);
785 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
786 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
787 amdgpu_virt_disable_access_debugfs(adev
);
792 * amdgpu_debugfs_regs_smc_write - Write to a SMC register
794 * @f: open file handle
795 * @buf: User buffer to write data from
796 * @size: Number of bytes to write
797 * @pos: Offset to seek to
799 * The lower bits are the BYTE offset of the register to write. This
800 * allows writing multiple registers in a single call and having
801 * the returned size reflect that.
803 static ssize_t
amdgpu_debugfs_regs_smc_write(struct file
*f
, const char __user
*buf
,
804 size_t size
, loff_t
*pos
)
806 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
813 if (size
& 0x3 || *pos
& 0x3)
816 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
818 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
822 r
= amdgpu_virt_enable_access_debugfs(adev
);
824 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
831 r
= get_user(value
, (uint32_t *)buf
);
835 WREG32_SMC(*pos
, value
);
845 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
846 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
847 amdgpu_virt_disable_access_debugfs(adev
);
852 * amdgpu_debugfs_gca_config_read - Read from gfx config data
854 * @f: open file handle
855 * @buf: User buffer to store read data in
856 * @size: Number of bytes to read
857 * @pos: Offset to seek to
859 * This file is used to access configuration data in a somewhat
860 * stable fashion. The format is a series of DWORDs with the first
861 * indicating which revision it is. New content is appended to the
862 * end so that older software can still read the data.
865 static ssize_t
amdgpu_debugfs_gca_config_read(struct file
*f
, char __user
*buf
,
866 size_t size
, loff_t
*pos
)
868 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
871 uint32_t *config
, no_regs
= 0;
873 if (size
& 0x3 || *pos
& 0x3)
876 config
= kmalloc_array(256, sizeof(*config
), GFP_KERNEL
);
880 /* version, increment each time something is added */
881 config
[no_regs
++] = 5;
882 config
[no_regs
++] = adev
->gfx
.config
.max_shader_engines
;
883 config
[no_regs
++] = adev
->gfx
.config
.max_tile_pipes
;
884 config
[no_regs
++] = adev
->gfx
.config
.max_cu_per_sh
;
885 config
[no_regs
++] = adev
->gfx
.config
.max_sh_per_se
;
886 config
[no_regs
++] = adev
->gfx
.config
.max_backends_per_se
;
887 config
[no_regs
++] = adev
->gfx
.config
.max_texture_channel_caches
;
888 config
[no_regs
++] = adev
->gfx
.config
.max_gprs
;
889 config
[no_regs
++] = adev
->gfx
.config
.max_gs_threads
;
890 config
[no_regs
++] = adev
->gfx
.config
.max_hw_contexts
;
891 config
[no_regs
++] = adev
->gfx
.config
.sc_prim_fifo_size_frontend
;
892 config
[no_regs
++] = adev
->gfx
.config
.sc_prim_fifo_size_backend
;
893 config
[no_regs
++] = adev
->gfx
.config
.sc_hiz_tile_fifo_size
;
894 config
[no_regs
++] = adev
->gfx
.config
.sc_earlyz_tile_fifo_size
;
895 config
[no_regs
++] = adev
->gfx
.config
.num_tile_pipes
;
896 config
[no_regs
++] = adev
->gfx
.config
.backend_enable_mask
;
897 config
[no_regs
++] = adev
->gfx
.config
.mem_max_burst_length_bytes
;
898 config
[no_regs
++] = adev
->gfx
.config
.mem_row_size_in_kb
;
899 config
[no_regs
++] = adev
->gfx
.config
.shader_engine_tile_size
;
900 config
[no_regs
++] = adev
->gfx
.config
.num_gpus
;
901 config
[no_regs
++] = adev
->gfx
.config
.multi_gpu_tile_size
;
902 config
[no_regs
++] = adev
->gfx
.config
.mc_arb_ramcfg
;
903 config
[no_regs
++] = adev
->gfx
.config
.gb_addr_config
;
904 config
[no_regs
++] = adev
->gfx
.config
.num_rbs
;
907 config
[no_regs
++] = adev
->rev_id
;
908 config
[no_regs
++] = lower_32_bits(adev
->pg_flags
);
909 config
[no_regs
++] = lower_32_bits(adev
->cg_flags
);
912 config
[no_regs
++] = adev
->family
;
913 config
[no_regs
++] = adev
->external_rev_id
;
916 config
[no_regs
++] = adev
->pdev
->device
;
917 config
[no_regs
++] = adev
->pdev
->revision
;
918 config
[no_regs
++] = adev
->pdev
->subsystem_device
;
919 config
[no_regs
++] = adev
->pdev
->subsystem_vendor
;
921 /* rev==4 APU flag */
922 config
[no_regs
++] = adev
->flags
& AMD_IS_APU
? 1 : 0;
924 /* rev==5 PG/CG flag upper 32bit */
925 config
[no_regs
++] = upper_32_bits(adev
->pg_flags
);
926 config
[no_regs
++] = upper_32_bits(adev
->cg_flags
);
928 while (size
&& (*pos
< no_regs
* 4)) {
931 value
= config
[*pos
>> 2];
932 r
= put_user(value
, (uint32_t *)buf
);
949 * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
951 * @f: open file handle
952 * @buf: User buffer to store read data in
953 * @size: Number of bytes to read
954 * @pos: Offset to seek to
956 * The offset is treated as the BYTE address of one of the sensors
957 * enumerated in amd/include/kgd_pp_interface.h under the
958 * 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK
959 * you would use the offset 3 * 4 = 12.
961 static ssize_t
amdgpu_debugfs_sensor_read(struct file
*f
, char __user
*buf
,
962 size_t size
, loff_t
*pos
)
964 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
965 int idx
, x
, outsize
, r
, valuesize
;
968 if (size
& 3 || *pos
& 0x3)
971 if (!adev
->pm
.dpm_enabled
)
974 /* convert offset to sensor number */
977 valuesize
= sizeof(values
);
979 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
981 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
985 r
= amdgpu_virt_enable_access_debugfs(adev
);
987 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
991 r
= amdgpu_dpm_read_sensor(adev
, idx
, &values
[0], &valuesize
);
993 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
994 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
997 amdgpu_virt_disable_access_debugfs(adev
);
1001 if (size
> valuesize
) {
1002 amdgpu_virt_disable_access_debugfs(adev
);
1010 r
= put_user(values
[x
++], (int32_t *)buf
);
1017 amdgpu_virt_disable_access_debugfs(adev
);
1018 return !r
? outsize
: r
;
1021 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
1023 * @f: open file handle
1024 * @buf: User buffer to store read data in
1025 * @size: Number of bytes to read
1026 * @pos: Offset to seek to
1028 * The offset being sought changes which wave that the status data
1029 * will be returned for. The bits are used as follows:
1031 * Bits 0..6: Byte offset into data
1032 * Bits 7..14: SE selector
1033 * Bits 15..22: SH/SA selector
1034 * Bits 23..30: CU/{WGP+SIMD} selector
1035 * Bits 31..36: WAVE ID selector
1036 * Bits 37..44: SIMD ID selector
1038 * The returned data begins with one DWORD of version information
1039 * Followed by WAVE STATUS registers relevant to the GFX IP version
1040 * being used. See gfx_v8_0_read_wave_data() for an example output.
1042 static ssize_t
amdgpu_debugfs_wave_read(struct file
*f
, char __user
*buf
,
1043 size_t size
, loff_t
*pos
)
1045 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
1048 uint32_t offset
, se
, sh
, cu
, wave
, simd
, data
[32];
1050 if (size
& 3 || *pos
& 3)
1054 offset
= (*pos
& GENMASK_ULL(6, 0));
1055 se
= (*pos
& GENMASK_ULL(14, 7)) >> 7;
1056 sh
= (*pos
& GENMASK_ULL(22, 15)) >> 15;
1057 cu
= (*pos
& GENMASK_ULL(30, 23)) >> 23;
1058 wave
= (*pos
& GENMASK_ULL(36, 31)) >> 31;
1059 simd
= (*pos
& GENMASK_ULL(44, 37)) >> 37;
1061 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
1063 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1067 r
= amdgpu_virt_enable_access_debugfs(adev
);
1069 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1073 /* switch to the specific se/sh/cu */
1074 mutex_lock(&adev
->grbm_idx_mutex
);
1075 amdgpu_gfx_select_se_sh(adev
, se
, sh
, cu
, 0);
1078 if (adev
->gfx
.funcs
->read_wave_data
)
1079 adev
->gfx
.funcs
->read_wave_data(adev
, 0, simd
, wave
, data
, &x
);
1081 amdgpu_gfx_select_se_sh(adev
, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);
1082 mutex_unlock(&adev
->grbm_idx_mutex
);
1084 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
1085 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1088 amdgpu_virt_disable_access_debugfs(adev
);
1092 while (size
&& (offset
< x
* 4)) {
1095 value
= data
[offset
>> 2];
1096 r
= put_user(value
, (uint32_t *)buf
);
1098 amdgpu_virt_disable_access_debugfs(adev
);
1108 amdgpu_virt_disable_access_debugfs(adev
);
1112 /** amdgpu_debugfs_gpr_read - Read wave gprs
1114 * @f: open file handle
1115 * @buf: User buffer to store read data in
1116 * @size: Number of bytes to read
1117 * @pos: Offset to seek to
1119 * The offset being sought changes which wave that the status data
1120 * will be returned for. The bits are used as follows:
1122 * Bits 0..11: Byte offset into data
1123 * Bits 12..19: SE selector
1124 * Bits 20..27: SH/SA selector
1125 * Bits 28..35: CU/{WGP+SIMD} selector
1126 * Bits 36..43: WAVE ID selector
1127 * Bits 37..44: SIMD ID selector
1128 * Bits 52..59: Thread selector
1129 * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
1131 * The return data comes from the SGPR or VGPR register bank for
1132 * the selected operational unit.
1134 static ssize_t
amdgpu_debugfs_gpr_read(struct file
*f
, char __user
*buf
,
1135 size_t size
, loff_t
*pos
)
1137 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
1140 uint32_t offset
, se
, sh
, cu
, wave
, simd
, thread
, bank
, *data
;
1142 if (size
> 4096 || size
& 3 || *pos
& 3)
1146 offset
= (*pos
& GENMASK_ULL(11, 0)) >> 2;
1147 se
= (*pos
& GENMASK_ULL(19, 12)) >> 12;
1148 sh
= (*pos
& GENMASK_ULL(27, 20)) >> 20;
1149 cu
= (*pos
& GENMASK_ULL(35, 28)) >> 28;
1150 wave
= (*pos
& GENMASK_ULL(43, 36)) >> 36;
1151 simd
= (*pos
& GENMASK_ULL(51, 44)) >> 44;
1152 thread
= (*pos
& GENMASK_ULL(59, 52)) >> 52;
1153 bank
= (*pos
& GENMASK_ULL(61, 60)) >> 60;
1155 data
= kcalloc(1024, sizeof(*data
), GFP_KERNEL
);
1159 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
1163 r
= amdgpu_virt_enable_access_debugfs(adev
);
1167 /* switch to the specific se/sh/cu */
1168 mutex_lock(&adev
->grbm_idx_mutex
);
1169 amdgpu_gfx_select_se_sh(adev
, se
, sh
, cu
, 0);
1172 if (adev
->gfx
.funcs
->read_wave_vgprs
)
1173 adev
->gfx
.funcs
->read_wave_vgprs(adev
, 0, simd
, wave
, thread
, offset
, size
>>2, data
);
1175 if (adev
->gfx
.funcs
->read_wave_sgprs
)
1176 adev
->gfx
.funcs
->read_wave_sgprs(adev
, 0, simd
, wave
, offset
, size
>>2, data
);
1179 amdgpu_gfx_select_se_sh(adev
, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);
1180 mutex_unlock(&adev
->grbm_idx_mutex
);
1182 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
1183 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1188 value
= data
[result
>> 2];
1189 r
= put_user(value
, (uint32_t *)buf
);
1191 amdgpu_virt_disable_access_debugfs(adev
);
1201 amdgpu_virt_disable_access_debugfs(adev
);
1205 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1211 * amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency
1213 * @f: open file handle
1214 * @buf: User buffer to store read data in
1215 * @size: Number of bytes to read
1216 * @pos: Offset to seek to
1218 * Read the last residency value logged. It doesn't auto update, one needs to
1219 * stop logging before getting the current value.
1221 static ssize_t
amdgpu_debugfs_gfxoff_residency_read(struct file
*f
, char __user
*buf
,
1222 size_t size
, loff_t
*pos
)
1224 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
1228 if (size
& 0x3 || *pos
& 0x3)
1231 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
1233 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1240 r
= amdgpu_get_gfx_off_residency(adev
, &value
);
1244 r
= put_user(value
, (uint32_t *)buf
);
1256 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
1257 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1263 * amdgpu_debugfs_gfxoff_residency_write - Log GFXOFF Residency
1265 * @f: open file handle
1266 * @buf: User buffer to write data from
1267 * @size: Number of bytes to write
1268 * @pos: Offset to seek to
1270 * Write a 32-bit non-zero to start logging; write a 32-bit zero to stop
1272 static ssize_t
amdgpu_debugfs_gfxoff_residency_write(struct file
*f
, const char __user
*buf
,
1273 size_t size
, loff_t
*pos
)
1275 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
1279 if (size
& 0x3 || *pos
& 0x3)
1282 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
1284 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1291 r
= get_user(value
, (uint32_t *)buf
);
1295 amdgpu_set_gfx_off_residency(adev
, value
? true : false);
1305 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
1306 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1313 * amdgpu_debugfs_gfxoff_count_read - Read GFXOFF entry count
1315 * @f: open file handle
1316 * @buf: User buffer to store read data in
1317 * @size: Number of bytes to read
1318 * @pos: Offset to seek to
1320 static ssize_t
amdgpu_debugfs_gfxoff_count_read(struct file
*f
, char __user
*buf
,
1321 size_t size
, loff_t
*pos
)
1323 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
1327 if (size
& 0x3 || *pos
& 0x3)
1330 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
1332 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1339 r
= amdgpu_get_gfx_off_entrycount(adev
, &value
);
1343 r
= put_user(value
, (u64
*)buf
);
1355 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
1356 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1362 * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF
1364 * @f: open file handle
1365 * @buf: User buffer to write data from
1366 * @size: Number of bytes to write
1367 * @pos: Offset to seek to
1369 * Write a 32-bit zero to disable or a 32-bit non-zero to enable
1371 static ssize_t
amdgpu_debugfs_gfxoff_write(struct file
*f
, const char __user
*buf
,
1372 size_t size
, loff_t
*pos
)
1374 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
1378 if (size
& 0x3 || *pos
& 0x3)
1381 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
1383 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1390 r
= get_user(value
, (uint32_t *)buf
);
1394 amdgpu_gfx_off_ctrl(adev
, value
? true : false);
1404 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
1405 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1412 * amdgpu_debugfs_gfxoff_read - read gfxoff status
1414 * @f: open file handle
1415 * @buf: User buffer to store read data in
1416 * @size: Number of bytes to read
1417 * @pos: Offset to seek to
1419 static ssize_t
amdgpu_debugfs_gfxoff_read(struct file
*f
, char __user
*buf
,
1420 size_t size
, loff_t
*pos
)
1422 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
1426 if (size
& 0x3 || *pos
& 0x3)
1429 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
1431 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1436 u32 value
= adev
->gfx
.gfx_off_state
;
1438 r
= put_user(value
, (u32
*)buf
);
1450 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
1451 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1456 static ssize_t
amdgpu_debugfs_gfxoff_status_read(struct file
*f
, char __user
*buf
,
1457 size_t size
, loff_t
*pos
)
1459 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
1463 if (size
& 0x3 || *pos
& 0x3)
1466 r
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
1468 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1475 r
= amdgpu_get_gfx_off_status(adev
, &value
);
1479 r
= put_user(value
, (u32
*)buf
);
1491 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
1492 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1497 static const struct file_operations amdgpu_debugfs_regs2_fops
= {
1498 .owner
= THIS_MODULE
,
1499 .unlocked_ioctl
= amdgpu_debugfs_regs2_ioctl
,
1500 .read
= amdgpu_debugfs_regs2_read
,
1501 .write
= amdgpu_debugfs_regs2_write
,
1502 .open
= amdgpu_debugfs_regs2_open
,
1503 .release
= amdgpu_debugfs_regs2_release
,
1504 .llseek
= default_llseek
1507 static const struct file_operations amdgpu_debugfs_gprwave_fops
= {
1508 .owner
= THIS_MODULE
,
1509 .unlocked_ioctl
= amdgpu_debugfs_gprwave_ioctl
,
1510 .read
= amdgpu_debugfs_gprwave_read
,
1511 .open
= amdgpu_debugfs_gprwave_open
,
1512 .release
= amdgpu_debugfs_gprwave_release
,
1513 .llseek
= default_llseek
1516 static const struct file_operations amdgpu_debugfs_regs_fops
= {
1517 .owner
= THIS_MODULE
,
1518 .read
= amdgpu_debugfs_regs_read
,
1519 .write
= amdgpu_debugfs_regs_write
,
1520 .llseek
= default_llseek
1522 static const struct file_operations amdgpu_debugfs_regs_didt_fops
= {
1523 .owner
= THIS_MODULE
,
1524 .read
= amdgpu_debugfs_regs_didt_read
,
1525 .write
= amdgpu_debugfs_regs_didt_write
,
1526 .llseek
= default_llseek
1528 static const struct file_operations amdgpu_debugfs_regs_pcie_fops
= {
1529 .owner
= THIS_MODULE
,
1530 .read
= amdgpu_debugfs_regs_pcie_read
,
1531 .write
= amdgpu_debugfs_regs_pcie_write
,
1532 .llseek
= default_llseek
1534 static const struct file_operations amdgpu_debugfs_regs_smc_fops
= {
1535 .owner
= THIS_MODULE
,
1536 .read
= amdgpu_debugfs_regs_smc_read
,
1537 .write
= amdgpu_debugfs_regs_smc_write
,
1538 .llseek
= default_llseek
1541 static const struct file_operations amdgpu_debugfs_gca_config_fops
= {
1542 .owner
= THIS_MODULE
,
1543 .read
= amdgpu_debugfs_gca_config_read
,
1544 .llseek
= default_llseek
1547 static const struct file_operations amdgpu_debugfs_sensors_fops
= {
1548 .owner
= THIS_MODULE
,
1549 .read
= amdgpu_debugfs_sensor_read
,
1550 .llseek
= default_llseek
1553 static const struct file_operations amdgpu_debugfs_wave_fops
= {
1554 .owner
= THIS_MODULE
,
1555 .read
= amdgpu_debugfs_wave_read
,
1556 .llseek
= default_llseek
1558 static const struct file_operations amdgpu_debugfs_gpr_fops
= {
1559 .owner
= THIS_MODULE
,
1560 .read
= amdgpu_debugfs_gpr_read
,
1561 .llseek
= default_llseek
1564 static const struct file_operations amdgpu_debugfs_gfxoff_fops
= {
1565 .owner
= THIS_MODULE
,
1566 .read
= amdgpu_debugfs_gfxoff_read
,
1567 .write
= amdgpu_debugfs_gfxoff_write
,
1568 .llseek
= default_llseek
1571 static const struct file_operations amdgpu_debugfs_gfxoff_status_fops
= {
1572 .owner
= THIS_MODULE
,
1573 .read
= amdgpu_debugfs_gfxoff_status_read
,
1574 .llseek
= default_llseek
1577 static const struct file_operations amdgpu_debugfs_gfxoff_count_fops
= {
1578 .owner
= THIS_MODULE
,
1579 .read
= amdgpu_debugfs_gfxoff_count_read
,
1580 .llseek
= default_llseek
1583 static const struct file_operations amdgpu_debugfs_gfxoff_residency_fops
= {
1584 .owner
= THIS_MODULE
,
1585 .read
= amdgpu_debugfs_gfxoff_residency_read
,
1586 .write
= amdgpu_debugfs_gfxoff_residency_write
,
1587 .llseek
= default_llseek
1590 static const struct file_operations
*debugfs_regs
[] = {
1591 &amdgpu_debugfs_regs_fops
,
1592 &amdgpu_debugfs_regs2_fops
,
1593 &amdgpu_debugfs_gprwave_fops
,
1594 &amdgpu_debugfs_regs_didt_fops
,
1595 &amdgpu_debugfs_regs_pcie_fops
,
1596 &amdgpu_debugfs_regs_smc_fops
,
1597 &amdgpu_debugfs_gca_config_fops
,
1598 &amdgpu_debugfs_sensors_fops
,
1599 &amdgpu_debugfs_wave_fops
,
1600 &amdgpu_debugfs_gpr_fops
,
1601 &amdgpu_debugfs_gfxoff_fops
,
1602 &amdgpu_debugfs_gfxoff_status_fops
,
1603 &amdgpu_debugfs_gfxoff_count_fops
,
1604 &amdgpu_debugfs_gfxoff_residency_fops
,
1607 static const char * const debugfs_regs_names
[] = {
1614 "amdgpu_gca_config",
1619 "amdgpu_gfxoff_status",
1620 "amdgpu_gfxoff_count",
1621 "amdgpu_gfxoff_residency",
1625 * amdgpu_debugfs_regs_init - Initialize debugfs entries that provide
1628 * @adev: The device to attach the debugfs entries to
1630 int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
)
1632 struct drm_minor
*minor
= adev_to_drm(adev
)->primary
;
1633 struct dentry
*ent
, *root
= minor
->debugfs_root
;
1636 for (i
= 0; i
< ARRAY_SIZE(debugfs_regs
); i
++) {
1637 ent
= debugfs_create_file(debugfs_regs_names
[i
],
1638 S_IFREG
| 0444, root
,
1639 adev
, debugfs_regs
[i
]);
1640 if (!i
&& !IS_ERR_OR_NULL(ent
))
1641 i_size_write(ent
->d_inode
, adev
->rmmio_size
);
1647 static int amdgpu_debugfs_test_ib_show(struct seq_file
*m
, void *unused
)
1649 struct amdgpu_device
*adev
= m
->private;
1650 struct drm_device
*dev
= adev_to_drm(adev
);
1653 r
= pm_runtime_get_sync(dev
->dev
);
1655 pm_runtime_put_autosuspend(dev
->dev
);
1659 /* Avoid accidently unparking the sched thread during GPU reset */
1660 r
= down_write_killable(&adev
->reset_domain
->sem
);
1664 /* hold on the scheduler */
1665 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
1666 struct amdgpu_ring
*ring
= adev
->rings
[i
];
1668 if (!ring
|| !ring
->sched
.thread
)
1670 kthread_park(ring
->sched
.thread
);
1673 seq_puts(m
, "run ib test:\n");
1674 r
= amdgpu_ib_ring_tests(adev
);
1676 seq_printf(m
, "ib ring tests failed (%d).\n", r
);
1678 seq_puts(m
, "ib ring tests passed.\n");
1680 /* go on the scheduler */
1681 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
1682 struct amdgpu_ring
*ring
= adev
->rings
[i
];
1684 if (!ring
|| !ring
->sched
.thread
)
1686 kthread_unpark(ring
->sched
.thread
);
1689 up_write(&adev
->reset_domain
->sem
);
1691 pm_runtime_mark_last_busy(dev
->dev
);
1692 pm_runtime_put_autosuspend(dev
->dev
);
1697 static int amdgpu_debugfs_evict_vram(void *data
, u64
*val
)
1699 struct amdgpu_device
*adev
= (struct amdgpu_device
*)data
;
1700 struct drm_device
*dev
= adev_to_drm(adev
);
1703 r
= pm_runtime_get_sync(dev
->dev
);
1705 pm_runtime_put_autosuspend(dev
->dev
);
1709 *val
= amdgpu_ttm_evict_resources(adev
, TTM_PL_VRAM
);
1711 pm_runtime_mark_last_busy(dev
->dev
);
1712 pm_runtime_put_autosuspend(dev
->dev
);
1718 static int amdgpu_debugfs_evict_gtt(void *data
, u64
*val
)
1720 struct amdgpu_device
*adev
= (struct amdgpu_device
*)data
;
1721 struct drm_device
*dev
= adev_to_drm(adev
);
1724 r
= pm_runtime_get_sync(dev
->dev
);
1726 pm_runtime_put_autosuspend(dev
->dev
);
1730 *val
= amdgpu_ttm_evict_resources(adev
, TTM_PL_TT
);
1732 pm_runtime_mark_last_busy(dev
->dev
);
1733 pm_runtime_put_autosuspend(dev
->dev
);
1738 static int amdgpu_debugfs_benchmark(void *data
, u64 val
)
1740 struct amdgpu_device
*adev
= (struct amdgpu_device
*)data
;
1741 struct drm_device
*dev
= adev_to_drm(adev
);
1744 r
= pm_runtime_get_sync(dev
->dev
);
1746 pm_runtime_put_autosuspend(dev
->dev
);
1750 r
= amdgpu_benchmark(adev
, val
);
1752 pm_runtime_mark_last_busy(dev
->dev
);
1753 pm_runtime_put_autosuspend(dev
->dev
);
1758 static int amdgpu_debugfs_vm_info_show(struct seq_file
*m
, void *unused
)
1760 struct amdgpu_device
*adev
= m
->private;
1761 struct drm_device
*dev
= adev_to_drm(adev
);
1762 struct drm_file
*file
;
1765 r
= mutex_lock_interruptible(&dev
->filelist_mutex
);
1769 list_for_each_entry(file
, &dev
->filelist
, lhead
) {
1770 struct amdgpu_fpriv
*fpriv
= file
->driver_priv
;
1771 struct amdgpu_vm
*vm
= &fpriv
->vm
;
1773 seq_printf(m
, "pid:%d\tProcess:%s ----------\n",
1774 vm
->task_info
.pid
, vm
->task_info
.process_name
);
1775 r
= amdgpu_bo_reserve(vm
->root
.bo
, true);
1778 amdgpu_debugfs_vm_bo_info(vm
, m
);
1779 amdgpu_bo_unreserve(vm
->root
.bo
);
1782 mutex_unlock(&dev
->filelist_mutex
);
1787 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib
);
1788 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info
);
1789 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops
, amdgpu_debugfs_evict_vram
,
1791 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops
, amdgpu_debugfs_evict_gtt
,
1793 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops
, NULL
, amdgpu_debugfs_benchmark
,
1796 static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring
*ring
,
1797 struct dma_fence
**fences
)
1799 struct amdgpu_fence_driver
*drv
= &ring
->fence_drv
;
1800 uint32_t sync_seq
, last_seq
;
1802 last_seq
= atomic_read(&ring
->fence_drv
.last_seq
);
1803 sync_seq
= ring
->fence_drv
.sync_seq
;
1805 last_seq
&= drv
->num_fences_mask
;
1806 sync_seq
&= drv
->num_fences_mask
;
1809 struct dma_fence
*fence
, **ptr
;
1812 last_seq
&= drv
->num_fences_mask
;
1813 ptr
= &drv
->fences
[last_seq
];
1815 fence
= rcu_dereference_protected(*ptr
, 1);
1816 RCU_INIT_POINTER(*ptr
, NULL
);
1821 fences
[last_seq
] = fence
;
1823 } while (last_seq
!= sync_seq
);
1826 static void amdgpu_ib_preempt_signal_fences(struct dma_fence
**fences
,
1830 struct dma_fence
*fence
;
1832 for (i
= 0; i
< length
; i
++) {
1836 dma_fence_signal(fence
);
1837 dma_fence_put(fence
);
1841 static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler
*sched
)
1843 struct drm_sched_job
*s_job
;
1844 struct dma_fence
*fence
;
1846 spin_lock(&sched
->job_list_lock
);
1847 list_for_each_entry(s_job
, &sched
->pending_list
, list
) {
1848 fence
= sched
->ops
->run_job(s_job
);
1849 dma_fence_put(fence
);
1851 spin_unlock(&sched
->job_list_lock
);
1854 static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring
*ring
)
1856 struct amdgpu_job
*job
;
1857 struct drm_sched_job
*s_job
, *tmp
;
1858 uint32_t preempt_seq
;
1859 struct dma_fence
*fence
, **ptr
;
1860 struct amdgpu_fence_driver
*drv
= &ring
->fence_drv
;
1861 struct drm_gpu_scheduler
*sched
= &ring
->sched
;
1862 bool preempted
= true;
1864 if (ring
->funcs
->type
!= AMDGPU_RING_TYPE_GFX
)
1867 preempt_seq
= le32_to_cpu(*(drv
->cpu_addr
+ 2));
1868 if (preempt_seq
<= atomic_read(&drv
->last_seq
)) {
1873 preempt_seq
&= drv
->num_fences_mask
;
1874 ptr
= &drv
->fences
[preempt_seq
];
1875 fence
= rcu_dereference_protected(*ptr
, 1);
1878 spin_lock(&sched
->job_list_lock
);
1879 list_for_each_entry_safe(s_job
, tmp
, &sched
->pending_list
, list
) {
1880 if (dma_fence_is_signaled(&s_job
->s_fence
->finished
)) {
1881 /* remove job from ring_mirror_list */
1882 list_del_init(&s_job
->list
);
1883 sched
->ops
->free_job(s_job
);
1886 job
= to_amdgpu_job(s_job
);
1887 if (preempted
&& (&job
->hw_fence
) == fence
)
1888 /* mark the job as preempted */
1889 job
->preemption_status
|= AMDGPU_IB_PREEMPTED
;
1891 spin_unlock(&sched
->job_list_lock
);
1894 static int amdgpu_debugfs_ib_preempt(void *data
, u64 val
)
1897 struct amdgpu_ring
*ring
;
1898 struct dma_fence
**fences
= NULL
;
1899 struct amdgpu_device
*adev
= (struct amdgpu_device
*)data
;
1901 if (val
>= AMDGPU_MAX_RINGS
)
1904 ring
= adev
->rings
[val
];
1906 if (!ring
|| !ring
->funcs
->preempt_ib
|| !ring
->sched
.thread
)
1909 /* the last preemption failed */
1910 if (ring
->trail_seq
!= le32_to_cpu(*ring
->trail_fence_cpu_addr
))
1913 length
= ring
->fence_drv
.num_fences_mask
+ 1;
1914 fences
= kcalloc(length
, sizeof(void *), GFP_KERNEL
);
1918 /* Avoid accidently unparking the sched thread during GPU reset */
1919 r
= down_read_killable(&adev
->reset_domain
->sem
);
1923 /* stop the scheduler */
1924 kthread_park(ring
->sched
.thread
);
1926 /* preempt the IB */
1927 r
= amdgpu_ring_preempt_ib(ring
);
1929 DRM_WARN("failed to preempt ring %d\n", ring
->idx
);
1933 amdgpu_fence_process(ring
);
1935 if (atomic_read(&ring
->fence_drv
.last_seq
) !=
1936 ring
->fence_drv
.sync_seq
) {
1937 DRM_INFO("ring %d was preempted\n", ring
->idx
);
1939 amdgpu_ib_preempt_mark_partial_job(ring
);
1941 /* swap out the old fences */
1942 amdgpu_ib_preempt_fences_swap(ring
, fences
);
1944 amdgpu_fence_driver_force_completion(ring
);
1946 /* resubmit unfinished jobs */
1947 amdgpu_ib_preempt_job_recovery(&ring
->sched
);
1949 /* wait for jobs finished */
1950 amdgpu_fence_wait_empty(ring
);
1952 /* signal the old fences */
1953 amdgpu_ib_preempt_signal_fences(fences
, length
);
1957 /* restart the scheduler */
1958 kthread_unpark(ring
->sched
.thread
);
1960 up_read(&adev
->reset_domain
->sem
);
1968 static int amdgpu_debugfs_sclk_set(void *data
, u64 val
)
1971 uint32_t max_freq
, min_freq
;
1972 struct amdgpu_device
*adev
= (struct amdgpu_device
*)data
;
1974 if (amdgpu_sriov_vf(adev
) && !amdgpu_sriov_is_pp_one_vf(adev
))
1977 ret
= pm_runtime_get_sync(adev_to_drm(adev
)->dev
);
1979 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
1983 ret
= amdgpu_dpm_get_dpm_freq_range(adev
, PP_SCLK
, &min_freq
, &max_freq
);
1984 if (ret
== -EOPNOTSUPP
) {
1988 if (ret
|| val
> max_freq
|| val
< min_freq
) {
1993 ret
= amdgpu_dpm_set_soft_freq_range(adev
, PP_SCLK
, (uint32_t)val
, (uint32_t)val
);
1998 pm_runtime_mark_last_busy(adev_to_drm(adev
)->dev
);
1999 pm_runtime_put_autosuspend(adev_to_drm(adev
)->dev
);
2004 DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt
, NULL
,
2005 amdgpu_debugfs_ib_preempt
, "%llu\n");
2007 DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set
, NULL
,
2008 amdgpu_debugfs_sclk_set
, "%llu\n");
2010 static ssize_t
amdgpu_reset_dump_register_list_read(struct file
*f
,
2011 char __user
*buf
, size_t size
, loff_t
*pos
)
2013 struct amdgpu_device
*adev
= (struct amdgpu_device
*)file_inode(f
)->i_private
;
2014 char reg_offset
[12];
2015 int i
, ret
, len
= 0;
2020 memset(reg_offset
, 0, 12);
2021 ret
= down_read_killable(&adev
->reset_domain
->sem
);
2025 for (i
= 0; i
< adev
->reset_info
.num_regs
; i
++) {
2026 sprintf(reg_offset
, "0x%x\n", adev
->reset_info
.reset_dump_reg_list
[i
]);
2027 up_read(&adev
->reset_domain
->sem
);
2028 if (copy_to_user(buf
+ len
, reg_offset
, strlen(reg_offset
)))
2031 len
+= strlen(reg_offset
);
2032 ret
= down_read_killable(&adev
->reset_domain
->sem
);
2037 up_read(&adev
->reset_domain
->sem
);
2043 static ssize_t
amdgpu_reset_dump_register_list_write(struct file
*f
,
2044 const char __user
*buf
, size_t size
, loff_t
*pos
)
2046 struct amdgpu_device
*adev
= (struct amdgpu_device
*)file_inode(f
)->i_private
;
2047 char reg_offset
[11];
2048 uint32_t *new = NULL
, *tmp
= NULL
;
2049 int ret
, i
= 0, len
= 0;
2052 memset(reg_offset
, 0, 11);
2053 if (copy_from_user(reg_offset
, buf
+ len
,
2054 min(10, ((int)size
-len
)))) {
2059 new = krealloc_array(tmp
, i
+ 1, sizeof(uint32_t), GFP_KERNEL
);
2065 if (sscanf(reg_offset
, "%X %n", &tmp
[i
], &ret
) != 1) {
2072 } while (len
< size
);
2074 new = kmalloc_array(i
, sizeof(uint32_t), GFP_KERNEL
);
2079 ret
= down_write_killable(&adev
->reset_domain
->sem
);
2083 swap(adev
->reset_info
.reset_dump_reg_list
, tmp
);
2084 swap(adev
->reset_info
.reset_dump_reg_value
, new);
2085 adev
->reset_info
.num_regs
= i
;
2086 up_write(&adev
->reset_domain
->sem
);
2096 static const struct file_operations amdgpu_reset_dump_register_list
= {
2097 .owner
= THIS_MODULE
,
2098 .read
= amdgpu_reset_dump_register_list_read
,
2099 .write
= amdgpu_reset_dump_register_list_write
,
2100 .llseek
= default_llseek
2103 int amdgpu_debugfs_init(struct amdgpu_device
*adev
)
2105 struct dentry
*root
= adev_to_drm(adev
)->primary
->debugfs_root
;
2109 if (!debugfs_initialized())
2112 debugfs_create_x32("amdgpu_smu_debug", 0600, root
,
2113 &adev
->pm
.smu_debug_mask
);
2115 ent
= debugfs_create_file("amdgpu_preempt_ib", 0600, root
, adev
,
2118 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
2119 return PTR_ERR(ent
);
2122 ent
= debugfs_create_file("amdgpu_force_sclk", 0200, root
, adev
,
2125 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
2126 return PTR_ERR(ent
);
2129 /* Register debugfs entries for amdgpu_ttm */
2130 amdgpu_ttm_debugfs_init(adev
);
2131 amdgpu_debugfs_pm_init(adev
);
2132 amdgpu_debugfs_sa_init(adev
);
2133 amdgpu_debugfs_fence_init(adev
);
2134 amdgpu_debugfs_gem_init(adev
);
2136 r
= amdgpu_debugfs_regs_init(adev
);
2138 DRM_ERROR("registering register debugfs failed (%d).\n", r
);
2140 amdgpu_debugfs_firmware_init(adev
);
2141 amdgpu_ta_if_debugfs_init(adev
);
2143 #if defined(CONFIG_DRM_AMD_DC)
2144 if (adev
->dc_enabled
)
2145 dtn_debugfs_init(adev
);
2148 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
2149 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2154 amdgpu_debugfs_ring_init(adev
, ring
);
2157 for (i
= 0; i
< adev
->vcn
.num_vcn_inst
; i
++) {
2158 if (!amdgpu_vcnfw_log
)
2161 if (adev
->vcn
.harvest_config
& (1 << i
))
2164 amdgpu_debugfs_vcn_fwlog_init(adev
, i
, &adev
->vcn
.inst
[i
]);
2167 amdgpu_ras_debugfs_create_all(adev
);
2168 amdgpu_rap_debugfs_init(adev
);
2169 amdgpu_securedisplay_debugfs_init(adev
);
2170 amdgpu_fw_attestation_debugfs_init(adev
);
2172 debugfs_create_file("amdgpu_evict_vram", 0444, root
, adev
,
2173 &amdgpu_evict_vram_fops
);
2174 debugfs_create_file("amdgpu_evict_gtt", 0444, root
, adev
,
2175 &amdgpu_evict_gtt_fops
);
2176 debugfs_create_file("amdgpu_test_ib", 0444, root
, adev
,
2177 &amdgpu_debugfs_test_ib_fops
);
2178 debugfs_create_file("amdgpu_vm_info", 0444, root
, adev
,
2179 &amdgpu_debugfs_vm_info_fops
);
2180 debugfs_create_file("amdgpu_benchmark", 0200, root
, adev
,
2181 &amdgpu_benchmark_fops
);
2182 debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root
, adev
,
2183 &amdgpu_reset_dump_register_list
);
2185 adev
->debugfs_vbios_blob
.data
= adev
->bios
;
2186 adev
->debugfs_vbios_blob
.size
= adev
->bios_size
;
2187 debugfs_create_blob("amdgpu_vbios", 0444, root
,
2188 &adev
->debugfs_vbios_blob
);
2190 adev
->debugfs_discovery_blob
.data
= adev
->mman
.discovery_bin
;
2191 adev
->debugfs_discovery_blob
.size
= adev
->mman
.discovery_tmr_size
;
2192 debugfs_create_blob("amdgpu_discovery", 0444, root
,
2193 &adev
->debugfs_discovery_blob
);
2199 int amdgpu_debugfs_init(struct amdgpu_device
*adev
)
2203 int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
)