2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
43 #include "amdgpu_atomfirmware.h"
45 #ifdef CONFIG_DRM_AMDGPU_SI
48 #ifdef CONFIG_DRM_AMDGPU_CIK
53 #include "bif/bif_4_1_d.h"
54 #include <linux/pci.h>
55 #include <linux/firmware.h>
56 #include "amdgpu_vf_error.h"
58 #include "amdgpu_amdkfd.h"
60 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
61 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
63 #define AMDGPU_RESUME_MS 2000
65 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
);
66 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
);
67 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device
*adev
);
69 static const char *amdgpu_asic_name
[] = {
93 bool amdgpu_device_is_px(struct drm_device
*dev
)
95 struct amdgpu_device
*adev
= dev
->dev_private
;
97 if (adev
->flags
& AMD_IS_PX
)
103 * MMIO register access helper functions.
105 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
110 if (!(acc_flags
& AMDGPU_REGS_NO_KIQ
) && amdgpu_sriov_runtime(adev
)) {
111 BUG_ON(in_interrupt());
112 return amdgpu_virt_kiq_rreg(adev
, reg
);
115 if ((reg
* 4) < adev
->rmmio_size
&& !(acc_flags
& AMDGPU_REGS_IDX
))
116 ret
= readl(((void __iomem
*)adev
->rmmio
) + (reg
* 4));
120 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
121 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
122 ret
= readl(((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
123 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
125 trace_amdgpu_mm_rreg(adev
->pdev
->device
, reg
, ret
);
129 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
132 trace_amdgpu_mm_wreg(adev
->pdev
->device
, reg
, v
);
134 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 0) {
135 adev
->last_mm_index
= v
;
138 if (!(acc_flags
& AMDGPU_REGS_NO_KIQ
) && amdgpu_sriov_runtime(adev
)) {
139 BUG_ON(in_interrupt());
140 return amdgpu_virt_kiq_wreg(adev
, reg
, v
);
143 if ((reg
* 4) < adev
->rmmio_size
&& !(acc_flags
& AMDGPU_REGS_IDX
))
144 writel(v
, ((void __iomem
*)adev
->rmmio
) + (reg
* 4));
148 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
149 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
150 writel(v
, ((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
151 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
154 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 1 && adev
->last_mm_index
== 0x5702C) {
159 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
)
161 if ((reg
* 4) < adev
->rio_mem_size
)
162 return ioread32(adev
->rio_mem
+ (reg
* 4));
164 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
165 return ioread32(adev
->rio_mem
+ (mmMM_DATA
* 4));
169 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
171 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 0) {
172 adev
->last_mm_index
= v
;
175 if ((reg
* 4) < adev
->rio_mem_size
)
176 iowrite32(v
, adev
->rio_mem
+ (reg
* 4));
178 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
179 iowrite32(v
, adev
->rio_mem
+ (mmMM_DATA
* 4));
182 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 1 && adev
->last_mm_index
== 0x5702C) {
188 * amdgpu_mm_rdoorbell - read a doorbell dword
190 * @adev: amdgpu_device pointer
191 * @index: doorbell index
193 * Returns the value in the doorbell aperture at the
194 * requested doorbell index (CIK).
196 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
)
198 if (index
< adev
->doorbell
.num_doorbells
) {
199 return readl(adev
->doorbell
.ptr
+ index
);
201 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index
);
207 * amdgpu_mm_wdoorbell - write a doorbell dword
209 * @adev: amdgpu_device pointer
210 * @index: doorbell index
213 * Writes @v to the doorbell aperture at the
214 * requested doorbell index (CIK).
216 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
)
218 if (index
< adev
->doorbell
.num_doorbells
) {
219 writel(v
, adev
->doorbell
.ptr
+ index
);
221 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index
);
226 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
228 * @adev: amdgpu_device pointer
229 * @index: doorbell index
231 * Returns the value in the doorbell aperture at the
232 * requested doorbell index (VEGA10+).
234 u64
amdgpu_mm_rdoorbell64(struct amdgpu_device
*adev
, u32 index
)
236 if (index
< adev
->doorbell
.num_doorbells
) {
237 return atomic64_read((atomic64_t
*)(adev
->doorbell
.ptr
+ index
));
239 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index
);
245 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
247 * @adev: amdgpu_device pointer
248 * @index: doorbell index
251 * Writes @v to the doorbell aperture at the
252 * requested doorbell index (VEGA10+).
254 void amdgpu_mm_wdoorbell64(struct amdgpu_device
*adev
, u32 index
, u64 v
)
256 if (index
< adev
->doorbell
.num_doorbells
) {
257 atomic64_set((atomic64_t
*)(adev
->doorbell
.ptr
+ index
), v
);
259 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index
);
264 * amdgpu_invalid_rreg - dummy reg read function
266 * @adev: amdgpu device pointer
267 * @reg: offset of register
269 * Dummy register read function. Used for register blocks
270 * that certain asics don't have (all asics).
271 * Returns the value in the register.
273 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device
*adev
, uint32_t reg
)
275 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
281 * amdgpu_invalid_wreg - dummy reg write function
283 * @adev: amdgpu device pointer
284 * @reg: offset of register
285 * @v: value to write to the register
287 * Dummy register read function. Used for register blocks
288 * that certain asics don't have (all asics).
290 static void amdgpu_invalid_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
)
292 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
298 * amdgpu_block_invalid_rreg - dummy reg read function
300 * @adev: amdgpu device pointer
301 * @block: offset of instance
302 * @reg: offset of register
304 * Dummy register read function. Used for register blocks
305 * that certain asics don't have (all asics).
306 * Returns the value in the register.
308 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device
*adev
,
309 uint32_t block
, uint32_t reg
)
311 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
318 * amdgpu_block_invalid_wreg - dummy reg write function
320 * @adev: amdgpu device pointer
321 * @block: offset of instance
322 * @reg: offset of register
323 * @v: value to write to the register
325 * Dummy register read function. Used for register blocks
326 * that certain asics don't have (all asics).
328 static void amdgpu_block_invalid_wreg(struct amdgpu_device
*adev
,
330 uint32_t reg
, uint32_t v
)
332 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
337 static int amdgpu_vram_scratch_init(struct amdgpu_device
*adev
)
341 if (adev
->vram_scratch
.robj
== NULL
) {
342 r
= amdgpu_bo_create(adev
, AMDGPU_GPU_PAGE_SIZE
,
343 PAGE_SIZE
, true, AMDGPU_GEM_DOMAIN_VRAM
,
344 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
345 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
,
346 NULL
, NULL
, &adev
->vram_scratch
.robj
);
352 r
= amdgpu_bo_reserve(adev
->vram_scratch
.robj
, false);
353 if (unlikely(r
!= 0))
355 r
= amdgpu_bo_pin(adev
->vram_scratch
.robj
,
356 AMDGPU_GEM_DOMAIN_VRAM
, &adev
->vram_scratch
.gpu_addr
);
358 amdgpu_bo_unreserve(adev
->vram_scratch
.robj
);
361 r
= amdgpu_bo_kmap(adev
->vram_scratch
.robj
,
362 (void **)&adev
->vram_scratch
.ptr
);
364 amdgpu_bo_unpin(adev
->vram_scratch
.robj
);
365 amdgpu_bo_unreserve(adev
->vram_scratch
.robj
);
370 static void amdgpu_vram_scratch_fini(struct amdgpu_device
*adev
)
374 if (adev
->vram_scratch
.robj
== NULL
) {
377 r
= amdgpu_bo_reserve(adev
->vram_scratch
.robj
, true);
378 if (likely(r
== 0)) {
379 amdgpu_bo_kunmap(adev
->vram_scratch
.robj
);
380 amdgpu_bo_unpin(adev
->vram_scratch
.robj
);
381 amdgpu_bo_unreserve(adev
->vram_scratch
.robj
);
383 amdgpu_bo_unref(&adev
->vram_scratch
.robj
);
387 * amdgpu_program_register_sequence - program an array of registers.
389 * @adev: amdgpu_device pointer
390 * @registers: pointer to the register array
391 * @array_size: size of the register array
393 * Programs an array or registers with and and or masks.
394 * This is a helper for setting golden registers.
396 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
397 const u32
*registers
,
398 const u32 array_size
)
400 u32 tmp
, reg
, and_mask
, or_mask
;
406 for (i
= 0; i
< array_size
; i
+=3) {
407 reg
= registers
[i
+ 0];
408 and_mask
= registers
[i
+ 1];
409 or_mask
= registers
[i
+ 2];
411 if (and_mask
== 0xffffffff) {
422 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
)
424 pci_write_config_dword(adev
->pdev
, 0x7c, AMDGPU_ASIC_RESET_DATA
);
428 * GPU doorbell aperture helpers function.
431 * amdgpu_doorbell_init - Init doorbell driver information.
433 * @adev: amdgpu_device pointer
435 * Init doorbell driver information (CIK)
436 * Returns 0 on success, error on failure.
438 static int amdgpu_doorbell_init(struct amdgpu_device
*adev
)
440 /* doorbell bar mapping */
441 adev
->doorbell
.base
= pci_resource_start(adev
->pdev
, 2);
442 adev
->doorbell
.size
= pci_resource_len(adev
->pdev
, 2);
444 adev
->doorbell
.num_doorbells
= min_t(u32
, adev
->doorbell
.size
/ sizeof(u32
),
445 AMDGPU_DOORBELL_MAX_ASSIGNMENT
+1);
446 if (adev
->doorbell
.num_doorbells
== 0)
449 adev
->doorbell
.ptr
= ioremap(adev
->doorbell
.base
,
450 adev
->doorbell
.num_doorbells
*
452 if (adev
->doorbell
.ptr
== NULL
)
459 * amdgpu_doorbell_fini - Tear down doorbell driver information.
461 * @adev: amdgpu_device pointer
463 * Tear down doorbell driver information (CIK)
465 static void amdgpu_doorbell_fini(struct amdgpu_device
*adev
)
467 iounmap(adev
->doorbell
.ptr
);
468 adev
->doorbell
.ptr
= NULL
;
472 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
475 * @adev: amdgpu_device pointer
476 * @aperture_base: output returning doorbell aperture base physical address
477 * @aperture_size: output returning doorbell aperture size in bytes
478 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
480 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
481 * takes doorbells required for its own rings and reports the setup to amdkfd.
482 * amdgpu reserved doorbells are at the start of the doorbell aperture.
484 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
485 phys_addr_t
*aperture_base
,
486 size_t *aperture_size
,
487 size_t *start_offset
)
490 * The first num_doorbells are used by amdgpu.
491 * amdkfd takes whatever's left in the aperture.
493 if (adev
->doorbell
.size
> adev
->doorbell
.num_doorbells
* sizeof(u32
)) {
494 *aperture_base
= adev
->doorbell
.base
;
495 *aperture_size
= adev
->doorbell
.size
;
496 *start_offset
= adev
->doorbell
.num_doorbells
* sizeof(u32
);
506 * Writeback is the method by which the GPU updates special pages in memory
507 * with the status of certain GPU events (fences, ring pointers,etc.).
511 * amdgpu_wb_fini - Disable Writeback and free memory
513 * @adev: amdgpu_device pointer
515 * Disables Writeback and frees the Writeback memory (all asics).
516 * Used at driver shutdown.
518 static void amdgpu_wb_fini(struct amdgpu_device
*adev
)
520 if (adev
->wb
.wb_obj
) {
521 amdgpu_bo_free_kernel(&adev
->wb
.wb_obj
,
523 (void **)&adev
->wb
.wb
);
524 adev
->wb
.wb_obj
= NULL
;
529 * amdgpu_wb_init- Init Writeback driver info and allocate memory
531 * @adev: amdgpu_device pointer
533 * Initializes writeback and allocates writeback memory (all asics).
534 * Used at driver startup.
535 * Returns 0 on success or an -error on failure.
537 static int amdgpu_wb_init(struct amdgpu_device
*adev
)
541 if (adev
->wb
.wb_obj
== NULL
) {
542 r
= amdgpu_bo_create_kernel(adev
, AMDGPU_MAX_WB
* sizeof(uint32_t),
543 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_GTT
,
544 &adev
->wb
.wb_obj
, &adev
->wb
.gpu_addr
,
545 (void **)&adev
->wb
.wb
);
547 dev_warn(adev
->dev
, "(%d) create WB bo failed\n", r
);
551 adev
->wb
.num_wb
= AMDGPU_MAX_WB
;
552 memset(&adev
->wb
.used
, 0, sizeof(adev
->wb
.used
));
554 /* clear wb memory */
555 memset((char *)adev
->wb
.wb
, 0, AMDGPU_MAX_WB
* sizeof(uint32_t));
562 * amdgpu_wb_get - Allocate a wb entry
564 * @adev: amdgpu_device pointer
567 * Allocate a wb slot for use by the driver (all asics).
568 * Returns 0 on success or -EINVAL on failure.
570 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
)
572 unsigned long offset
= find_first_zero_bit(adev
->wb
.used
, adev
->wb
.num_wb
);
573 if (offset
< adev
->wb
.num_wb
) {
574 __set_bit(offset
, adev
->wb
.used
);
583 * amdgpu_wb_get_64bit - Allocate a wb entry
585 * @adev: amdgpu_device pointer
588 * Allocate a wb slot for use by the driver (all asics).
589 * Returns 0 on success or -EINVAL on failure.
591 int amdgpu_wb_get_64bit(struct amdgpu_device
*adev
, u32
*wb
)
593 unsigned long offset
= bitmap_find_next_zero_area_off(adev
->wb
.used
,
594 adev
->wb
.num_wb
, 0, 2, 7, 0);
595 if ((offset
+ 1) < adev
->wb
.num_wb
) {
596 __set_bit(offset
, adev
->wb
.used
);
597 __set_bit(offset
+ 1, adev
->wb
.used
);
605 int amdgpu_wb_get_256Bit(struct amdgpu_device
*adev
, u32
*wb
)
608 unsigned long offset
= bitmap_find_next_zero_area_off(adev
->wb
.used
,
609 adev
->wb
.num_wb
, 0, 8, 63, 0);
610 if ((offset
+ 7) < adev
->wb
.num_wb
) {
611 for (i
= 0; i
< 8; i
++)
612 __set_bit(offset
+ i
, adev
->wb
.used
);
621 * amdgpu_wb_free - Free a wb entry
623 * @adev: amdgpu_device pointer
626 * Free a wb slot allocated for use by the driver (all asics)
628 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
)
630 if (wb
< adev
->wb
.num_wb
)
631 __clear_bit(wb
, adev
->wb
.used
);
635 * amdgpu_wb_free_64bit - Free a wb entry
637 * @adev: amdgpu_device pointer
640 * Free a wb slot allocated for use by the driver (all asics)
642 void amdgpu_wb_free_64bit(struct amdgpu_device
*adev
, u32 wb
)
644 if ((wb
+ 1) < adev
->wb
.num_wb
) {
645 __clear_bit(wb
, adev
->wb
.used
);
646 __clear_bit(wb
+ 1, adev
->wb
.used
);
651 * amdgpu_wb_free_256bit - Free a wb entry
653 * @adev: amdgpu_device pointer
656 * Free a wb slot allocated for use by the driver (all asics)
658 void amdgpu_wb_free_256bit(struct amdgpu_device
*adev
, u32 wb
)
662 if ((wb
+ 7) < adev
->wb
.num_wb
)
663 for (i
= 0; i
< 8; i
++)
664 __clear_bit(wb
+ i
, adev
->wb
.used
);
668 * amdgpu_vram_location - try to find VRAM location
669 * @adev: amdgpu device structure holding all necessary informations
670 * @mc: memory controller structure holding memory informations
671 * @base: base address at which to put VRAM
673 * Function will try to place VRAM at base address provided
674 * as parameter (which is so far either PCI aperture address or
675 * for IGP TOM base address).
677 * If there is not enough space to fit the unvisible VRAM in the 32bits
678 * address space then we limit the VRAM size to the aperture.
680 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
681 * this shouldn't be a problem as we are using the PCI aperture as a reference.
682 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
685 * Note: we use mc_vram_size as on some board we need to program the mc to
686 * cover the whole aperture even if VRAM size is inferior to aperture size
687 * Novell bug 204882 + along with lots of ubuntu ones
689 * Note: when limiting vram it's safe to overwritte real_vram_size because
690 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
691 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
694 * Note: IGP TOM addr should be the same as the aperture addr, we don't
695 * explicitly check for that though.
697 * FIXME: when reducing VRAM size align new size on power of 2.
699 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
)
701 uint64_t limit
= (uint64_t)amdgpu_vram_limit
<< 20;
703 mc
->vram_start
= base
;
704 if (mc
->mc_vram_size
> (adev
->mc
.mc_mask
- base
+ 1)) {
705 dev_warn(adev
->dev
, "limiting VRAM to PCI aperture size\n");
706 mc
->real_vram_size
= mc
->aper_size
;
707 mc
->mc_vram_size
= mc
->aper_size
;
709 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
710 if (limit
&& limit
< mc
->real_vram_size
)
711 mc
->real_vram_size
= limit
;
712 dev_info(adev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
713 mc
->mc_vram_size
>> 20, mc
->vram_start
,
714 mc
->vram_end
, mc
->real_vram_size
>> 20);
718 * amdgpu_gart_location - try to find GTT location
719 * @adev: amdgpu device structure holding all necessary informations
720 * @mc: memory controller structure holding memory informations
722 * Function will place try to place GTT before or after VRAM.
724 * If GTT size is bigger than space left then we ajust GTT size.
725 * Thus function will never fails.
727 * FIXME: when reducing GTT size align new size on power of 2.
729 void amdgpu_gart_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
)
731 u64 size_af
, size_bf
;
733 size_af
= adev
->mc
.mc_mask
- mc
->vram_end
;
734 size_bf
= mc
->vram_start
;
735 if (size_bf
> size_af
) {
736 if (mc
->gart_size
> size_bf
) {
737 dev_warn(adev
->dev
, "limiting GTT\n");
738 mc
->gart_size
= size_bf
;
742 if (mc
->gart_size
> size_af
) {
743 dev_warn(adev
->dev
, "limiting GTT\n");
744 mc
->gart_size
= size_af
;
746 mc
->gart_start
= mc
->vram_end
+ 1;
748 mc
->gart_end
= mc
->gart_start
+ mc
->gart_size
- 1;
749 dev_info(adev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
750 mc
->gart_size
>> 20, mc
->gart_start
, mc
->gart_end
);
754 * GPU helpers function.
757 * amdgpu_need_post - check if the hw need post or not
759 * @adev: amdgpu_device pointer
761 * Check if the asic has been initialized (all asics) at driver startup
762 * or post is needed if hw reset is performed.
763 * Returns true if need or false if not.
765 bool amdgpu_need_post(struct amdgpu_device
*adev
)
769 if (adev
->has_hw_reset
) {
770 adev
->has_hw_reset
= false;
774 /* bios scratch used on CIK+ */
775 if (adev
->asic_type
>= CHIP_BONAIRE
)
776 return amdgpu_atombios_scratch_need_asic_init(adev
);
778 /* check MEM_SIZE for older asics */
779 reg
= amdgpu_asic_get_config_memsize(adev
);
781 if ((reg
!= 0) && (reg
!= 0xffffffff))
788 static bool amdgpu_vpost_needed(struct amdgpu_device
*adev
)
790 if (amdgpu_sriov_vf(adev
))
793 if (amdgpu_passthrough(adev
)) {
794 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
795 * some old smc fw still need driver do vPost otherwise gpu hang, while
796 * those smc fw version above 22.15 doesn't have this flaw, so we force
797 * vpost executed for smc version below 22.15
799 if (adev
->asic_type
== CHIP_FIJI
) {
802 err
= request_firmware(&adev
->pm
.fw
, "amdgpu/fiji_smc.bin", adev
->dev
);
803 /* force vPost if error occured */
807 fw_ver
= *((uint32_t *)adev
->pm
.fw
->data
+ 69);
808 if (fw_ver
< 0x00160e00)
812 return amdgpu_need_post(adev
);
816 * amdgpu_dummy_page_init - init dummy page used by the driver
818 * @adev: amdgpu_device pointer
820 * Allocate the dummy page used by the driver (all asics).
821 * This dummy page is used by the driver as a filler for gart entries
822 * when pages are taken out of the GART
823 * Returns 0 on sucess, -ENOMEM on failure.
825 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
)
827 if (adev
->dummy_page
.page
)
829 adev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
830 if (adev
->dummy_page
.page
== NULL
)
832 adev
->dummy_page
.addr
= pci_map_page(adev
->pdev
, adev
->dummy_page
.page
,
833 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
834 if (pci_dma_mapping_error(adev
->pdev
, adev
->dummy_page
.addr
)) {
835 dev_err(&adev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
836 __free_page(adev
->dummy_page
.page
);
837 adev
->dummy_page
.page
= NULL
;
844 * amdgpu_dummy_page_fini - free dummy page used by the driver
846 * @adev: amdgpu_device pointer
848 * Frees the dummy page used by the driver (all asics).
850 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
)
852 if (adev
->dummy_page
.page
== NULL
)
854 pci_unmap_page(adev
->pdev
, adev
->dummy_page
.addr
,
855 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
856 __free_page(adev
->dummy_page
.page
);
857 adev
->dummy_page
.page
= NULL
;
861 /* ATOM accessor methods */
863 * ATOM is an interpreted byte code stored in tables in the vbios. The
864 * driver registers callbacks to access registers and the interpreter
865 * in the driver parses the tables and executes then to program specific
866 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
867 * atombios.h, and atom.c
871 * cail_pll_read - read PLL register
873 * @info: atom card_info pointer
874 * @reg: PLL register offset
876 * Provides a PLL register accessor for the atom interpreter (r4xx+).
877 * Returns the value of the PLL register.
879 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
885 * cail_pll_write - write PLL register
887 * @info: atom card_info pointer
888 * @reg: PLL register offset
889 * @val: value to write to the pll register
891 * Provides a PLL register accessor for the atom interpreter (r4xx+).
893 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
899 * cail_mc_read - read MC (Memory Controller) register
901 * @info: atom card_info pointer
902 * @reg: MC register offset
904 * Provides an MC register accessor for the atom interpreter (r4xx+).
905 * Returns the value of the MC register.
907 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
913 * cail_mc_write - write MC (Memory Controller) register
915 * @info: atom card_info pointer
916 * @reg: MC register offset
917 * @val: value to write to the pll register
919 * Provides a MC register accessor for the atom interpreter (r4xx+).
921 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
927 * cail_reg_write - write MMIO register
929 * @info: atom card_info pointer
930 * @reg: MMIO register offset
931 * @val: value to write to the pll register
933 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
935 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
937 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
943 * cail_reg_read - read MMIO register
945 * @info: atom card_info pointer
946 * @reg: MMIO register offset
948 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
949 * Returns the value of the MMIO register.
951 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
953 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
961 * cail_ioreg_write - write IO register
963 * @info: atom card_info pointer
964 * @reg: IO register offset
965 * @val: value to write to the pll register
967 * Provides a IO register accessor for the atom interpreter (r4xx+).
969 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
971 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
977 * cail_ioreg_read - read IO register
979 * @info: atom card_info pointer
980 * @reg: IO register offset
982 * Provides an IO register accessor for the atom interpreter (r4xx+).
983 * Returns the value of the IO register.
985 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
987 struct amdgpu_device
*adev
= info
->dev
->dev_private
;
995 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
997 * @adev: amdgpu_device pointer
999 * Frees the driver info and register access callbacks for the ATOM
1000 * interpreter (r4xx+).
1001 * Called at driver shutdown.
1003 static void amdgpu_atombios_fini(struct amdgpu_device
*adev
)
1005 if (adev
->mode_info
.atom_context
) {
1006 kfree(adev
->mode_info
.atom_context
->scratch
);
1007 kfree(adev
->mode_info
.atom_context
->iio
);
1009 kfree(adev
->mode_info
.atom_context
);
1010 adev
->mode_info
.atom_context
= NULL
;
1011 kfree(adev
->mode_info
.atom_card_info
);
1012 adev
->mode_info
.atom_card_info
= NULL
;
1016 * amdgpu_atombios_init - init the driver info and callbacks for atombios
1018 * @adev: amdgpu_device pointer
1020 * Initializes the driver info and register access callbacks for the
1021 * ATOM interpreter (r4xx+).
1022 * Returns 0 on sucess, -ENOMEM on failure.
1023 * Called at driver startup.
1025 static int amdgpu_atombios_init(struct amdgpu_device
*adev
)
1027 struct card_info
*atom_card_info
=
1028 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
1030 if (!atom_card_info
)
1033 adev
->mode_info
.atom_card_info
= atom_card_info
;
1034 atom_card_info
->dev
= adev
->ddev
;
1035 atom_card_info
->reg_read
= cail_reg_read
;
1036 atom_card_info
->reg_write
= cail_reg_write
;
1037 /* needed for iio ops */
1038 if (adev
->rio_mem
) {
1039 atom_card_info
->ioreg_read
= cail_ioreg_read
;
1040 atom_card_info
->ioreg_write
= cail_ioreg_write
;
1042 DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
1043 atom_card_info
->ioreg_read
= cail_reg_read
;
1044 atom_card_info
->ioreg_write
= cail_reg_write
;
1046 atom_card_info
->mc_read
= cail_mc_read
;
1047 atom_card_info
->mc_write
= cail_mc_write
;
1048 atom_card_info
->pll_read
= cail_pll_read
;
1049 atom_card_info
->pll_write
= cail_pll_write
;
1051 adev
->mode_info
.atom_context
= amdgpu_atom_parse(atom_card_info
, adev
->bios
);
1052 if (!adev
->mode_info
.atom_context
) {
1053 amdgpu_atombios_fini(adev
);
1057 mutex_init(&adev
->mode_info
.atom_context
->mutex
);
1058 if (adev
->is_atom_fw
) {
1059 amdgpu_atomfirmware_scratch_regs_init(adev
);
1060 amdgpu_atomfirmware_allocate_fb_scratch(adev
);
1062 amdgpu_atombios_scratch_regs_init(adev
);
1063 amdgpu_atombios_allocate_fb_scratch(adev
);
1068 /* if we get transitioned to only one device, take VGA back */
1070 * amdgpu_vga_set_decode - enable/disable vga decode
1072 * @cookie: amdgpu_device pointer
1073 * @state: enable/disable vga decode
1075 * Enable/disable vga decode (all asics).
1076 * Returns VGA resource flags.
1078 static unsigned int amdgpu_vga_set_decode(void *cookie
, bool state
)
1080 struct amdgpu_device
*adev
= cookie
;
1081 amdgpu_asic_set_vga_state(adev
, state
);
1083 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1084 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1086 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1089 static void amdgpu_check_block_size(struct amdgpu_device
*adev
)
1091 /* defines number of bits in page table versus page directory,
1092 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1093 * page table and the remaining bits are in the page directory */
1094 if (amdgpu_vm_block_size
== -1)
1097 if (amdgpu_vm_block_size
< 9) {
1098 dev_warn(adev
->dev
, "VM page table size (%d) too small\n",
1099 amdgpu_vm_block_size
);
1103 if (amdgpu_vm_block_size
> 24 ||
1104 (amdgpu_vm_size
* 1024) < (1ull << amdgpu_vm_block_size
)) {
1105 dev_warn(adev
->dev
, "VM page table size (%d) too large\n",
1106 amdgpu_vm_block_size
);
1113 amdgpu_vm_block_size
= -1;
1116 static void amdgpu_check_vm_size(struct amdgpu_device
*adev
)
1118 /* no need to check the default value */
1119 if (amdgpu_vm_size
== -1)
1122 if (!is_power_of_2(amdgpu_vm_size
)) {
1123 dev_warn(adev
->dev
, "VM size (%d) must be a power of 2\n",
1128 if (amdgpu_vm_size
< 1) {
1129 dev_warn(adev
->dev
, "VM size (%d) too small, min is 1GB\n",
1135 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1137 if (amdgpu_vm_size
> 1024) {
1138 dev_warn(adev
->dev
, "VM size (%d) too large, max is 1TB\n",
1146 amdgpu_vm_size
= -1;
1150 * amdgpu_check_arguments - validate module params
1152 * @adev: amdgpu_device pointer
1154 * Validates certain module parameters and updates
1155 * the associated values used by the driver (all asics).
1157 static void amdgpu_check_arguments(struct amdgpu_device
*adev
)
1159 if (amdgpu_sched_jobs
< 4) {
1160 dev_warn(adev
->dev
, "sched jobs (%d) must be at least 4\n",
1162 amdgpu_sched_jobs
= 4;
1163 } else if (!is_power_of_2(amdgpu_sched_jobs
)){
1164 dev_warn(adev
->dev
, "sched jobs (%d) must be a power of 2\n",
1166 amdgpu_sched_jobs
= roundup_pow_of_two(amdgpu_sched_jobs
);
1169 if (amdgpu_gart_size
< 32) {
1170 /* gart size must be greater or equal to 32M */
1171 dev_warn(adev
->dev
, "gart size (%d) too small\n",
1173 amdgpu_gart_size
= 32;
1176 if (amdgpu_gtt_size
!= -1 && amdgpu_gtt_size
< 32) {
1177 /* gtt size must be greater or equal to 32M */
1178 dev_warn(adev
->dev
, "gtt size (%d) too small\n",
1180 amdgpu_gtt_size
= -1;
1183 amdgpu_check_vm_size(adev
);
1185 amdgpu_check_block_size(adev
);
1187 if (amdgpu_vram_page_split
!= -1 && (amdgpu_vram_page_split
< 16 ||
1188 !is_power_of_2(amdgpu_vram_page_split
))) {
1189 dev_warn(adev
->dev
, "invalid VRAM page split (%d)\n",
1190 amdgpu_vram_page_split
);
1191 amdgpu_vram_page_split
= 1024;
1196 * amdgpu_switcheroo_set_state - set switcheroo state
1198 * @pdev: pci dev pointer
1199 * @state: vga_switcheroo state
1201 * Callback for the switcheroo driver. Suspends or resumes the
1202 * the asics before or after it is powered up using ACPI methods.
1204 static void amdgpu_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1206 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1208 if (amdgpu_device_is_px(dev
) && state
== VGA_SWITCHEROO_OFF
)
1211 if (state
== VGA_SWITCHEROO_ON
) {
1212 pr_info("amdgpu: switched on\n");
1213 /* don't suspend or resume card normally */
1214 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1216 amdgpu_device_resume(dev
, true, true);
1218 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1219 drm_kms_helper_poll_enable(dev
);
1221 pr_info("amdgpu: switched off\n");
1222 drm_kms_helper_poll_disable(dev
);
1223 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1224 amdgpu_device_suspend(dev
, true, true);
1225 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1230 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1232 * @pdev: pci dev pointer
1234 * Callback for the switcheroo driver. Check of the switcheroo
1235 * state can be changed.
1236 * Returns true if the state can be changed, false if not.
1238 static bool amdgpu_switcheroo_can_switch(struct pci_dev
*pdev
)
1240 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1243 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1244 * locking inversion with the driver load path. And the access here is
1245 * completely racy anyway. So don't bother with locking for now.
1247 return dev
->open_count
== 0;
1250 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops
= {
1251 .set_gpu_state
= amdgpu_switcheroo_set_state
,
1253 .can_switch
= amdgpu_switcheroo_can_switch
,
1256 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
1257 enum amd_ip_block_type block_type
,
1258 enum amd_clockgating_state state
)
1262 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1263 if (!adev
->ip_blocks
[i
].status
.valid
)
1265 if (adev
->ip_blocks
[i
].version
->type
!= block_type
)
1267 if (!adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state
)
1269 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state(
1270 (void *)adev
, state
);
1272 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1273 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1278 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
1279 enum amd_ip_block_type block_type
,
1280 enum amd_powergating_state state
)
1284 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1285 if (!adev
->ip_blocks
[i
].status
.valid
)
1287 if (adev
->ip_blocks
[i
].version
->type
!= block_type
)
1289 if (!adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state
)
1291 r
= adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state(
1292 (void *)adev
, state
);
1294 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1295 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1300 void amdgpu_get_clockgating_state(struct amdgpu_device
*adev
, u32
*flags
)
1304 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1305 if (!adev
->ip_blocks
[i
].status
.valid
)
1307 if (adev
->ip_blocks
[i
].version
->funcs
->get_clockgating_state
)
1308 adev
->ip_blocks
[i
].version
->funcs
->get_clockgating_state((void *)adev
, flags
);
1312 int amdgpu_wait_for_idle(struct amdgpu_device
*adev
,
1313 enum amd_ip_block_type block_type
)
1317 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1318 if (!adev
->ip_blocks
[i
].status
.valid
)
1320 if (adev
->ip_blocks
[i
].version
->type
== block_type
) {
1321 r
= adev
->ip_blocks
[i
].version
->funcs
->wait_for_idle((void *)adev
);
1331 bool amdgpu_is_idle(struct amdgpu_device
*adev
,
1332 enum amd_ip_block_type block_type
)
1336 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1337 if (!adev
->ip_blocks
[i
].status
.valid
)
1339 if (adev
->ip_blocks
[i
].version
->type
== block_type
)
1340 return adev
->ip_blocks
[i
].version
->funcs
->is_idle((void *)adev
);
1346 struct amdgpu_ip_block
* amdgpu_get_ip_block(struct amdgpu_device
*adev
,
1347 enum amd_ip_block_type type
)
1351 for (i
= 0; i
< adev
->num_ip_blocks
; i
++)
1352 if (adev
->ip_blocks
[i
].version
->type
== type
)
1353 return &adev
->ip_blocks
[i
];
1359 * amdgpu_ip_block_version_cmp
1361 * @adev: amdgpu_device pointer
1362 * @type: enum amd_ip_block_type
1363 * @major: major version
1364 * @minor: minor version
1366 * return 0 if equal or greater
1367 * return 1 if smaller or the ip_block doesn't exist
1369 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
1370 enum amd_ip_block_type type
,
1371 u32 major
, u32 minor
)
1373 struct amdgpu_ip_block
*ip_block
= amdgpu_get_ip_block(adev
, type
);
1375 if (ip_block
&& ((ip_block
->version
->major
> major
) ||
1376 ((ip_block
->version
->major
== major
) &&
1377 (ip_block
->version
->minor
>= minor
))))
1384 * amdgpu_ip_block_add
1386 * @adev: amdgpu_device pointer
1387 * @ip_block_version: pointer to the IP to add
1389 * Adds the IP block driver information to the collection of IPs
1392 int amdgpu_ip_block_add(struct amdgpu_device
*adev
,
1393 const struct amdgpu_ip_block_version
*ip_block_version
)
1395 if (!ip_block_version
)
1398 DRM_DEBUG("add ip block number %d <%s>\n", adev
->num_ip_blocks
,
1399 ip_block_version
->funcs
->name
);
1401 adev
->ip_blocks
[adev
->num_ip_blocks
++].version
= ip_block_version
;
1406 static void amdgpu_device_enable_virtual_display(struct amdgpu_device
*adev
)
1408 adev
->enable_virtual_display
= false;
1410 if (amdgpu_virtual_display
) {
1411 struct drm_device
*ddev
= adev
->ddev
;
1412 const char *pci_address_name
= pci_name(ddev
->pdev
);
1413 char *pciaddstr
, *pciaddstr_tmp
, *pciaddname_tmp
, *pciaddname
;
1415 pciaddstr
= kstrdup(amdgpu_virtual_display
, GFP_KERNEL
);
1416 pciaddstr_tmp
= pciaddstr
;
1417 while ((pciaddname_tmp
= strsep(&pciaddstr_tmp
, ";"))) {
1418 pciaddname
= strsep(&pciaddname_tmp
, ",");
1419 if (!strcmp("all", pciaddname
)
1420 || !strcmp(pci_address_name
, pciaddname
)) {
1424 adev
->enable_virtual_display
= true;
1427 res
= kstrtol(pciaddname_tmp
, 10,
1435 adev
->mode_info
.num_crtc
= num_crtc
;
1437 adev
->mode_info
.num_crtc
= 1;
1443 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1444 amdgpu_virtual_display
, pci_address_name
,
1445 adev
->enable_virtual_display
, adev
->mode_info
.num_crtc
);
1451 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device
*adev
)
1453 const char *chip_name
;
1456 const struct gpu_info_firmware_header_v1_0
*hdr
;
1458 adev
->firmware
.gpu_info_fw
= NULL
;
1460 switch (adev
->asic_type
) {
1464 case CHIP_POLARIS11
:
1465 case CHIP_POLARIS10
:
1466 case CHIP_POLARIS12
:
1469 #ifdef CONFIG_DRM_AMDGPU_SI
1476 #ifdef CONFIG_DRM_AMDGPU_CIK
1486 chip_name
= "vega10";
1489 chip_name
= "raven";
1493 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_gpu_info.bin", chip_name
);
1494 err
= request_firmware(&adev
->firmware
.gpu_info_fw
, fw_name
, adev
->dev
);
1497 "Failed to load gpu_info firmware \"%s\"\n",
1501 err
= amdgpu_ucode_validate(adev
->firmware
.gpu_info_fw
);
1504 "Failed to validate gpu_info firmware \"%s\"\n",
1509 hdr
= (const struct gpu_info_firmware_header_v1_0
*)adev
->firmware
.gpu_info_fw
->data
;
1510 amdgpu_ucode_print_gpu_info_hdr(&hdr
->header
);
1512 switch (hdr
->version_major
) {
1515 const struct gpu_info_firmware_v1_0
*gpu_info_fw
=
1516 (const struct gpu_info_firmware_v1_0
*)(adev
->firmware
.gpu_info_fw
->data
+
1517 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
1519 adev
->gfx
.config
.max_shader_engines
= le32_to_cpu(gpu_info_fw
->gc_num_se
);
1520 adev
->gfx
.config
.max_cu_per_sh
= le32_to_cpu(gpu_info_fw
->gc_num_cu_per_sh
);
1521 adev
->gfx
.config
.max_sh_per_se
= le32_to_cpu(gpu_info_fw
->gc_num_sh_per_se
);
1522 adev
->gfx
.config
.max_backends_per_se
= le32_to_cpu(gpu_info_fw
->gc_num_rb_per_se
);
1523 adev
->gfx
.config
.max_texture_channel_caches
=
1524 le32_to_cpu(gpu_info_fw
->gc_num_tccs
);
1525 adev
->gfx
.config
.max_gprs
= le32_to_cpu(gpu_info_fw
->gc_num_gprs
);
1526 adev
->gfx
.config
.max_gs_threads
= le32_to_cpu(gpu_info_fw
->gc_num_max_gs_thds
);
1527 adev
->gfx
.config
.gs_vgt_table_depth
= le32_to_cpu(gpu_info_fw
->gc_gs_table_depth
);
1528 adev
->gfx
.config
.gs_prim_buffer_depth
= le32_to_cpu(gpu_info_fw
->gc_gsprim_buff_depth
);
1529 adev
->gfx
.config
.double_offchip_lds_buf
=
1530 le32_to_cpu(gpu_info_fw
->gc_double_offchip_lds_buffer
);
1531 adev
->gfx
.cu_info
.wave_front_size
= le32_to_cpu(gpu_info_fw
->gc_wave_size
);
1532 adev
->gfx
.cu_info
.max_waves_per_simd
=
1533 le32_to_cpu(gpu_info_fw
->gc_max_waves_per_simd
);
1534 adev
->gfx
.cu_info
.max_scratch_slots_per_cu
=
1535 le32_to_cpu(gpu_info_fw
->gc_max_scratch_slots_per_cu
);
1536 adev
->gfx
.cu_info
.lds_size
= le32_to_cpu(gpu_info_fw
->gc_lds_size
);
1541 "Unsupported gpu_info table %d\n", hdr
->header
.ucode_version
);
1549 static int amdgpu_early_init(struct amdgpu_device
*adev
)
1553 amdgpu_device_enable_virtual_display(adev
);
1555 switch (adev
->asic_type
) {
1559 case CHIP_POLARIS11
:
1560 case CHIP_POLARIS10
:
1561 case CHIP_POLARIS12
:
1564 if (adev
->asic_type
== CHIP_CARRIZO
|| adev
->asic_type
== CHIP_STONEY
)
1565 adev
->family
= AMDGPU_FAMILY_CZ
;
1567 adev
->family
= AMDGPU_FAMILY_VI
;
1569 r
= vi_set_ip_blocks(adev
);
1573 #ifdef CONFIG_DRM_AMDGPU_SI
1579 adev
->family
= AMDGPU_FAMILY_SI
;
1580 r
= si_set_ip_blocks(adev
);
1585 #ifdef CONFIG_DRM_AMDGPU_CIK
1591 if ((adev
->asic_type
== CHIP_BONAIRE
) || (adev
->asic_type
== CHIP_HAWAII
))
1592 adev
->family
= AMDGPU_FAMILY_CI
;
1594 adev
->family
= AMDGPU_FAMILY_KV
;
1596 r
= cik_set_ip_blocks(adev
);
1603 if (adev
->asic_type
== CHIP_RAVEN
)
1604 adev
->family
= AMDGPU_FAMILY_RV
;
1606 adev
->family
= AMDGPU_FAMILY_AI
;
1608 r
= soc15_set_ip_blocks(adev
);
1613 /* FIXME: not supported yet */
1617 r
= amdgpu_device_parse_gpu_info_fw(adev
);
1621 if (amdgpu_sriov_vf(adev
)) {
1622 r
= amdgpu_virt_request_full_gpu(adev
, true);
1627 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1628 if ((amdgpu_ip_block_mask
& (1 << i
)) == 0) {
1629 DRM_ERROR("disabled ip block: %d <%s>\n",
1630 i
, adev
->ip_blocks
[i
].version
->funcs
->name
);
1631 adev
->ip_blocks
[i
].status
.valid
= false;
1633 if (adev
->ip_blocks
[i
].version
->funcs
->early_init
) {
1634 r
= adev
->ip_blocks
[i
].version
->funcs
->early_init((void *)adev
);
1636 adev
->ip_blocks
[i
].status
.valid
= false;
1638 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1639 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1642 adev
->ip_blocks
[i
].status
.valid
= true;
1645 adev
->ip_blocks
[i
].status
.valid
= true;
1650 adev
->cg_flags
&= amdgpu_cg_mask
;
1651 adev
->pg_flags
&= amdgpu_pg_mask
;
1656 static int amdgpu_init(struct amdgpu_device
*adev
)
1660 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1661 if (!adev
->ip_blocks
[i
].status
.valid
)
1663 r
= adev
->ip_blocks
[i
].version
->funcs
->sw_init((void *)adev
);
1665 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1666 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1669 adev
->ip_blocks
[i
].status
.sw
= true;
1670 /* need to do gmc hw init early so we can allocate gpu mem */
1671 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) {
1672 r
= amdgpu_vram_scratch_init(adev
);
1674 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r
);
1677 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init((void *)adev
);
1679 DRM_ERROR("hw_init %d failed %d\n", i
, r
);
1682 r
= amdgpu_wb_init(adev
);
1684 DRM_ERROR("amdgpu_wb_init failed %d\n", r
);
1687 adev
->ip_blocks
[i
].status
.hw
= true;
1689 /* right after GMC hw init, we create CSA */
1690 if (amdgpu_sriov_vf(adev
)) {
1691 r
= amdgpu_allocate_static_csa(adev
);
1693 DRM_ERROR("allocate CSA failed %d\n", r
);
1700 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1701 if (!adev
->ip_blocks
[i
].status
.sw
)
1703 /* gmc hw init is done early */
1704 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
)
1706 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init((void *)adev
);
1708 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1709 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1712 adev
->ip_blocks
[i
].status
.hw
= true;
1718 static void amdgpu_fill_reset_magic(struct amdgpu_device
*adev
)
1720 memcpy(adev
->reset_magic
, adev
->gart
.ptr
, AMDGPU_RESET_MAGIC_NUM
);
1723 static bool amdgpu_check_vram_lost(struct amdgpu_device
*adev
)
1725 return !!memcmp(adev
->gart
.ptr
, adev
->reset_magic
,
1726 AMDGPU_RESET_MAGIC_NUM
);
1729 static int amdgpu_late_set_cg_state(struct amdgpu_device
*adev
)
1733 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1734 if (!adev
->ip_blocks
[i
].status
.valid
)
1736 /* skip CG for VCE/UVD, it's handled specially */
1737 if (adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_UVD
&&
1738 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCE
) {
1739 /* enable clockgating to save power */
1740 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1743 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1744 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1752 static int amdgpu_late_init(struct amdgpu_device
*adev
)
1756 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1757 if (!adev
->ip_blocks
[i
].status
.valid
)
1759 if (adev
->ip_blocks
[i
].version
->funcs
->late_init
) {
1760 r
= adev
->ip_blocks
[i
].version
->funcs
->late_init((void *)adev
);
1762 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1763 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1766 adev
->ip_blocks
[i
].status
.late_initialized
= true;
1770 mod_delayed_work(system_wq
, &adev
->late_init_work
,
1771 msecs_to_jiffies(AMDGPU_RESUME_MS
));
1773 amdgpu_fill_reset_magic(adev
);
1778 static int amdgpu_fini(struct amdgpu_device
*adev
)
1782 /* need to disable SMC first */
1783 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1784 if (!adev
->ip_blocks
[i
].status
.hw
)
1786 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_SMC
) {
1787 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1788 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1789 AMD_CG_STATE_UNGATE
);
1791 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1792 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1795 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_fini((void *)adev
);
1796 /* XXX handle errors */
1798 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1799 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1801 adev
->ip_blocks
[i
].status
.hw
= false;
1806 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1807 if (!adev
->ip_blocks
[i
].status
.hw
)
1809 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) {
1810 amdgpu_wb_fini(adev
);
1811 amdgpu_vram_scratch_fini(adev
);
1814 if (adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_UVD
&&
1815 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCE
) {
1816 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1817 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1818 AMD_CG_STATE_UNGATE
);
1820 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1821 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1826 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_fini((void *)adev
);
1827 /* XXX handle errors */
1829 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1830 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1833 adev
->ip_blocks
[i
].status
.hw
= false;
1836 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1837 if (!adev
->ip_blocks
[i
].status
.sw
)
1839 r
= adev
->ip_blocks
[i
].version
->funcs
->sw_fini((void *)adev
);
1840 /* XXX handle errors */
1842 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1843 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1845 adev
->ip_blocks
[i
].status
.sw
= false;
1846 adev
->ip_blocks
[i
].status
.valid
= false;
1849 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1850 if (!adev
->ip_blocks
[i
].status
.late_initialized
)
1852 if (adev
->ip_blocks
[i
].version
->funcs
->late_fini
)
1853 adev
->ip_blocks
[i
].version
->funcs
->late_fini((void *)adev
);
1854 adev
->ip_blocks
[i
].status
.late_initialized
= false;
1857 if (amdgpu_sriov_vf(adev
)) {
1858 amdgpu_bo_free_kernel(&adev
->virt
.csa_obj
, &adev
->virt
.csa_vmid0_addr
, NULL
);
1859 amdgpu_virt_release_full_gpu(adev
, false);
1865 static void amdgpu_late_init_func_handler(struct work_struct
*work
)
1867 struct amdgpu_device
*adev
=
1868 container_of(work
, struct amdgpu_device
, late_init_work
.work
);
1869 amdgpu_late_set_cg_state(adev
);
1872 int amdgpu_suspend(struct amdgpu_device
*adev
)
1876 if (amdgpu_sriov_vf(adev
))
1877 amdgpu_virt_request_full_gpu(adev
, false);
1879 /* ungate SMC block first */
1880 r
= amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_SMC
,
1881 AMD_CG_STATE_UNGATE
);
1883 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r
);
1886 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
1887 if (!adev
->ip_blocks
[i
].status
.valid
)
1889 /* ungate blocks so that suspend can properly shut them down */
1890 if (i
!= AMD_IP_BLOCK_TYPE_SMC
) {
1891 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
1892 AMD_CG_STATE_UNGATE
);
1894 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1895 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1898 /* XXX handle errors */
1899 r
= adev
->ip_blocks
[i
].version
->funcs
->suspend(adev
);
1900 /* XXX handle errors */
1902 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1903 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1907 if (amdgpu_sriov_vf(adev
))
1908 amdgpu_virt_release_full_gpu(adev
, false);
1913 static int amdgpu_sriov_reinit_early(struct amdgpu_device
*adev
)
1917 static enum amd_ip_block_type ip_order
[] = {
1918 AMD_IP_BLOCK_TYPE_GMC
,
1919 AMD_IP_BLOCK_TYPE_COMMON
,
1920 AMD_IP_BLOCK_TYPE_IH
,
1923 for (i
= 0; i
< ARRAY_SIZE(ip_order
); i
++) {
1925 struct amdgpu_ip_block
*block
;
1927 for (j
= 0; j
< adev
->num_ip_blocks
; j
++) {
1928 block
= &adev
->ip_blocks
[j
];
1930 if (block
->version
->type
!= ip_order
[i
] ||
1931 !block
->status
.valid
)
1934 r
= block
->version
->funcs
->hw_init(adev
);
1935 DRM_INFO("RE-INIT: %s %s\n", block
->version
->funcs
->name
, r
?"failed":"successed");
1942 static int amdgpu_sriov_reinit_late(struct amdgpu_device
*adev
)
1946 static enum amd_ip_block_type ip_order
[] = {
1947 AMD_IP_BLOCK_TYPE_SMC
,
1948 AMD_IP_BLOCK_TYPE_DCE
,
1949 AMD_IP_BLOCK_TYPE_GFX
,
1950 AMD_IP_BLOCK_TYPE_SDMA
,
1951 AMD_IP_BLOCK_TYPE_VCE
,
1954 for (i
= 0; i
< ARRAY_SIZE(ip_order
); i
++) {
1956 struct amdgpu_ip_block
*block
;
1958 for (j
= 0; j
< adev
->num_ip_blocks
; j
++) {
1959 block
= &adev
->ip_blocks
[j
];
1961 if (block
->version
->type
!= ip_order
[i
] ||
1962 !block
->status
.valid
)
1965 r
= block
->version
->funcs
->hw_init(adev
);
1966 DRM_INFO("RE-INIT: %s %s\n", block
->version
->funcs
->name
, r
?"failed":"successed");
1973 static int amdgpu_resume_phase1(struct amdgpu_device
*adev
)
1977 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1978 if (!adev
->ip_blocks
[i
].status
.valid
)
1980 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_COMMON
||
1981 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
||
1982 adev
->ip_blocks
[i
].version
->type
==
1983 AMD_IP_BLOCK_TYPE_IH
) {
1984 r
= adev
->ip_blocks
[i
].version
->funcs
->resume(adev
);
1986 DRM_ERROR("resume of IP block <%s> failed %d\n",
1987 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1996 static int amdgpu_resume_phase2(struct amdgpu_device
*adev
)
2000 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2001 if (!adev
->ip_blocks
[i
].status
.valid
)
2003 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_COMMON
||
2004 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
||
2005 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_IH
)
2007 r
= adev
->ip_blocks
[i
].version
->funcs
->resume(adev
);
2009 DRM_ERROR("resume of IP block <%s> failed %d\n",
2010 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2018 static int amdgpu_resume(struct amdgpu_device
*adev
)
2022 r
= amdgpu_resume_phase1(adev
);
2025 r
= amdgpu_resume_phase2(adev
);
2030 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device
*adev
)
2032 if (adev
->is_atom_fw
) {
2033 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev
))
2034 adev
->virt
.caps
|= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS
;
2036 if (amdgpu_atombios_has_gpu_virtualization_table(adev
))
2037 adev
->virt
.caps
|= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS
;
2042 * amdgpu_device_init - initialize the driver
2044 * @adev: amdgpu_device pointer
2045 * @pdev: drm dev pointer
2046 * @pdev: pci dev pointer
2047 * @flags: driver flags
2049 * Initializes the driver info and hw (all asics).
2050 * Returns 0 for success or an error on failure.
2051 * Called at driver startup.
2053 int amdgpu_device_init(struct amdgpu_device
*adev
,
2054 struct drm_device
*ddev
,
2055 struct pci_dev
*pdev
,
2059 bool runtime
= false;
2062 adev
->shutdown
= false;
2063 adev
->dev
= &pdev
->dev
;
2066 adev
->flags
= flags
;
2067 adev
->asic_type
= flags
& AMD_ASIC_MASK
;
2068 adev
->usec_timeout
= AMDGPU_MAX_USEC_TIMEOUT
;
2069 adev
->mc
.gart_size
= 512 * 1024 * 1024;
2070 adev
->accel_working
= false;
2071 adev
->num_rings
= 0;
2072 adev
->mman
.buffer_funcs
= NULL
;
2073 adev
->mman
.buffer_funcs_ring
= NULL
;
2074 adev
->vm_manager
.vm_pte_funcs
= NULL
;
2075 adev
->vm_manager
.vm_pte_num_rings
= 0;
2076 adev
->gart
.gart_funcs
= NULL
;
2077 adev
->fence_context
= dma_fence_context_alloc(AMDGPU_MAX_RINGS
);
2079 adev
->smc_rreg
= &amdgpu_invalid_rreg
;
2080 adev
->smc_wreg
= &amdgpu_invalid_wreg
;
2081 adev
->pcie_rreg
= &amdgpu_invalid_rreg
;
2082 adev
->pcie_wreg
= &amdgpu_invalid_wreg
;
2083 adev
->pciep_rreg
= &amdgpu_invalid_rreg
;
2084 adev
->pciep_wreg
= &amdgpu_invalid_wreg
;
2085 adev
->uvd_ctx_rreg
= &amdgpu_invalid_rreg
;
2086 adev
->uvd_ctx_wreg
= &amdgpu_invalid_wreg
;
2087 adev
->didt_rreg
= &amdgpu_invalid_rreg
;
2088 adev
->didt_wreg
= &amdgpu_invalid_wreg
;
2089 adev
->gc_cac_rreg
= &amdgpu_invalid_rreg
;
2090 adev
->gc_cac_wreg
= &amdgpu_invalid_wreg
;
2091 adev
->audio_endpt_rreg
= &amdgpu_block_invalid_rreg
;
2092 adev
->audio_endpt_wreg
= &amdgpu_block_invalid_wreg
;
2095 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2096 amdgpu_asic_name
[adev
->asic_type
], pdev
->vendor
, pdev
->device
,
2097 pdev
->subsystem_vendor
, pdev
->subsystem_device
, pdev
->revision
);
2099 /* mutex initialization are all done here so we
2100 * can recall function without having locking issues */
2101 atomic_set(&adev
->irq
.ih
.lock
, 0);
2102 mutex_init(&adev
->firmware
.mutex
);
2103 mutex_init(&adev
->pm
.mutex
);
2104 mutex_init(&adev
->gfx
.gpu_clock_mutex
);
2105 mutex_init(&adev
->srbm_mutex
);
2106 mutex_init(&adev
->grbm_idx_mutex
);
2107 mutex_init(&adev
->mn_lock
);
2108 hash_init(adev
->mn_hash
);
2110 amdgpu_check_arguments(adev
);
2112 spin_lock_init(&adev
->mmio_idx_lock
);
2113 spin_lock_init(&adev
->smc_idx_lock
);
2114 spin_lock_init(&adev
->pcie_idx_lock
);
2115 spin_lock_init(&adev
->uvd_ctx_idx_lock
);
2116 spin_lock_init(&adev
->didt_idx_lock
);
2117 spin_lock_init(&adev
->gc_cac_idx_lock
);
2118 spin_lock_init(&adev
->se_cac_idx_lock
);
2119 spin_lock_init(&adev
->audio_endpt_idx_lock
);
2120 spin_lock_init(&adev
->mm_stats
.lock
);
2122 INIT_LIST_HEAD(&adev
->shadow_list
);
2123 mutex_init(&adev
->shadow_list_lock
);
2125 INIT_LIST_HEAD(&adev
->gtt_list
);
2126 spin_lock_init(&adev
->gtt_list_lock
);
2128 INIT_LIST_HEAD(&adev
->ring_lru_list
);
2129 spin_lock_init(&adev
->ring_lru_list_lock
);
2131 INIT_DELAYED_WORK(&adev
->late_init_work
, amdgpu_late_init_func_handler
);
2133 /* Registers mapping */
2134 /* TODO: block userspace mapping of io register */
2135 if (adev
->asic_type
>= CHIP_BONAIRE
) {
2136 adev
->rmmio_base
= pci_resource_start(adev
->pdev
, 5);
2137 adev
->rmmio_size
= pci_resource_len(adev
->pdev
, 5);
2139 adev
->rmmio_base
= pci_resource_start(adev
->pdev
, 2);
2140 adev
->rmmio_size
= pci_resource_len(adev
->pdev
, 2);
2143 adev
->rmmio
= ioremap(adev
->rmmio_base
, adev
->rmmio_size
);
2144 if (adev
->rmmio
== NULL
) {
2147 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev
->rmmio_base
);
2148 DRM_INFO("register mmio size: %u\n", (unsigned)adev
->rmmio_size
);
2150 if (adev
->asic_type
>= CHIP_BONAIRE
)
2151 /* doorbell bar mapping */
2152 amdgpu_doorbell_init(adev
);
2154 /* io port mapping */
2155 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
2156 if (pci_resource_flags(adev
->pdev
, i
) & IORESOURCE_IO
) {
2157 adev
->rio_mem_size
= pci_resource_len(adev
->pdev
, i
);
2158 adev
->rio_mem
= pci_iomap(adev
->pdev
, i
, adev
->rio_mem_size
);
2162 if (adev
->rio_mem
== NULL
)
2163 DRM_INFO("PCI I/O BAR is not found.\n");
2165 /* early init functions */
2166 r
= amdgpu_early_init(adev
);
2170 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2171 /* this will fail for cards that aren't VGA class devices, just
2173 vga_client_register(adev
->pdev
, adev
, NULL
, amdgpu_vga_set_decode
);
2175 if (amdgpu_runtime_pm
== 1)
2177 if (amdgpu_device_is_px(ddev
))
2179 if (!pci_is_thunderbolt_attached(adev
->pdev
))
2180 vga_switcheroo_register_client(adev
->pdev
,
2181 &amdgpu_switcheroo_ops
, runtime
);
2183 vga_switcheroo_init_domain_pm_ops(adev
->dev
, &adev
->vga_pm_domain
);
2186 if (!amdgpu_get_bios(adev
)) {
2191 r
= amdgpu_atombios_init(adev
);
2193 dev_err(adev
->dev
, "amdgpu_atombios_init failed\n");
2194 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL
, 0, 0);
2198 /* detect if we are with an SRIOV vbios */
2199 amdgpu_device_detect_sriov_bios(adev
);
2201 /* Post card if necessary */
2202 if (amdgpu_vpost_needed(adev
)) {
2204 dev_err(adev
->dev
, "no vBIOS found\n");
2205 amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS
, 0, 0);
2209 DRM_INFO("GPU posting now...\n");
2210 r
= amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
2212 dev_err(adev
->dev
, "gpu post error!\n");
2213 amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR
, 0, 0);
2217 DRM_INFO("GPU post is not needed\n");
2220 if (adev
->is_atom_fw
) {
2221 /* Initialize clocks */
2222 r
= amdgpu_atomfirmware_get_clock_info(adev
);
2224 dev_err(adev
->dev
, "amdgpu_atomfirmware_get_clock_info failed\n");
2225 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL
, 0, 0);
2229 /* Initialize clocks */
2230 r
= amdgpu_atombios_get_clock_info(adev
);
2232 dev_err(adev
->dev
, "amdgpu_atombios_get_clock_info failed\n");
2233 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL
, 0, 0);
2236 /* init i2c buses */
2237 amdgpu_atombios_i2c_init(adev
);
2241 r
= amdgpu_fence_driver_init(adev
);
2243 dev_err(adev
->dev
, "amdgpu_fence_driver_init failed\n");
2244 amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL
, 0, 0);
2248 /* init the mode config */
2249 drm_mode_config_init(adev
->ddev
);
2251 r
= amdgpu_init(adev
);
2253 dev_err(adev
->dev
, "amdgpu_init failed\n");
2254 amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL
, 0, 0);
2259 adev
->accel_working
= true;
2261 amdgpu_vm_check_compute_bug(adev
);
2263 /* Initialize the buffer migration limit. */
2264 if (amdgpu_moverate
>= 0)
2265 max_MBps
= amdgpu_moverate
;
2267 max_MBps
= 8; /* Allow 8 MB/s. */
2268 /* Get a log2 for easy divisions. */
2269 adev
->mm_stats
.log2_max_MBps
= ilog2(max(1u, max_MBps
));
2271 r
= amdgpu_ib_pool_init(adev
);
2273 dev_err(adev
->dev
, "IB initialization failed (%d).\n", r
);
2274 amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL
, 0, r
);
2278 r
= amdgpu_ib_ring_tests(adev
);
2280 DRM_ERROR("ib ring test failed (%d).\n", r
);
2282 amdgpu_fbdev_init(adev
);
2284 r
= amdgpu_gem_debugfs_init(adev
);
2286 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
2288 r
= amdgpu_debugfs_regs_init(adev
);
2290 DRM_ERROR("registering register debugfs failed (%d).\n", r
);
2292 r
= amdgpu_debugfs_test_ib_ring_init(adev
);
2294 DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r
);
2296 r
= amdgpu_debugfs_firmware_init(adev
);
2298 DRM_ERROR("registering firmware debugfs failed (%d).\n", r
);
2300 if ((amdgpu_testing
& 1)) {
2301 if (adev
->accel_working
)
2302 amdgpu_test_moves(adev
);
2304 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2306 if (amdgpu_benchmarking
) {
2307 if (adev
->accel_working
)
2308 amdgpu_benchmark(adev
, amdgpu_benchmarking
);
2310 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2313 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2314 * explicit gating rather than handling it automatically.
2316 r
= amdgpu_late_init(adev
);
2318 dev_err(adev
->dev
, "amdgpu_late_init failed\n");
2319 amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL
, 0, r
);
2326 amdgpu_vf_error_trans_all(adev
);
2328 vga_switcheroo_fini_domain_pm_ops(adev
->dev
);
2333 * amdgpu_device_fini - tear down the driver
2335 * @adev: amdgpu_device pointer
2337 * Tear down the driver info (all asics).
2338 * Called at driver shutdown.
2340 void amdgpu_device_fini(struct amdgpu_device
*adev
)
2344 DRM_INFO("amdgpu: finishing device.\n");
2345 adev
->shutdown
= true;
2346 if (adev
->mode_info
.mode_config_initialized
)
2347 drm_crtc_force_disable_all(adev
->ddev
);
2348 /* evict vram memory */
2349 amdgpu_bo_evict_vram(adev
);
2350 amdgpu_ib_pool_fini(adev
);
2351 amdgpu_fence_driver_fini(adev
);
2352 amdgpu_fbdev_fini(adev
);
2353 r
= amdgpu_fini(adev
);
2354 if (adev
->firmware
.gpu_info_fw
) {
2355 release_firmware(adev
->firmware
.gpu_info_fw
);
2356 adev
->firmware
.gpu_info_fw
= NULL
;
2358 adev
->accel_working
= false;
2359 cancel_delayed_work_sync(&adev
->late_init_work
);
2360 /* free i2c buses */
2361 amdgpu_i2c_fini(adev
);
2362 amdgpu_atombios_fini(adev
);
2365 if (!pci_is_thunderbolt_attached(adev
->pdev
))
2366 vga_switcheroo_unregister_client(adev
->pdev
);
2367 if (adev
->flags
& AMD_IS_PX
)
2368 vga_switcheroo_fini_domain_pm_ops(adev
->dev
);
2369 vga_client_register(adev
->pdev
, NULL
, NULL
, NULL
);
2371 pci_iounmap(adev
->pdev
, adev
->rio_mem
);
2372 adev
->rio_mem
= NULL
;
2373 iounmap(adev
->rmmio
);
2375 if (adev
->asic_type
>= CHIP_BONAIRE
)
2376 amdgpu_doorbell_fini(adev
);
2377 amdgpu_debugfs_regs_cleanup(adev
);
2385 * amdgpu_device_suspend - initiate device suspend
2387 * @pdev: drm dev pointer
2388 * @state: suspend state
2390 * Puts the hw in the suspend state (all asics).
2391 * Returns 0 for success or an error on failure.
2392 * Called at driver suspend.
2394 int amdgpu_device_suspend(struct drm_device
*dev
, bool suspend
, bool fbcon
)
2396 struct amdgpu_device
*adev
;
2397 struct drm_crtc
*crtc
;
2398 struct drm_connector
*connector
;
2401 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
2405 adev
= dev
->dev_private
;
2407 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2410 drm_kms_helper_poll_disable(dev
);
2412 /* turn off display hw */
2413 drm_modeset_lock_all(dev
);
2414 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2415 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
2417 drm_modeset_unlock_all(dev
);
2419 amdgpu_amdkfd_suspend(adev
);
2421 /* unpin the front buffers and cursors */
2422 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2423 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2424 struct amdgpu_framebuffer
*rfb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2425 struct amdgpu_bo
*robj
;
2427 if (amdgpu_crtc
->cursor_bo
) {
2428 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2429 r
= amdgpu_bo_reserve(aobj
, true);
2431 amdgpu_bo_unpin(aobj
);
2432 amdgpu_bo_unreserve(aobj
);
2436 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
2439 robj
= gem_to_amdgpu_bo(rfb
->obj
);
2440 /* don't unpin kernel fb objects */
2441 if (!amdgpu_fbdev_robj_is_fb(adev
, robj
)) {
2442 r
= amdgpu_bo_reserve(robj
, true);
2444 amdgpu_bo_unpin(robj
);
2445 amdgpu_bo_unreserve(robj
);
2449 /* evict vram memory */
2450 amdgpu_bo_evict_vram(adev
);
2452 amdgpu_fence_driver_suspend(adev
);
2454 r
= amdgpu_suspend(adev
);
2456 /* evict remaining vram memory
2457 * This second call to evict vram is to evict the gart page table
2460 amdgpu_bo_evict_vram(adev
);
2462 amdgpu_atombios_scratch_regs_save(adev
);
2463 pci_save_state(dev
->pdev
);
2465 /* Shut down the device */
2466 pci_disable_device(dev
->pdev
);
2467 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
2469 r
= amdgpu_asic_reset(adev
);
2471 DRM_ERROR("amdgpu asic reset failed\n");
2476 amdgpu_fbdev_set_suspend(adev
, 1);
2483 * amdgpu_device_resume - initiate device resume
2485 * @pdev: drm dev pointer
2487 * Bring the hw back to operating state (all asics).
2488 * Returns 0 for success or an error on failure.
2489 * Called at driver resume.
2491 int amdgpu_device_resume(struct drm_device
*dev
, bool resume
, bool fbcon
)
2493 struct drm_connector
*connector
;
2494 struct amdgpu_device
*adev
= dev
->dev_private
;
2495 struct drm_crtc
*crtc
;
2498 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2505 pci_set_power_state(dev
->pdev
, PCI_D0
);
2506 pci_restore_state(dev
->pdev
);
2507 r
= pci_enable_device(dev
->pdev
);
2511 amdgpu_atombios_scratch_regs_restore(adev
);
2514 if (amdgpu_need_post(adev
)) {
2515 r
= amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
2517 DRM_ERROR("amdgpu asic init failed\n");
2520 r
= amdgpu_resume(adev
);
2522 DRM_ERROR("amdgpu_resume failed (%d).\n", r
);
2525 amdgpu_fence_driver_resume(adev
);
2528 r
= amdgpu_ib_ring_tests(adev
);
2530 DRM_ERROR("ib ring test failed (%d).\n", r
);
2533 r
= amdgpu_late_init(adev
);
2538 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2539 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2541 if (amdgpu_crtc
->cursor_bo
) {
2542 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2543 r
= amdgpu_bo_reserve(aobj
, true);
2545 r
= amdgpu_bo_pin(aobj
,
2546 AMDGPU_GEM_DOMAIN_VRAM
,
2547 &amdgpu_crtc
->cursor_addr
);
2549 DRM_ERROR("Failed to pin cursor BO (%d)\n", r
);
2550 amdgpu_bo_unreserve(aobj
);
2554 r
= amdgpu_amdkfd_resume(adev
);
2558 /* blat the mode back in */
2560 drm_helper_resume_force_mode(dev
);
2561 /* turn on display hw */
2562 drm_modeset_lock_all(dev
);
2563 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2564 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
2566 drm_modeset_unlock_all(dev
);
2569 drm_kms_helper_poll_enable(dev
);
2572 * Most of the connector probing functions try to acquire runtime pm
2573 * refs to ensure that the GPU is powered on when connector polling is
2574 * performed. Since we're calling this from a runtime PM callback,
2575 * trying to acquire rpm refs will cause us to deadlock.
2577 * Since we're guaranteed to be holding the rpm lock, it's safe to
2578 * temporarily disable the rpm helpers so this doesn't deadlock us.
2581 dev
->dev
->power
.disable_depth
++;
2583 drm_helper_hpd_irq_event(dev
);
2585 dev
->dev
->power
.disable_depth
--;
2589 amdgpu_fbdev_set_suspend(adev
, 0);
2598 static bool amdgpu_check_soft_reset(struct amdgpu_device
*adev
)
2601 bool asic_hang
= false;
2603 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2604 if (!adev
->ip_blocks
[i
].status
.valid
)
2606 if (adev
->ip_blocks
[i
].version
->funcs
->check_soft_reset
)
2607 adev
->ip_blocks
[i
].status
.hang
=
2608 adev
->ip_blocks
[i
].version
->funcs
->check_soft_reset(adev
);
2609 if (adev
->ip_blocks
[i
].status
.hang
) {
2610 DRM_INFO("IP block:%s is hung!\n", adev
->ip_blocks
[i
].version
->funcs
->name
);
2617 static int amdgpu_pre_soft_reset(struct amdgpu_device
*adev
)
2621 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2622 if (!adev
->ip_blocks
[i
].status
.valid
)
2624 if (adev
->ip_blocks
[i
].status
.hang
&&
2625 adev
->ip_blocks
[i
].version
->funcs
->pre_soft_reset
) {
2626 r
= adev
->ip_blocks
[i
].version
->funcs
->pre_soft_reset(adev
);
2635 static bool amdgpu_need_full_reset(struct amdgpu_device
*adev
)
2639 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2640 if (!adev
->ip_blocks
[i
].status
.valid
)
2642 if ((adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) ||
2643 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_SMC
) ||
2644 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_ACP
) ||
2645 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_DCE
)) {
2646 if (adev
->ip_blocks
[i
].status
.hang
) {
2647 DRM_INFO("Some block need full reset!\n");
2655 static int amdgpu_soft_reset(struct amdgpu_device
*adev
)
2659 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2660 if (!adev
->ip_blocks
[i
].status
.valid
)
2662 if (adev
->ip_blocks
[i
].status
.hang
&&
2663 adev
->ip_blocks
[i
].version
->funcs
->soft_reset
) {
2664 r
= adev
->ip_blocks
[i
].version
->funcs
->soft_reset(adev
);
2673 static int amdgpu_post_soft_reset(struct amdgpu_device
*adev
)
2677 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2678 if (!adev
->ip_blocks
[i
].status
.valid
)
2680 if (adev
->ip_blocks
[i
].status
.hang
&&
2681 adev
->ip_blocks
[i
].version
->funcs
->post_soft_reset
)
2682 r
= adev
->ip_blocks
[i
].version
->funcs
->post_soft_reset(adev
);
2690 bool amdgpu_need_backup(struct amdgpu_device
*adev
)
2692 if (adev
->flags
& AMD_IS_APU
)
2695 return amdgpu_lockup_timeout
> 0 ? true : false;
2698 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device
*adev
,
2699 struct amdgpu_ring
*ring
,
2700 struct amdgpu_bo
*bo
,
2701 struct dma_fence
**fence
)
2709 r
= amdgpu_bo_reserve(bo
, true);
2712 domain
= amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
2713 /* if bo has been evicted, then no need to recover */
2714 if (domain
== AMDGPU_GEM_DOMAIN_VRAM
) {
2715 r
= amdgpu_bo_validate(bo
->shadow
);
2717 DRM_ERROR("bo validate failed!\n");
2721 r
= amdgpu_ttm_bind(&bo
->shadow
->tbo
, &bo
->shadow
->tbo
.mem
);
2723 DRM_ERROR("%p bind failed\n", bo
->shadow
);
2727 r
= amdgpu_bo_restore_from_shadow(adev
, ring
, bo
,
2730 DRM_ERROR("recover page table failed!\n");
2735 amdgpu_bo_unreserve(bo
);
2740 * amdgpu_sriov_gpu_reset - reset the asic
2742 * @adev: amdgpu device pointer
2743 * @job: which job trigger hang
2745 * Attempt the reset the GPU if it has hung (all asics).
2747 * Returns 0 for success or an error on failure.
2749 int amdgpu_sriov_gpu_reset(struct amdgpu_device
*adev
, struct amdgpu_job
*job
)
2753 struct amdgpu_bo
*bo
, *tmp
;
2754 struct amdgpu_ring
*ring
;
2755 struct dma_fence
*fence
= NULL
, *next
= NULL
;
2757 mutex_lock(&adev
->virt
.lock_reset
);
2758 atomic_inc(&adev
->gpu_reset_counter
);
2759 adev
->gfx
.in_reset
= true;
2762 resched
= ttm_bo_lock_delayed_workqueue(&adev
->mman
.bdev
);
2764 /* we start from the ring trigger GPU hang */
2765 j
= job
? job
->ring
->idx
: 0;
2767 /* block scheduler */
2768 for (i
= j
; i
< j
+ AMDGPU_MAX_RINGS
; ++i
) {
2769 ring
= adev
->rings
[i
% AMDGPU_MAX_RINGS
];
2770 if (!ring
|| !ring
->sched
.thread
)
2773 kthread_park(ring
->sched
.thread
);
2778 /* here give the last chance to check if job removed from mirror-list
2779 * since we already pay some time on kthread_park */
2780 if (job
&& list_empty(&job
->base
.node
)) {
2781 kthread_unpark(ring
->sched
.thread
);
2785 if (amd_sched_invalidate_job(&job
->base
, amdgpu_job_hang_limit
))
2786 amd_sched_job_kickout(&job
->base
);
2788 /* only do job_reset on the hang ring if @job not NULL */
2789 amd_sched_hw_job_reset(&ring
->sched
);
2791 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2792 amdgpu_fence_driver_force_completion_ring(ring
);
2795 /* request to take full control of GPU before re-initialization */
2797 amdgpu_virt_reset_gpu(adev
);
2799 amdgpu_virt_request_full_gpu(adev
, true);
2802 /* Resume IP prior to SMC */
2803 amdgpu_sriov_reinit_early(adev
);
2805 /* we need recover gart prior to run SMC/CP/SDMA resume */
2806 amdgpu_ttm_recover_gart(adev
);
2808 /* now we are okay to resume SMC/CP/SDMA */
2809 amdgpu_sriov_reinit_late(adev
);
2811 amdgpu_irq_gpu_reset_resume_helper(adev
);
2813 if (amdgpu_ib_ring_tests(adev
))
2814 dev_err(adev
->dev
, "[GPU_RESET] ib ring test failed (%d).\n", r
);
2816 /* release full control of GPU after ib test */
2817 amdgpu_virt_release_full_gpu(adev
, true);
2819 DRM_INFO("recover vram bo from shadow\n");
2821 ring
= adev
->mman
.buffer_funcs_ring
;
2822 mutex_lock(&adev
->shadow_list_lock
);
2823 list_for_each_entry_safe(bo
, tmp
, &adev
->shadow_list
, shadow_list
) {
2825 amdgpu_recover_vram_from_shadow(adev
, ring
, bo
, &next
);
2827 r
= dma_fence_wait(fence
, false);
2829 WARN(r
, "recovery from shadow isn't completed\n");
2834 dma_fence_put(fence
);
2837 mutex_unlock(&adev
->shadow_list_lock
);
2840 r
= dma_fence_wait(fence
, false);
2842 WARN(r
, "recovery from shadow isn't completed\n");
2844 dma_fence_put(fence
);
2846 for (i
= j
; i
< j
+ AMDGPU_MAX_RINGS
; ++i
) {
2847 ring
= adev
->rings
[i
% AMDGPU_MAX_RINGS
];
2848 if (!ring
|| !ring
->sched
.thread
)
2851 if (job
&& j
!= i
) {
2852 kthread_unpark(ring
->sched
.thread
);
2856 amd_sched_job_recovery(&ring
->sched
);
2857 kthread_unpark(ring
->sched
.thread
);
2860 drm_helper_resume_force_mode(adev
->ddev
);
2862 ttm_bo_unlock_delayed_workqueue(&adev
->mman
.bdev
, resched
);
2864 /* bad news, how to tell it to userspace ? */
2865 dev_info(adev
->dev
, "GPU reset failed\n");
2867 dev_info(adev
->dev
, "GPU reset successed!\n");
2870 adev
->gfx
.in_reset
= false;
2871 mutex_unlock(&adev
->virt
.lock_reset
);
2876 * amdgpu_gpu_reset - reset the asic
2878 * @adev: amdgpu device pointer
2880 * Attempt the reset the GPU if it has hung (all asics).
2881 * Returns 0 for success or an error on failure.
2883 int amdgpu_gpu_reset(struct amdgpu_device
*adev
)
2887 bool need_full_reset
, vram_lost
= false;
2889 if (!amdgpu_check_soft_reset(adev
)) {
2890 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2894 atomic_inc(&adev
->gpu_reset_counter
);
2897 resched
= ttm_bo_lock_delayed_workqueue(&adev
->mman
.bdev
);
2899 /* block scheduler */
2900 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
2901 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2903 if (!ring
|| !ring
->sched
.thread
)
2905 kthread_park(ring
->sched
.thread
);
2906 amd_sched_hw_job_reset(&ring
->sched
);
2908 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2909 amdgpu_fence_driver_force_completion(adev
);
2911 need_full_reset
= amdgpu_need_full_reset(adev
);
2913 if (!need_full_reset
) {
2914 amdgpu_pre_soft_reset(adev
);
2915 r
= amdgpu_soft_reset(adev
);
2916 amdgpu_post_soft_reset(adev
);
2917 if (r
|| amdgpu_check_soft_reset(adev
)) {
2918 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2919 need_full_reset
= true;
2923 if (need_full_reset
) {
2924 r
= amdgpu_suspend(adev
);
2927 amdgpu_atombios_scratch_regs_save(adev
);
2928 r
= amdgpu_asic_reset(adev
);
2929 amdgpu_atombios_scratch_regs_restore(adev
);
2931 amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
2934 dev_info(adev
->dev
, "GPU reset succeeded, trying to resume\n");
2935 r
= amdgpu_resume_phase1(adev
);
2938 vram_lost
= amdgpu_check_vram_lost(adev
);
2940 DRM_ERROR("VRAM is lost!\n");
2941 atomic_inc(&adev
->vram_lost_counter
);
2943 r
= amdgpu_ttm_recover_gart(adev
);
2946 r
= amdgpu_resume_phase2(adev
);
2950 amdgpu_fill_reset_magic(adev
);
2955 amdgpu_irq_gpu_reset_resume_helper(adev
);
2956 r
= amdgpu_ib_ring_tests(adev
);
2958 dev_err(adev
->dev
, "ib ring test failed (%d).\n", r
);
2959 r
= amdgpu_suspend(adev
);
2960 need_full_reset
= true;
2964 * recovery vm page tables, since we cannot depend on VRAM is
2965 * consistent after gpu full reset.
2967 if (need_full_reset
&& amdgpu_need_backup(adev
)) {
2968 struct amdgpu_ring
*ring
= adev
->mman
.buffer_funcs_ring
;
2969 struct amdgpu_bo
*bo
, *tmp
;
2970 struct dma_fence
*fence
= NULL
, *next
= NULL
;
2972 DRM_INFO("recover vram bo from shadow\n");
2973 mutex_lock(&adev
->shadow_list_lock
);
2974 list_for_each_entry_safe(bo
, tmp
, &adev
->shadow_list
, shadow_list
) {
2976 amdgpu_recover_vram_from_shadow(adev
, ring
, bo
, &next
);
2978 r
= dma_fence_wait(fence
, false);
2980 WARN(r
, "recovery from shadow isn't completed\n");
2985 dma_fence_put(fence
);
2988 mutex_unlock(&adev
->shadow_list_lock
);
2990 r
= dma_fence_wait(fence
, false);
2992 WARN(r
, "recovery from shadow isn't completed\n");
2994 dma_fence_put(fence
);
2996 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
2997 struct amdgpu_ring
*ring
= adev
->rings
[i
];
2999 if (!ring
|| !ring
->sched
.thread
)
3002 amd_sched_job_recovery(&ring
->sched
);
3003 kthread_unpark(ring
->sched
.thread
);
3006 dev_err(adev
->dev
, "asic resume failed (%d).\n", r
);
3007 amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL
, 0, r
);
3008 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
3009 if (adev
->rings
[i
] && adev
->rings
[i
]->sched
.thread
) {
3010 kthread_unpark(adev
->rings
[i
]->sched
.thread
);
3015 drm_helper_resume_force_mode(adev
->ddev
);
3017 ttm_bo_unlock_delayed_workqueue(&adev
->mman
.bdev
, resched
);
3019 /* bad news, how to tell it to userspace ? */
3020 dev_info(adev
->dev
, "GPU reset failed\n");
3021 amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL
, 0, r
);
3024 dev_info(adev
->dev
, "GPU reset successed!\n");
3027 amdgpu_vf_error_trans_all(adev
);
3031 void amdgpu_get_pcie_info(struct amdgpu_device
*adev
)
3036 if (amdgpu_pcie_gen_cap
)
3037 adev
->pm
.pcie_gen_mask
= amdgpu_pcie_gen_cap
;
3039 if (amdgpu_pcie_lane_cap
)
3040 adev
->pm
.pcie_mlw_mask
= amdgpu_pcie_lane_cap
;
3042 /* covers APUs as well */
3043 if (pci_is_root_bus(adev
->pdev
->bus
)) {
3044 if (adev
->pm
.pcie_gen_mask
== 0)
3045 adev
->pm
.pcie_gen_mask
= AMDGPU_DEFAULT_PCIE_GEN_MASK
;
3046 if (adev
->pm
.pcie_mlw_mask
== 0)
3047 adev
->pm
.pcie_mlw_mask
= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
3051 if (adev
->pm
.pcie_gen_mask
== 0) {
3052 ret
= drm_pcie_get_speed_cap_mask(adev
->ddev
, &mask
);
3054 adev
->pm
.pcie_gen_mask
= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1
|
3055 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2
|
3056 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3
);
3058 if (mask
& DRM_PCIE_SPEED_25
)
3059 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1
;
3060 if (mask
& DRM_PCIE_SPEED_50
)
3061 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
;
3062 if (mask
& DRM_PCIE_SPEED_80
)
3063 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
;
3065 adev
->pm
.pcie_gen_mask
= AMDGPU_DEFAULT_PCIE_GEN_MASK
;
3068 if (adev
->pm
.pcie_mlw_mask
== 0) {
3069 ret
= drm_pcie_get_max_link_width(adev
->ddev
, &mask
);
3073 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32
|
3074 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16
|
3075 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
3076 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
3077 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3078 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3079 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3082 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16
|
3083 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
3084 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
3085 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3086 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3087 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3090 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
3091 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
3092 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3093 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3094 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3097 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
3098 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3099 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3100 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3103 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
3104 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3105 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3108 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
3109 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
3112 adev
->pm
.pcie_mlw_mask
= CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
;
3118 adev
->pm
.pcie_mlw_mask
= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
3126 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
3127 const struct drm_info_list
*files
,
3132 for (i
= 0; i
< adev
->debugfs_count
; i
++) {
3133 if (adev
->debugfs
[i
].files
== files
) {
3134 /* Already registered */
3139 i
= adev
->debugfs_count
+ 1;
3140 if (i
> AMDGPU_DEBUGFS_MAX_COMPONENTS
) {
3141 DRM_ERROR("Reached maximum number of debugfs components.\n");
3142 DRM_ERROR("Report so we increase "
3143 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
3146 adev
->debugfs
[adev
->debugfs_count
].files
= files
;
3147 adev
->debugfs
[adev
->debugfs_count
].num_files
= nfiles
;
3148 adev
->debugfs_count
= i
;
3149 #if defined(CONFIG_DEBUG_FS)
3150 drm_debugfs_create_files(files
, nfiles
,
3151 adev
->ddev
->primary
->debugfs_root
,
3152 adev
->ddev
->primary
);
3157 #if defined(CONFIG_DEBUG_FS)
3159 static ssize_t
amdgpu_debugfs_regs_read(struct file
*f
, char __user
*buf
,
3160 size_t size
, loff_t
*pos
)
3162 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3165 bool pm_pg_lock
, use_bank
;
3166 unsigned instance_bank
, sh_bank
, se_bank
;
3168 if (size
& 0x3 || *pos
& 0x3)
3171 /* are we reading registers for which a PG lock is necessary? */
3172 pm_pg_lock
= (*pos
>> 23) & 1;
3174 if (*pos
& (1ULL << 62)) {
3175 se_bank
= (*pos
>> 24) & 0x3FF;
3176 sh_bank
= (*pos
>> 34) & 0x3FF;
3177 instance_bank
= (*pos
>> 44) & 0x3FF;
3179 if (se_bank
== 0x3FF)
3180 se_bank
= 0xFFFFFFFF;
3181 if (sh_bank
== 0x3FF)
3182 sh_bank
= 0xFFFFFFFF;
3183 if (instance_bank
== 0x3FF)
3184 instance_bank
= 0xFFFFFFFF;
3190 *pos
&= (1UL << 22) - 1;
3193 if ((sh_bank
!= 0xFFFFFFFF && sh_bank
>= adev
->gfx
.config
.max_sh_per_se
) ||
3194 (se_bank
!= 0xFFFFFFFF && se_bank
>= adev
->gfx
.config
.max_shader_engines
))
3196 mutex_lock(&adev
->grbm_idx_mutex
);
3197 amdgpu_gfx_select_se_sh(adev
, se_bank
,
3198 sh_bank
, instance_bank
);
3202 mutex_lock(&adev
->pm
.mutex
);
3207 if (*pos
> adev
->rmmio_size
)
3210 value
= RREG32(*pos
>> 2);
3211 r
= put_user(value
, (uint32_t *)buf
);
3225 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3226 mutex_unlock(&adev
->grbm_idx_mutex
);
3230 mutex_unlock(&adev
->pm
.mutex
);
3235 static ssize_t
amdgpu_debugfs_regs_write(struct file
*f
, const char __user
*buf
,
3236 size_t size
, loff_t
*pos
)
3238 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3241 bool pm_pg_lock
, use_bank
;
3242 unsigned instance_bank
, sh_bank
, se_bank
;
3244 if (size
& 0x3 || *pos
& 0x3)
3247 /* are we reading registers for which a PG lock is necessary? */
3248 pm_pg_lock
= (*pos
>> 23) & 1;
3250 if (*pos
& (1ULL << 62)) {
3251 se_bank
= (*pos
>> 24) & 0x3FF;
3252 sh_bank
= (*pos
>> 34) & 0x3FF;
3253 instance_bank
= (*pos
>> 44) & 0x3FF;
3255 if (se_bank
== 0x3FF)
3256 se_bank
= 0xFFFFFFFF;
3257 if (sh_bank
== 0x3FF)
3258 sh_bank
= 0xFFFFFFFF;
3259 if (instance_bank
== 0x3FF)
3260 instance_bank
= 0xFFFFFFFF;
3266 *pos
&= (1UL << 22) - 1;
3269 if ((sh_bank
!= 0xFFFFFFFF && sh_bank
>= adev
->gfx
.config
.max_sh_per_se
) ||
3270 (se_bank
!= 0xFFFFFFFF && se_bank
>= adev
->gfx
.config
.max_shader_engines
))
3272 mutex_lock(&adev
->grbm_idx_mutex
);
3273 amdgpu_gfx_select_se_sh(adev
, se_bank
,
3274 sh_bank
, instance_bank
);
3278 mutex_lock(&adev
->pm
.mutex
);
3283 if (*pos
> adev
->rmmio_size
)
3286 r
= get_user(value
, (uint32_t *)buf
);
3290 WREG32(*pos
>> 2, value
);
3299 amdgpu_gfx_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
3300 mutex_unlock(&adev
->grbm_idx_mutex
);
3304 mutex_unlock(&adev
->pm
.mutex
);
3309 static ssize_t
amdgpu_debugfs_regs_pcie_read(struct file
*f
, char __user
*buf
,
3310 size_t size
, loff_t
*pos
)
3312 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3316 if (size
& 0x3 || *pos
& 0x3)
3322 value
= RREG32_PCIE(*pos
>> 2);
3323 r
= put_user(value
, (uint32_t *)buf
);
3336 static ssize_t
amdgpu_debugfs_regs_pcie_write(struct file
*f
, const char __user
*buf
,
3337 size_t size
, loff_t
*pos
)
3339 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3343 if (size
& 0x3 || *pos
& 0x3)
3349 r
= get_user(value
, (uint32_t *)buf
);
3353 WREG32_PCIE(*pos
>> 2, value
);
3364 static ssize_t
amdgpu_debugfs_regs_didt_read(struct file
*f
, char __user
*buf
,
3365 size_t size
, loff_t
*pos
)
3367 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3371 if (size
& 0x3 || *pos
& 0x3)
3377 value
= RREG32_DIDT(*pos
>> 2);
3378 r
= put_user(value
, (uint32_t *)buf
);
3391 static ssize_t
amdgpu_debugfs_regs_didt_write(struct file
*f
, const char __user
*buf
,
3392 size_t size
, loff_t
*pos
)
3394 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3398 if (size
& 0x3 || *pos
& 0x3)
3404 r
= get_user(value
, (uint32_t *)buf
);
3408 WREG32_DIDT(*pos
>> 2, value
);
3419 static ssize_t
amdgpu_debugfs_regs_smc_read(struct file
*f
, char __user
*buf
,
3420 size_t size
, loff_t
*pos
)
3422 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3426 if (size
& 0x3 || *pos
& 0x3)
3432 value
= RREG32_SMC(*pos
);
3433 r
= put_user(value
, (uint32_t *)buf
);
3446 static ssize_t
amdgpu_debugfs_regs_smc_write(struct file
*f
, const char __user
*buf
,
3447 size_t size
, loff_t
*pos
)
3449 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3453 if (size
& 0x3 || *pos
& 0x3)
3459 r
= get_user(value
, (uint32_t *)buf
);
3463 WREG32_SMC(*pos
, value
);
3474 static ssize_t
amdgpu_debugfs_gca_config_read(struct file
*f
, char __user
*buf
,
3475 size_t size
, loff_t
*pos
)
3477 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3480 uint32_t *config
, no_regs
= 0;
3482 if (size
& 0x3 || *pos
& 0x3)
3485 config
= kmalloc_array(256, sizeof(*config
), GFP_KERNEL
);
3489 /* version, increment each time something is added */
3490 config
[no_regs
++] = 3;
3491 config
[no_regs
++] = adev
->gfx
.config
.max_shader_engines
;
3492 config
[no_regs
++] = adev
->gfx
.config
.max_tile_pipes
;
3493 config
[no_regs
++] = adev
->gfx
.config
.max_cu_per_sh
;
3494 config
[no_regs
++] = adev
->gfx
.config
.max_sh_per_se
;
3495 config
[no_regs
++] = adev
->gfx
.config
.max_backends_per_se
;
3496 config
[no_regs
++] = adev
->gfx
.config
.max_texture_channel_caches
;
3497 config
[no_regs
++] = adev
->gfx
.config
.max_gprs
;
3498 config
[no_regs
++] = adev
->gfx
.config
.max_gs_threads
;
3499 config
[no_regs
++] = adev
->gfx
.config
.max_hw_contexts
;
3500 config
[no_regs
++] = adev
->gfx
.config
.sc_prim_fifo_size_frontend
;
3501 config
[no_regs
++] = adev
->gfx
.config
.sc_prim_fifo_size_backend
;
3502 config
[no_regs
++] = adev
->gfx
.config
.sc_hiz_tile_fifo_size
;
3503 config
[no_regs
++] = adev
->gfx
.config
.sc_earlyz_tile_fifo_size
;
3504 config
[no_regs
++] = adev
->gfx
.config
.num_tile_pipes
;
3505 config
[no_regs
++] = adev
->gfx
.config
.backend_enable_mask
;
3506 config
[no_regs
++] = adev
->gfx
.config
.mem_max_burst_length_bytes
;
3507 config
[no_regs
++] = adev
->gfx
.config
.mem_row_size_in_kb
;
3508 config
[no_regs
++] = adev
->gfx
.config
.shader_engine_tile_size
;
3509 config
[no_regs
++] = adev
->gfx
.config
.num_gpus
;
3510 config
[no_regs
++] = adev
->gfx
.config
.multi_gpu_tile_size
;
3511 config
[no_regs
++] = adev
->gfx
.config
.mc_arb_ramcfg
;
3512 config
[no_regs
++] = adev
->gfx
.config
.gb_addr_config
;
3513 config
[no_regs
++] = adev
->gfx
.config
.num_rbs
;
3516 config
[no_regs
++] = adev
->rev_id
;
3517 config
[no_regs
++] = adev
->pg_flags
;
3518 config
[no_regs
++] = adev
->cg_flags
;
3521 config
[no_regs
++] = adev
->family
;
3522 config
[no_regs
++] = adev
->external_rev_id
;
3525 config
[no_regs
++] = adev
->pdev
->device
;
3526 config
[no_regs
++] = adev
->pdev
->revision
;
3527 config
[no_regs
++] = adev
->pdev
->subsystem_device
;
3528 config
[no_regs
++] = adev
->pdev
->subsystem_vendor
;
3530 while (size
&& (*pos
< no_regs
* 4)) {
3533 value
= config
[*pos
>> 2];
3534 r
= put_user(value
, (uint32_t *)buf
);
3550 static ssize_t
amdgpu_debugfs_sensor_read(struct file
*f
, char __user
*buf
,
3551 size_t size
, loff_t
*pos
)
3553 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
3554 int idx
, x
, outsize
, r
, valuesize
;
3555 uint32_t values
[16];
3557 if (size
& 3 || *pos
& 0x3)
3560 if (amdgpu_dpm
== 0)
3563 /* convert offset to sensor number */
3566 valuesize
= sizeof(values
);
3567 if (adev
->powerplay
.pp_funcs
&& adev
->powerplay
.pp_funcs
->read_sensor
)
3568 r
= adev
->powerplay
.pp_funcs
->read_sensor(adev
->powerplay
.pp_handle
, idx
, &values
[0], &valuesize
);
3569 else if (adev
->pm
.funcs
&& adev
->pm
.funcs
->read_sensor
)
3570 r
= adev
->pm
.funcs
->read_sensor(adev
, idx
, &values
[0],
3575 if (size
> valuesize
)
3582 r
= put_user(values
[x
++], (int32_t *)buf
);
3589 return !r
? outsize
: r
;
3592 static ssize_t
amdgpu_debugfs_wave_read(struct file
*f
, char __user
*buf
,
3593 size_t size
, loff_t
*pos
)
3595 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
3598 uint32_t offset
, se
, sh
, cu
, wave
, simd
, data
[32];
3600 if (size
& 3 || *pos
& 3)
3604 offset
= (*pos
& 0x7F);
3605 se
= ((*pos
>> 7) & 0xFF);
3606 sh
= ((*pos
>> 15) & 0xFF);
3607 cu
= ((*pos
>> 23) & 0xFF);
3608 wave
= ((*pos
>> 31) & 0xFF);
3609 simd
= ((*pos
>> 37) & 0xFF);
3611 /* switch to the specific se/sh/cu */
3612 mutex_lock(&adev
->grbm_idx_mutex
);
3613 amdgpu_gfx_select_se_sh(adev
, se
, sh
, cu
);
3616 if (adev
->gfx
.funcs
->read_wave_data
)
3617 adev
->gfx
.funcs
->read_wave_data(adev
, simd
, wave
, data
, &x
);
3619 amdgpu_gfx_select_se_sh(adev
, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3620 mutex_unlock(&adev
->grbm_idx_mutex
);
3625 while (size
&& (offset
< x
* 4)) {
3628 value
= data
[offset
>> 2];
3629 r
= put_user(value
, (uint32_t *)buf
);
3642 static ssize_t
amdgpu_debugfs_gpr_read(struct file
*f
, char __user
*buf
,
3643 size_t size
, loff_t
*pos
)
3645 struct amdgpu_device
*adev
= f
->f_inode
->i_private
;
3648 uint32_t offset
, se
, sh
, cu
, wave
, simd
, thread
, bank
, *data
;
3650 if (size
& 3 || *pos
& 3)
3654 offset
= (*pos
& 0xFFF); /* in dwords */
3655 se
= ((*pos
>> 12) & 0xFF);
3656 sh
= ((*pos
>> 20) & 0xFF);
3657 cu
= ((*pos
>> 28) & 0xFF);
3658 wave
= ((*pos
>> 36) & 0xFF);
3659 simd
= ((*pos
>> 44) & 0xFF);
3660 thread
= ((*pos
>> 52) & 0xFF);
3661 bank
= ((*pos
>> 60) & 1);
3663 data
= kmalloc_array(1024, sizeof(*data
), GFP_KERNEL
);
3667 /* switch to the specific se/sh/cu */
3668 mutex_lock(&adev
->grbm_idx_mutex
);
3669 amdgpu_gfx_select_se_sh(adev
, se
, sh
, cu
);
3672 if (adev
->gfx
.funcs
->read_wave_vgprs
)
3673 adev
->gfx
.funcs
->read_wave_vgprs(adev
, simd
, wave
, thread
, offset
, size
>>2, data
);
3675 if (adev
->gfx
.funcs
->read_wave_sgprs
)
3676 adev
->gfx
.funcs
->read_wave_sgprs(adev
, simd
, wave
, offset
, size
>>2, data
);
3679 amdgpu_gfx_select_se_sh(adev
, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3680 mutex_unlock(&adev
->grbm_idx_mutex
);
3685 value
= data
[offset
++];
3686 r
= put_user(value
, (uint32_t *)buf
);
3702 static const struct file_operations amdgpu_debugfs_regs_fops
= {
3703 .owner
= THIS_MODULE
,
3704 .read
= amdgpu_debugfs_regs_read
,
3705 .write
= amdgpu_debugfs_regs_write
,
3706 .llseek
= default_llseek
3708 static const struct file_operations amdgpu_debugfs_regs_didt_fops
= {
3709 .owner
= THIS_MODULE
,
3710 .read
= amdgpu_debugfs_regs_didt_read
,
3711 .write
= amdgpu_debugfs_regs_didt_write
,
3712 .llseek
= default_llseek
3714 static const struct file_operations amdgpu_debugfs_regs_pcie_fops
= {
3715 .owner
= THIS_MODULE
,
3716 .read
= amdgpu_debugfs_regs_pcie_read
,
3717 .write
= amdgpu_debugfs_regs_pcie_write
,
3718 .llseek
= default_llseek
3720 static const struct file_operations amdgpu_debugfs_regs_smc_fops
= {
3721 .owner
= THIS_MODULE
,
3722 .read
= amdgpu_debugfs_regs_smc_read
,
3723 .write
= amdgpu_debugfs_regs_smc_write
,
3724 .llseek
= default_llseek
3727 static const struct file_operations amdgpu_debugfs_gca_config_fops
= {
3728 .owner
= THIS_MODULE
,
3729 .read
= amdgpu_debugfs_gca_config_read
,
3730 .llseek
= default_llseek
3733 static const struct file_operations amdgpu_debugfs_sensors_fops
= {
3734 .owner
= THIS_MODULE
,
3735 .read
= amdgpu_debugfs_sensor_read
,
3736 .llseek
= default_llseek
3739 static const struct file_operations amdgpu_debugfs_wave_fops
= {
3740 .owner
= THIS_MODULE
,
3741 .read
= amdgpu_debugfs_wave_read
,
3742 .llseek
= default_llseek
3744 static const struct file_operations amdgpu_debugfs_gpr_fops
= {
3745 .owner
= THIS_MODULE
,
3746 .read
= amdgpu_debugfs_gpr_read
,
3747 .llseek
= default_llseek
3750 static const struct file_operations
*debugfs_regs
[] = {
3751 &amdgpu_debugfs_regs_fops
,
3752 &amdgpu_debugfs_regs_didt_fops
,
3753 &amdgpu_debugfs_regs_pcie_fops
,
3754 &amdgpu_debugfs_regs_smc_fops
,
3755 &amdgpu_debugfs_gca_config_fops
,
3756 &amdgpu_debugfs_sensors_fops
,
3757 &amdgpu_debugfs_wave_fops
,
3758 &amdgpu_debugfs_gpr_fops
,
3761 static const char *debugfs_regs_names
[] = {
3766 "amdgpu_gca_config",
3772 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
)
3774 struct drm_minor
*minor
= adev
->ddev
->primary
;
3775 struct dentry
*ent
, *root
= minor
->debugfs_root
;
3778 for (i
= 0; i
< ARRAY_SIZE(debugfs_regs
); i
++) {
3779 ent
= debugfs_create_file(debugfs_regs_names
[i
],
3780 S_IFREG
| S_IRUGO
, root
,
3781 adev
, debugfs_regs
[i
]);
3783 for (j
= 0; j
< i
; j
++) {
3784 debugfs_remove(adev
->debugfs_regs
[i
]);
3785 adev
->debugfs_regs
[i
] = NULL
;
3787 return PTR_ERR(ent
);
3791 i_size_write(ent
->d_inode
, adev
->rmmio_size
);
3792 adev
->debugfs_regs
[i
] = ent
;
3798 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
)
3802 for (i
= 0; i
< ARRAY_SIZE(debugfs_regs
); i
++) {
3803 if (adev
->debugfs_regs
[i
]) {
3804 debugfs_remove(adev
->debugfs_regs
[i
]);
3805 adev
->debugfs_regs
[i
] = NULL
;
3810 static int amdgpu_debugfs_test_ib(struct seq_file
*m
, void *data
)
3812 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3813 struct drm_device
*dev
= node
->minor
->dev
;
3814 struct amdgpu_device
*adev
= dev
->dev_private
;
3817 /* hold on the scheduler */
3818 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
3819 struct amdgpu_ring
*ring
= adev
->rings
[i
];
3821 if (!ring
|| !ring
->sched
.thread
)
3823 kthread_park(ring
->sched
.thread
);
3826 seq_printf(m
, "run ib test:\n");
3827 r
= amdgpu_ib_ring_tests(adev
);
3829 seq_printf(m
, "ib ring tests failed (%d).\n", r
);
3831 seq_printf(m
, "ib ring tests passed.\n");
3833 /* go on the scheduler */
3834 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
3835 struct amdgpu_ring
*ring
= adev
->rings
[i
];
3837 if (!ring
|| !ring
->sched
.thread
)
3839 kthread_unpark(ring
->sched
.thread
);
3845 static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list
[] = {
3846 {"amdgpu_test_ib", &amdgpu_debugfs_test_ib
}
3849 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device
*adev
)
3851 return amdgpu_debugfs_add_files(adev
,
3852 amdgpu_debugfs_test_ib_ring_list
, 1);
3855 int amdgpu_debugfs_init(struct drm_minor
*minor
)
3860 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device
*adev
)
3864 static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev
)
3868 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device
*adev
) { }