2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #include "bif/bif_4_1_d.h"
57 #include <linux/pci.h>
58 #include <linux/firmware.h>
59 #include "amdgpu_vf_error.h"
61 #include "amdgpu_amdkfd.h"
62 #include "amdgpu_pm.h"
64 #include "amdgpu_xgmi.h"
65 #include "amdgpu_ras.h"
66 #include "amdgpu_pmu.h"
68 #include <linux/suspend.h>
69 #include <drm/task_barrier.h>
71 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
72 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
73 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
74 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
75 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
76 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
77 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
78 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
79 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
80 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
82 #define AMDGPU_RESUME_MS 2000
84 const char *amdgpu_asic_name
[] = {
117 * DOC: pcie_replay_count
119 * The amdgpu driver provides a sysfs API for reporting the total number
120 * of PCIe replays (NAKs)
121 * The file pcie_replay_count is used for this and returns the total
122 * number of replays as a sum of the NAKs generated and NAKs received
125 static ssize_t
amdgpu_device_get_pcie_replay_count(struct device
*dev
,
126 struct device_attribute
*attr
, char *buf
)
128 struct drm_device
*ddev
= dev_get_drvdata(dev
);
129 struct amdgpu_device
*adev
= ddev
->dev_private
;
130 uint64_t cnt
= amdgpu_asic_get_pcie_replay_count(adev
);
132 return snprintf(buf
, PAGE_SIZE
, "%llu\n", cnt
);
135 static DEVICE_ATTR(pcie_replay_count
, S_IRUGO
,
136 amdgpu_device_get_pcie_replay_count
, NULL
);
138 static void amdgpu_device_get_pcie_info(struct amdgpu_device
*adev
);
141 * amdgpu_device_supports_boco - Is the device a dGPU with HG/PX power control
143 * @dev: drm_device pointer
145 * Returns true if the device is a dGPU with HG/PX power control,
146 * otherwise return false.
148 bool amdgpu_device_supports_boco(struct drm_device
*dev
)
150 struct amdgpu_device
*adev
= dev
->dev_private
;
152 if (adev
->flags
& AMD_IS_PX
)
158 * amdgpu_device_supports_baco - Does the device support BACO
160 * @dev: drm_device pointer
162 * Returns true if the device supporte BACO,
163 * otherwise return false.
165 bool amdgpu_device_supports_baco(struct drm_device
*dev
)
167 struct amdgpu_device
*adev
= dev
->dev_private
;
169 return amdgpu_asic_supports_baco(adev
);
173 * VRAM access helper functions.
175 * amdgpu_device_vram_access - read/write a buffer in vram
177 * @adev: amdgpu_device pointer
178 * @pos: offset of the buffer in vram
179 * @buf: virtual address of the buffer in system memory
180 * @size: read/write size, sizeof(@buf) must > @size
181 * @write: true - write to vram, otherwise - read from vram
183 void amdgpu_device_vram_access(struct amdgpu_device
*adev
, loff_t pos
,
184 uint32_t *buf
, size_t size
, bool write
)
192 last
= min(pos
+ size
, adev
->gmc
.visible_vram_size
);
194 void __iomem
*addr
= adev
->mman
.aper_base_kaddr
+ pos
;
195 size_t count
= last
- pos
;
198 memcpy_toio(addr
, buf
, count
);
200 amdgpu_asic_flush_hdp(adev
, NULL
);
202 amdgpu_asic_invalidate_hdp(adev
, NULL
);
204 memcpy_fromio(buf
, addr
, count
);
216 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
217 for (last
= pos
+ size
; pos
< last
; pos
+= 4) {
218 uint32_t tmp
= pos
>> 31;
220 WREG32_NO_KIQ(mmMM_INDEX
, ((uint32_t)pos
) | 0x80000000);
222 WREG32_NO_KIQ(mmMM_INDEX_HI
, tmp
);
226 WREG32_NO_KIQ(mmMM_DATA
, *buf
++);
228 *buf
++ = RREG32_NO_KIQ(mmMM_DATA
);
230 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
234 * MMIO register access helper functions.
237 * amdgpu_mm_rreg - read a memory mapped IO register
239 * @adev: amdgpu_device pointer
240 * @reg: dword aligned register offset
241 * @acc_flags: access flags which require special behavior
243 * Returns the 32 bit value from the offset specified.
245 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
250 if ((acc_flags
& AMDGPU_REGS_KIQ
) || (!(acc_flags
& AMDGPU_REGS_NO_KIQ
) && amdgpu_sriov_runtime(adev
)))
251 return amdgpu_kiq_rreg(adev
, reg
);
253 if ((reg
* 4) < adev
->rmmio_size
&& !(acc_flags
& AMDGPU_REGS_IDX
))
254 ret
= readl(((void __iomem
*)adev
->rmmio
) + (reg
* 4));
258 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
259 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
260 ret
= readl(((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
261 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
263 trace_amdgpu_mm_rreg(adev
->pdev
->device
, reg
, ret
);
268 * MMIO register read with bytes helper functions
269 * @offset:bytes offset from MMIO start
274 * amdgpu_mm_rreg8 - read a memory mapped IO register
276 * @adev: amdgpu_device pointer
277 * @offset: byte aligned register offset
279 * Returns the 8 bit value from the offset specified.
281 uint8_t amdgpu_mm_rreg8(struct amdgpu_device
*adev
, uint32_t offset
) {
282 if (offset
< adev
->rmmio_size
)
283 return (readb(adev
->rmmio
+ offset
));
288 * MMIO register write with bytes helper functions
289 * @offset:bytes offset from MMIO start
290 * @value: the value want to be written to the register
294 * amdgpu_mm_wreg8 - read a memory mapped IO register
296 * @adev: amdgpu_device pointer
297 * @offset: byte aligned register offset
298 * @value: 8 bit value to write
300 * Writes the value specified to the offset specified.
302 void amdgpu_mm_wreg8(struct amdgpu_device
*adev
, uint32_t offset
, uint8_t value
) {
303 if (offset
< adev
->rmmio_size
)
304 writeb(value
, adev
->rmmio
+ offset
);
309 void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
, uint32_t acc_flags
)
311 trace_amdgpu_mm_wreg(adev
->pdev
->device
, reg
, v
);
313 if ((reg
* 4) < adev
->rmmio_size
&& !(acc_flags
& AMDGPU_REGS_IDX
))
314 writel(v
, ((void __iomem
*)adev
->rmmio
) + (reg
* 4));
318 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
319 writel((reg
* 4), ((void __iomem
*)adev
->rmmio
) + (mmMM_INDEX
* 4));
320 writel(v
, ((void __iomem
*)adev
->rmmio
) + (mmMM_DATA
* 4));
321 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
324 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 1 && adev
->last_mm_index
== 0x5702C) {
330 * amdgpu_mm_wreg - write to a memory mapped IO register
332 * @adev: amdgpu_device pointer
333 * @reg: dword aligned register offset
334 * @v: 32 bit value to write to the register
335 * @acc_flags: access flags which require special behavior
337 * Writes the value specified to the offset specified.
339 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
342 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 0) {
343 adev
->last_mm_index
= v
;
346 if ((acc_flags
& AMDGPU_REGS_KIQ
) || (!(acc_flags
& AMDGPU_REGS_NO_KIQ
) && amdgpu_sriov_runtime(adev
)))
347 return amdgpu_kiq_wreg(adev
, reg
, v
);
349 amdgpu_mm_wreg_mmio(adev
, reg
, v
, acc_flags
);
353 * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range
355 * this function is invoked only the debugfs register access
357 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
360 if (amdgpu_sriov_fullaccess(adev
) &&
361 adev
->gfx
.rlc
.funcs
&&
362 adev
->gfx
.rlc
.funcs
->is_rlcg_access_range
) {
364 if (adev
->gfx
.rlc
.funcs
->is_rlcg_access_range(adev
, reg
))
365 return adev
->gfx
.rlc
.funcs
->rlcg_wreg(adev
, reg
, v
);
368 amdgpu_mm_wreg_mmio(adev
, reg
, v
, acc_flags
);
372 * amdgpu_io_rreg - read an IO register
374 * @adev: amdgpu_device pointer
375 * @reg: dword aligned register offset
377 * Returns the 32 bit value from the offset specified.
379 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
)
381 if ((reg
* 4) < adev
->rio_mem_size
)
382 return ioread32(adev
->rio_mem
+ (reg
* 4));
384 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
385 return ioread32(adev
->rio_mem
+ (mmMM_DATA
* 4));
390 * amdgpu_io_wreg - write to an IO register
392 * @adev: amdgpu_device pointer
393 * @reg: dword aligned register offset
394 * @v: 32 bit value to write to the register
396 * Writes the value specified to the offset specified.
398 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
400 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 0) {
401 adev
->last_mm_index
= v
;
404 if ((reg
* 4) < adev
->rio_mem_size
)
405 iowrite32(v
, adev
->rio_mem
+ (reg
* 4));
407 iowrite32((reg
* 4), adev
->rio_mem
+ (mmMM_INDEX
* 4));
408 iowrite32(v
, adev
->rio_mem
+ (mmMM_DATA
* 4));
411 if (adev
->asic_type
>= CHIP_VEGA10
&& reg
== 1 && adev
->last_mm_index
== 0x5702C) {
417 * amdgpu_mm_rdoorbell - read a doorbell dword
419 * @adev: amdgpu_device pointer
420 * @index: doorbell index
422 * Returns the value in the doorbell aperture at the
423 * requested doorbell index (CIK).
425 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
)
427 if (index
< adev
->doorbell
.num_doorbells
) {
428 return readl(adev
->doorbell
.ptr
+ index
);
430 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index
);
436 * amdgpu_mm_wdoorbell - write a doorbell dword
438 * @adev: amdgpu_device pointer
439 * @index: doorbell index
442 * Writes @v to the doorbell aperture at the
443 * requested doorbell index (CIK).
445 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
)
447 if (index
< adev
->doorbell
.num_doorbells
) {
448 writel(v
, adev
->doorbell
.ptr
+ index
);
450 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index
);
455 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
457 * @adev: amdgpu_device pointer
458 * @index: doorbell index
460 * Returns the value in the doorbell aperture at the
461 * requested doorbell index (VEGA10+).
463 u64
amdgpu_mm_rdoorbell64(struct amdgpu_device
*adev
, u32 index
)
465 if (index
< adev
->doorbell
.num_doorbells
) {
466 return atomic64_read((atomic64_t
*)(adev
->doorbell
.ptr
+ index
));
468 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index
);
474 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
476 * @adev: amdgpu_device pointer
477 * @index: doorbell index
480 * Writes @v to the doorbell aperture at the
481 * requested doorbell index (VEGA10+).
483 void amdgpu_mm_wdoorbell64(struct amdgpu_device
*adev
, u32 index
, u64 v
)
485 if (index
< adev
->doorbell
.num_doorbells
) {
486 atomic64_set((atomic64_t
*)(adev
->doorbell
.ptr
+ index
), v
);
488 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index
);
493 * amdgpu_invalid_rreg - dummy reg read function
495 * @adev: amdgpu device pointer
496 * @reg: offset of register
498 * Dummy register read function. Used for register blocks
499 * that certain asics don't have (all asics).
500 * Returns the value in the register.
502 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device
*adev
, uint32_t reg
)
504 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
510 * amdgpu_invalid_wreg - dummy reg write function
512 * @adev: amdgpu device pointer
513 * @reg: offset of register
514 * @v: value to write to the register
516 * Dummy register read function. Used for register blocks
517 * that certain asics don't have (all asics).
519 static void amdgpu_invalid_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
)
521 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
527 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
529 * @adev: amdgpu device pointer
530 * @reg: offset of register
532 * Dummy register read function. Used for register blocks
533 * that certain asics don't have (all asics).
534 * Returns the value in the register.
536 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device
*adev
, uint32_t reg
)
538 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg
);
544 * amdgpu_invalid_wreg64 - dummy reg write function
546 * @adev: amdgpu device pointer
547 * @reg: offset of register
548 * @v: value to write to the register
550 * Dummy register read function. Used for register blocks
551 * that certain asics don't have (all asics).
553 static void amdgpu_invalid_wreg64(struct amdgpu_device
*adev
, uint32_t reg
, uint64_t v
)
555 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
561 * amdgpu_block_invalid_rreg - dummy reg read function
563 * @adev: amdgpu device pointer
564 * @block: offset of instance
565 * @reg: offset of register
567 * Dummy register read function. Used for register blocks
568 * that certain asics don't have (all asics).
569 * Returns the value in the register.
571 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device
*adev
,
572 uint32_t block
, uint32_t reg
)
574 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
581 * amdgpu_block_invalid_wreg - dummy reg write function
583 * @adev: amdgpu device pointer
584 * @block: offset of instance
585 * @reg: offset of register
586 * @v: value to write to the register
588 * Dummy register read function. Used for register blocks
589 * that certain asics don't have (all asics).
591 static void amdgpu_block_invalid_wreg(struct amdgpu_device
*adev
,
593 uint32_t reg
, uint32_t v
)
595 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
601 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
603 * @adev: amdgpu device pointer
605 * Allocates a scratch page of VRAM for use by various things in the
608 static int amdgpu_device_vram_scratch_init(struct amdgpu_device
*adev
)
610 return amdgpu_bo_create_kernel(adev
, AMDGPU_GPU_PAGE_SIZE
,
611 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_VRAM
,
612 &adev
->vram_scratch
.robj
,
613 &adev
->vram_scratch
.gpu_addr
,
614 (void **)&adev
->vram_scratch
.ptr
);
618 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
620 * @adev: amdgpu device pointer
622 * Frees the VRAM scratch page.
624 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device
*adev
)
626 amdgpu_bo_free_kernel(&adev
->vram_scratch
.robj
, NULL
, NULL
);
630 * amdgpu_device_program_register_sequence - program an array of registers.
632 * @adev: amdgpu_device pointer
633 * @registers: pointer to the register array
634 * @array_size: size of the register array
636 * Programs an array or registers with and and or masks.
637 * This is a helper for setting golden registers.
639 void amdgpu_device_program_register_sequence(struct amdgpu_device
*adev
,
640 const u32
*registers
,
641 const u32 array_size
)
643 u32 tmp
, reg
, and_mask
, or_mask
;
649 for (i
= 0; i
< array_size
; i
+=3) {
650 reg
= registers
[i
+ 0];
651 and_mask
= registers
[i
+ 1];
652 or_mask
= registers
[i
+ 2];
654 if (and_mask
== 0xffffffff) {
659 if (adev
->family
>= AMDGPU_FAMILY_AI
)
660 tmp
|= (or_mask
& and_mask
);
669 * amdgpu_device_pci_config_reset - reset the GPU
671 * @adev: amdgpu_device pointer
673 * Resets the GPU using the pci config reset sequence.
674 * Only applicable to asics prior to vega10.
676 void amdgpu_device_pci_config_reset(struct amdgpu_device
*adev
)
678 pci_write_config_dword(adev
->pdev
, 0x7c, AMDGPU_ASIC_RESET_DATA
);
682 * GPU doorbell aperture helpers function.
685 * amdgpu_device_doorbell_init - Init doorbell driver information.
687 * @adev: amdgpu_device pointer
689 * Init doorbell driver information (CIK)
690 * Returns 0 on success, error on failure.
692 static int amdgpu_device_doorbell_init(struct amdgpu_device
*adev
)
695 /* No doorbell on SI hardware generation */
696 if (adev
->asic_type
< CHIP_BONAIRE
) {
697 adev
->doorbell
.base
= 0;
698 adev
->doorbell
.size
= 0;
699 adev
->doorbell
.num_doorbells
= 0;
700 adev
->doorbell
.ptr
= NULL
;
704 if (pci_resource_flags(adev
->pdev
, 2) & IORESOURCE_UNSET
)
707 amdgpu_asic_init_doorbell_index(adev
);
709 /* doorbell bar mapping */
710 adev
->doorbell
.base
= pci_resource_start(adev
->pdev
, 2);
711 adev
->doorbell
.size
= pci_resource_len(adev
->pdev
, 2);
713 adev
->doorbell
.num_doorbells
= min_t(u32
, adev
->doorbell
.size
/ sizeof(u32
),
714 adev
->doorbell_index
.max_assignment
+1);
715 if (adev
->doorbell
.num_doorbells
== 0)
718 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
719 * paging queue doorbell use the second page. The
720 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
721 * doorbells are in the first page. So with paging queue enabled,
722 * the max num_doorbells should + 1 page (0x400 in dword)
724 if (adev
->asic_type
>= CHIP_VEGA10
)
725 adev
->doorbell
.num_doorbells
+= 0x400;
727 adev
->doorbell
.ptr
= ioremap(adev
->doorbell
.base
,
728 adev
->doorbell
.num_doorbells
*
730 if (adev
->doorbell
.ptr
== NULL
)
737 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
739 * @adev: amdgpu_device pointer
741 * Tear down doorbell driver information (CIK)
743 static void amdgpu_device_doorbell_fini(struct amdgpu_device
*adev
)
745 iounmap(adev
->doorbell
.ptr
);
746 adev
->doorbell
.ptr
= NULL
;
752 * amdgpu_device_wb_*()
753 * Writeback is the method by which the GPU updates special pages in memory
754 * with the status of certain GPU events (fences, ring pointers,etc.).
758 * amdgpu_device_wb_fini - Disable Writeback and free memory
760 * @adev: amdgpu_device pointer
762 * Disables Writeback and frees the Writeback memory (all asics).
763 * Used at driver shutdown.
765 static void amdgpu_device_wb_fini(struct amdgpu_device
*adev
)
767 if (adev
->wb
.wb_obj
) {
768 amdgpu_bo_free_kernel(&adev
->wb
.wb_obj
,
770 (void **)&adev
->wb
.wb
);
771 adev
->wb
.wb_obj
= NULL
;
776 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
778 * @adev: amdgpu_device pointer
780 * Initializes writeback and allocates writeback memory (all asics).
781 * Used at driver startup.
782 * Returns 0 on success or an -error on failure.
784 static int amdgpu_device_wb_init(struct amdgpu_device
*adev
)
788 if (adev
->wb
.wb_obj
== NULL
) {
789 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
790 r
= amdgpu_bo_create_kernel(adev
, AMDGPU_MAX_WB
* sizeof(uint32_t) * 8,
791 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_GTT
,
792 &adev
->wb
.wb_obj
, &adev
->wb
.gpu_addr
,
793 (void **)&adev
->wb
.wb
);
795 dev_warn(adev
->dev
, "(%d) create WB bo failed\n", r
);
799 adev
->wb
.num_wb
= AMDGPU_MAX_WB
;
800 memset(&adev
->wb
.used
, 0, sizeof(adev
->wb
.used
));
802 /* clear wb memory */
803 memset((char *)adev
->wb
.wb
, 0, AMDGPU_MAX_WB
* sizeof(uint32_t) * 8);
810 * amdgpu_device_wb_get - Allocate a wb entry
812 * @adev: amdgpu_device pointer
815 * Allocate a wb slot for use by the driver (all asics).
816 * Returns 0 on success or -EINVAL on failure.
818 int amdgpu_device_wb_get(struct amdgpu_device
*adev
, u32
*wb
)
820 unsigned long offset
= find_first_zero_bit(adev
->wb
.used
, adev
->wb
.num_wb
);
822 if (offset
< adev
->wb
.num_wb
) {
823 __set_bit(offset
, adev
->wb
.used
);
824 *wb
= offset
<< 3; /* convert to dw offset */
832 * amdgpu_device_wb_free - Free a wb entry
834 * @adev: amdgpu_device pointer
837 * Free a wb slot allocated for use by the driver (all asics)
839 void amdgpu_device_wb_free(struct amdgpu_device
*adev
, u32 wb
)
842 if (wb
< adev
->wb
.num_wb
)
843 __clear_bit(wb
, adev
->wb
.used
);
847 * amdgpu_device_resize_fb_bar - try to resize FB BAR
849 * @adev: amdgpu_device pointer
851 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
852 * to fail, but if any of the BARs is not accessible after the size we abort
853 * driver loading by returning -ENODEV.
855 int amdgpu_device_resize_fb_bar(struct amdgpu_device
*adev
)
857 u64 space_needed
= roundup_pow_of_two(adev
->gmc
.real_vram_size
);
858 u32 rbar_size
= order_base_2(((space_needed
>> 20) | 1)) - 1;
859 struct pci_bus
*root
;
860 struct resource
*res
;
866 if (amdgpu_sriov_vf(adev
))
869 /* Check if the root BUS has 64bit memory resources */
870 root
= adev
->pdev
->bus
;
874 pci_bus_for_each_resource(root
, res
, i
) {
875 if (res
&& res
->flags
& (IORESOURCE_MEM
| IORESOURCE_MEM_64
) &&
876 res
->start
> 0x100000000ull
)
880 /* Trying to resize is pointless without a root hub window above 4GB */
884 /* Disable memory decoding while we change the BAR addresses and size */
885 pci_read_config_word(adev
->pdev
, PCI_COMMAND
, &cmd
);
886 pci_write_config_word(adev
->pdev
, PCI_COMMAND
,
887 cmd
& ~PCI_COMMAND_MEMORY
);
889 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
890 amdgpu_device_doorbell_fini(adev
);
891 if (adev
->asic_type
>= CHIP_BONAIRE
)
892 pci_release_resource(adev
->pdev
, 2);
894 pci_release_resource(adev
->pdev
, 0);
896 r
= pci_resize_resource(adev
->pdev
, 0, rbar_size
);
898 DRM_INFO("Not enough PCI address space for a large BAR.");
899 else if (r
&& r
!= -ENOTSUPP
)
900 DRM_ERROR("Problem resizing BAR0 (%d).", r
);
902 pci_assign_unassigned_bus_resources(adev
->pdev
->bus
);
904 /* When the doorbell or fb BAR isn't available we have no chance of
907 r
= amdgpu_device_doorbell_init(adev
);
908 if (r
|| (pci_resource_flags(adev
->pdev
, 0) & IORESOURCE_UNSET
))
911 pci_write_config_word(adev
->pdev
, PCI_COMMAND
, cmd
);
917 * GPU helpers function.
920 * amdgpu_device_need_post - check if the hw need post or not
922 * @adev: amdgpu_device pointer
924 * Check if the asic has been initialized (all asics) at driver startup
925 * or post is needed if hw reset is performed.
926 * Returns true if need or false if not.
928 bool amdgpu_device_need_post(struct amdgpu_device
*adev
)
932 if (amdgpu_sriov_vf(adev
))
935 if (amdgpu_passthrough(adev
)) {
936 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
937 * some old smc fw still need driver do vPost otherwise gpu hang, while
938 * those smc fw version above 22.15 doesn't have this flaw, so we force
939 * vpost executed for smc version below 22.15
941 if (adev
->asic_type
== CHIP_FIJI
) {
944 err
= request_firmware(&adev
->pm
.fw
, "amdgpu/fiji_smc.bin", adev
->dev
);
945 /* force vPost if error occured */
949 fw_ver
= *((uint32_t *)adev
->pm
.fw
->data
+ 69);
950 if (fw_ver
< 0x00160e00)
955 if (adev
->has_hw_reset
) {
956 adev
->has_hw_reset
= false;
960 /* bios scratch used on CIK+ */
961 if (adev
->asic_type
>= CHIP_BONAIRE
)
962 return amdgpu_atombios_scratch_need_asic_init(adev
);
964 /* check MEM_SIZE for older asics */
965 reg
= amdgpu_asic_get_config_memsize(adev
);
967 if ((reg
!= 0) && (reg
!= 0xffffffff))
973 /* if we get transitioned to only one device, take VGA back */
975 * amdgpu_device_vga_set_decode - enable/disable vga decode
977 * @cookie: amdgpu_device pointer
978 * @state: enable/disable vga decode
980 * Enable/disable vga decode (all asics).
981 * Returns VGA resource flags.
983 static unsigned int amdgpu_device_vga_set_decode(void *cookie
, bool state
)
985 struct amdgpu_device
*adev
= cookie
;
986 amdgpu_asic_set_vga_state(adev
, state
);
988 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
989 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
991 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
995 * amdgpu_device_check_block_size - validate the vm block size
997 * @adev: amdgpu_device pointer
999 * Validates the vm block size specified via module parameter.
1000 * The vm block size defines number of bits in page table versus page directory,
1001 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1002 * page table and the remaining bits are in the page directory.
1004 static void amdgpu_device_check_block_size(struct amdgpu_device
*adev
)
1006 /* defines number of bits in page table versus page directory,
1007 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1008 * page table and the remaining bits are in the page directory */
1009 if (amdgpu_vm_block_size
== -1)
1012 if (amdgpu_vm_block_size
< 9) {
1013 dev_warn(adev
->dev
, "VM page table size (%d) too small\n",
1014 amdgpu_vm_block_size
);
1015 amdgpu_vm_block_size
= -1;
1020 * amdgpu_device_check_vm_size - validate the vm size
1022 * @adev: amdgpu_device pointer
1024 * Validates the vm size in GB specified via module parameter.
1025 * The VM size is the size of the GPU virtual memory space in GB.
1027 static void amdgpu_device_check_vm_size(struct amdgpu_device
*adev
)
1029 /* no need to check the default value */
1030 if (amdgpu_vm_size
== -1)
1033 if (amdgpu_vm_size
< 1) {
1034 dev_warn(adev
->dev
, "VM size (%d) too small, min is 1GB\n",
1036 amdgpu_vm_size
= -1;
1040 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device
*adev
)
1043 bool is_os_64
= (sizeof(void *) == 8);
1044 uint64_t total_memory
;
1045 uint64_t dram_size_seven_GB
= 0x1B8000000;
1046 uint64_t dram_size_three_GB
= 0xB8000000;
1048 if (amdgpu_smu_memory_pool_size
== 0)
1052 DRM_WARN("Not 64-bit OS, feature not supported\n");
1056 total_memory
= (uint64_t)si
.totalram
* si
.mem_unit
;
1058 if ((amdgpu_smu_memory_pool_size
== 1) ||
1059 (amdgpu_smu_memory_pool_size
== 2)) {
1060 if (total_memory
< dram_size_three_GB
)
1062 } else if ((amdgpu_smu_memory_pool_size
== 4) ||
1063 (amdgpu_smu_memory_pool_size
== 8)) {
1064 if (total_memory
< dram_size_seven_GB
)
1067 DRM_WARN("Smu memory pool size not supported\n");
1070 adev
->pm
.smu_prv_buffer_size
= amdgpu_smu_memory_pool_size
<< 28;
1075 DRM_WARN("No enough system memory\n");
1077 adev
->pm
.smu_prv_buffer_size
= 0;
1081 * amdgpu_device_check_arguments - validate module params
1083 * @adev: amdgpu_device pointer
1085 * Validates certain module parameters and updates
1086 * the associated values used by the driver (all asics).
1088 static int amdgpu_device_check_arguments(struct amdgpu_device
*adev
)
1090 if (amdgpu_sched_jobs
< 4) {
1091 dev_warn(adev
->dev
, "sched jobs (%d) must be at least 4\n",
1093 amdgpu_sched_jobs
= 4;
1094 } else if (!is_power_of_2(amdgpu_sched_jobs
)){
1095 dev_warn(adev
->dev
, "sched jobs (%d) must be a power of 2\n",
1097 amdgpu_sched_jobs
= roundup_pow_of_two(amdgpu_sched_jobs
);
1100 if (amdgpu_gart_size
!= -1 && amdgpu_gart_size
< 32) {
1101 /* gart size must be greater or equal to 32M */
1102 dev_warn(adev
->dev
, "gart size (%d) too small\n",
1104 amdgpu_gart_size
= -1;
1107 if (amdgpu_gtt_size
!= -1 && amdgpu_gtt_size
< 32) {
1108 /* gtt size must be greater or equal to 32M */
1109 dev_warn(adev
->dev
, "gtt size (%d) too small\n",
1111 amdgpu_gtt_size
= -1;
1114 /* valid range is between 4 and 9 inclusive */
1115 if (amdgpu_vm_fragment_size
!= -1 &&
1116 (amdgpu_vm_fragment_size
> 9 || amdgpu_vm_fragment_size
< 4)) {
1117 dev_warn(adev
->dev
, "valid range is between 4 and 9\n");
1118 amdgpu_vm_fragment_size
= -1;
1121 amdgpu_device_check_smu_prv_buffer_size(adev
);
1123 amdgpu_device_check_vm_size(adev
);
1125 amdgpu_device_check_block_size(adev
);
1127 adev
->firmware
.load_type
= amdgpu_ucode_get_load_type(adev
, amdgpu_fw_load_type
);
1133 * amdgpu_switcheroo_set_state - set switcheroo state
1135 * @pdev: pci dev pointer
1136 * @state: vga_switcheroo state
1138 * Callback for the switcheroo driver. Suspends or resumes the
1139 * the asics before or after it is powered up using ACPI methods.
1141 static void amdgpu_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1143 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1146 if (amdgpu_device_supports_boco(dev
) && state
== VGA_SWITCHEROO_OFF
)
1149 if (state
== VGA_SWITCHEROO_ON
) {
1150 pr_info("amdgpu: switched on\n");
1151 /* don't suspend or resume card normally */
1152 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1154 pci_set_power_state(dev
->pdev
, PCI_D0
);
1155 pci_restore_state(dev
->pdev
);
1156 r
= pci_enable_device(dev
->pdev
);
1158 DRM_WARN("pci_enable_device failed (%d)\n", r
);
1159 amdgpu_device_resume(dev
, true);
1161 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1162 drm_kms_helper_poll_enable(dev
);
1164 pr_info("amdgpu: switched off\n");
1165 drm_kms_helper_poll_disable(dev
);
1166 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1167 amdgpu_device_suspend(dev
, true);
1168 pci_save_state(dev
->pdev
);
1169 /* Shut down the device */
1170 pci_disable_device(dev
->pdev
);
1171 pci_set_power_state(dev
->pdev
, PCI_D3cold
);
1172 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1177 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1179 * @pdev: pci dev pointer
1181 * Callback for the switcheroo driver. Check of the switcheroo
1182 * state can be changed.
1183 * Returns true if the state can be changed, false if not.
1185 static bool amdgpu_switcheroo_can_switch(struct pci_dev
*pdev
)
1187 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1190 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1191 * locking inversion with the driver load path. And the access here is
1192 * completely racy anyway. So don't bother with locking for now.
1194 return atomic_read(&dev
->open_count
) == 0;
1197 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops
= {
1198 .set_gpu_state
= amdgpu_switcheroo_set_state
,
1200 .can_switch
= amdgpu_switcheroo_can_switch
,
1204 * amdgpu_device_ip_set_clockgating_state - set the CG state
1206 * @dev: amdgpu_device pointer
1207 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1208 * @state: clockgating state (gate or ungate)
1210 * Sets the requested clockgating state for all instances of
1211 * the hardware IP specified.
1212 * Returns the error code from the last instance.
1214 int amdgpu_device_ip_set_clockgating_state(void *dev
,
1215 enum amd_ip_block_type block_type
,
1216 enum amd_clockgating_state state
)
1218 struct amdgpu_device
*adev
= dev
;
1221 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1222 if (!adev
->ip_blocks
[i
].status
.valid
)
1224 if (adev
->ip_blocks
[i
].version
->type
!= block_type
)
1226 if (!adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state
)
1228 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state(
1229 (void *)adev
, state
);
1231 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1232 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1238 * amdgpu_device_ip_set_powergating_state - set the PG state
1240 * @dev: amdgpu_device pointer
1241 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1242 * @state: powergating state (gate or ungate)
1244 * Sets the requested powergating state for all instances of
1245 * the hardware IP specified.
1246 * Returns the error code from the last instance.
1248 int amdgpu_device_ip_set_powergating_state(void *dev
,
1249 enum amd_ip_block_type block_type
,
1250 enum amd_powergating_state state
)
1252 struct amdgpu_device
*adev
= dev
;
1255 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1256 if (!adev
->ip_blocks
[i
].status
.valid
)
1258 if (adev
->ip_blocks
[i
].version
->type
!= block_type
)
1260 if (!adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state
)
1262 r
= adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state(
1263 (void *)adev
, state
);
1265 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1266 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1272 * amdgpu_device_ip_get_clockgating_state - get the CG state
1274 * @adev: amdgpu_device pointer
1275 * @flags: clockgating feature flags
1277 * Walks the list of IPs on the device and updates the clockgating
1278 * flags for each IP.
1279 * Updates @flags with the feature flags for each hardware IP where
1280 * clockgating is enabled.
1282 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device
*adev
,
1287 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1288 if (!adev
->ip_blocks
[i
].status
.valid
)
1290 if (adev
->ip_blocks
[i
].version
->funcs
->get_clockgating_state
)
1291 adev
->ip_blocks
[i
].version
->funcs
->get_clockgating_state((void *)adev
, flags
);
1296 * amdgpu_device_ip_wait_for_idle - wait for idle
1298 * @adev: amdgpu_device pointer
1299 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1301 * Waits for the request hardware IP to be idle.
1302 * Returns 0 for success or a negative error code on failure.
1304 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device
*adev
,
1305 enum amd_ip_block_type block_type
)
1309 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1310 if (!adev
->ip_blocks
[i
].status
.valid
)
1312 if (adev
->ip_blocks
[i
].version
->type
== block_type
) {
1313 r
= adev
->ip_blocks
[i
].version
->funcs
->wait_for_idle((void *)adev
);
1324 * amdgpu_device_ip_is_idle - is the hardware IP idle
1326 * @adev: amdgpu_device pointer
1327 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1329 * Check if the hardware IP is idle or not.
1330 * Returns true if it the IP is idle, false if not.
1332 bool amdgpu_device_ip_is_idle(struct amdgpu_device
*adev
,
1333 enum amd_ip_block_type block_type
)
1337 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1338 if (!adev
->ip_blocks
[i
].status
.valid
)
1340 if (adev
->ip_blocks
[i
].version
->type
== block_type
)
1341 return adev
->ip_blocks
[i
].version
->funcs
->is_idle((void *)adev
);
1348 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1350 * @adev: amdgpu_device pointer
1351 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1353 * Returns a pointer to the hardware IP block structure
1354 * if it exists for the asic, otherwise NULL.
1356 struct amdgpu_ip_block
*
1357 amdgpu_device_ip_get_ip_block(struct amdgpu_device
*adev
,
1358 enum amd_ip_block_type type
)
1362 for (i
= 0; i
< adev
->num_ip_blocks
; i
++)
1363 if (adev
->ip_blocks
[i
].version
->type
== type
)
1364 return &adev
->ip_blocks
[i
];
1370 * amdgpu_device_ip_block_version_cmp
1372 * @adev: amdgpu_device pointer
1373 * @type: enum amd_ip_block_type
1374 * @major: major version
1375 * @minor: minor version
1377 * return 0 if equal or greater
1378 * return 1 if smaller or the ip_block doesn't exist
1380 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device
*adev
,
1381 enum amd_ip_block_type type
,
1382 u32 major
, u32 minor
)
1384 struct amdgpu_ip_block
*ip_block
= amdgpu_device_ip_get_ip_block(adev
, type
);
1386 if (ip_block
&& ((ip_block
->version
->major
> major
) ||
1387 ((ip_block
->version
->major
== major
) &&
1388 (ip_block
->version
->minor
>= minor
))))
1395 * amdgpu_device_ip_block_add
1397 * @adev: amdgpu_device pointer
1398 * @ip_block_version: pointer to the IP to add
1400 * Adds the IP block driver information to the collection of IPs
1403 int amdgpu_device_ip_block_add(struct amdgpu_device
*adev
,
1404 const struct amdgpu_ip_block_version
*ip_block_version
)
1406 if (!ip_block_version
)
1409 DRM_INFO("add ip block number %d <%s>\n", adev
->num_ip_blocks
,
1410 ip_block_version
->funcs
->name
);
1412 adev
->ip_blocks
[adev
->num_ip_blocks
++].version
= ip_block_version
;
1418 * amdgpu_device_enable_virtual_display - enable virtual display feature
1420 * @adev: amdgpu_device pointer
1422 * Enabled the virtual display feature if the user has enabled it via
1423 * the module parameter virtual_display. This feature provides a virtual
1424 * display hardware on headless boards or in virtualized environments.
1425 * This function parses and validates the configuration string specified by
1426 * the user and configues the virtual display configuration (number of
1427 * virtual connectors, crtcs, etc.) specified.
1429 static void amdgpu_device_enable_virtual_display(struct amdgpu_device
*adev
)
1431 adev
->enable_virtual_display
= false;
1433 if (amdgpu_virtual_display
) {
1434 struct drm_device
*ddev
= adev
->ddev
;
1435 const char *pci_address_name
= pci_name(ddev
->pdev
);
1436 char *pciaddstr
, *pciaddstr_tmp
, *pciaddname_tmp
, *pciaddname
;
1438 pciaddstr
= kstrdup(amdgpu_virtual_display
, GFP_KERNEL
);
1439 pciaddstr_tmp
= pciaddstr
;
1440 while ((pciaddname_tmp
= strsep(&pciaddstr_tmp
, ";"))) {
1441 pciaddname
= strsep(&pciaddname_tmp
, ",");
1442 if (!strcmp("all", pciaddname
)
1443 || !strcmp(pci_address_name
, pciaddname
)) {
1447 adev
->enable_virtual_display
= true;
1450 res
= kstrtol(pciaddname_tmp
, 10,
1458 adev
->mode_info
.num_crtc
= num_crtc
;
1460 adev
->mode_info
.num_crtc
= 1;
1466 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1467 amdgpu_virtual_display
, pci_address_name
,
1468 adev
->enable_virtual_display
, adev
->mode_info
.num_crtc
);
1475 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1477 * @adev: amdgpu_device pointer
1479 * Parses the asic configuration parameters specified in the gpu info
1480 * firmware and makes them availale to the driver for use in configuring
1482 * Returns 0 on success, -EINVAL on failure.
1484 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device
*adev
)
1486 const char *chip_name
;
1489 const struct gpu_info_firmware_header_v1_0
*hdr
;
1491 adev
->firmware
.gpu_info_fw
= NULL
;
1493 switch (adev
->asic_type
) {
1497 case CHIP_POLARIS10
:
1498 case CHIP_POLARIS11
:
1499 case CHIP_POLARIS12
:
1503 #ifdef CONFIG_DRM_AMDGPU_SI
1510 #ifdef CONFIG_DRM_AMDGPU_CIK
1521 chip_name
= "vega10";
1524 chip_name
= "vega12";
1527 if (adev
->rev_id
>= 8)
1528 chip_name
= "raven2";
1529 else if (adev
->pdev
->device
== 0x15d8)
1530 chip_name
= "picasso";
1532 chip_name
= "raven";
1535 chip_name
= "arcturus";
1538 chip_name
= "renoir";
1541 chip_name
= "navi10";
1544 chip_name
= "navi14";
1547 chip_name
= "navi12";
1551 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_gpu_info.bin", chip_name
);
1552 err
= request_firmware(&adev
->firmware
.gpu_info_fw
, fw_name
, adev
->dev
);
1555 "Failed to load gpu_info firmware \"%s\"\n",
1559 err
= amdgpu_ucode_validate(adev
->firmware
.gpu_info_fw
);
1562 "Failed to validate gpu_info firmware \"%s\"\n",
1567 hdr
= (const struct gpu_info_firmware_header_v1_0
*)adev
->firmware
.gpu_info_fw
->data
;
1568 amdgpu_ucode_print_gpu_info_hdr(&hdr
->header
);
1570 switch (hdr
->version_major
) {
1573 const struct gpu_info_firmware_v1_0
*gpu_info_fw
=
1574 (const struct gpu_info_firmware_v1_0
*)(adev
->firmware
.gpu_info_fw
->data
+
1575 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
1577 if (amdgpu_discovery
&& adev
->asic_type
>= CHIP_NAVI10
)
1578 goto parse_soc_bounding_box
;
1580 adev
->gfx
.config
.max_shader_engines
= le32_to_cpu(gpu_info_fw
->gc_num_se
);
1581 adev
->gfx
.config
.max_cu_per_sh
= le32_to_cpu(gpu_info_fw
->gc_num_cu_per_sh
);
1582 adev
->gfx
.config
.max_sh_per_se
= le32_to_cpu(gpu_info_fw
->gc_num_sh_per_se
);
1583 adev
->gfx
.config
.max_backends_per_se
= le32_to_cpu(gpu_info_fw
->gc_num_rb_per_se
);
1584 adev
->gfx
.config
.max_texture_channel_caches
=
1585 le32_to_cpu(gpu_info_fw
->gc_num_tccs
);
1586 adev
->gfx
.config
.max_gprs
= le32_to_cpu(gpu_info_fw
->gc_num_gprs
);
1587 adev
->gfx
.config
.max_gs_threads
= le32_to_cpu(gpu_info_fw
->gc_num_max_gs_thds
);
1588 adev
->gfx
.config
.gs_vgt_table_depth
= le32_to_cpu(gpu_info_fw
->gc_gs_table_depth
);
1589 adev
->gfx
.config
.gs_prim_buffer_depth
= le32_to_cpu(gpu_info_fw
->gc_gsprim_buff_depth
);
1590 adev
->gfx
.config
.double_offchip_lds_buf
=
1591 le32_to_cpu(gpu_info_fw
->gc_double_offchip_lds_buffer
);
1592 adev
->gfx
.cu_info
.wave_front_size
= le32_to_cpu(gpu_info_fw
->gc_wave_size
);
1593 adev
->gfx
.cu_info
.max_waves_per_simd
=
1594 le32_to_cpu(gpu_info_fw
->gc_max_waves_per_simd
);
1595 adev
->gfx
.cu_info
.max_scratch_slots_per_cu
=
1596 le32_to_cpu(gpu_info_fw
->gc_max_scratch_slots_per_cu
);
1597 adev
->gfx
.cu_info
.lds_size
= le32_to_cpu(gpu_info_fw
->gc_lds_size
);
1598 if (hdr
->version_minor
>= 1) {
1599 const struct gpu_info_firmware_v1_1
*gpu_info_fw
=
1600 (const struct gpu_info_firmware_v1_1
*)(adev
->firmware
.gpu_info_fw
->data
+
1601 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
1602 adev
->gfx
.config
.num_sc_per_sh
=
1603 le32_to_cpu(gpu_info_fw
->num_sc_per_sh
);
1604 adev
->gfx
.config
.num_packer_per_sc
=
1605 le32_to_cpu(gpu_info_fw
->num_packer_per_sc
);
1608 parse_soc_bounding_box
:
1610 * soc bounding box info is not integrated in disocovery table,
1611 * we always need to parse it from gpu info firmware.
1613 if (hdr
->version_minor
== 2) {
1614 const struct gpu_info_firmware_v1_2
*gpu_info_fw
=
1615 (const struct gpu_info_firmware_v1_2
*)(adev
->firmware
.gpu_info_fw
->data
+
1616 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
1617 adev
->dm
.soc_bounding_box
= &gpu_info_fw
->soc_bounding_box
;
1623 "Unsupported gpu_info table %d\n", hdr
->header
.ucode_version
);
1632 * amdgpu_device_ip_early_init - run early init for hardware IPs
1634 * @adev: amdgpu_device pointer
1636 * Early initialization pass for hardware IPs. The hardware IPs that make
1637 * up each asic are discovered each IP's early_init callback is run. This
1638 * is the first stage in initializing the asic.
1639 * Returns 0 on success, negative error code on failure.
1641 static int amdgpu_device_ip_early_init(struct amdgpu_device
*adev
)
1645 amdgpu_device_enable_virtual_display(adev
);
1647 switch (adev
->asic_type
) {
1651 case CHIP_POLARIS10
:
1652 case CHIP_POLARIS11
:
1653 case CHIP_POLARIS12
:
1657 if (adev
->asic_type
== CHIP_CARRIZO
|| adev
->asic_type
== CHIP_STONEY
)
1658 adev
->family
= AMDGPU_FAMILY_CZ
;
1660 adev
->family
= AMDGPU_FAMILY_VI
;
1662 r
= vi_set_ip_blocks(adev
);
1666 #ifdef CONFIG_DRM_AMDGPU_SI
1672 adev
->family
= AMDGPU_FAMILY_SI
;
1673 r
= si_set_ip_blocks(adev
);
1678 #ifdef CONFIG_DRM_AMDGPU_CIK
1684 if ((adev
->asic_type
== CHIP_BONAIRE
) || (adev
->asic_type
== CHIP_HAWAII
))
1685 adev
->family
= AMDGPU_FAMILY_CI
;
1687 adev
->family
= AMDGPU_FAMILY_KV
;
1689 r
= cik_set_ip_blocks(adev
);
1700 if (adev
->asic_type
== CHIP_RAVEN
||
1701 adev
->asic_type
== CHIP_RENOIR
)
1702 adev
->family
= AMDGPU_FAMILY_RV
;
1704 adev
->family
= AMDGPU_FAMILY_AI
;
1706 r
= soc15_set_ip_blocks(adev
);
1713 adev
->family
= AMDGPU_FAMILY_NV
;
1715 r
= nv_set_ip_blocks(adev
);
1720 /* FIXME: not supported yet */
1724 r
= amdgpu_device_parse_gpu_info_fw(adev
);
1728 if (amdgpu_discovery
&& adev
->asic_type
>= CHIP_NAVI10
)
1729 amdgpu_discovery_get_gfx_info(adev
);
1731 amdgpu_amdkfd_device_probe(adev
);
1733 if (amdgpu_sriov_vf(adev
)) {
1734 r
= amdgpu_virt_request_full_gpu(adev
, true);
1739 adev
->pm
.pp_feature
= amdgpu_pp_feature_mask
;
1740 if (amdgpu_sriov_vf(adev
) || sched_policy
== KFD_SCHED_POLICY_NO_HWS
)
1741 adev
->pm
.pp_feature
&= ~PP_GFXOFF_MASK
;
1743 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1744 if ((amdgpu_ip_block_mask
& (1 << i
)) == 0) {
1745 DRM_ERROR("disabled ip block: %d <%s>\n",
1746 i
, adev
->ip_blocks
[i
].version
->funcs
->name
);
1747 adev
->ip_blocks
[i
].status
.valid
= false;
1749 if (adev
->ip_blocks
[i
].version
->funcs
->early_init
) {
1750 r
= adev
->ip_blocks
[i
].version
->funcs
->early_init((void *)adev
);
1752 adev
->ip_blocks
[i
].status
.valid
= false;
1754 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1755 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1758 adev
->ip_blocks
[i
].status
.valid
= true;
1761 adev
->ip_blocks
[i
].status
.valid
= true;
1764 /* get the vbios after the asic_funcs are set up */
1765 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_COMMON
) {
1767 if (!amdgpu_get_bios(adev
))
1770 r
= amdgpu_atombios_init(adev
);
1772 dev_err(adev
->dev
, "amdgpu_atombios_init failed\n");
1773 amdgpu_vf_error_put(adev
, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL
, 0, 0);
1779 adev
->cg_flags
&= amdgpu_cg_mask
;
1780 adev
->pg_flags
&= amdgpu_pg_mask
;
1785 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device
*adev
)
1789 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1790 if (!adev
->ip_blocks
[i
].status
.sw
)
1792 if (adev
->ip_blocks
[i
].status
.hw
)
1794 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_COMMON
||
1795 (amdgpu_sriov_vf(adev
) && (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_PSP
)) ||
1796 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_IH
) {
1797 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init(adev
);
1799 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1800 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1803 adev
->ip_blocks
[i
].status
.hw
= true;
1810 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device
*adev
)
1814 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1815 if (!adev
->ip_blocks
[i
].status
.sw
)
1817 if (adev
->ip_blocks
[i
].status
.hw
)
1819 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init(adev
);
1821 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1822 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1825 adev
->ip_blocks
[i
].status
.hw
= true;
1831 static int amdgpu_device_fw_loading(struct amdgpu_device
*adev
)
1835 uint32_t smu_version
;
1837 if (adev
->asic_type
>= CHIP_VEGA10
) {
1838 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1839 if (adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_PSP
)
1842 /* no need to do the fw loading again if already done*/
1843 if (adev
->ip_blocks
[i
].status
.hw
== true)
1846 if (adev
->in_gpu_reset
|| adev
->in_suspend
) {
1847 r
= adev
->ip_blocks
[i
].version
->funcs
->resume(adev
);
1849 DRM_ERROR("resume of IP block <%s> failed %d\n",
1850 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1854 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init(adev
);
1856 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1857 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1862 adev
->ip_blocks
[i
].status
.hw
= true;
1867 if (!amdgpu_sriov_vf(adev
) || adev
->asic_type
== CHIP_TONGA
)
1868 r
= amdgpu_pm_load_smu_firmware(adev
, &smu_version
);
1874 * amdgpu_device_ip_init - run init for hardware IPs
1876 * @adev: amdgpu_device pointer
1878 * Main initialization pass for hardware IPs. The list of all the hardware
1879 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1880 * are run. sw_init initializes the software state associated with each IP
1881 * and hw_init initializes the hardware associated with each IP.
1882 * Returns 0 on success, negative error code on failure.
1884 static int amdgpu_device_ip_init(struct amdgpu_device
*adev
)
1888 r
= amdgpu_ras_init(adev
);
1892 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
1893 if (!adev
->ip_blocks
[i
].status
.valid
)
1895 r
= adev
->ip_blocks
[i
].version
->funcs
->sw_init((void *)adev
);
1897 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1898 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
1901 adev
->ip_blocks
[i
].status
.sw
= true;
1903 /* need to do gmc hw init early so we can allocate gpu mem */
1904 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) {
1905 r
= amdgpu_device_vram_scratch_init(adev
);
1907 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r
);
1910 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_init((void *)adev
);
1912 DRM_ERROR("hw_init %d failed %d\n", i
, r
);
1915 r
= amdgpu_device_wb_init(adev
);
1917 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r
);
1920 adev
->ip_blocks
[i
].status
.hw
= true;
1922 /* right after GMC hw init, we create CSA */
1923 if (amdgpu_mcbp
|| amdgpu_sriov_vf(adev
)) {
1924 r
= amdgpu_allocate_static_csa(adev
, &adev
->virt
.csa_obj
,
1925 AMDGPU_GEM_DOMAIN_VRAM
,
1928 DRM_ERROR("allocate CSA failed %d\n", r
);
1935 if (amdgpu_sriov_vf(adev
))
1936 amdgpu_virt_init_data_exchange(adev
);
1938 r
= amdgpu_ib_pool_init(adev
);
1940 dev_err(adev
->dev
, "IB initialization failed (%d).\n", r
);
1941 amdgpu_vf_error_put(adev
, AMDGIM_ERROR_VF_IB_INIT_FAIL
, 0, r
);
1945 r
= amdgpu_ucode_create_bo(adev
); /* create ucode bo when sw_init complete*/
1949 r
= amdgpu_device_ip_hw_init_phase1(adev
);
1953 r
= amdgpu_device_fw_loading(adev
);
1957 r
= amdgpu_device_ip_hw_init_phase2(adev
);
1962 * retired pages will be loaded from eeprom and reserved here,
1963 * it should be called after amdgpu_device_ip_hw_init_phase2 since
1964 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
1965 * for I2C communication which only true at this point.
1966 * recovery_init may fail, but it can free all resources allocated by
1967 * itself and its failure should not stop amdgpu init process.
1969 * Note: theoretically, this should be called before all vram allocations
1970 * to protect retired page from abusing
1972 amdgpu_ras_recovery_init(adev
);
1974 if (adev
->gmc
.xgmi
.num_physical_nodes
> 1)
1975 amdgpu_xgmi_add_device(adev
);
1976 amdgpu_amdkfd_device_init(adev
);
1979 if (amdgpu_sriov_vf(adev
))
1980 amdgpu_virt_release_full_gpu(adev
, true);
1986 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1988 * @adev: amdgpu_device pointer
1990 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
1991 * this function before a GPU reset. If the value is retained after a
1992 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
1994 static void amdgpu_device_fill_reset_magic(struct amdgpu_device
*adev
)
1996 memcpy(adev
->reset_magic
, adev
->gart
.ptr
, AMDGPU_RESET_MAGIC_NUM
);
2000 * amdgpu_device_check_vram_lost - check if vram is valid
2002 * @adev: amdgpu_device pointer
2004 * Checks the reset magic value written to the gart pointer in VRAM.
2005 * The driver calls this after a GPU reset to see if the contents of
2006 * VRAM is lost or now.
2007 * returns true if vram is lost, false if not.
2009 static bool amdgpu_device_check_vram_lost(struct amdgpu_device
*adev
)
2011 if (memcmp(adev
->gart
.ptr
, adev
->reset_magic
,
2012 AMDGPU_RESET_MAGIC_NUM
))
2015 if (!adev
->in_gpu_reset
)
2019 * For all ASICs with baco/mode1 reset, the VRAM is
2020 * always assumed to be lost.
2022 switch (amdgpu_asic_reset_method(adev
)) {
2023 case AMD_RESET_METHOD_BACO
:
2024 case AMD_RESET_METHOD_MODE1
:
2032 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2034 * @adev: amdgpu_device pointer
2035 * @state: clockgating state (gate or ungate)
2037 * The list of all the hardware IPs that make up the asic is walked and the
2038 * set_clockgating_state callbacks are run.
2039 * Late initialization pass enabling clockgating for hardware IPs.
2040 * Fini or suspend, pass disabling clockgating for hardware IPs.
2041 * Returns 0 on success, negative error code on failure.
2044 static int amdgpu_device_set_cg_state(struct amdgpu_device
*adev
,
2045 enum amd_clockgating_state state
)
2049 if (amdgpu_emu_mode
== 1)
2052 for (j
= 0; j
< adev
->num_ip_blocks
; j
++) {
2053 i
= state
== AMD_CG_STATE_GATE
? j
: adev
->num_ip_blocks
- j
- 1;
2054 if (!adev
->ip_blocks
[i
].status
.late_initialized
)
2056 /* skip CG for VCE/UVD, it's handled specially */
2057 if (adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_UVD
&&
2058 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCE
&&
2059 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCN
&&
2060 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_JPEG
&&
2061 adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state
) {
2062 /* enable clockgating to save power */
2063 r
= adev
->ip_blocks
[i
].version
->funcs
->set_clockgating_state((void *)adev
,
2066 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2067 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2076 static int amdgpu_device_set_pg_state(struct amdgpu_device
*adev
, enum amd_powergating_state state
)
2080 if (amdgpu_emu_mode
== 1)
2083 for (j
= 0; j
< adev
->num_ip_blocks
; j
++) {
2084 i
= state
== AMD_PG_STATE_GATE
? j
: adev
->num_ip_blocks
- j
- 1;
2085 if (!adev
->ip_blocks
[i
].status
.late_initialized
)
2087 /* skip CG for VCE/UVD, it's handled specially */
2088 if (adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_UVD
&&
2089 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCE
&&
2090 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_VCN
&&
2091 adev
->ip_blocks
[i
].version
->type
!= AMD_IP_BLOCK_TYPE_JPEG
&&
2092 adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state
) {
2093 /* enable powergating to save power */
2094 r
= adev
->ip_blocks
[i
].version
->funcs
->set_powergating_state((void *)adev
,
2097 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2098 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2106 static int amdgpu_device_enable_mgpu_fan_boost(void)
2108 struct amdgpu_gpu_instance
*gpu_ins
;
2109 struct amdgpu_device
*adev
;
2112 mutex_lock(&mgpu_info
.mutex
);
2115 * MGPU fan boost feature should be enabled
2116 * only when there are two or more dGPUs in
2119 if (mgpu_info
.num_dgpu
< 2)
2122 for (i
= 0; i
< mgpu_info
.num_dgpu
; i
++) {
2123 gpu_ins
= &(mgpu_info
.gpu_ins
[i
]);
2124 adev
= gpu_ins
->adev
;
2125 if (!(adev
->flags
& AMD_IS_APU
) &&
2126 !gpu_ins
->mgpu_fan_enabled
&&
2127 adev
->powerplay
.pp_funcs
&&
2128 adev
->powerplay
.pp_funcs
->enable_mgpu_fan_boost
) {
2129 ret
= amdgpu_dpm_enable_mgpu_fan_boost(adev
);
2133 gpu_ins
->mgpu_fan_enabled
= 1;
2138 mutex_unlock(&mgpu_info
.mutex
);
2144 * amdgpu_device_ip_late_init - run late init for hardware IPs
2146 * @adev: amdgpu_device pointer
2148 * Late initialization pass for hardware IPs. The list of all the hardware
2149 * IPs that make up the asic is walked and the late_init callbacks are run.
2150 * late_init covers any special initialization that an IP requires
2151 * after all of the have been initialized or something that needs to happen
2152 * late in the init process.
2153 * Returns 0 on success, negative error code on failure.
2155 static int amdgpu_device_ip_late_init(struct amdgpu_device
*adev
)
2157 struct amdgpu_gpu_instance
*gpu_instance
;
2160 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2161 if (!adev
->ip_blocks
[i
].status
.hw
)
2163 if (adev
->ip_blocks
[i
].version
->funcs
->late_init
) {
2164 r
= adev
->ip_blocks
[i
].version
->funcs
->late_init((void *)adev
);
2166 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2167 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2171 adev
->ip_blocks
[i
].status
.late_initialized
= true;
2174 amdgpu_device_set_cg_state(adev
, AMD_CG_STATE_GATE
);
2175 amdgpu_device_set_pg_state(adev
, AMD_PG_STATE_GATE
);
2177 amdgpu_device_fill_reset_magic(adev
);
2179 r
= amdgpu_device_enable_mgpu_fan_boost();
2181 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r
);
2184 if (adev
->gmc
.xgmi
.num_physical_nodes
> 1) {
2185 mutex_lock(&mgpu_info
.mutex
);
2188 * Reset device p-state to low as this was booted with high.
2190 * This should be performed only after all devices from the same
2191 * hive get initialized.
2193 * However, it's unknown how many device in the hive in advance.
2194 * As this is counted one by one during devices initializations.
2196 * So, we wait for all XGMI interlinked devices initialized.
2197 * This may bring some delays as those devices may come from
2198 * different hives. But that should be OK.
2200 if (mgpu_info
.num_dgpu
== adev
->gmc
.xgmi
.num_physical_nodes
) {
2201 for (i
= 0; i
< mgpu_info
.num_gpu
; i
++) {
2202 gpu_instance
= &(mgpu_info
.gpu_ins
[i
]);
2203 if (gpu_instance
->adev
->flags
& AMD_IS_APU
)
2206 r
= amdgpu_xgmi_set_pstate(gpu_instance
->adev
, 0);
2208 DRM_ERROR("pstate setting failed (%d).\n", r
);
2214 mutex_unlock(&mgpu_info
.mutex
);
2221 * amdgpu_device_ip_fini - run fini for hardware IPs
2223 * @adev: amdgpu_device pointer
2225 * Main teardown pass for hardware IPs. The list of all the hardware
2226 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2227 * are run. hw_fini tears down the hardware associated with each IP
2228 * and sw_fini tears down any software state associated with each IP.
2229 * Returns 0 on success, negative error code on failure.
2231 static int amdgpu_device_ip_fini(struct amdgpu_device
*adev
)
2235 amdgpu_ras_pre_fini(adev
);
2237 if (adev
->gmc
.xgmi
.num_physical_nodes
> 1)
2238 amdgpu_xgmi_remove_device(adev
);
2240 amdgpu_amdkfd_device_fini(adev
);
2242 amdgpu_device_set_pg_state(adev
, AMD_PG_STATE_UNGATE
);
2243 amdgpu_device_set_cg_state(adev
, AMD_CG_STATE_UNGATE
);
2245 /* need to disable SMC first */
2246 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2247 if (!adev
->ip_blocks
[i
].status
.hw
)
2249 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_SMC
) {
2250 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_fini((void *)adev
);
2251 /* XXX handle errors */
2253 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2254 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2256 adev
->ip_blocks
[i
].status
.hw
= false;
2261 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
2262 if (!adev
->ip_blocks
[i
].status
.hw
)
2265 r
= adev
->ip_blocks
[i
].version
->funcs
->hw_fini((void *)adev
);
2266 /* XXX handle errors */
2268 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2269 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2272 adev
->ip_blocks
[i
].status
.hw
= false;
2276 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
2277 if (!adev
->ip_blocks
[i
].status
.sw
)
2280 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) {
2281 amdgpu_ucode_free_bo(adev
);
2282 amdgpu_free_static_csa(&adev
->virt
.csa_obj
);
2283 amdgpu_device_wb_fini(adev
);
2284 amdgpu_device_vram_scratch_fini(adev
);
2285 amdgpu_ib_pool_fini(adev
);
2288 r
= adev
->ip_blocks
[i
].version
->funcs
->sw_fini((void *)adev
);
2289 /* XXX handle errors */
2291 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2292 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2294 adev
->ip_blocks
[i
].status
.sw
= false;
2295 adev
->ip_blocks
[i
].status
.valid
= false;
2298 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
2299 if (!adev
->ip_blocks
[i
].status
.late_initialized
)
2301 if (adev
->ip_blocks
[i
].version
->funcs
->late_fini
)
2302 adev
->ip_blocks
[i
].version
->funcs
->late_fini((void *)adev
);
2303 adev
->ip_blocks
[i
].status
.late_initialized
= false;
2306 amdgpu_ras_fini(adev
);
2308 if (amdgpu_sriov_vf(adev
))
2309 if (amdgpu_virt_release_full_gpu(adev
, false))
2310 DRM_ERROR("failed to release exclusive mode on fini\n");
2316 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2318 * @work: work_struct.
2320 static void amdgpu_device_delayed_init_work_handler(struct work_struct
*work
)
2322 struct amdgpu_device
*adev
=
2323 container_of(work
, struct amdgpu_device
, delayed_init_work
.work
);
2326 r
= amdgpu_ib_ring_tests(adev
);
2328 DRM_ERROR("ib ring test failed (%d).\n", r
);
2331 static void amdgpu_device_delay_enable_gfx_off(struct work_struct
*work
)
2333 struct amdgpu_device
*adev
=
2334 container_of(work
, struct amdgpu_device
, gfx
.gfx_off_delay_work
.work
);
2336 mutex_lock(&adev
->gfx
.gfx_off_mutex
);
2337 if (!adev
->gfx
.gfx_off_state
&& !adev
->gfx
.gfx_off_req_count
) {
2338 if (!amdgpu_dpm_set_powergating_by_smu(adev
, AMD_IP_BLOCK_TYPE_GFX
, true))
2339 adev
->gfx
.gfx_off_state
= true;
2341 mutex_unlock(&adev
->gfx
.gfx_off_mutex
);
2345 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2347 * @adev: amdgpu_device pointer
2349 * Main suspend function for hardware IPs. The list of all the hardware
2350 * IPs that make up the asic is walked, clockgating is disabled and the
2351 * suspend callbacks are run. suspend puts the hardware and software state
2352 * in each IP into a state suitable for suspend.
2353 * Returns 0 on success, negative error code on failure.
2355 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device
*adev
)
2359 amdgpu_device_set_pg_state(adev
, AMD_PG_STATE_UNGATE
);
2360 amdgpu_device_set_cg_state(adev
, AMD_CG_STATE_UNGATE
);
2362 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
2363 if (!adev
->ip_blocks
[i
].status
.valid
)
2365 /* displays are handled separately */
2366 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_DCE
) {
2367 /* XXX handle errors */
2368 r
= adev
->ip_blocks
[i
].version
->funcs
->suspend(adev
);
2369 /* XXX handle errors */
2371 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2372 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2375 adev
->ip_blocks
[i
].status
.hw
= false;
2383 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2385 * @adev: amdgpu_device pointer
2387 * Main suspend function for hardware IPs. The list of all the hardware
2388 * IPs that make up the asic is walked, clockgating is disabled and the
2389 * suspend callbacks are run. suspend puts the hardware and software state
2390 * in each IP into a state suitable for suspend.
2391 * Returns 0 on success, negative error code on failure.
2393 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device
*adev
)
2397 for (i
= adev
->num_ip_blocks
- 1; i
>= 0; i
--) {
2398 if (!adev
->ip_blocks
[i
].status
.valid
)
2400 /* displays are handled in phase1 */
2401 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_DCE
)
2403 /* PSP lost connection when err_event_athub occurs */
2404 if (amdgpu_ras_intr_triggered() &&
2405 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_PSP
) {
2406 adev
->ip_blocks
[i
].status
.hw
= false;
2409 /* XXX handle errors */
2410 r
= adev
->ip_blocks
[i
].version
->funcs
->suspend(adev
);
2411 /* XXX handle errors */
2413 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2414 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2416 adev
->ip_blocks
[i
].status
.hw
= false;
2417 /* handle putting the SMC in the appropriate state */
2418 if(!amdgpu_sriov_vf(adev
)){
2419 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_SMC
) {
2420 r
= amdgpu_dpm_set_mp1_state(adev
, adev
->mp1_state
);
2422 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2423 adev
->mp1_state
, r
);
2428 adev
->ip_blocks
[i
].status
.hw
= false;
2435 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2437 * @adev: amdgpu_device pointer
2439 * Main suspend function for hardware IPs. The list of all the hardware
2440 * IPs that make up the asic is walked, clockgating is disabled and the
2441 * suspend callbacks are run. suspend puts the hardware and software state
2442 * in each IP into a state suitable for suspend.
2443 * Returns 0 on success, negative error code on failure.
2445 int amdgpu_device_ip_suspend(struct amdgpu_device
*adev
)
2449 if (amdgpu_sriov_vf(adev
))
2450 amdgpu_virt_request_full_gpu(adev
, false);
2452 r
= amdgpu_device_ip_suspend_phase1(adev
);
2455 r
= amdgpu_device_ip_suspend_phase2(adev
);
2457 if (amdgpu_sriov_vf(adev
))
2458 amdgpu_virt_release_full_gpu(adev
, false);
2463 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device
*adev
)
2467 static enum amd_ip_block_type ip_order
[] = {
2468 AMD_IP_BLOCK_TYPE_GMC
,
2469 AMD_IP_BLOCK_TYPE_COMMON
,
2470 AMD_IP_BLOCK_TYPE_PSP
,
2471 AMD_IP_BLOCK_TYPE_IH
,
2474 for (i
= 0; i
< ARRAY_SIZE(ip_order
); i
++) {
2476 struct amdgpu_ip_block
*block
;
2478 for (j
= 0; j
< adev
->num_ip_blocks
; j
++) {
2479 block
= &adev
->ip_blocks
[j
];
2481 block
->status
.hw
= false;
2482 if (block
->version
->type
!= ip_order
[i
] ||
2483 !block
->status
.valid
)
2486 r
= block
->version
->funcs
->hw_init(adev
);
2487 DRM_INFO("RE-INIT-early: %s %s\n", block
->version
->funcs
->name
, r
?"failed":"succeeded");
2490 block
->status
.hw
= true;
2497 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device
*adev
)
2501 static enum amd_ip_block_type ip_order
[] = {
2502 AMD_IP_BLOCK_TYPE_SMC
,
2503 AMD_IP_BLOCK_TYPE_DCE
,
2504 AMD_IP_BLOCK_TYPE_GFX
,
2505 AMD_IP_BLOCK_TYPE_SDMA
,
2506 AMD_IP_BLOCK_TYPE_UVD
,
2507 AMD_IP_BLOCK_TYPE_VCE
,
2508 AMD_IP_BLOCK_TYPE_VCN
2511 for (i
= 0; i
< ARRAY_SIZE(ip_order
); i
++) {
2513 struct amdgpu_ip_block
*block
;
2515 for (j
= 0; j
< adev
->num_ip_blocks
; j
++) {
2516 block
= &adev
->ip_blocks
[j
];
2518 if (block
->version
->type
!= ip_order
[i
] ||
2519 !block
->status
.valid
||
2523 if (block
->version
->type
== AMD_IP_BLOCK_TYPE_SMC
)
2524 r
= block
->version
->funcs
->resume(adev
);
2526 r
= block
->version
->funcs
->hw_init(adev
);
2528 DRM_INFO("RE-INIT-late: %s %s\n", block
->version
->funcs
->name
, r
?"failed":"succeeded");
2531 block
->status
.hw
= true;
2539 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2541 * @adev: amdgpu_device pointer
2543 * First resume function for hardware IPs. The list of all the hardware
2544 * IPs that make up the asic is walked and the resume callbacks are run for
2545 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2546 * after a suspend and updates the software state as necessary. This
2547 * function is also used for restoring the GPU after a GPU reset.
2548 * Returns 0 on success, negative error code on failure.
2550 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device
*adev
)
2554 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2555 if (!adev
->ip_blocks
[i
].status
.valid
|| adev
->ip_blocks
[i
].status
.hw
)
2557 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_COMMON
||
2558 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
||
2559 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_IH
) {
2561 r
= adev
->ip_blocks
[i
].version
->funcs
->resume(adev
);
2563 DRM_ERROR("resume of IP block <%s> failed %d\n",
2564 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2567 adev
->ip_blocks
[i
].status
.hw
= true;
2575 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2577 * @adev: amdgpu_device pointer
2579 * First resume function for hardware IPs. The list of all the hardware
2580 * IPs that make up the asic is walked and the resume callbacks are run for
2581 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2582 * functional state after a suspend and updates the software state as
2583 * necessary. This function is also used for restoring the GPU after a GPU
2585 * Returns 0 on success, negative error code on failure.
2587 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device
*adev
)
2591 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
2592 if (!adev
->ip_blocks
[i
].status
.valid
|| adev
->ip_blocks
[i
].status
.hw
)
2594 if (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_COMMON
||
2595 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
||
2596 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_IH
||
2597 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_PSP
)
2599 r
= adev
->ip_blocks
[i
].version
->funcs
->resume(adev
);
2601 DRM_ERROR("resume of IP block <%s> failed %d\n",
2602 adev
->ip_blocks
[i
].version
->funcs
->name
, r
);
2605 adev
->ip_blocks
[i
].status
.hw
= true;
2612 * amdgpu_device_ip_resume - run resume for hardware IPs
2614 * @adev: amdgpu_device pointer
2616 * Main resume function for hardware IPs. The hardware IPs
2617 * are split into two resume functions because they are
2618 * are also used in in recovering from a GPU reset and some additional
2619 * steps need to be take between them. In this case (S3/S4) they are
2621 * Returns 0 on success, negative error code on failure.
2623 static int amdgpu_device_ip_resume(struct amdgpu_device
*adev
)
2627 r
= amdgpu_device_ip_resume_phase1(adev
);
2631 r
= amdgpu_device_fw_loading(adev
);
2635 r
= amdgpu_device_ip_resume_phase2(adev
);
2641 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2643 * @adev: amdgpu_device pointer
2645 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2647 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device
*adev
)
2649 if (amdgpu_sriov_vf(adev
)) {
2650 if (adev
->is_atom_fw
) {
2651 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev
))
2652 adev
->virt
.caps
|= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS
;
2654 if (amdgpu_atombios_has_gpu_virtualization_table(adev
))
2655 adev
->virt
.caps
|= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS
;
2658 if (!(adev
->virt
.caps
& AMDGPU_SRIOV_CAPS_SRIOV_VBIOS
))
2659 amdgpu_vf_error_put(adev
, AMDGIM_ERROR_VF_NO_VBIOS
, 0, 0);
2664 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2666 * @asic_type: AMD asic type
2668 * Check if there is DC (new modesetting infrastructre) support for an asic.
2669 * returns true if DC has support, false if not.
2671 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type
)
2673 switch (asic_type
) {
2674 #if defined(CONFIG_DRM_AMD_DC)
2680 * We have systems in the wild with these ASICs that require
2681 * LVDS and VGA support which is not supported with DC.
2683 * Fallback to the non-DC driver here by default so as not to
2684 * cause regressions.
2686 return amdgpu_dc
> 0;
2690 case CHIP_POLARIS10
:
2691 case CHIP_POLARIS11
:
2692 case CHIP_POLARIS12
:
2699 #if defined(CONFIG_DRM_AMD_DC_DCN)
2706 return amdgpu_dc
!= 0;
2710 DRM_INFO("Display Core has been requested via kernel parameter "
2711 "but isn't supported by ASIC, ignoring\n");
2717 * amdgpu_device_has_dc_support - check if dc is supported
2719 * @adev: amdgpu_device_pointer
2721 * Returns true for supported, false for not supported
2723 bool amdgpu_device_has_dc_support(struct amdgpu_device
*adev
)
2725 if (amdgpu_sriov_vf(adev
))
2728 return amdgpu_device_asic_has_dc_support(adev
->asic_type
);
2732 static void amdgpu_device_xgmi_reset_func(struct work_struct
*__work
)
2734 struct amdgpu_device
*adev
=
2735 container_of(__work
, struct amdgpu_device
, xgmi_reset_work
);
2736 struct amdgpu_hive_info
*hive
= amdgpu_get_xgmi_hive(adev
, 0);
2738 /* It's a bug to not have a hive within this function */
2743 * Use task barrier to synchronize all xgmi reset works across the
2744 * hive. task_barrier_enter and task_barrier_exit will block
2745 * until all the threads running the xgmi reset works reach
2746 * those points. task_barrier_full will do both blocks.
2748 if (amdgpu_asic_reset_method(adev
) == AMD_RESET_METHOD_BACO
) {
2750 task_barrier_enter(&hive
->tb
);
2751 adev
->asic_reset_res
= amdgpu_device_baco_enter(adev
->ddev
);
2753 if (adev
->asic_reset_res
)
2756 task_barrier_exit(&hive
->tb
);
2757 adev
->asic_reset_res
= amdgpu_device_baco_exit(adev
->ddev
);
2759 if (adev
->asic_reset_res
)
2762 if (adev
->mmhub
.funcs
&& adev
->mmhub
.funcs
->reset_ras_error_count
)
2763 adev
->mmhub
.funcs
->reset_ras_error_count(adev
);
2766 task_barrier_full(&hive
->tb
);
2767 adev
->asic_reset_res
= amdgpu_asic_reset(adev
);
2771 if (adev
->asic_reset_res
)
2772 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2773 adev
->asic_reset_res
, adev
->ddev
->unique
);
2776 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device
*adev
)
2778 char *input
= amdgpu_lockup_timeout
;
2779 char *timeout_setting
= NULL
;
2785 * By default timeout for non compute jobs is 10000.
2786 * And there is no timeout enforced on compute jobs.
2787 * In SR-IOV or passthrough mode, timeout for compute
2788 * jobs are 10000 by default.
2790 adev
->gfx_timeout
= msecs_to_jiffies(10000);
2791 adev
->sdma_timeout
= adev
->video_timeout
= adev
->gfx_timeout
;
2792 if (amdgpu_sriov_vf(adev
) || amdgpu_passthrough(adev
))
2793 adev
->compute_timeout
= adev
->gfx_timeout
;
2795 adev
->compute_timeout
= MAX_SCHEDULE_TIMEOUT
;
2797 if (strnlen(input
, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH
)) {
2798 while ((timeout_setting
= strsep(&input
, ",")) &&
2799 strnlen(timeout_setting
, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH
)) {
2800 ret
= kstrtol(timeout_setting
, 0, &timeout
);
2807 } else if (timeout
< 0) {
2808 timeout
= MAX_SCHEDULE_TIMEOUT
;
2810 timeout
= msecs_to_jiffies(timeout
);
2815 adev
->gfx_timeout
= timeout
;
2818 adev
->compute_timeout
= timeout
;
2821 adev
->sdma_timeout
= timeout
;
2824 adev
->video_timeout
= timeout
;
2831 * There is only one value specified and
2832 * it should apply to all non-compute jobs.
2835 adev
->sdma_timeout
= adev
->video_timeout
= adev
->gfx_timeout
;
2836 if (amdgpu_sriov_vf(adev
) || amdgpu_passthrough(adev
))
2837 adev
->compute_timeout
= adev
->gfx_timeout
;
2845 * amdgpu_device_init - initialize the driver
2847 * @adev: amdgpu_device pointer
2848 * @ddev: drm dev pointer
2849 * @pdev: pci dev pointer
2850 * @flags: driver flags
2852 * Initializes the driver info and hw (all asics).
2853 * Returns 0 for success or an error on failure.
2854 * Called at driver startup.
2856 int amdgpu_device_init(struct amdgpu_device
*adev
,
2857 struct drm_device
*ddev
,
2858 struct pci_dev
*pdev
,
2865 adev
->shutdown
= false;
2866 adev
->dev
= &pdev
->dev
;
2869 adev
->flags
= flags
;
2871 if (amdgpu_force_asic_type
>= 0 && amdgpu_force_asic_type
< CHIP_LAST
)
2872 adev
->asic_type
= amdgpu_force_asic_type
;
2874 adev
->asic_type
= flags
& AMD_ASIC_MASK
;
2876 adev
->usec_timeout
= AMDGPU_MAX_USEC_TIMEOUT
;
2877 if (amdgpu_emu_mode
== 1)
2878 adev
->usec_timeout
*= 10;
2879 adev
->gmc
.gart_size
= 512 * 1024 * 1024;
2880 adev
->accel_working
= false;
2881 adev
->num_rings
= 0;
2882 adev
->mman
.buffer_funcs
= NULL
;
2883 adev
->mman
.buffer_funcs_ring
= NULL
;
2884 adev
->vm_manager
.vm_pte_funcs
= NULL
;
2885 adev
->vm_manager
.vm_pte_num_scheds
= 0;
2886 adev
->gmc
.gmc_funcs
= NULL
;
2887 adev
->fence_context
= dma_fence_context_alloc(AMDGPU_MAX_RINGS
);
2888 bitmap_zero(adev
->gfx
.pipe_reserve_bitmap
, AMDGPU_MAX_COMPUTE_QUEUES
);
2890 adev
->smc_rreg
= &amdgpu_invalid_rreg
;
2891 adev
->smc_wreg
= &amdgpu_invalid_wreg
;
2892 adev
->pcie_rreg
= &amdgpu_invalid_rreg
;
2893 adev
->pcie_wreg
= &amdgpu_invalid_wreg
;
2894 adev
->pciep_rreg
= &amdgpu_invalid_rreg
;
2895 adev
->pciep_wreg
= &amdgpu_invalid_wreg
;
2896 adev
->pcie_rreg64
= &amdgpu_invalid_rreg64
;
2897 adev
->pcie_wreg64
= &amdgpu_invalid_wreg64
;
2898 adev
->uvd_ctx_rreg
= &amdgpu_invalid_rreg
;
2899 adev
->uvd_ctx_wreg
= &amdgpu_invalid_wreg
;
2900 adev
->didt_rreg
= &amdgpu_invalid_rreg
;
2901 adev
->didt_wreg
= &amdgpu_invalid_wreg
;
2902 adev
->gc_cac_rreg
= &amdgpu_invalid_rreg
;
2903 adev
->gc_cac_wreg
= &amdgpu_invalid_wreg
;
2904 adev
->audio_endpt_rreg
= &amdgpu_block_invalid_rreg
;
2905 adev
->audio_endpt_wreg
= &amdgpu_block_invalid_wreg
;
2907 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2908 amdgpu_asic_name
[adev
->asic_type
], pdev
->vendor
, pdev
->device
,
2909 pdev
->subsystem_vendor
, pdev
->subsystem_device
, pdev
->revision
);
2911 /* mutex initialization are all done here so we
2912 * can recall function without having locking issues */
2913 atomic_set(&adev
->irq
.ih
.lock
, 0);
2914 mutex_init(&adev
->firmware
.mutex
);
2915 mutex_init(&adev
->pm
.mutex
);
2916 mutex_init(&adev
->gfx
.gpu_clock_mutex
);
2917 mutex_init(&adev
->srbm_mutex
);
2918 mutex_init(&adev
->gfx
.pipe_reserve_mutex
);
2919 mutex_init(&adev
->gfx
.gfx_off_mutex
);
2920 mutex_init(&adev
->grbm_idx_mutex
);
2921 mutex_init(&adev
->mn_lock
);
2922 mutex_init(&adev
->virt
.vf_errors
.lock
);
2923 hash_init(adev
->mn_hash
);
2924 mutex_init(&adev
->lock_reset
);
2925 mutex_init(&adev
->psp
.mutex
);
2926 mutex_init(&adev
->notifier_lock
);
2928 r
= amdgpu_device_check_arguments(adev
);
2932 spin_lock_init(&adev
->mmio_idx_lock
);
2933 spin_lock_init(&adev
->smc_idx_lock
);
2934 spin_lock_init(&adev
->pcie_idx_lock
);
2935 spin_lock_init(&adev
->uvd_ctx_idx_lock
);
2936 spin_lock_init(&adev
->didt_idx_lock
);
2937 spin_lock_init(&adev
->gc_cac_idx_lock
);
2938 spin_lock_init(&adev
->se_cac_idx_lock
);
2939 spin_lock_init(&adev
->audio_endpt_idx_lock
);
2940 spin_lock_init(&adev
->mm_stats
.lock
);
2942 INIT_LIST_HEAD(&adev
->shadow_list
);
2943 mutex_init(&adev
->shadow_list_lock
);
2945 INIT_LIST_HEAD(&adev
->ring_lru_list
);
2946 spin_lock_init(&adev
->ring_lru_list_lock
);
2948 INIT_DELAYED_WORK(&adev
->delayed_init_work
,
2949 amdgpu_device_delayed_init_work_handler
);
2950 INIT_DELAYED_WORK(&adev
->gfx
.gfx_off_delay_work
,
2951 amdgpu_device_delay_enable_gfx_off
);
2953 INIT_WORK(&adev
->xgmi_reset_work
, amdgpu_device_xgmi_reset_func
);
2955 adev
->gfx
.gfx_off_req_count
= 1;
2956 adev
->pm
.ac_power
= power_supply_is_system_supplied() > 0 ? true : false;
2958 /* Registers mapping */
2959 /* TODO: block userspace mapping of io register */
2960 if (adev
->asic_type
>= CHIP_BONAIRE
) {
2961 adev
->rmmio_base
= pci_resource_start(adev
->pdev
, 5);
2962 adev
->rmmio_size
= pci_resource_len(adev
->pdev
, 5);
2964 adev
->rmmio_base
= pci_resource_start(adev
->pdev
, 2);
2965 adev
->rmmio_size
= pci_resource_len(adev
->pdev
, 2);
2968 adev
->rmmio
= ioremap(adev
->rmmio_base
, adev
->rmmio_size
);
2969 if (adev
->rmmio
== NULL
) {
2972 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev
->rmmio_base
);
2973 DRM_INFO("register mmio size: %u\n", (unsigned)adev
->rmmio_size
);
2975 /* io port mapping */
2976 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
2977 if (pci_resource_flags(adev
->pdev
, i
) & IORESOURCE_IO
) {
2978 adev
->rio_mem_size
= pci_resource_len(adev
->pdev
, i
);
2979 adev
->rio_mem
= pci_iomap(adev
->pdev
, i
, adev
->rio_mem_size
);
2983 if (adev
->rio_mem
== NULL
)
2984 DRM_INFO("PCI I/O BAR is not found.\n");
2986 /* enable PCIE atomic ops */
2987 r
= pci_enable_atomic_ops_to_root(adev
->pdev
,
2988 PCI_EXP_DEVCAP2_ATOMIC_COMP32
|
2989 PCI_EXP_DEVCAP2_ATOMIC_COMP64
);
2991 adev
->have_atomics_support
= false;
2992 DRM_INFO("PCIE atomic ops is not supported\n");
2994 adev
->have_atomics_support
= true;
2997 amdgpu_device_get_pcie_info(adev
);
3000 DRM_INFO("MCBP is enabled\n");
3002 if (amdgpu_mes
&& adev
->asic_type
>= CHIP_NAVI10
)
3003 adev
->enable_mes
= true;
3005 if (amdgpu_discovery
&& adev
->asic_type
>= CHIP_NAVI10
) {
3006 r
= amdgpu_discovery_init(adev
);
3008 dev_err(adev
->dev
, "amdgpu_discovery_init failed\n");
3013 /* early init functions */
3014 r
= amdgpu_device_ip_early_init(adev
);
3018 r
= amdgpu_device_get_job_timeout_settings(adev
);
3020 dev_err(adev
->dev
, "invalid lockup_timeout parameter syntax\n");
3024 /* doorbell bar mapping and doorbell index init*/
3025 amdgpu_device_doorbell_init(adev
);
3027 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3028 /* this will fail for cards that aren't VGA class devices, just
3030 vga_client_register(adev
->pdev
, adev
, NULL
, amdgpu_device_vga_set_decode
);
3032 if (amdgpu_device_supports_boco(ddev
))
3034 if (amdgpu_has_atpx() &&
3035 (amdgpu_is_atpx_hybrid() ||
3036 amdgpu_has_atpx_dgpu_power_cntl()) &&
3037 !pci_is_thunderbolt_attached(adev
->pdev
))
3038 vga_switcheroo_register_client(adev
->pdev
,
3039 &amdgpu_switcheroo_ops
, boco
);
3041 vga_switcheroo_init_domain_pm_ops(adev
->dev
, &adev
->vga_pm_domain
);
3043 if (amdgpu_emu_mode
== 1) {
3044 /* post the asic on emulation mode */
3045 emu_soc_asic_init(adev
);
3046 goto fence_driver_init
;
3049 /* detect if we are with an SRIOV vbios */
3050 amdgpu_device_detect_sriov_bios(adev
);
3052 /* check if we need to reset the asic
3053 * E.g., driver was not cleanly unloaded previously, etc.
3055 if (!amdgpu_sriov_vf(adev
) && amdgpu_asic_need_reset_on_init(adev
)) {
3056 r
= amdgpu_asic_reset(adev
);
3058 dev_err(adev
->dev
, "asic reset on init failed\n");
3063 /* Post card if necessary */
3064 if (amdgpu_device_need_post(adev
)) {
3066 dev_err(adev
->dev
, "no vBIOS found\n");
3070 DRM_INFO("GPU posting now...\n");
3071 r
= amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
3073 dev_err(adev
->dev
, "gpu post error!\n");
3078 if (adev
->is_atom_fw
) {
3079 /* Initialize clocks */
3080 r
= amdgpu_atomfirmware_get_clock_info(adev
);
3082 dev_err(adev
->dev
, "amdgpu_atomfirmware_get_clock_info failed\n");
3083 amdgpu_vf_error_put(adev
, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL
, 0, 0);
3087 /* Initialize clocks */
3088 r
= amdgpu_atombios_get_clock_info(adev
);
3090 dev_err(adev
->dev
, "amdgpu_atombios_get_clock_info failed\n");
3091 amdgpu_vf_error_put(adev
, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL
, 0, 0);
3094 /* init i2c buses */
3095 if (!amdgpu_device_has_dc_support(adev
))
3096 amdgpu_atombios_i2c_init(adev
);
3101 r
= amdgpu_fence_driver_init(adev
);
3103 dev_err(adev
->dev
, "amdgpu_fence_driver_init failed\n");
3104 amdgpu_vf_error_put(adev
, AMDGIM_ERROR_VF_FENCE_INIT_FAIL
, 0, 0);
3108 /* init the mode config */
3109 drm_mode_config_init(adev
->ddev
);
3111 r
= amdgpu_device_ip_init(adev
);
3113 /* failed in exclusive mode due to timeout */
3114 if (amdgpu_sriov_vf(adev
) &&
3115 !amdgpu_sriov_runtime(adev
) &&
3116 amdgpu_virt_mmio_blocked(adev
) &&
3117 !amdgpu_virt_wait_reset(adev
)) {
3118 dev_err(adev
->dev
, "VF exclusive mode timeout\n");
3119 /* Don't send request since VF is inactive. */
3120 adev
->virt
.caps
&= ~AMDGPU_SRIOV_CAPS_RUNTIME
;
3121 adev
->virt
.ops
= NULL
;
3125 dev_err(adev
->dev
, "amdgpu_device_ip_init failed\n");
3126 amdgpu_vf_error_put(adev
, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL
, 0, 0);
3130 DRM_DEBUG("SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3131 adev
->gfx
.config
.max_shader_engines
,
3132 adev
->gfx
.config
.max_sh_per_se
,
3133 adev
->gfx
.config
.max_cu_per_sh
,
3134 adev
->gfx
.cu_info
.number
);
3136 amdgpu_ctx_init_sched(adev
);
3138 adev
->accel_working
= true;
3140 amdgpu_vm_check_compute_bug(adev
);
3142 /* Initialize the buffer migration limit. */
3143 if (amdgpu_moverate
>= 0)
3144 max_MBps
= amdgpu_moverate
;
3146 max_MBps
= 8; /* Allow 8 MB/s. */
3147 /* Get a log2 for easy divisions. */
3148 adev
->mm_stats
.log2_max_MBps
= ilog2(max(1u, max_MBps
));
3150 amdgpu_fbdev_init(adev
);
3152 r
= amdgpu_pm_sysfs_init(adev
);
3154 adev
->pm_sysfs_en
= false;
3155 DRM_ERROR("registering pm debugfs failed (%d).\n", r
);
3157 adev
->pm_sysfs_en
= true;
3159 r
= amdgpu_ucode_sysfs_init(adev
);
3161 adev
->ucode_sysfs_en
= false;
3162 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r
);
3164 adev
->ucode_sysfs_en
= true;
3166 if ((amdgpu_testing
& 1)) {
3167 if (adev
->accel_working
)
3168 amdgpu_test_moves(adev
);
3170 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
3172 if (amdgpu_benchmarking
) {
3173 if (adev
->accel_working
)
3174 amdgpu_benchmark(adev
, amdgpu_benchmarking
);
3176 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
3180 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3181 * Otherwise the mgpu fan boost feature will be skipped due to the
3182 * gpu instance is counted less.
3184 amdgpu_register_gpu_instance(adev
);
3186 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3187 * explicit gating rather than handling it automatically.
3189 r
= amdgpu_device_ip_late_init(adev
);
3191 dev_err(adev
->dev
, "amdgpu_device_ip_late_init failed\n");
3192 amdgpu_vf_error_put(adev
, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL
, 0, r
);
3197 amdgpu_ras_resume(adev
);
3199 queue_delayed_work(system_wq
, &adev
->delayed_init_work
,
3200 msecs_to_jiffies(AMDGPU_RESUME_MS
));
3202 r
= device_create_file(adev
->dev
, &dev_attr_pcie_replay_count
);
3204 dev_err(adev
->dev
, "Could not create pcie_replay_count");
3208 if (IS_ENABLED(CONFIG_PERF_EVENTS
))
3209 r
= amdgpu_pmu_init(adev
);
3211 dev_err(adev
->dev
, "amdgpu_pmu_init failed\n");
3216 amdgpu_vf_error_trans_all(adev
);
3218 vga_switcheroo_fini_domain_pm_ops(adev
->dev
);
3224 * amdgpu_device_fini - tear down the driver
3226 * @adev: amdgpu_device pointer
3228 * Tear down the driver info (all asics).
3229 * Called at driver shutdown.
3231 void amdgpu_device_fini(struct amdgpu_device
*adev
)
3235 DRM_INFO("amdgpu: finishing device.\n");
3236 flush_delayed_work(&adev
->delayed_init_work
);
3237 adev
->shutdown
= true;
3239 /* make sure IB test finished before entering exclusive mode
3240 * to avoid preemption on IB test
3242 if (amdgpu_sriov_vf(adev
))
3243 amdgpu_virt_request_full_gpu(adev
, false);
3245 /* disable all interrupts */
3246 amdgpu_irq_disable_all(adev
);
3247 if (adev
->mode_info
.mode_config_initialized
){
3248 if (!amdgpu_device_has_dc_support(adev
))
3249 drm_helper_force_disable_all(adev
->ddev
);
3251 drm_atomic_helper_shutdown(adev
->ddev
);
3253 amdgpu_fence_driver_fini(adev
);
3254 if (adev
->pm_sysfs_en
)
3255 amdgpu_pm_sysfs_fini(adev
);
3256 amdgpu_fbdev_fini(adev
);
3257 r
= amdgpu_device_ip_fini(adev
);
3258 if (adev
->firmware
.gpu_info_fw
) {
3259 release_firmware(adev
->firmware
.gpu_info_fw
);
3260 adev
->firmware
.gpu_info_fw
= NULL
;
3262 adev
->accel_working
= false;
3263 /* free i2c buses */
3264 if (!amdgpu_device_has_dc_support(adev
))
3265 amdgpu_i2c_fini(adev
);
3267 if (amdgpu_emu_mode
!= 1)
3268 amdgpu_atombios_fini(adev
);
3272 if (amdgpu_has_atpx() &&
3273 (amdgpu_is_atpx_hybrid() ||
3274 amdgpu_has_atpx_dgpu_power_cntl()) &&
3275 !pci_is_thunderbolt_attached(adev
->pdev
))
3276 vga_switcheroo_unregister_client(adev
->pdev
);
3277 if (amdgpu_device_supports_boco(adev
->ddev
))
3278 vga_switcheroo_fini_domain_pm_ops(adev
->dev
);
3279 vga_client_register(adev
->pdev
, NULL
, NULL
, NULL
);
3281 pci_iounmap(adev
->pdev
, adev
->rio_mem
);
3282 adev
->rio_mem
= NULL
;
3283 iounmap(adev
->rmmio
);
3285 amdgpu_device_doorbell_fini(adev
);
3287 device_remove_file(adev
->dev
, &dev_attr_pcie_replay_count
);
3288 if (adev
->ucode_sysfs_en
)
3289 amdgpu_ucode_sysfs_fini(adev
);
3290 if (IS_ENABLED(CONFIG_PERF_EVENTS
))
3291 amdgpu_pmu_fini(adev
);
3292 if (amdgpu_discovery
&& adev
->asic_type
>= CHIP_NAVI10
)
3293 amdgpu_discovery_fini(adev
);
3301 * amdgpu_device_suspend - initiate device suspend
3303 * @dev: drm dev pointer
3304 * @suspend: suspend state
3305 * @fbcon : notify the fbdev of suspend
3307 * Puts the hw in the suspend state (all asics).
3308 * Returns 0 for success or an error on failure.
3309 * Called at driver suspend.
3311 int amdgpu_device_suspend(struct drm_device
*dev
, bool fbcon
)
3313 struct amdgpu_device
*adev
;
3314 struct drm_crtc
*crtc
;
3315 struct drm_connector
*connector
;
3316 struct drm_connector_list_iter iter
;
3319 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
3323 adev
= dev
->dev_private
;
3325 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
3328 adev
->in_suspend
= true;
3329 drm_kms_helper_poll_disable(dev
);
3332 amdgpu_fbdev_set_suspend(adev
, 1);
3334 cancel_delayed_work_sync(&adev
->delayed_init_work
);
3336 if (!amdgpu_device_has_dc_support(adev
)) {
3337 /* turn off display hw */
3338 drm_modeset_lock_all(dev
);
3339 drm_connector_list_iter_begin(dev
, &iter
);
3340 drm_for_each_connector_iter(connector
, &iter
)
3341 drm_helper_connector_dpms(connector
,
3343 drm_connector_list_iter_end(&iter
);
3344 drm_modeset_unlock_all(dev
);
3345 /* unpin the front buffers and cursors */
3346 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3347 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
3348 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
3349 struct amdgpu_bo
*robj
;
3351 if (amdgpu_crtc
->cursor_bo
&& !adev
->enable_virtual_display
) {
3352 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
3353 r
= amdgpu_bo_reserve(aobj
, true);
3355 amdgpu_bo_unpin(aobj
);
3356 amdgpu_bo_unreserve(aobj
);
3360 if (fb
== NULL
|| fb
->obj
[0] == NULL
) {
3363 robj
= gem_to_amdgpu_bo(fb
->obj
[0]);
3364 /* don't unpin kernel fb objects */
3365 if (!amdgpu_fbdev_robj_is_fb(adev
, robj
)) {
3366 r
= amdgpu_bo_reserve(robj
, true);
3368 amdgpu_bo_unpin(robj
);
3369 amdgpu_bo_unreserve(robj
);
3375 amdgpu_device_set_pg_state(adev
, AMD_PG_STATE_UNGATE
);
3376 amdgpu_device_set_cg_state(adev
, AMD_CG_STATE_UNGATE
);
3378 amdgpu_amdkfd_suspend(adev
, !fbcon
);
3380 amdgpu_ras_suspend(adev
);
3382 r
= amdgpu_device_ip_suspend_phase1(adev
);
3384 /* evict vram memory */
3385 amdgpu_bo_evict_vram(adev
);
3387 amdgpu_fence_driver_suspend(adev
);
3389 r
= amdgpu_device_ip_suspend_phase2(adev
);
3391 /* evict remaining vram memory
3392 * This second call to evict vram is to evict the gart page table
3395 amdgpu_bo_evict_vram(adev
);
3401 * amdgpu_device_resume - initiate device resume
3403 * @dev: drm dev pointer
3404 * @resume: resume state
3405 * @fbcon : notify the fbdev of resume
3407 * Bring the hw back to operating state (all asics).
3408 * Returns 0 for success or an error on failure.
3409 * Called at driver resume.
3411 int amdgpu_device_resume(struct drm_device
*dev
, bool fbcon
)
3413 struct drm_connector
*connector
;
3414 struct drm_connector_list_iter iter
;
3415 struct amdgpu_device
*adev
= dev
->dev_private
;
3416 struct drm_crtc
*crtc
;
3419 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
3423 if (amdgpu_device_need_post(adev
)) {
3424 r
= amdgpu_atom_asic_init(adev
->mode_info
.atom_context
);
3426 DRM_ERROR("amdgpu asic init failed\n");
3429 r
= amdgpu_device_ip_resume(adev
);
3431 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r
);
3434 amdgpu_fence_driver_resume(adev
);
3437 r
= amdgpu_device_ip_late_init(adev
);
3441 queue_delayed_work(system_wq
, &adev
->delayed_init_work
,
3442 msecs_to_jiffies(AMDGPU_RESUME_MS
));
3444 if (!amdgpu_device_has_dc_support(adev
)) {
3446 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3447 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
3449 if (amdgpu_crtc
->cursor_bo
&& !adev
->enable_virtual_display
) {
3450 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
3451 r
= amdgpu_bo_reserve(aobj
, true);
3453 r
= amdgpu_bo_pin(aobj
, AMDGPU_GEM_DOMAIN_VRAM
);
3455 DRM_ERROR("Failed to pin cursor BO (%d)\n", r
);
3456 amdgpu_crtc
->cursor_addr
= amdgpu_bo_gpu_offset(aobj
);
3457 amdgpu_bo_unreserve(aobj
);
3462 r
= amdgpu_amdkfd_resume(adev
, !fbcon
);
3466 /* Make sure IB tests flushed */
3467 flush_delayed_work(&adev
->delayed_init_work
);
3469 /* blat the mode back in */
3471 if (!amdgpu_device_has_dc_support(adev
)) {
3473 drm_helper_resume_force_mode(dev
);
3475 /* turn on display hw */
3476 drm_modeset_lock_all(dev
);
3478 drm_connector_list_iter_begin(dev
, &iter
);
3479 drm_for_each_connector_iter(connector
, &iter
)
3480 drm_helper_connector_dpms(connector
,
3482 drm_connector_list_iter_end(&iter
);
3484 drm_modeset_unlock_all(dev
);
3486 amdgpu_fbdev_set_suspend(adev
, 0);
3489 drm_kms_helper_poll_enable(dev
);
3491 amdgpu_ras_resume(adev
);
3494 * Most of the connector probing functions try to acquire runtime pm
3495 * refs to ensure that the GPU is powered on when connector polling is
3496 * performed. Since we're calling this from a runtime PM callback,
3497 * trying to acquire rpm refs will cause us to deadlock.
3499 * Since we're guaranteed to be holding the rpm lock, it's safe to
3500 * temporarily disable the rpm helpers so this doesn't deadlock us.
3503 dev
->dev
->power
.disable_depth
++;
3505 if (!amdgpu_device_has_dc_support(adev
))
3506 drm_helper_hpd_irq_event(dev
);
3508 drm_kms_helper_hotplug_event(dev
);
3510 dev
->dev
->power
.disable_depth
--;
3512 adev
->in_suspend
= false;
3518 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3520 * @adev: amdgpu_device pointer
3522 * The list of all the hardware IPs that make up the asic is walked and
3523 * the check_soft_reset callbacks are run. check_soft_reset determines
3524 * if the asic is still hung or not.
3525 * Returns true if any of the IPs are still in a hung state, false if not.
3527 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device
*adev
)
3530 bool asic_hang
= false;
3532 if (amdgpu_sriov_vf(adev
))
3535 if (amdgpu_asic_need_full_reset(adev
))
3538 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
3539 if (!adev
->ip_blocks
[i
].status
.valid
)
3541 if (adev
->ip_blocks
[i
].version
->funcs
->check_soft_reset
)
3542 adev
->ip_blocks
[i
].status
.hang
=
3543 adev
->ip_blocks
[i
].version
->funcs
->check_soft_reset(adev
);
3544 if (adev
->ip_blocks
[i
].status
.hang
) {
3545 DRM_INFO("IP block:%s is hung!\n", adev
->ip_blocks
[i
].version
->funcs
->name
);
3553 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3555 * @adev: amdgpu_device pointer
3557 * The list of all the hardware IPs that make up the asic is walked and the
3558 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3559 * handles any IP specific hardware or software state changes that are
3560 * necessary for a soft reset to succeed.
3561 * Returns 0 on success, negative error code on failure.
3563 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device
*adev
)
3567 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
3568 if (!adev
->ip_blocks
[i
].status
.valid
)
3570 if (adev
->ip_blocks
[i
].status
.hang
&&
3571 adev
->ip_blocks
[i
].version
->funcs
->pre_soft_reset
) {
3572 r
= adev
->ip_blocks
[i
].version
->funcs
->pre_soft_reset(adev
);
3582 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3584 * @adev: amdgpu_device pointer
3586 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3587 * reset is necessary to recover.
3588 * Returns true if a full asic reset is required, false if not.
3590 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device
*adev
)
3594 if (amdgpu_asic_need_full_reset(adev
))
3597 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
3598 if (!adev
->ip_blocks
[i
].status
.valid
)
3600 if ((adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_GMC
) ||
3601 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_SMC
) ||
3602 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_ACP
) ||
3603 (adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_DCE
) ||
3604 adev
->ip_blocks
[i
].version
->type
== AMD_IP_BLOCK_TYPE_PSP
) {
3605 if (adev
->ip_blocks
[i
].status
.hang
) {
3606 DRM_INFO("Some block need full reset!\n");
3615 * amdgpu_device_ip_soft_reset - do a soft reset
3617 * @adev: amdgpu_device pointer
3619 * The list of all the hardware IPs that make up the asic is walked and the
3620 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3621 * IP specific hardware or software state changes that are necessary to soft
3623 * Returns 0 on success, negative error code on failure.
3625 static int amdgpu_device_ip_soft_reset(struct amdgpu_device
*adev
)
3629 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
3630 if (!adev
->ip_blocks
[i
].status
.valid
)
3632 if (adev
->ip_blocks
[i
].status
.hang
&&
3633 adev
->ip_blocks
[i
].version
->funcs
->soft_reset
) {
3634 r
= adev
->ip_blocks
[i
].version
->funcs
->soft_reset(adev
);
3644 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3646 * @adev: amdgpu_device pointer
3648 * The list of all the hardware IPs that make up the asic is walked and the
3649 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
3650 * handles any IP specific hardware or software state changes that are
3651 * necessary after the IP has been soft reset.
3652 * Returns 0 on success, negative error code on failure.
3654 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device
*adev
)
3658 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
3659 if (!adev
->ip_blocks
[i
].status
.valid
)
3661 if (adev
->ip_blocks
[i
].status
.hang
&&
3662 adev
->ip_blocks
[i
].version
->funcs
->post_soft_reset
)
3663 r
= adev
->ip_blocks
[i
].version
->funcs
->post_soft_reset(adev
);
3672 * amdgpu_device_recover_vram - Recover some VRAM contents
3674 * @adev: amdgpu_device pointer
3676 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
3677 * restore things like GPUVM page tables after a GPU reset where
3678 * the contents of VRAM might be lost.
3681 * 0 on success, negative error code on failure.
3683 static int amdgpu_device_recover_vram(struct amdgpu_device
*adev
)
3685 struct dma_fence
*fence
= NULL
, *next
= NULL
;
3686 struct amdgpu_bo
*shadow
;
3689 if (amdgpu_sriov_runtime(adev
))
3690 tmo
= msecs_to_jiffies(8000);
3692 tmo
= msecs_to_jiffies(100);
3694 DRM_INFO("recover vram bo from shadow start\n");
3695 mutex_lock(&adev
->shadow_list_lock
);
3696 list_for_each_entry(shadow
, &adev
->shadow_list
, shadow_list
) {
3698 /* No need to recover an evicted BO */
3699 if (shadow
->tbo
.mem
.mem_type
!= TTM_PL_TT
||
3700 shadow
->tbo
.mem
.start
== AMDGPU_BO_INVALID_OFFSET
||
3701 shadow
->parent
->tbo
.mem
.mem_type
!= TTM_PL_VRAM
)
3704 r
= amdgpu_bo_restore_shadow(shadow
, &next
);
3709 tmo
= dma_fence_wait_timeout(fence
, false, tmo
);
3710 dma_fence_put(fence
);
3715 } else if (tmo
< 0) {
3723 mutex_unlock(&adev
->shadow_list_lock
);
3726 tmo
= dma_fence_wait_timeout(fence
, false, tmo
);
3727 dma_fence_put(fence
);
3729 if (r
< 0 || tmo
<= 0) {
3730 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r
, tmo
);
3734 DRM_INFO("recover vram bo from shadow done\n");
3740 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3742 * @adev: amdgpu device pointer
3743 * @from_hypervisor: request from hypervisor
3745 * do VF FLR and reinitialize Asic
3746 * return 0 means succeeded otherwise failed
3748 static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev
,
3749 bool from_hypervisor
)
3753 if (from_hypervisor
)
3754 r
= amdgpu_virt_request_full_gpu(adev
, true);
3756 r
= amdgpu_virt_reset_gpu(adev
);
3760 /* Resume IP prior to SMC */
3761 r
= amdgpu_device_ip_reinit_early_sriov(adev
);
3765 amdgpu_virt_init_data_exchange(adev
);
3766 /* we need recover gart prior to run SMC/CP/SDMA resume */
3767 amdgpu_gtt_mgr_recover(&adev
->mman
.bdev
.man
[TTM_PL_TT
]);
3769 r
= amdgpu_device_fw_loading(adev
);
3773 /* now we are okay to resume SMC/CP/SDMA */
3774 r
= amdgpu_device_ip_reinit_late_sriov(adev
);
3778 amdgpu_irq_gpu_reset_resume_helper(adev
);
3779 r
= amdgpu_ib_ring_tests(adev
);
3780 amdgpu_amdkfd_post_reset(adev
);
3783 amdgpu_virt_release_full_gpu(adev
, true);
3784 if (!r
&& adev
->virt
.gim_feature
& AMDGIM_FEATURE_GIM_FLR_VRAMLOST
) {
3785 amdgpu_inc_vram_lost(adev
);
3786 r
= amdgpu_device_recover_vram(adev
);
3793 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3795 * @adev: amdgpu device pointer
3797 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3800 bool amdgpu_device_should_recover_gpu(struct amdgpu_device
*adev
)
3802 if (!amdgpu_device_ip_check_soft_reset(adev
)) {
3803 DRM_INFO("Timeout, but no hardware hang detected.\n");
3807 if (amdgpu_gpu_recovery
== 0)
3810 if (amdgpu_sriov_vf(adev
))
3813 if (amdgpu_gpu_recovery
== -1) {
3814 switch (adev
->asic_type
) {
3820 case CHIP_POLARIS10
:
3821 case CHIP_POLARIS11
:
3822 case CHIP_POLARIS12
:
3842 DRM_INFO("GPU recovery disabled.\n");
3847 static int amdgpu_device_pre_asic_reset(struct amdgpu_device
*adev
,
3848 struct amdgpu_job
*job
,
3849 bool *need_full_reset_arg
)
3852 bool need_full_reset
= *need_full_reset_arg
;
3854 /* block all schedulers and reset given job's ring */
3855 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
3856 struct amdgpu_ring
*ring
= adev
->rings
[i
];
3858 if (!ring
|| !ring
->sched
.thread
)
3861 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3862 amdgpu_fence_driver_force_completion(ring
);
3866 drm_sched_increase_karma(&job
->base
);
3868 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
3869 if (!amdgpu_sriov_vf(adev
)) {
3871 if (!need_full_reset
)
3872 need_full_reset
= amdgpu_device_ip_need_full_reset(adev
);
3874 if (!need_full_reset
) {
3875 amdgpu_device_ip_pre_soft_reset(adev
);
3876 r
= amdgpu_device_ip_soft_reset(adev
);
3877 amdgpu_device_ip_post_soft_reset(adev
);
3878 if (r
|| amdgpu_device_ip_check_soft_reset(adev
)) {
3879 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3880 need_full_reset
= true;
3884 if (need_full_reset
)
3885 r
= amdgpu_device_ip_suspend(adev
);
3887 *need_full_reset_arg
= need_full_reset
;
3893 static int amdgpu_do_asic_reset(struct amdgpu_hive_info
*hive
,
3894 struct list_head
*device_list_handle
,
3895 bool *need_full_reset_arg
)
3897 struct amdgpu_device
*tmp_adev
= NULL
;
3898 bool need_full_reset
= *need_full_reset_arg
, vram_lost
= false;
3902 * ASIC reset has to be done on all HGMI hive nodes ASAP
3903 * to allow proper links negotiation in FW (within 1 sec)
3905 if (need_full_reset
) {
3906 list_for_each_entry(tmp_adev
, device_list_handle
, gmc
.xgmi
.head
) {
3907 /* For XGMI run all resets in parallel to speed up the process */
3908 if (tmp_adev
->gmc
.xgmi
.num_physical_nodes
> 1) {
3909 if (!queue_work(system_unbound_wq
, &tmp_adev
->xgmi_reset_work
))
3912 r
= amdgpu_asic_reset(tmp_adev
);
3915 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3916 r
, tmp_adev
->ddev
->unique
);
3921 /* For XGMI wait for all resets to complete before proceed */
3923 list_for_each_entry(tmp_adev
, device_list_handle
,
3925 if (tmp_adev
->gmc
.xgmi
.num_physical_nodes
> 1) {
3926 flush_work(&tmp_adev
->xgmi_reset_work
);
3927 r
= tmp_adev
->asic_reset_res
;
3935 if (!r
&& amdgpu_ras_intr_triggered()) {
3936 list_for_each_entry(tmp_adev
, device_list_handle
, gmc
.xgmi
.head
) {
3937 if (tmp_adev
->mmhub
.funcs
&&
3938 tmp_adev
->mmhub
.funcs
->reset_ras_error_count
)
3939 tmp_adev
->mmhub
.funcs
->reset_ras_error_count(tmp_adev
);
3942 amdgpu_ras_intr_cleared();
3945 list_for_each_entry(tmp_adev
, device_list_handle
, gmc
.xgmi
.head
) {
3946 if (need_full_reset
) {
3948 if (amdgpu_atom_asic_init(tmp_adev
->mode_info
.atom_context
))
3949 DRM_WARN("asic atom init failed!");
3952 dev_info(tmp_adev
->dev
, "GPU reset succeeded, trying to resume\n");
3953 r
= amdgpu_device_ip_resume_phase1(tmp_adev
);
3957 vram_lost
= amdgpu_device_check_vram_lost(tmp_adev
);
3959 DRM_INFO("VRAM is lost due to GPU reset!\n");
3960 amdgpu_inc_vram_lost(tmp_adev
);
3963 r
= amdgpu_gtt_mgr_recover(
3964 &tmp_adev
->mman
.bdev
.man
[TTM_PL_TT
]);
3968 r
= amdgpu_device_fw_loading(tmp_adev
);
3972 r
= amdgpu_device_ip_resume_phase2(tmp_adev
);
3977 amdgpu_device_fill_reset_magic(tmp_adev
);
3980 * Add this ASIC as tracked as reset was already
3981 * complete successfully.
3983 amdgpu_register_gpu_instance(tmp_adev
);
3985 r
= amdgpu_device_ip_late_init(tmp_adev
);
3989 amdgpu_fbdev_set_suspend(tmp_adev
, 0);
3992 amdgpu_ras_resume(tmp_adev
);
3994 /* Update PSP FW topology after reset */
3995 if (hive
&& tmp_adev
->gmc
.xgmi
.num_physical_nodes
> 1)
3996 r
= amdgpu_xgmi_update_topology(hive
, tmp_adev
);
4003 amdgpu_irq_gpu_reset_resume_helper(tmp_adev
);
4004 r
= amdgpu_ib_ring_tests(tmp_adev
);
4006 dev_err(tmp_adev
->dev
, "ib ring test failed (%d).\n", r
);
4007 r
= amdgpu_device_ip_suspend(tmp_adev
);
4008 need_full_reset
= true;
4015 r
= amdgpu_device_recover_vram(tmp_adev
);
4017 tmp_adev
->asic_reset_res
= r
;
4021 *need_full_reset_arg
= need_full_reset
;
4025 static bool amdgpu_device_lock_adev(struct amdgpu_device
*adev
, bool trylock
)
4028 if (!mutex_trylock(&adev
->lock_reset
))
4031 mutex_lock(&adev
->lock_reset
);
4033 atomic_inc(&adev
->gpu_reset_counter
);
4034 adev
->in_gpu_reset
= true;
4035 switch (amdgpu_asic_reset_method(adev
)) {
4036 case AMD_RESET_METHOD_MODE1
:
4037 adev
->mp1_state
= PP_MP1_STATE_SHUTDOWN
;
4039 case AMD_RESET_METHOD_MODE2
:
4040 adev
->mp1_state
= PP_MP1_STATE_RESET
;
4043 adev
->mp1_state
= PP_MP1_STATE_NONE
;
4050 static void amdgpu_device_unlock_adev(struct amdgpu_device
*adev
)
4052 amdgpu_vf_error_trans_all(adev
);
4053 adev
->mp1_state
= PP_MP1_STATE_NONE
;
4054 adev
->in_gpu_reset
= false;
4055 mutex_unlock(&adev
->lock_reset
);
4059 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
4061 * @adev: amdgpu device pointer
4062 * @job: which job trigger hang
4064 * Attempt to reset the GPU if it has hung (all asics).
4065 * Attempt to do soft-reset or full-reset and reinitialize Asic
4066 * Returns 0 for success or an error on failure.
4069 int amdgpu_device_gpu_recover(struct amdgpu_device
*adev
,
4070 struct amdgpu_job
*job
)
4072 struct list_head device_list
, *device_list_handle
= NULL
;
4073 bool need_full_reset
, job_signaled
;
4074 struct amdgpu_hive_info
*hive
= NULL
;
4075 struct amdgpu_device
*tmp_adev
= NULL
;
4077 bool in_ras_intr
= amdgpu_ras_intr_triggered();
4079 (amdgpu_asic_reset_method(adev
) == AMD_RESET_METHOD_BACO
) ?
4083 * Flush RAM to disk so that after reboot
4084 * the user can read log and see why the system rebooted.
4086 if (in_ras_intr
&& !use_baco
&& amdgpu_ras_get_context(adev
)->reboot
) {
4088 DRM_WARN("Emergency reboot.");
4091 emergency_restart();
4094 need_full_reset
= job_signaled
= false;
4095 INIT_LIST_HEAD(&device_list
);
4097 dev_info(adev
->dev
, "GPU %s begin!\n",
4098 (in_ras_intr
&& !use_baco
) ? "jobs stop":"reset");
4100 cancel_delayed_work_sync(&adev
->delayed_init_work
);
4102 hive
= amdgpu_get_xgmi_hive(adev
, false);
4105 * Here we trylock to avoid chain of resets executing from
4106 * either trigger by jobs on different adevs in XGMI hive or jobs on
4107 * different schedulers for same device while this TO handler is running.
4108 * We always reset all schedulers for device and all devices for XGMI
4109 * hive so that should take care of them too.
4112 if (hive
&& !mutex_trylock(&hive
->reset_lock
)) {
4113 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
4114 job
? job
->base
.id
: -1, hive
->hive_id
);
4118 /* Start with adev pre asic reset first for soft reset check.*/
4119 if (!amdgpu_device_lock_adev(adev
, !hive
)) {
4120 DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
4121 job
? job
->base
.id
: -1);
4125 /* Block kfd: SRIOV would do it separately */
4126 if (!amdgpu_sriov_vf(adev
))
4127 amdgpu_amdkfd_pre_reset(adev
);
4129 /* Build list of devices to reset */
4130 if (adev
->gmc
.xgmi
.num_physical_nodes
> 1) {
4132 /*unlock kfd: SRIOV would do it separately */
4133 if (!amdgpu_sriov_vf(adev
))
4134 amdgpu_amdkfd_post_reset(adev
);
4135 amdgpu_device_unlock_adev(adev
);
4140 * In case we are in XGMI hive mode device reset is done for all the
4141 * nodes in the hive to retrain all XGMI links and hence the reset
4142 * sequence is executed in loop on all nodes.
4144 device_list_handle
= &hive
->device_list
;
4146 list_add_tail(&adev
->gmc
.xgmi
.head
, &device_list
);
4147 device_list_handle
= &device_list
;
4150 /* block all schedulers and reset given job's ring */
4151 list_for_each_entry(tmp_adev
, device_list_handle
, gmc
.xgmi
.head
) {
4152 if (tmp_adev
!= adev
) {
4153 amdgpu_device_lock_adev(tmp_adev
, false);
4154 if (!amdgpu_sriov_vf(tmp_adev
))
4155 amdgpu_amdkfd_pre_reset(tmp_adev
);
4159 * Mark these ASICs to be reseted as untracked first
4160 * And add them back after reset completed
4162 amdgpu_unregister_gpu_instance(tmp_adev
);
4164 amdgpu_fbdev_set_suspend(adev
, 1);
4166 /* disable ras on ALL IPs */
4167 if (!(in_ras_intr
&& !use_baco
) &&
4168 amdgpu_device_ip_need_full_reset(tmp_adev
))
4169 amdgpu_ras_suspend(tmp_adev
);
4171 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
4172 struct amdgpu_ring
*ring
= tmp_adev
->rings
[i
];
4174 if (!ring
|| !ring
->sched
.thread
)
4177 drm_sched_stop(&ring
->sched
, job
? &job
->base
: NULL
);
4179 if (in_ras_intr
&& !use_baco
)
4180 amdgpu_job_stop_all_jobs_on_sched(&ring
->sched
);
4185 if (in_ras_intr
&& !use_baco
)
4186 goto skip_sched_resume
;
4189 * Must check guilty signal here since after this point all old
4190 * HW fences are force signaled.
4192 * job->base holds a reference to parent fence
4194 if (job
&& job
->base
.s_fence
->parent
&&
4195 dma_fence_is_signaled(job
->base
.s_fence
->parent
))
4196 job_signaled
= true;
4199 dev_info(adev
->dev
, "Guilty job already signaled, skipping HW reset");
4204 /* Guilty job will be freed after this*/
4205 r
= amdgpu_device_pre_asic_reset(adev
, job
, &need_full_reset
);
4207 /*TODO Should we stop ?*/
4208 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
4209 r
, adev
->ddev
->unique
);
4210 adev
->asic_reset_res
= r
;
4213 retry
: /* Rest of adevs pre asic reset from XGMI hive. */
4214 list_for_each_entry(tmp_adev
, device_list_handle
, gmc
.xgmi
.head
) {
4216 if (tmp_adev
== adev
)
4219 r
= amdgpu_device_pre_asic_reset(tmp_adev
,
4222 /*TODO Should we stop ?*/
4224 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
4225 r
, tmp_adev
->ddev
->unique
);
4226 tmp_adev
->asic_reset_res
= r
;
4230 /* Actual ASIC resets if needed.*/
4231 /* TODO Implement XGMI hive reset logic for SRIOV */
4232 if (amdgpu_sriov_vf(adev
)) {
4233 r
= amdgpu_device_reset_sriov(adev
, job
? false : true);
4235 adev
->asic_reset_res
= r
;
4237 r
= amdgpu_do_asic_reset(hive
, device_list_handle
, &need_full_reset
);
4238 if (r
&& r
== -EAGAIN
)
4244 /* Post ASIC reset for all devs .*/
4245 list_for_each_entry(tmp_adev
, device_list_handle
, gmc
.xgmi
.head
) {
4247 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
4248 struct amdgpu_ring
*ring
= tmp_adev
->rings
[i
];
4250 if (!ring
|| !ring
->sched
.thread
)
4253 /* No point to resubmit jobs if we didn't HW reset*/
4254 if (!tmp_adev
->asic_reset_res
&& !job_signaled
)
4255 drm_sched_resubmit_jobs(&ring
->sched
);
4257 drm_sched_start(&ring
->sched
, !tmp_adev
->asic_reset_res
);
4260 if (!amdgpu_device_has_dc_support(tmp_adev
) && !job_signaled
) {
4261 drm_helper_resume_force_mode(tmp_adev
->ddev
);
4264 tmp_adev
->asic_reset_res
= 0;
4267 /* bad news, how to tell it to userspace ? */
4268 dev_info(tmp_adev
->dev
, "GPU reset(%d) failed\n", atomic_read(&tmp_adev
->gpu_reset_counter
));
4269 amdgpu_vf_error_put(tmp_adev
, AMDGIM_ERROR_VF_GPU_RESET_FAIL
, 0, r
);
4271 dev_info(tmp_adev
->dev
, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev
->gpu_reset_counter
));
4276 list_for_each_entry(tmp_adev
, device_list_handle
, gmc
.xgmi
.head
) {
4277 /*unlock kfd: SRIOV would do it separately */
4278 if (!(in_ras_intr
&& !use_baco
) && !amdgpu_sriov_vf(tmp_adev
))
4279 amdgpu_amdkfd_post_reset(tmp_adev
);
4280 amdgpu_device_unlock_adev(tmp_adev
);
4284 mutex_unlock(&hive
->reset_lock
);
4287 dev_info(adev
->dev
, "GPU reset end with ret = %d\n", r
);
4292 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
4294 * @adev: amdgpu_device pointer
4296 * Fetchs and stores in the driver the PCIE capabilities (gen speed
4297 * and lanes) of the slot the device is in. Handles APUs and
4298 * virtualized environments where PCIE config space may not be available.
4300 static void amdgpu_device_get_pcie_info(struct amdgpu_device
*adev
)
4302 struct pci_dev
*pdev
;
4303 enum pci_bus_speed speed_cap
, platform_speed_cap
;
4304 enum pcie_link_width platform_link_width
;
4306 if (amdgpu_pcie_gen_cap
)
4307 adev
->pm
.pcie_gen_mask
= amdgpu_pcie_gen_cap
;
4309 if (amdgpu_pcie_lane_cap
)
4310 adev
->pm
.pcie_mlw_mask
= amdgpu_pcie_lane_cap
;
4312 /* covers APUs as well */
4313 if (pci_is_root_bus(adev
->pdev
->bus
)) {
4314 if (adev
->pm
.pcie_gen_mask
== 0)
4315 adev
->pm
.pcie_gen_mask
= AMDGPU_DEFAULT_PCIE_GEN_MASK
;
4316 if (adev
->pm
.pcie_mlw_mask
== 0)
4317 adev
->pm
.pcie_mlw_mask
= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
4321 if (adev
->pm
.pcie_gen_mask
&& adev
->pm
.pcie_mlw_mask
)
4324 pcie_bandwidth_available(adev
->pdev
, NULL
,
4325 &platform_speed_cap
, &platform_link_width
);
4327 if (adev
->pm
.pcie_gen_mask
== 0) {
4330 speed_cap
= pcie_get_speed_cap(pdev
);
4331 if (speed_cap
== PCI_SPEED_UNKNOWN
) {
4332 adev
->pm
.pcie_gen_mask
|= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1
|
4333 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2
|
4334 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3
);
4336 if (speed_cap
== PCIE_SPEED_16_0GT
)
4337 adev
->pm
.pcie_gen_mask
|= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1
|
4338 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2
|
4339 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3
|
4340 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4
);
4341 else if (speed_cap
== PCIE_SPEED_8_0GT
)
4342 adev
->pm
.pcie_gen_mask
|= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1
|
4343 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2
|
4344 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3
);
4345 else if (speed_cap
== PCIE_SPEED_5_0GT
)
4346 adev
->pm
.pcie_gen_mask
|= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1
|
4347 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2
);
4349 adev
->pm
.pcie_gen_mask
|= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1
;
4352 if (platform_speed_cap
== PCI_SPEED_UNKNOWN
) {
4353 adev
->pm
.pcie_gen_mask
|= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1
|
4354 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
);
4356 if (platform_speed_cap
== PCIE_SPEED_16_0GT
)
4357 adev
->pm
.pcie_gen_mask
|= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1
|
4358 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
|
4359 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
|
4360 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4
);
4361 else if (platform_speed_cap
== PCIE_SPEED_8_0GT
)
4362 adev
->pm
.pcie_gen_mask
|= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1
|
4363 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
|
4364 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
);
4365 else if (platform_speed_cap
== PCIE_SPEED_5_0GT
)
4366 adev
->pm
.pcie_gen_mask
|= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1
|
4367 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
);
4369 adev
->pm
.pcie_gen_mask
|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1
;
4373 if (adev
->pm
.pcie_mlw_mask
== 0) {
4374 if (platform_link_width
== PCIE_LNK_WIDTH_UNKNOWN
) {
4375 adev
->pm
.pcie_mlw_mask
|= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
4377 switch (platform_link_width
) {
4379 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32
|
4380 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16
|
4381 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
4382 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
4383 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
4384 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
4385 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
4388 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16
|
4389 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
4390 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
4391 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
4392 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
4393 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
4396 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12
|
4397 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
4398 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
4399 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
4400 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
4403 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8
|
4404 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
4405 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
4406 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
4409 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4
|
4410 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
4411 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
4414 adev
->pm
.pcie_mlw_mask
= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2
|
4415 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
);
4418 adev
->pm
.pcie_mlw_mask
= CAIL_PCIE_LINK_WIDTH_SUPPORT_X1
;
4427 int amdgpu_device_baco_enter(struct drm_device
*dev
)
4429 struct amdgpu_device
*adev
= dev
->dev_private
;
4430 struct amdgpu_ras
*ras
= amdgpu_ras_get_context(adev
);
4432 if (!amdgpu_device_supports_baco(adev
->ddev
))
4435 if (ras
&& ras
->supported
)
4436 adev
->nbio
.funcs
->enable_doorbell_interrupt(adev
, false);
4438 return amdgpu_dpm_baco_enter(adev
);
4441 int amdgpu_device_baco_exit(struct drm_device
*dev
)
4443 struct amdgpu_device
*adev
= dev
->dev_private
;
4444 struct amdgpu_ras
*ras
= amdgpu_ras_get_context(adev
);
4447 if (!amdgpu_device_supports_baco(adev
->ddev
))
4450 ret
= amdgpu_dpm_baco_exit(adev
);
4454 if (ras
&& ras
->supported
)
4455 adev
->nbio
.funcs
->enable_doorbell_interrupt(adev
, true);