drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

   1 /*
   2  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/amdgpu_drm.h>
  27 #include <drm/drm_gem.h>
  28 #include "amdgpu_drv.h"
  29
  30 #include <drm/drm_pciids.h>
  31 #include <linux/console.h>
  32 #include <linux/module.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drm_probe_helper.h>
  36
  37 #include "amdgpu.h"
  38 #include "amdgpu_irq.h"
  39 #include "amdgpu_gem.h"
  40
  41 #include "amdgpu_amdkfd.h"
  42
  43 /*
  44  * KMS wrapper.
  45  * - 3.0.0 - initial driver
  46  * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
  47  * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
  48  *           at the end of IBs.
  49  * - 3.3.0 - Add VM support for UVD on supported hardware.
  50  * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
  51  * - 3.5.0 - Add support for new UVD_NO_OP register.
  52  * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
  53  * - 3.7.0 - Add support for VCE clock list packet
  54  * - 3.8.0 - Add support raster config init in the kernel
  55  * - 3.9.0 - Add support for memory query info about VRAM and GTT.
  56  * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
  57  * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
  58  * - 3.12.0 - Add query for double offchip LDS buffers
  59  * - 3.13.0 - Add PRT support
  60  * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
  61  * - 3.15.0 - Export more gpu info for gfx9
  62  * - 3.16.0 - Add reserved vmid support
  63  * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
  64  * - 3.18.0 - Export gpu always on cu bitmap
  65  * - 3.19.0 - Add support for UVD MJPEG decode
  66  * - 3.20.0 - Add support for local BOs
  67  * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
  68  * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
  69  * - 3.23.0 - Add query for VRAM lost counter
  70  * - 3.24.0 - Add high priority compute support for gfx9
  71  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
  72  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
  73  * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
  74  * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
  75  * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
  76  */
  77 #define KMS_DRIVER_MAJOR        3
  78 #define KMS_DRIVER_MINOR        29
  79 #define KMS_DRIVER_PATCHLEVEL   0
  80
  81 int amdgpu_vram_limit = 0;
  82 int amdgpu_vis_vram_limit = 0;
  83 int amdgpu_gart_size = -1; /* auto */
  84 int amdgpu_gtt_size = -1; /* auto */
  85 int amdgpu_moverate = -1; /* auto */
  86 int amdgpu_benchmarking = 0;
  87 int amdgpu_testing = 0;
  88 int amdgpu_audio = -1;
  89 int amdgpu_disp_priority = 0;
  90 int amdgpu_hw_i2c = 0;
  91 int amdgpu_pcie_gen2 = -1;
  92 int amdgpu_msi = -1;
  93 int amdgpu_lockup_timeout = 10000;
  94 int amdgpu_dpm = -1;
  95 int amdgpu_fw_load_type = -1;
  96 int amdgpu_aspm = -1;
  97 int amdgpu_runtime_pm = -1;
  98 uint amdgpu_ip_block_mask = 0xffffffff;
  99 int amdgpu_bapm = -1;
 100 int amdgpu_deep_color = 0;
 101 int amdgpu_vm_size = -1;
 102 int amdgpu_vm_fragment_size = -1;
 103 int amdgpu_vm_block_size = -1;
 104 int amdgpu_vm_fault_stop = 0;
 105 int amdgpu_vm_debug = 0;
 106 int amdgpu_vram_page_split = 512;
 107 int amdgpu_vm_update_mode = -1;
 108 int amdgpu_exp_hw_support = 0;
 109 int amdgpu_dc = -1;
 110 int amdgpu_sched_jobs = 32;
 111 int amdgpu_sched_hw_submission = 2;
 112 uint amdgpu_pcie_gen_cap = 0;
 113 uint amdgpu_pcie_lane_cap = 0;
 114 uint amdgpu_cg_mask = 0xffffffff;
 115 uint amdgpu_pg_mask = 0xffffffff;
 116 uint amdgpu_sdma_phase_quantum = 32;
 117 char *amdgpu_disable_cu = NULL;
 118 char *amdgpu_virtual_display = NULL;
 119 /* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/
 120 uint amdgpu_pp_feature_mask = 0xfffd3fff;
 121 int amdgpu_ngg = 0;
 122 int amdgpu_prim_buf_per_se = 0;
 123 int amdgpu_pos_buf_per_se = 0;
 124 int amdgpu_cntl_sb_buf_per_se = 0;
 125 int amdgpu_param_buf_per_se = 0;
 126 int amdgpu_job_hang_limit = 0;
 127 int amdgpu_lbpw = -1;
 128 int amdgpu_compute_multipipe = -1;
 129 int amdgpu_gpu_recovery = -1; /* auto */
 130 int amdgpu_emu_mode = 0;
 131 uint amdgpu_smu_memory_pool_size = 0;
 132 /* FBC (bit 0) disabled by default*/
 133 uint amdgpu_dc_feature_mask = 0;
 134
 135 struct amdgpu_mgpu_info mgpu_info = {
 136         .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
 137 };
 138
 139 /**
 140  * DOC: vramlimit (int)
 141  * Restrict the total amount of VRAM in MiB for testing.  The default is 0 (Use full VRAM).
 142  */
 143 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 144 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 145
 146 /**
 147  * DOC: vis_vramlimit (int)
 148  * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 0 (Use full CPU visible VRAM).
 149  */
 150 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
 151 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 152
 153 /**
 154  * DOC: gartsize (uint)
 155  * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
 156  */
 157 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
 158 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 159
 160 /**
 161  * DOC: gttsize (int)
 162  * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
 163  * otherwise 3/4 RAM size).
 164  */
 165 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 166 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 167
 168 /**
 169  * DOC: moverate (int)
 170  * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
 171  */
 172 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
 173 module_param_named(moverate, amdgpu_moverate, int, 0600);
 174
 175 /**
 176  * DOC: benchmark (int)
 177  * Run benchmarks. The default is 0 (Skip benchmarks).
 178  */
 179 MODULE_PARM_DESC(benchmark, "Run benchmark");
 180 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 181
 182 /**
 183  * DOC: test (int)
 184  * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
 185  */
 186 MODULE_PARM_DESC(test, "Run tests");
 187 module_param_named(test, amdgpu_testing, int, 0444);
 188
 189 /**
 190  * DOC: audio (int)
 191  * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
 192  */
 193 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 194 module_param_named(audio, amdgpu_audio, int, 0444);
 195
 196 /**
 197  * DOC: disp_priority (int)
 198  * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
 199  */
 200 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
 201 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 202
 203 /**
 204  * DOC: hw_i2c (int)
 205  * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
 206  */
 207 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 208 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 209
 210 /**
 211  * DOC: pcie_gen2 (int)
 212  * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
 213  */
 214 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
 215 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 216
 217 /**
 218  * DOC: msi (int)
 219  * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 220  */
 221 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 222 module_param_named(msi, amdgpu_msi, int, 0444);
 223
 224 /**
 225  * DOC: lockup_timeout (int)
 226  * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be adjusted to 10000.
 227  * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 10000.
 228  */
 229 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
 230 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
 231
 232 /**
 233  * DOC: dpm (int)
 234  * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto).
 235  */
 236 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
 237 module_param_named(dpm, amdgpu_dpm, int, 0444);
 238
 239 /**
 240  * DOC: fw_load_type (int)
 241  * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
 242  */
 243 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
 244 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
 245
 246 /**
 247  * DOC: aspm (int)
 248  * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 249  */
 250 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
 251 module_param_named(aspm, amdgpu_aspm, int, 0444);
 252
 253 /**
 254  * DOC: runpm (int)
 255  * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
 256  * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
 257  */
 258 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
 259 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
 260
 261 /**
 262  * DOC: ip_block_mask (uint)
 263  * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
 264  * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
 265  * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
 266  * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
 267  */
 268 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
 269 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
 270
 271 /**
 272  * DOC: bapm (int)
 273  * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
 274  * The default -1 (auto, enabled)
 275  */
 276 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
 277 module_param_named(bapm, amdgpu_bapm, int, 0444);
 278
 279 /**
 280  * DOC: deep_color (int)
 281  * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
 282  */
 283 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
 284 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
 285
 286 /**
 287  * DOC: vm_size (int)
 288  * Override the size of the GPU's per client virtual address space in GiB.  The default is -1 (automatic for each asic).
 289  */
 290 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
 291 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
 292
 293 /**
 294  * DOC: vm_fragment_size (int)
 295  * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
 296  */
 297 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
 298 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
 299
 300 /**
 301  * DOC: vm_block_size (int)
 302  * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
 303  */
 304 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
 305 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
 306
 307 /**
 308  * DOC: vm_fault_stop (int)
 309  * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
 310  */
 311 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
 312 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
 313
 314 /**
 315  * DOC: vm_debug (int)
 316  * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
 317  */
 318 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
 319 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
 320
 321 /**
 322  * DOC: vm_update_mode (int)
 323  * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
 324  * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
 325  */
 326 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
 327 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
 328
 329 /**
 330  * DOC: vram_page_split (int)
 331  * Override the number of pages after we split VRAM allocations (default 512, -1 = disable). The default is 512.
 332  */
 333 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
 334 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
 335
 336 /**
 337  * DOC: exp_hw_support (int)
 338  * Enable experimental hw support (1 = enable). The default is 0 (disabled).
 339  */
 340 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
 341 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
 342
 343 /**
 344  * DOC: dc (int)
 345  * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
 346  */
 347 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
 348 module_param_named(dc, amdgpu_dc, int, 0444);
 349
 350 /**
 351  * DOC: sched_jobs (int)
 352  * Override the max number of jobs supported in the sw queue. The default is 32.
 353  */
 354 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
 355 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
 356
 357 /**
 358  * DOC: sched_hw_submission (int)
 359  * Override the max number of HW submissions. The default is 2.
 360  */
 361 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
 362 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
 363
 364 /**
 365  * DOC: ppfeaturemask (uint)
 366  * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
 367  * The default is the current set of stable power features.
 368  */
 369 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
 370 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
 371
 372 /**
 373  * DOC: pcie_gen_cap (uint)
 374  * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
 375  * The default is 0 (automatic for each asic).
 376  */
 377 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
 378 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
 379
 380 /**
 381  * DOC: pcie_lane_cap (uint)
 382  * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
 383  * The default is 0 (automatic for each asic).
 384  */
 385 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
 386 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
 387
 388 /**
 389  * DOC: cg_mask (uint)
 390  * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
 391  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
 392  */
 393 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
 394 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
 395
 396 /**
 397  * DOC: pg_mask (uint)
 398  * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
 399  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
 400  */
 401 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
 402 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
 403
 404 /**
 405  * DOC: sdma_phase_quantum (uint)
 406  * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
 407  */
 408 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
 409 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
 410
 411 /**
 412  * DOC: disable_cu (charp)
 413  * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
 414  */
 415 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
 416 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
 417
 418 /**
 419  * DOC: virtual_display (charp)
 420  * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
 421  * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
 422  * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
 423  * device at 26:00.0. The default is NULL.
 424  */
 425 MODULE_PARM_DESC(virtual_display,
 426                  "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
 427 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
 428
 429 /**
 430  * DOC: ngg (int)
 431  * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
 432  */
 433 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
 434 module_param_named(ngg, amdgpu_ngg, int, 0444);
 435
 436 /**
 437  * DOC: prim_buf_per_se (int)
 438  * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
 439  */
 440 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
 441 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
 442
 443 /**
 444  * DOC: pos_buf_per_se (int)
 445  * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
 446  */
 447 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
 448 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
 449
 450 /**
 451  * DOC: cntl_sb_buf_per_se (int)
 452  * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
 453  */
 454 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
 455 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
 456
 457 /**
 458  * DOC: param_buf_per_se (int)
 459  * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
 460  * The default is 0 (depending on gfx).
 461  */
 462 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
 463 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
 464
 465 /**
 466  * DOC: job_hang_limit (int)
 467  * Set how much time allow a job hang and not drop it. The default is 0.
 468  */
 469 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
 470 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
 471
 472 /**
 473  * DOC: lbpw (int)
 474  * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 475  */
 476 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
 477 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
 478
 479 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
 480 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
 481
 482 /**
 483  * DOC: gpu_recovery (int)
 484  * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
 485  */
 486 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
 487 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
 488
 489 /**
 490  * DOC: emu_mode (int)
 491  * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
 492  */
 493 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
 494 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
 495
 496 /**
 497  * DOC: si_support (int)
 498  * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
 499  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 500  * otherwise using amdgpu driver.
 501  */
 502 #ifdef CONFIG_DRM_AMDGPU_SI
 503
 504 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
 505 int amdgpu_si_support = 0;
 506 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
 507 #else
 508 int amdgpu_si_support = 1;
 509 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
 510 #endif
 511
 512 module_param_named(si_support, amdgpu_si_support, int, 0444);
 513 #endif
 514
 515 /**
 516  * DOC: cik_support (int)
 517  * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
 518  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 519  * otherwise using amdgpu driver.
 520  */
 521 #ifdef CONFIG_DRM_AMDGPU_CIK
 522
 523 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
 524 int amdgpu_cik_support = 0;
 525 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
 526 #else
 527 int amdgpu_cik_support = 1;
 528 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
 529 #endif
 530
 531 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 532 #endif
 533
 534 /**
 535  * DOC: smu_memory_pool_size (uint)
 536  * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
 537  * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
 538  */
 539 MODULE_PARM_DESC(smu_memory_pool_size,
 540         "reserve gtt for smu debug usage, 0 = disable,"
 541                 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
 542 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
 543
 544 #ifdef CONFIG_HSA_AMD
 545 /**
 546  * DOC: sched_policy (int)
 547  * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
 548  * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
 549  * assigns queues to HQDs.
 550  */
 551 int sched_policy = KFD_SCHED_POLICY_HWS;
 552 module_param(sched_policy, int, 0444);
 553 MODULE_PARM_DESC(sched_policy,
 554         "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
 555
 556 /**
 557  * DOC: hws_max_conc_proc (int)
 558  * Maximum number of processes that HWS can schedule concurrently. The maximum is the
 559  * number of VMIDs assigned to the HWS, which is also the default.
 560  */
 561 int hws_max_conc_proc = 8;
 562 module_param(hws_max_conc_proc, int, 0444);
 563 MODULE_PARM_DESC(hws_max_conc_proc,
 564         "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
 565
 566 /**
 567  * DOC: cwsr_enable (int)
 568  * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
 569  * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
 570  * disables it.
 571  */
 572 int cwsr_enable = 1;
 573 module_param(cwsr_enable, int, 0444);
 574 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
 575
 576 /**
 577  * DOC: max_num_of_queues_per_device (int)
 578  * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
 579  * is 4096.
 580  */
 581 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
 582 module_param(max_num_of_queues_per_device, int, 0444);
 583 MODULE_PARM_DESC(max_num_of_queues_per_device,
 584         "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
 585
 586 /**
 587  * DOC: send_sigterm (int)
 588  * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
 589  * but just print errors on dmesg. Setting 1 enables sending sigterm.
 590  */
 591 int send_sigterm;
 592 module_param(send_sigterm, int, 0444);
 593 MODULE_PARM_DESC(send_sigterm,
 594         "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
 595
 596 /**
 597  * DOC: debug_largebar (int)
 598  * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
 599  * system. This limits the VRAM size reported to ROCm applications to the visible
 600  * size, usually 256MB.
 601  * Default value is 0, diabled.
 602  */
 603 int debug_largebar;
 604 module_param(debug_largebar, int, 0444);
 605 MODULE_PARM_DESC(debug_largebar,
 606         "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
 607
 608 /**
 609  * DOC: ignore_crat (int)
 610  * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
 611  * table to get information about AMD APUs. This option can serve as a workaround on
 612  * systems with a broken CRAT table.
 613  */
 614 int ignore_crat;
 615 module_param(ignore_crat, int, 0444);
 616 MODULE_PARM_DESC(ignore_crat,
 617         "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
 618
 619 /**
 620  * DOC: noretry (int)
 621  * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry.
 622  * Setting 1 disables retry.
 623  * Retry is needed for recoverable page faults.
 624  */
 625 int noretry;
 626 module_param(noretry, int, 0644);
 627 MODULE_PARM_DESC(noretry,
 628         "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)");
 629
 630 /**
 631  * DOC: halt_if_hws_hang (int)
 632  * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
 633  * Setting 1 enables halt on hang.
 634  */
 635 int halt_if_hws_hang;
 636 module_param(halt_if_hws_hang, int, 0644);
 637 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
 638 #endif
 639
 640 /**
 641  * DOC: dcfeaturemask (uint)
 642  * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
 643  * The default is the current set of stable display features.
 644  */
 645 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
 646 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
 647
 648 static const struct pci_device_id pciidlist[] = {
 649 #ifdef  CONFIG_DRM_AMDGPU_SI
 650         {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 651         {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 652         {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 653         {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 654         {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 655         {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 656         {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 657         {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 658         {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 659         {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 660         {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 661         {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 662         {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 663         {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
 664         {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
 665         {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
 666         {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 667         {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 668         {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 669         {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 670         {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 671         {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 672         {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 673         {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 674         {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 675         {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 676         {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 677         {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 678         {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 679         {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 680         {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 681         {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 682         {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 683         {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 684         {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 685         {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 686         {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 687         {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 688         {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 689         {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 690         {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 691         {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 692         {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 693         {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 694         {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 695         {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 696         {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 697         {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 698         {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 699         {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 700         {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 701         {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 702         {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 703         {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 704         {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 705         {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 706         {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 707         {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 708         {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 709         {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 710         {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 711         {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 712         {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 713         {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 714         {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 715         {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 716         {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 717         {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 718         {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 719         {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 720         {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 721         {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 722 #endif
 723 #ifdef CONFIG_DRM_AMDGPU_CIK
 724         /* Kaveri */
 725         {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 726         {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 727         {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 728         {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 729         {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 730         {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 731         {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 732         {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 733         {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 734         {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 735         {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 736         {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 737         {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 738         {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 739         {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 740         {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 741         {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 742         {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 743         {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 744         {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 745         {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 746         {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 747         /* Bonaire */
 748         {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 749         {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 750         {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 751         {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 752         {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 753         {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 754         {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 755         {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 756         {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 757         {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 758         {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 759         /* Hawaii */
 760         {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 761         {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 762         {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 763         {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 764         {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 765         {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 766         {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 767         {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 768         {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 769         {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 770         {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 771         {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 772         /* Kabini */
 773         {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 774         {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 775         {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 776         {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 777         {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 778         {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 779         {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 780         {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 781         {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 782         {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 783         {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 784         {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 785         {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 786         {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 787         {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 788         {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 789         /* mullins */
 790         {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 791         {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 792         {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 793         {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 794         {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 795         {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 796         {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 797         {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 798         {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 799         {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 800         {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 801         {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 802         {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 803         {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 804         {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 805         {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 806 #endif
 807         /* topaz */
 808         {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 809         {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 810         {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 811         {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 812         {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 813         /* tonga */
 814         {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 815         {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 816         {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 817         {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 818         {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 819         {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 820         {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 821         {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 822         {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 823         /* fiji */
 824         {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
 825         {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
 826         /* carrizo */
 827         {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 828         {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 829         {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 830         {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 831         {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 832         /* stoney */
 833         {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
 834         /* Polaris11 */
 835         {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 836         {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 837         {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 838         {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 839         {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 840         {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 841         {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 842         {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 843         {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 844         /* Polaris10 */
 845         {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 846         {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 847         {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 848         {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 849         {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 850         {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 851         {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 852         {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 853         {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 854         {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 855         {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 856         {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 857         {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 858         /* Polaris12 */
 859         {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 860         {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 861         {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 862         {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 863         {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 864         {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 865         {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 866         {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 867         /* VEGAM */
 868         {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
 869         {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
 870         {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
 871         /* Vega 10 */
 872         {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 873         {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 874         {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 875         {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 876         {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 877         {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 878         {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 879         {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 880         {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 881         {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 882         {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 883         {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 884         {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 885         {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 886         {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 887         /* Vega 12 */
 888         {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 889         {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 890         {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 891         {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 892         {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 893         /* Vega 20 */
 894         {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 895         {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 896         {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 897         {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 898         {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 899         {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 900         {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 901         /* Raven */
 902         {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
 903         {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
 904
 905         {0, 0, 0}
 906 };
 907
 908 MODULE_DEVICE_TABLE(pci, pciidlist);
 909
 910 static struct drm_driver kms_driver;
 911
 912 static int amdgpu_pci_probe(struct pci_dev *pdev,
 913                             const struct pci_device_id *ent)
 914 {
 915         struct drm_device *dev;
 916         unsigned long flags = ent->driver_data;
 917         int ret, retry = 0;
 918         bool supports_atomic = false;
 919
 920         if (!amdgpu_virtual_display &&
 921             amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
 922                 supports_atomic = true;
 923
 924         if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
 925                 DRM_INFO("This hardware requires experimental hardware support.\n"
 926                          "See modparam exp_hw_support\n");
 927                 return -ENODEV;
 928         }
 929
 930         /* Get rid of things like offb */
 931         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb");
 932         if (ret)
 933                 return ret;
 934
 935         dev = drm_dev_alloc(&kms_driver, &pdev->dev);
 936         if (IS_ERR(dev))
 937                 return PTR_ERR(dev);
 938
 939         if (!supports_atomic)
 940                 dev->driver_features &= ~DRIVER_ATOMIC;
 941
 942         ret = pci_enable_device(pdev);
 943         if (ret)
 944                 goto err_free;
 945
 946         dev->pdev = pdev;
 947
 948         pci_set_drvdata(pdev, dev);
 949
 950 retry_init:
 951         ret = drm_dev_register(dev, ent->driver_data);
 952         if (ret == -EAGAIN && ++retry <= 3) {
 953                 DRM_INFO("retry init %d\n", retry);
 954                 /* Don't request EX mode too frequently which is attacking */
 955                 msleep(5000);
 956                 goto retry_init;
 957         } else if (ret)
 958                 goto err_pci;
 959
 960         return 0;
 961
 962 err_pci:
 963         pci_disable_device(pdev);
 964 err_free:
 965         drm_dev_put(dev);
 966         return ret;
 967 }
 968
 969 static void
 970 amdgpu_pci_remove(struct pci_dev *pdev)
 971 {
 972         struct drm_device *dev = pci_get_drvdata(pdev);
 973
 974         DRM_ERROR("Device removal is currently not supported outside of fbcon\n");
 975         drm_dev_unplug(dev);
 976         pci_disable_device(pdev);
 977         pci_set_drvdata(pdev, NULL);
 978 }
 979
 980 static void
 981 amdgpu_pci_shutdown(struct pci_dev *pdev)
 982 {
 983         struct drm_device *dev = pci_get_drvdata(pdev);
 984         struct amdgpu_device *adev = dev->dev_private;
 985
 986         /* if we are running in a VM, make sure the device
 987          * torn down properly on reboot/shutdown.
 988          * unfortunately we can't detect certain
 989          * hypervisors so just do this all the time.
 990          */
 991         amdgpu_device_ip_suspend(adev);
 992 }
 993
 994 static int amdgpu_pmops_suspend(struct device *dev)
 995 {
 996         struct pci_dev *pdev = to_pci_dev(dev);
 997
 998         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 999         return amdgpu_device_suspend(drm_dev, true, true);
1000 }
1001
1002 static int amdgpu_pmops_resume(struct device *dev)
1003 {
1004         struct pci_dev *pdev = to_pci_dev(dev);
1005         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1006
1007         /* GPU comes up enabled by the bios on resume */
1008         if (amdgpu_device_is_px(drm_dev)) {
1009                 pm_runtime_disable(dev);
1010                 pm_runtime_set_active(dev);
1011                 pm_runtime_enable(dev);
1012         }
1013
1014         return amdgpu_device_resume(drm_dev, true, true);
1015 }
1016
1017 static int amdgpu_pmops_freeze(struct device *dev)
1018 {
1019         struct pci_dev *pdev = to_pci_dev(dev);
1020
1021         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1022         return amdgpu_device_suspend(drm_dev, false, true);
1023 }
1024
1025 static int amdgpu_pmops_thaw(struct device *dev)
1026 {
1027         struct pci_dev *pdev = to_pci_dev(dev);
1028
1029         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1030         return amdgpu_device_resume(drm_dev, false, true);
1031 }
1032
1033 static int amdgpu_pmops_poweroff(struct device *dev)
1034 {
1035         struct pci_dev *pdev = to_pci_dev(dev);
1036
1037         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1038         return amdgpu_device_suspend(drm_dev, true, true);
1039 }
1040
1041 static int amdgpu_pmops_restore(struct device *dev)
1042 {
1043         struct pci_dev *pdev = to_pci_dev(dev);
1044
1045         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1046         return amdgpu_device_resume(drm_dev, false, true);
1047 }
1048
1049 static int amdgpu_pmops_runtime_suspend(struct device *dev)
1050 {
1051         struct pci_dev *pdev = to_pci_dev(dev);
1052         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1053         int ret;
1054
1055         if (!amdgpu_device_is_px(drm_dev)) {
1056                 pm_runtime_forbid(dev);
1057                 return -EBUSY;
1058         }
1059
1060         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1061         drm_kms_helper_poll_disable(drm_dev);
1062
1063         ret = amdgpu_device_suspend(drm_dev, false, false);
1064         pci_save_state(pdev);
1065         pci_disable_device(pdev);
1066         pci_ignore_hotplug(pdev);
1067         if (amdgpu_is_atpx_hybrid())
1068                 pci_set_power_state(pdev, PCI_D3cold);
1069         else if (!amdgpu_has_atpx_dgpu_power_cntl())
1070                 pci_set_power_state(pdev, PCI_D3hot);
1071         drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1072
1073         return 0;
1074 }
1075
1076 static int amdgpu_pmops_runtime_resume(struct device *dev)
1077 {
1078         struct pci_dev *pdev = to_pci_dev(dev);
1079         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1080         int ret;
1081
1082         if (!amdgpu_device_is_px(drm_dev))
1083                 return -EINVAL;
1084
1085         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1086
1087         if (amdgpu_is_atpx_hybrid() ||
1088             !amdgpu_has_atpx_dgpu_power_cntl())
1089                 pci_set_power_state(pdev, PCI_D0);
1090         pci_restore_state(pdev);
1091         ret = pci_enable_device(pdev);
1092         if (ret)
1093                 return ret;
1094         pci_set_master(pdev);
1095
1096         ret = amdgpu_device_resume(drm_dev, false, false);
1097         drm_kms_helper_poll_enable(drm_dev);
1098         drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1099         return 0;
1100 }
1101
1102 static int amdgpu_pmops_runtime_idle(struct device *dev)
1103 {
1104         struct pci_dev *pdev = to_pci_dev(dev);
1105         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1106         struct drm_crtc *crtc;
1107
1108         if (!amdgpu_device_is_px(drm_dev)) {
1109                 pm_runtime_forbid(dev);
1110                 return -EBUSY;
1111         }
1112
1113         list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
1114                 if (crtc->enabled) {
1115                         DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1116                         return -EBUSY;
1117                 }
1118         }
1119
1120         pm_runtime_mark_last_busy(dev);
1121         pm_runtime_autosuspend(dev);
1122         /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1123         return 1;
1124 }
1125
1126 long amdgpu_drm_ioctl(struct file *filp,
1127                       unsigned int cmd, unsigned long arg)
1128 {
1129         struct drm_file *file_priv = filp->private_data;
1130         struct drm_device *dev;
1131         long ret;
1132         dev = file_priv->minor->dev;
1133         ret = pm_runtime_get_sync(dev->dev);
1134         if (ret < 0)
1135                 return ret;
1136
1137         ret = drm_ioctl(filp, cmd, arg);
1138
1139         pm_runtime_mark_last_busy(dev->dev);
1140         pm_runtime_put_autosuspend(dev->dev);
1141         return ret;
1142 }
1143
1144 static const struct dev_pm_ops amdgpu_pm_ops = {
1145         .suspend = amdgpu_pmops_suspend,
1146         .resume = amdgpu_pmops_resume,
1147         .freeze = amdgpu_pmops_freeze,
1148         .thaw = amdgpu_pmops_thaw,
1149         .poweroff = amdgpu_pmops_poweroff,
1150         .restore = amdgpu_pmops_restore,
1151         .runtime_suspend = amdgpu_pmops_runtime_suspend,
1152         .runtime_resume = amdgpu_pmops_runtime_resume,
1153         .runtime_idle = amdgpu_pmops_runtime_idle,
1154 };
1155
1156 static int amdgpu_flush(struct file *f, fl_owner_t id)
1157 {
1158         struct drm_file *file_priv = f->private_data;
1159         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1160
1161         amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr);
1162
1163         return 0;
1164 }
1165
1166
1167 static const struct file_operations amdgpu_driver_kms_fops = {
1168         .owner = THIS_MODULE,
1169         .open = drm_open,
1170         .flush = amdgpu_flush,
1171         .release = drm_release,
1172         .unlocked_ioctl = amdgpu_drm_ioctl,
1173         .mmap = amdgpu_mmap,
1174         .poll = drm_poll,
1175         .read = drm_read,
1176 #ifdef CONFIG_COMPAT
1177         .compat_ioctl = amdgpu_kms_compat_ioctl,
1178 #endif
1179 };
1180
1181 static bool
1182 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
1183                                  bool in_vblank_irq, int *vpos, int *hpos,
1184                                  ktime_t *stime, ktime_t *etime,
1185                                  const struct drm_display_mode *mode)
1186 {
1187         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1188                                                   stime, etime, mode);
1189 }
1190
1191 static struct drm_driver kms_driver = {
1192         .driver_features =
1193             DRIVER_USE_AGP | DRIVER_ATOMIC |
1194             DRIVER_GEM |
1195             DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
1196         .load = amdgpu_driver_load_kms,
1197         .open = amdgpu_driver_open_kms,
1198         .postclose = amdgpu_driver_postclose_kms,
1199         .lastclose = amdgpu_driver_lastclose_kms,
1200         .unload = amdgpu_driver_unload_kms,
1201         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
1202         .enable_vblank = amdgpu_enable_vblank_kms,
1203         .disable_vblank = amdgpu_disable_vblank_kms,
1204         .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
1205         .get_scanout_position = amdgpu_get_crtc_scanout_position,
1206         .irq_handler = amdgpu_irq_handler,
1207         .ioctls = amdgpu_ioctls_kms,
1208         .gem_free_object_unlocked = amdgpu_gem_object_free,
1209         .gem_open_object = amdgpu_gem_object_open,
1210         .gem_close_object = amdgpu_gem_object_close,
1211         .dumb_create = amdgpu_mode_dumb_create,
1212         .dumb_map_offset = amdgpu_mode_dumb_mmap,
1213         .fops = &amdgpu_driver_kms_fops,
1214
1215         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1216         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1217         .gem_prime_export = amdgpu_gem_prime_export,
1218         .gem_prime_import = amdgpu_gem_prime_import,
1219         .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
1220         .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
1221         .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
1222         .gem_prime_vmap = amdgpu_gem_prime_vmap,
1223         .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
1224         .gem_prime_mmap = amdgpu_gem_prime_mmap,
1225
1226         .name = DRIVER_NAME,
1227         .desc = DRIVER_DESC,
1228         .date = DRIVER_DATE,
1229         .major = KMS_DRIVER_MAJOR,
1230         .minor = KMS_DRIVER_MINOR,
1231         .patchlevel = KMS_DRIVER_PATCHLEVEL,
1232 };
1233
1234 static struct pci_driver amdgpu_kms_pci_driver = {
1235         .name = DRIVER_NAME,
1236         .id_table = pciidlist,
1237         .probe = amdgpu_pci_probe,
1238         .remove = amdgpu_pci_remove,
1239         .shutdown = amdgpu_pci_shutdown,
1240         .driver.pm = &amdgpu_pm_ops,
1241 };
1242
1243
1244
1245 static int __init amdgpu_init(void)
1246 {
1247         int r;
1248
1249         if (vgacon_text_force()) {
1250                 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1251                 return -EINVAL;
1252         }
1253
1254         r = amdgpu_sync_init();
1255         if (r)
1256                 goto error_sync;
1257
1258         r = amdgpu_fence_slab_init();
1259         if (r)
1260                 goto error_fence;
1261
1262         DRM_INFO("amdgpu kernel modesetting enabled.\n");
1263         kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
1264         amdgpu_register_atpx_handler();
1265
1266         /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
1267         amdgpu_amdkfd_init();
1268
1269         /* let modprobe override vga console setting */
1270         return pci_register_driver(&amdgpu_kms_pci_driver);
1271
1272 error_fence:
1273         amdgpu_sync_fini();
1274
1275 error_sync:
1276         return r;
1277 }
1278
1279 static void __exit amdgpu_exit(void)
1280 {
1281         amdgpu_amdkfd_fini();
1282         pci_unregister_driver(&amdgpu_kms_pci_driver);
1283         amdgpu_unregister_atpx_handler();
1284         amdgpu_sync_fini();
1285         amdgpu_fence_slab_fini();
1286 }
1287
1288 module_init(amdgpu_init);
1289 module_exit(amdgpu_exit);
1290
1291 MODULE_AUTHOR(DRIVER_AUTHOR);
1292 MODULE_DESCRIPTION(DRIVER_DESC);
1293 MODULE_LICENSE("GPL and additional rights");