2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm/amdgpu_drm.h>
27 #include <drm/drm_gem.h>
28 #include "amdgpu_drv.h"
30 #include <drm/drm_pciids.h>
31 #include <linux/console.h>
32 #include <linux/module.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/vga_switcheroo.h>
35 #include <drm/drm_probe_helper.h>
38 #include "amdgpu_irq.h"
39 #include "amdgpu_gem.h"
41 #include "amdgpu_amdkfd.h"
45 * - 3.0.0 - initial driver
46 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
47 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
49 * - 3.3.0 - Add VM support for UVD on supported hardware.
50 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
51 * - 3.5.0 - Add support for new UVD_NO_OP register.
52 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
53 * - 3.7.0 - Add support for VCE clock list packet
54 * - 3.8.0 - Add support raster config init in the kernel
55 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
56 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
57 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
58 * - 3.12.0 - Add query for double offchip LDS buffers
59 * - 3.13.0 - Add PRT support
60 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
61 * - 3.15.0 - Export more gpu info for gfx9
62 * - 3.16.0 - Add reserved vmid support
63 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
64 * - 3.18.0 - Export gpu always on cu bitmap
65 * - 3.19.0 - Add support for UVD MJPEG decode
66 * - 3.20.0 - Add support for local BOs
67 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
68 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
69 * - 3.23.0 - Add query for VRAM lost counter
70 * - 3.24.0 - Add high priority compute support for gfx9
71 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
72 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
73 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
75 #define KMS_DRIVER_MAJOR 3
76 #define KMS_DRIVER_MINOR 27
77 #define KMS_DRIVER_PATCHLEVEL 0
79 int amdgpu_vram_limit
= 0;
80 int amdgpu_vis_vram_limit
= 0;
81 int amdgpu_gart_size
= -1; /* auto */
82 int amdgpu_gtt_size
= -1; /* auto */
83 int amdgpu_moverate
= -1; /* auto */
84 int amdgpu_benchmarking
= 0;
85 int amdgpu_testing
= 0;
86 int amdgpu_audio
= -1;
87 int amdgpu_disp_priority
= 0;
88 int amdgpu_hw_i2c
= 0;
89 int amdgpu_pcie_gen2
= -1;
91 int amdgpu_lockup_timeout
= 10000;
93 int amdgpu_fw_load_type
= -1;
95 int amdgpu_runtime_pm
= -1;
96 uint amdgpu_ip_block_mask
= 0xffffffff;
98 int amdgpu_deep_color
= 0;
99 int amdgpu_vm_size
= -1;
100 int amdgpu_vm_fragment_size
= -1;
101 int amdgpu_vm_block_size
= -1;
102 int amdgpu_vm_fault_stop
= 0;
103 int amdgpu_vm_debug
= 0;
104 int amdgpu_vram_page_split
= 512;
105 int amdgpu_vm_update_mode
= -1;
106 int amdgpu_exp_hw_support
= 0;
108 int amdgpu_sched_jobs
= 32;
109 int amdgpu_sched_hw_submission
= 2;
110 uint amdgpu_pcie_gen_cap
= 0;
111 uint amdgpu_pcie_lane_cap
= 0;
112 uint amdgpu_cg_mask
= 0xffffffff;
113 uint amdgpu_pg_mask
= 0xffffffff;
114 uint amdgpu_sdma_phase_quantum
= 32;
115 char *amdgpu_disable_cu
= NULL
;
116 char *amdgpu_virtual_display
= NULL
;
117 /* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/
118 uint amdgpu_pp_feature_mask
= 0xfffd3fff;
120 int amdgpu_prim_buf_per_se
= 0;
121 int amdgpu_pos_buf_per_se
= 0;
122 int amdgpu_cntl_sb_buf_per_se
= 0;
123 int amdgpu_param_buf_per_se
= 0;
124 int amdgpu_job_hang_limit
= 0;
125 int amdgpu_lbpw
= -1;
126 int amdgpu_compute_multipipe
= -1;
127 int amdgpu_gpu_recovery
= -1; /* auto */
128 int amdgpu_emu_mode
= 0;
129 uint amdgpu_smu_memory_pool_size
= 0;
130 /* FBC (bit 0) disabled by default*/
131 uint amdgpu_dc_feature_mask
= 0;
133 struct amdgpu_mgpu_info mgpu_info
= {
134 .mutex
= __MUTEX_INITIALIZER(mgpu_info
.mutex
),
138 * DOC: vramlimit (int)
139 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
141 MODULE_PARM_DESC(vramlimit
, "Restrict VRAM for testing, in megabytes");
142 module_param_named(vramlimit
, amdgpu_vram_limit
, int, 0600);
145 * DOC: vis_vramlimit (int)
146 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
148 MODULE_PARM_DESC(vis_vramlimit
, "Restrict visible VRAM for testing, in megabytes");
149 module_param_named(vis_vramlimit
, amdgpu_vis_vram_limit
, int, 0444);
152 * DOC: gartsize (uint)
153 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
155 MODULE_PARM_DESC(gartsize
, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
156 module_param_named(gartsize
, amdgpu_gart_size
, uint
, 0600);
160 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
161 * otherwise 3/4 RAM size).
163 MODULE_PARM_DESC(gttsize
, "Size of the GTT domain in megabytes (-1 = auto)");
164 module_param_named(gttsize
, amdgpu_gtt_size
, int, 0600);
167 * DOC: moverate (int)
168 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
170 MODULE_PARM_DESC(moverate
, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
171 module_param_named(moverate
, amdgpu_moverate
, int, 0600);
174 * DOC: benchmark (int)
175 * Run benchmarks. The default is 0 (Skip benchmarks).
177 MODULE_PARM_DESC(benchmark
, "Run benchmark");
178 module_param_named(benchmark
, amdgpu_benchmarking
, int, 0444);
182 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
184 MODULE_PARM_DESC(test
, "Run tests");
185 module_param_named(test
, amdgpu_testing
, int, 0444);
189 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
191 MODULE_PARM_DESC(audio
, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
192 module_param_named(audio
, amdgpu_audio
, int, 0444);
195 * DOC: disp_priority (int)
196 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
198 MODULE_PARM_DESC(disp_priority
, "Display Priority (0 = auto, 1 = normal, 2 = high)");
199 module_param_named(disp_priority
, amdgpu_disp_priority
, int, 0444);
203 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
205 MODULE_PARM_DESC(hw_i2c
, "hw i2c engine enable (0 = disable)");
206 module_param_named(hw_i2c
, amdgpu_hw_i2c
, int, 0444);
209 * DOC: pcie_gen2 (int)
210 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
212 MODULE_PARM_DESC(pcie_gen2
, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
213 module_param_named(pcie_gen2
, amdgpu_pcie_gen2
, int, 0444);
217 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
219 MODULE_PARM_DESC(msi
, "MSI support (1 = enable, 0 = disable, -1 = auto)");
220 module_param_named(msi
, amdgpu_msi
, int, 0444);
223 * DOC: lockup_timeout (int)
224 * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be adjusted to 10000.
225 * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 10000.
227 MODULE_PARM_DESC(lockup_timeout
, "GPU lockup timeout in ms > 0 (default 10000)");
228 module_param_named(lockup_timeout
, amdgpu_lockup_timeout
, int, 0444);
232 * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto).
234 MODULE_PARM_DESC(dpm
, "DPM support (1 = enable, 0 = disable, -1 = auto)");
235 module_param_named(dpm
, amdgpu_dpm
, int, 0444);
238 * DOC: fw_load_type (int)
239 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
241 MODULE_PARM_DESC(fw_load_type
, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
242 module_param_named(fw_load_type
, amdgpu_fw_load_type
, int, 0444);
246 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
248 MODULE_PARM_DESC(aspm
, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
249 module_param_named(aspm
, amdgpu_aspm
, int, 0444);
253 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
254 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
256 MODULE_PARM_DESC(runpm
, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
257 module_param_named(runpm
, amdgpu_runtime_pm
, int, 0444);
260 * DOC: ip_block_mask (uint)
261 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
262 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
263 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
264 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
266 MODULE_PARM_DESC(ip_block_mask
, "IP Block Mask (all blocks enabled (default))");
267 module_param_named(ip_block_mask
, amdgpu_ip_block_mask
, uint
, 0444);
271 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
272 * The default -1 (auto, enabled)
274 MODULE_PARM_DESC(bapm
, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
275 module_param_named(bapm
, amdgpu_bapm
, int, 0444);
278 * DOC: deep_color (int)
279 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
281 MODULE_PARM_DESC(deep_color
, "Deep Color support (1 = enable, 0 = disable (default))");
282 module_param_named(deep_color
, amdgpu_deep_color
, int, 0444);
286 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
288 MODULE_PARM_DESC(vm_size
, "VM address space size in gigabytes (default 64GB)");
289 module_param_named(vm_size
, amdgpu_vm_size
, int, 0444);
292 * DOC: vm_fragment_size (int)
293 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
295 MODULE_PARM_DESC(vm_fragment_size
, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
296 module_param_named(vm_fragment_size
, amdgpu_vm_fragment_size
, int, 0444);
299 * DOC: vm_block_size (int)
300 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
302 MODULE_PARM_DESC(vm_block_size
, "VM page table size in bits (default depending on vm_size)");
303 module_param_named(vm_block_size
, amdgpu_vm_block_size
, int, 0444);
306 * DOC: vm_fault_stop (int)
307 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
309 MODULE_PARM_DESC(vm_fault_stop
, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
310 module_param_named(vm_fault_stop
, amdgpu_vm_fault_stop
, int, 0444);
313 * DOC: vm_debug (int)
314 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
316 MODULE_PARM_DESC(vm_debug
, "Debug VM handling (0 = disabled (default), 1 = enabled)");
317 module_param_named(vm_debug
, amdgpu_vm_debug
, int, 0644);
320 * DOC: vm_update_mode (int)
321 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
322 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
324 MODULE_PARM_DESC(vm_update_mode
, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
325 module_param_named(vm_update_mode
, amdgpu_vm_update_mode
, int, 0444);
328 * DOC: vram_page_split (int)
329 * Override the number of pages after we split VRAM allocations (default 512, -1 = disable). The default is 512.
331 MODULE_PARM_DESC(vram_page_split
, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
332 module_param_named(vram_page_split
, amdgpu_vram_page_split
, int, 0444);
335 * DOC: exp_hw_support (int)
336 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
338 MODULE_PARM_DESC(exp_hw_support
, "experimental hw support (1 = enable, 0 = disable (default))");
339 module_param_named(exp_hw_support
, amdgpu_exp_hw_support
, int, 0444);
343 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
345 MODULE_PARM_DESC(dc
, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
346 module_param_named(dc
, amdgpu_dc
, int, 0444);
349 * DOC: sched_jobs (int)
350 * Override the max number of jobs supported in the sw queue. The default is 32.
352 MODULE_PARM_DESC(sched_jobs
, "the max number of jobs supported in the sw queue (default 32)");
353 module_param_named(sched_jobs
, amdgpu_sched_jobs
, int, 0444);
356 * DOC: sched_hw_submission (int)
357 * Override the max number of HW submissions. The default is 2.
359 MODULE_PARM_DESC(sched_hw_submission
, "the max number of HW submissions (default 2)");
360 module_param_named(sched_hw_submission
, amdgpu_sched_hw_submission
, int, 0444);
363 * DOC: ppfeaturemask (uint)
364 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
365 * The default is the current set of stable power features.
367 MODULE_PARM_DESC(ppfeaturemask
, "all power features enabled (default))");
368 module_param_named(ppfeaturemask
, amdgpu_pp_feature_mask
, uint
, 0444);
371 * DOC: pcie_gen_cap (uint)
372 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
373 * The default is 0 (automatic for each asic).
375 MODULE_PARM_DESC(pcie_gen_cap
, "PCIE Gen Caps (0: autodetect (default))");
376 module_param_named(pcie_gen_cap
, amdgpu_pcie_gen_cap
, uint
, 0444);
379 * DOC: pcie_lane_cap (uint)
380 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
381 * The default is 0 (automatic for each asic).
383 MODULE_PARM_DESC(pcie_lane_cap
, "PCIE Lane Caps (0: autodetect (default))");
384 module_param_named(pcie_lane_cap
, amdgpu_pcie_lane_cap
, uint
, 0444);
387 * DOC: cg_mask (uint)
388 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
389 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
391 MODULE_PARM_DESC(cg_mask
, "Clockgating flags mask (0 = disable clock gating)");
392 module_param_named(cg_mask
, amdgpu_cg_mask
, uint
, 0444);
395 * DOC: pg_mask (uint)
396 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
397 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
399 MODULE_PARM_DESC(pg_mask
, "Powergating flags mask (0 = disable power gating)");
400 module_param_named(pg_mask
, amdgpu_pg_mask
, uint
, 0444);
403 * DOC: sdma_phase_quantum (uint)
404 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
406 MODULE_PARM_DESC(sdma_phase_quantum
, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
407 module_param_named(sdma_phase_quantum
, amdgpu_sdma_phase_quantum
, uint
, 0444);
410 * DOC: disable_cu (charp)
411 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
413 MODULE_PARM_DESC(disable_cu
, "Disable CUs (se.sh.cu,...)");
414 module_param_named(disable_cu
, amdgpu_disable_cu
, charp
, 0444);
417 * DOC: virtual_display (charp)
418 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
419 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
420 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
421 * device at 26:00.0. The default is NULL.
423 MODULE_PARM_DESC(virtual_display
,
424 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
425 module_param_named(virtual_display
, amdgpu_virtual_display
, charp
, 0444);
429 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
431 MODULE_PARM_DESC(ngg
, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
432 module_param_named(ngg
, amdgpu_ngg
, int, 0444);
435 * DOC: prim_buf_per_se (int)
436 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
438 MODULE_PARM_DESC(prim_buf_per_se
, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
439 module_param_named(prim_buf_per_se
, amdgpu_prim_buf_per_se
, int, 0444);
442 * DOC: pos_buf_per_se (int)
443 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
445 MODULE_PARM_DESC(pos_buf_per_se
, "the size of Position Buffer per Shader Engine (default depending on gfx)");
446 module_param_named(pos_buf_per_se
, amdgpu_pos_buf_per_se
, int, 0444);
449 * DOC: cntl_sb_buf_per_se (int)
450 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
452 MODULE_PARM_DESC(cntl_sb_buf_per_se
, "the size of Control Sideband per Shader Engine (default depending on gfx)");
453 module_param_named(cntl_sb_buf_per_se
, amdgpu_cntl_sb_buf_per_se
, int, 0444);
456 * DOC: param_buf_per_se (int)
457 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
458 * The default is 0 (depending on gfx).
460 MODULE_PARM_DESC(param_buf_per_se
, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
461 module_param_named(param_buf_per_se
, amdgpu_param_buf_per_se
, int, 0444);
464 * DOC: job_hang_limit (int)
465 * Set how much time allow a job hang and not drop it. The default is 0.
467 MODULE_PARM_DESC(job_hang_limit
, "how much time allow a job hang and not drop it (default 0)");
468 module_param_named(job_hang_limit
, amdgpu_job_hang_limit
, int ,0444);
472 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
474 MODULE_PARM_DESC(lbpw
, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
475 module_param_named(lbpw
, amdgpu_lbpw
, int, 0444);
477 MODULE_PARM_DESC(compute_multipipe
, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
478 module_param_named(compute_multipipe
, amdgpu_compute_multipipe
, int, 0444);
481 * DOC: gpu_recovery (int)
482 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
484 MODULE_PARM_DESC(gpu_recovery
, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
485 module_param_named(gpu_recovery
, amdgpu_gpu_recovery
, int, 0444);
488 * DOC: emu_mode (int)
489 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
491 MODULE_PARM_DESC(emu_mode
, "Emulation mode, (1 = enable, 0 = disable)");
492 module_param_named(emu_mode
, amdgpu_emu_mode
, int, 0444);
495 * DOC: si_support (int)
496 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
497 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
498 * otherwise using amdgpu driver.
500 #ifdef CONFIG_DRM_AMDGPU_SI
502 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
503 int amdgpu_si_support
= 0;
504 MODULE_PARM_DESC(si_support
, "SI support (1 = enabled, 0 = disabled (default))");
506 int amdgpu_si_support
= 1;
507 MODULE_PARM_DESC(si_support
, "SI support (1 = enabled (default), 0 = disabled)");
510 module_param_named(si_support
, amdgpu_si_support
, int, 0444);
514 * DOC: cik_support (int)
515 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
516 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
517 * otherwise using amdgpu driver.
519 #ifdef CONFIG_DRM_AMDGPU_CIK
521 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
522 int amdgpu_cik_support
= 0;
523 MODULE_PARM_DESC(cik_support
, "CIK support (1 = enabled, 0 = disabled (default))");
525 int amdgpu_cik_support
= 1;
526 MODULE_PARM_DESC(cik_support
, "CIK support (1 = enabled (default), 0 = disabled)");
529 module_param_named(cik_support
, amdgpu_cik_support
, int, 0444);
533 * DOC: smu_memory_pool_size (uint)
534 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
535 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
537 MODULE_PARM_DESC(smu_memory_pool_size
,
538 "reserve gtt for smu debug usage, 0 = disable,"
539 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
540 module_param_named(smu_memory_pool_size
, amdgpu_smu_memory_pool_size
, uint
, 0444);
542 #ifdef CONFIG_HSA_AMD
544 * DOC: sched_policy (int)
545 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
546 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
547 * assigns queues to HQDs.
549 int sched_policy
= KFD_SCHED_POLICY_HWS
;
550 module_param(sched_policy
, int, 0444);
551 MODULE_PARM_DESC(sched_policy
,
552 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
555 * DOC: hws_max_conc_proc (int)
556 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
557 * number of VMIDs assigned to the HWS, which is also the default.
559 int hws_max_conc_proc
= 8;
560 module_param(hws_max_conc_proc
, int, 0444);
561 MODULE_PARM_DESC(hws_max_conc_proc
,
562 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
565 * DOC: cwsr_enable (int)
566 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
567 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
571 module_param(cwsr_enable
, int, 0444);
572 MODULE_PARM_DESC(cwsr_enable
, "CWSR enable (0 = Off, 1 = On (Default))");
575 * DOC: max_num_of_queues_per_device (int)
576 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
579 int max_num_of_queues_per_device
= KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT
;
580 module_param(max_num_of_queues_per_device
, int, 0444);
581 MODULE_PARM_DESC(max_num_of_queues_per_device
,
582 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
585 * DOC: send_sigterm (int)
586 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
587 * but just print errors on dmesg. Setting 1 enables sending sigterm.
590 module_param(send_sigterm
, int, 0444);
591 MODULE_PARM_DESC(send_sigterm
,
592 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
595 * DOC: debug_largebar (int)
596 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
597 * system. This limits the VRAM size reported to ROCm applications to the visible
598 * size, usually 256MB.
599 * Default value is 0, diabled.
602 module_param(debug_largebar
, int, 0444);
603 MODULE_PARM_DESC(debug_largebar
,
604 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
607 * DOC: ignore_crat (int)
608 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
609 * table to get information about AMD APUs. This option can serve as a workaround on
610 * systems with a broken CRAT table.
613 module_param(ignore_crat
, int, 0444);
614 MODULE_PARM_DESC(ignore_crat
,
615 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
619 * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry.
620 * Setting 1 disables retry.
621 * Retry is needed for recoverable page faults.
624 module_param(noretry
, int, 0644);
625 MODULE_PARM_DESC(noretry
,
626 "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)");
629 * DOC: halt_if_hws_hang (int)
630 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
631 * Setting 1 enables halt on hang.
633 int halt_if_hws_hang
;
634 module_param(halt_if_hws_hang
, int, 0644);
635 MODULE_PARM_DESC(halt_if_hws_hang
, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
639 * DOC: dcfeaturemask (uint)
640 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
641 * The default is the current set of stable display features.
643 MODULE_PARM_DESC(dcfeaturemask
, "all stable DC features enabled (default))");
644 module_param_named(dcfeaturemask
, amdgpu_dc_feature_mask
, uint
, 0444);
646 static const struct pci_device_id pciidlist
[] = {
647 #ifdef CONFIG_DRM_AMDGPU_SI
648 {0x1002, 0x6780, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
649 {0x1002, 0x6784, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
650 {0x1002, 0x6788, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
651 {0x1002, 0x678A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
652 {0x1002, 0x6790, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
653 {0x1002, 0x6791, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
654 {0x1002, 0x6792, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
655 {0x1002, 0x6798, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
656 {0x1002, 0x6799, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
657 {0x1002, 0x679A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
658 {0x1002, 0x679B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
659 {0x1002, 0x679E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
660 {0x1002, 0x679F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TAHITI
},
661 {0x1002, 0x6800, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
|AMD_IS_MOBILITY
},
662 {0x1002, 0x6801, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
|AMD_IS_MOBILITY
},
663 {0x1002, 0x6802, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
|AMD_IS_MOBILITY
},
664 {0x1002, 0x6806, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
665 {0x1002, 0x6808, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
666 {0x1002, 0x6809, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
667 {0x1002, 0x6810, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
668 {0x1002, 0x6811, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
669 {0x1002, 0x6816, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
670 {0x1002, 0x6817, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
671 {0x1002, 0x6818, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
672 {0x1002, 0x6819, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_PITCAIRN
},
673 {0x1002, 0x6600, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
674 {0x1002, 0x6601, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
675 {0x1002, 0x6602, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
676 {0x1002, 0x6603, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
677 {0x1002, 0x6604, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
678 {0x1002, 0x6605, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
679 {0x1002, 0x6606, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
680 {0x1002, 0x6607, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
681 {0x1002, 0x6608, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
682 {0x1002, 0x6610, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
683 {0x1002, 0x6611, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
684 {0x1002, 0x6613, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
685 {0x1002, 0x6617, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
686 {0x1002, 0x6620, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
687 {0x1002, 0x6621, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
688 {0x1002, 0x6623, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
|AMD_IS_MOBILITY
},
689 {0x1002, 0x6631, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_OLAND
},
690 {0x1002, 0x6820, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
691 {0x1002, 0x6821, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
692 {0x1002, 0x6822, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
693 {0x1002, 0x6823, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
694 {0x1002, 0x6824, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
695 {0x1002, 0x6825, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
696 {0x1002, 0x6826, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
697 {0x1002, 0x6827, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
698 {0x1002, 0x6828, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
699 {0x1002, 0x6829, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
700 {0x1002, 0x682A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
701 {0x1002, 0x682B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
702 {0x1002, 0x682C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
703 {0x1002, 0x682D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
704 {0x1002, 0x682F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
705 {0x1002, 0x6830, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
706 {0x1002, 0x6831, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
|AMD_IS_MOBILITY
},
707 {0x1002, 0x6835, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
708 {0x1002, 0x6837, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
709 {0x1002, 0x6838, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
710 {0x1002, 0x6839, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
711 {0x1002, 0x683B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
712 {0x1002, 0x683D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
713 {0x1002, 0x683F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VERDE
},
714 {0x1002, 0x6660, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
715 {0x1002, 0x6663, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
716 {0x1002, 0x6664, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
717 {0x1002, 0x6665, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
718 {0x1002, 0x6667, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
719 {0x1002, 0x666F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAINAN
|AMD_IS_MOBILITY
},
721 #ifdef CONFIG_DRM_AMDGPU_CIK
723 {0x1002, 0x1304, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
724 {0x1002, 0x1305, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
725 {0x1002, 0x1306, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
726 {0x1002, 0x1307, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
727 {0x1002, 0x1309, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
728 {0x1002, 0x130A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
729 {0x1002, 0x130B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
730 {0x1002, 0x130C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
731 {0x1002, 0x130D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
732 {0x1002, 0x130E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
733 {0x1002, 0x130F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
734 {0x1002, 0x1310, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
735 {0x1002, 0x1311, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
736 {0x1002, 0x1312, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
737 {0x1002, 0x1313, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
738 {0x1002, 0x1315, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
739 {0x1002, 0x1316, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
740 {0x1002, 0x1317, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
741 {0x1002, 0x1318, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
742 {0x1002, 0x131B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
743 {0x1002, 0x131C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
744 {0x1002, 0x131D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
746 {0x1002, 0x6640, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
747 {0x1002, 0x6641, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
748 {0x1002, 0x6646, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
749 {0x1002, 0x6647, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
750 {0x1002, 0x6649, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
751 {0x1002, 0x6650, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
752 {0x1002, 0x6651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
753 {0x1002, 0x6658, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
754 {0x1002, 0x665c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
755 {0x1002, 0x665d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
756 {0x1002, 0x665f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
758 {0x1002, 0x67A0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
759 {0x1002, 0x67A1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
760 {0x1002, 0x67A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
761 {0x1002, 0x67A8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
762 {0x1002, 0x67A9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
763 {0x1002, 0x67AA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
764 {0x1002, 0x67B0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
765 {0x1002, 0x67B1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
766 {0x1002, 0x67B8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
767 {0x1002, 0x67B9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
768 {0x1002, 0x67BA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
769 {0x1002, 0x67BE, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
771 {0x1002, 0x9830, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
772 {0x1002, 0x9831, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
773 {0x1002, 0x9832, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
774 {0x1002, 0x9833, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
775 {0x1002, 0x9834, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
776 {0x1002, 0x9835, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
777 {0x1002, 0x9836, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
778 {0x1002, 0x9837, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
779 {0x1002, 0x9838, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
780 {0x1002, 0x9839, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
781 {0x1002, 0x983a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
782 {0x1002, 0x983b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
783 {0x1002, 0x983c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
784 {0x1002, 0x983d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
785 {0x1002, 0x983e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
786 {0x1002, 0x983f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
788 {0x1002, 0x9850, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
789 {0x1002, 0x9851, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
790 {0x1002, 0x9852, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
791 {0x1002, 0x9853, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
792 {0x1002, 0x9854, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
793 {0x1002, 0x9855, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
794 {0x1002, 0x9856, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
795 {0x1002, 0x9857, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
796 {0x1002, 0x9858, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
797 {0x1002, 0x9859, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
798 {0x1002, 0x985A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
799 {0x1002, 0x985B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
800 {0x1002, 0x985C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
801 {0x1002, 0x985D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
802 {0x1002, 0x985E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
803 {0x1002, 0x985F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
806 {0x1002, 0x6900, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
807 {0x1002, 0x6901, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
808 {0x1002, 0x6902, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
809 {0x1002, 0x6903, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
810 {0x1002, 0x6907, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
812 {0x1002, 0x6920, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
813 {0x1002, 0x6921, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
814 {0x1002, 0x6928, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
815 {0x1002, 0x6929, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
816 {0x1002, 0x692B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
817 {0x1002, 0x692F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
818 {0x1002, 0x6930, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
819 {0x1002, 0x6938, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
820 {0x1002, 0x6939, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
822 {0x1002, 0x7300, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_FIJI
},
823 {0x1002, 0x730F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_FIJI
},
825 {0x1002, 0x9870, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
826 {0x1002, 0x9874, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
827 {0x1002, 0x9875, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
828 {0x1002, 0x9876, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
829 {0x1002, 0x9877, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
831 {0x1002, 0x98E4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_STONEY
|AMD_IS_APU
},
833 {0x1002, 0x67E0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
834 {0x1002, 0x67E3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
835 {0x1002, 0x67E8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
836 {0x1002, 0x67EB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
837 {0x1002, 0x67EF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
838 {0x1002, 0x67FF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
839 {0x1002, 0x67E1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
840 {0x1002, 0x67E7, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
841 {0x1002, 0x67E9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
843 {0x1002, 0x67C0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
844 {0x1002, 0x67C1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
845 {0x1002, 0x67C2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
846 {0x1002, 0x67C4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
847 {0x1002, 0x67C7, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
848 {0x1002, 0x67D0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
849 {0x1002, 0x67DF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
850 {0x1002, 0x67C8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
851 {0x1002, 0x67C9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
852 {0x1002, 0x67CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
853 {0x1002, 0x67CC, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
854 {0x1002, 0x67CF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
855 {0x1002, 0x6FDF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
857 {0x1002, 0x6980, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
858 {0x1002, 0x6981, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
859 {0x1002, 0x6985, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
860 {0x1002, 0x6986, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
861 {0x1002, 0x6987, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
862 {0x1002, 0x6995, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
863 {0x1002, 0x6997, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
864 {0x1002, 0x699F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS12
},
866 {0x1002, 0x694C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGAM
},
867 {0x1002, 0x694E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGAM
},
868 {0x1002, 0x694F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGAM
},
870 {0x1002, 0x6860, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
871 {0x1002, 0x6861, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
872 {0x1002, 0x6862, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
873 {0x1002, 0x6863, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
874 {0x1002, 0x6864, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
875 {0x1002, 0x6867, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
876 {0x1002, 0x6868, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
877 {0x1002, 0x6869, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
878 {0x1002, 0x686a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
879 {0x1002, 0x686b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
880 {0x1002, 0x686c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
881 {0x1002, 0x686d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
882 {0x1002, 0x686e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
883 {0x1002, 0x686f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
884 {0x1002, 0x687f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA10
},
886 {0x1002, 0x69A0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA12
},
887 {0x1002, 0x69A1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA12
},
888 {0x1002, 0x69A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA12
},
889 {0x1002, 0x69A3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA12
},
890 {0x1002, 0x69AF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA12
},
892 {0x1002, 0x66A0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA20
},
893 {0x1002, 0x66A1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA20
},
894 {0x1002, 0x66A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA20
},
895 {0x1002, 0x66A3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA20
},
896 {0x1002, 0x66A4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA20
},
897 {0x1002, 0x66A7, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA20
},
898 {0x1002, 0x66AF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_VEGA20
},
900 {0x1002, 0x15dd, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_RAVEN
|AMD_IS_APU
},
901 {0x1002, 0x15d8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_RAVEN
|AMD_IS_APU
},
906 MODULE_DEVICE_TABLE(pci
, pciidlist
);
908 static struct drm_driver kms_driver
;
910 static int amdgpu_pci_probe(struct pci_dev
*pdev
,
911 const struct pci_device_id
*ent
)
913 struct drm_device
*dev
;
914 unsigned long flags
= ent
->driver_data
;
916 bool supports_atomic
= false;
918 if (!amdgpu_virtual_display
&&
919 amdgpu_device_asic_has_dc_support(flags
& AMD_ASIC_MASK
))
920 supports_atomic
= true;
922 if ((flags
& AMD_EXP_HW_SUPPORT
) && !amdgpu_exp_hw_support
) {
923 DRM_INFO("This hardware requires experimental hardware support.\n"
924 "See modparam exp_hw_support\n");
928 /* Get rid of things like offb */
929 ret
= drm_fb_helper_remove_conflicting_pci_framebuffers(pdev
, 0, "amdgpudrmfb");
933 dev
= drm_dev_alloc(&kms_driver
, &pdev
->dev
);
937 if (!supports_atomic
)
938 dev
->driver_features
&= ~DRIVER_ATOMIC
;
940 ret
= pci_enable_device(pdev
);
946 pci_set_drvdata(pdev
, dev
);
949 ret
= drm_dev_register(dev
, ent
->driver_data
);
950 if (ret
== -EAGAIN
&& ++retry
<= 3) {
951 DRM_INFO("retry init %d\n", retry
);
952 /* Don't request EX mode too frequently which is attacking */
961 pci_disable_device(pdev
);
968 amdgpu_pci_remove(struct pci_dev
*pdev
)
970 struct drm_device
*dev
= pci_get_drvdata(pdev
);
972 DRM_ERROR("Device removal is currently not supported outside of fbcon\n");
974 pci_disable_device(pdev
);
975 pci_set_drvdata(pdev
, NULL
);
979 amdgpu_pci_shutdown(struct pci_dev
*pdev
)
981 struct drm_device
*dev
= pci_get_drvdata(pdev
);
982 struct amdgpu_device
*adev
= dev
->dev_private
;
984 /* if we are running in a VM, make sure the device
985 * torn down properly on reboot/shutdown.
986 * unfortunately we can't detect certain
987 * hypervisors so just do this all the time.
989 amdgpu_device_ip_suspend(adev
);
992 static int amdgpu_pmops_suspend(struct device
*dev
)
994 struct pci_dev
*pdev
= to_pci_dev(dev
);
996 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
997 return amdgpu_device_suspend(drm_dev
, true, true);
1000 static int amdgpu_pmops_resume(struct device
*dev
)
1002 struct pci_dev
*pdev
= to_pci_dev(dev
);
1003 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1005 /* GPU comes up enabled by the bios on resume */
1006 if (amdgpu_device_is_px(drm_dev
)) {
1007 pm_runtime_disable(dev
);
1008 pm_runtime_set_active(dev
);
1009 pm_runtime_enable(dev
);
1012 return amdgpu_device_resume(drm_dev
, true, true);
1015 static int amdgpu_pmops_freeze(struct device
*dev
)
1017 struct pci_dev
*pdev
= to_pci_dev(dev
);
1019 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1020 return amdgpu_device_suspend(drm_dev
, false, true);
1023 static int amdgpu_pmops_thaw(struct device
*dev
)
1025 struct pci_dev
*pdev
= to_pci_dev(dev
);
1027 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1028 return amdgpu_device_resume(drm_dev
, false, true);
1031 static int amdgpu_pmops_poweroff(struct device
*dev
)
1033 struct pci_dev
*pdev
= to_pci_dev(dev
);
1035 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1036 return amdgpu_device_suspend(drm_dev
, true, true);
1039 static int amdgpu_pmops_restore(struct device
*dev
)
1041 struct pci_dev
*pdev
= to_pci_dev(dev
);
1043 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1044 return amdgpu_device_resume(drm_dev
, false, true);
1047 static int amdgpu_pmops_runtime_suspend(struct device
*dev
)
1049 struct pci_dev
*pdev
= to_pci_dev(dev
);
1050 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1053 if (!amdgpu_device_is_px(drm_dev
)) {
1054 pm_runtime_forbid(dev
);
1058 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1059 drm_kms_helper_poll_disable(drm_dev
);
1061 ret
= amdgpu_device_suspend(drm_dev
, false, false);
1062 pci_save_state(pdev
);
1063 pci_disable_device(pdev
);
1064 pci_ignore_hotplug(pdev
);
1065 if (amdgpu_is_atpx_hybrid())
1066 pci_set_power_state(pdev
, PCI_D3cold
);
1067 else if (!amdgpu_has_atpx_dgpu_power_cntl())
1068 pci_set_power_state(pdev
, PCI_D3hot
);
1069 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_DYNAMIC_OFF
;
1074 static int amdgpu_pmops_runtime_resume(struct device
*dev
)
1076 struct pci_dev
*pdev
= to_pci_dev(dev
);
1077 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1080 if (!amdgpu_device_is_px(drm_dev
))
1083 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1085 if (amdgpu_is_atpx_hybrid() ||
1086 !amdgpu_has_atpx_dgpu_power_cntl())
1087 pci_set_power_state(pdev
, PCI_D0
);
1088 pci_restore_state(pdev
);
1089 ret
= pci_enable_device(pdev
);
1092 pci_set_master(pdev
);
1094 ret
= amdgpu_device_resume(drm_dev
, false, false);
1095 drm_kms_helper_poll_enable(drm_dev
);
1096 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1100 static int amdgpu_pmops_runtime_idle(struct device
*dev
)
1102 struct pci_dev
*pdev
= to_pci_dev(dev
);
1103 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1104 struct drm_crtc
*crtc
;
1106 if (!amdgpu_device_is_px(drm_dev
)) {
1107 pm_runtime_forbid(dev
);
1111 list_for_each_entry(crtc
, &drm_dev
->mode_config
.crtc_list
, head
) {
1112 if (crtc
->enabled
) {
1113 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1118 pm_runtime_mark_last_busy(dev
);
1119 pm_runtime_autosuspend(dev
);
1120 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1124 long amdgpu_drm_ioctl(struct file
*filp
,
1125 unsigned int cmd
, unsigned long arg
)
1127 struct drm_file
*file_priv
= filp
->private_data
;
1128 struct drm_device
*dev
;
1130 dev
= file_priv
->minor
->dev
;
1131 ret
= pm_runtime_get_sync(dev
->dev
);
1135 ret
= drm_ioctl(filp
, cmd
, arg
);
1137 pm_runtime_mark_last_busy(dev
->dev
);
1138 pm_runtime_put_autosuspend(dev
->dev
);
1142 static const struct dev_pm_ops amdgpu_pm_ops
= {
1143 .suspend
= amdgpu_pmops_suspend
,
1144 .resume
= amdgpu_pmops_resume
,
1145 .freeze
= amdgpu_pmops_freeze
,
1146 .thaw
= amdgpu_pmops_thaw
,
1147 .poweroff
= amdgpu_pmops_poweroff
,
1148 .restore
= amdgpu_pmops_restore
,
1149 .runtime_suspend
= amdgpu_pmops_runtime_suspend
,
1150 .runtime_resume
= amdgpu_pmops_runtime_resume
,
1151 .runtime_idle
= amdgpu_pmops_runtime_idle
,
1154 static int amdgpu_flush(struct file
*f
, fl_owner_t id
)
1156 struct drm_file
*file_priv
= f
->private_data
;
1157 struct amdgpu_fpriv
*fpriv
= file_priv
->driver_priv
;
1159 amdgpu_ctx_mgr_entity_flush(&fpriv
->ctx_mgr
);
1165 static const struct file_operations amdgpu_driver_kms_fops
= {
1166 .owner
= THIS_MODULE
,
1168 .flush
= amdgpu_flush
,
1169 .release
= drm_release
,
1170 .unlocked_ioctl
= amdgpu_drm_ioctl
,
1171 .mmap
= amdgpu_mmap
,
1174 #ifdef CONFIG_COMPAT
1175 .compat_ioctl
= amdgpu_kms_compat_ioctl
,
1180 amdgpu_get_crtc_scanout_position(struct drm_device
*dev
, unsigned int pipe
,
1181 bool in_vblank_irq
, int *vpos
, int *hpos
,
1182 ktime_t
*stime
, ktime_t
*etime
,
1183 const struct drm_display_mode
*mode
)
1185 return amdgpu_display_get_crtc_scanoutpos(dev
, pipe
, 0, vpos
, hpos
,
1186 stime
, etime
, mode
);
1189 static struct drm_driver kms_driver
= {
1191 DRIVER_USE_AGP
| DRIVER_ATOMIC
|
1193 DRIVER_PRIME
| DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_SYNCOBJ
,
1194 .load
= amdgpu_driver_load_kms
,
1195 .open
= amdgpu_driver_open_kms
,
1196 .postclose
= amdgpu_driver_postclose_kms
,
1197 .lastclose
= amdgpu_driver_lastclose_kms
,
1198 .unload
= amdgpu_driver_unload_kms
,
1199 .get_vblank_counter
= amdgpu_get_vblank_counter_kms
,
1200 .enable_vblank
= amdgpu_enable_vblank_kms
,
1201 .disable_vblank
= amdgpu_disable_vblank_kms
,
1202 .get_vblank_timestamp
= drm_calc_vbltimestamp_from_scanoutpos
,
1203 .get_scanout_position
= amdgpu_get_crtc_scanout_position
,
1204 .irq_handler
= amdgpu_irq_handler
,
1205 .ioctls
= amdgpu_ioctls_kms
,
1206 .gem_free_object_unlocked
= amdgpu_gem_object_free
,
1207 .gem_open_object
= amdgpu_gem_object_open
,
1208 .gem_close_object
= amdgpu_gem_object_close
,
1209 .dumb_create
= amdgpu_mode_dumb_create
,
1210 .dumb_map_offset
= amdgpu_mode_dumb_mmap
,
1211 .fops
= &amdgpu_driver_kms_fops
,
1213 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1214 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1215 .gem_prime_export
= amdgpu_gem_prime_export
,
1216 .gem_prime_import
= amdgpu_gem_prime_import
,
1217 .gem_prime_res_obj
= amdgpu_gem_prime_res_obj
,
1218 .gem_prime_get_sg_table
= amdgpu_gem_prime_get_sg_table
,
1219 .gem_prime_import_sg_table
= amdgpu_gem_prime_import_sg_table
,
1220 .gem_prime_vmap
= amdgpu_gem_prime_vmap
,
1221 .gem_prime_vunmap
= amdgpu_gem_prime_vunmap
,
1222 .gem_prime_mmap
= amdgpu_gem_prime_mmap
,
1224 .name
= DRIVER_NAME
,
1225 .desc
= DRIVER_DESC
,
1226 .date
= DRIVER_DATE
,
1227 .major
= KMS_DRIVER_MAJOR
,
1228 .minor
= KMS_DRIVER_MINOR
,
1229 .patchlevel
= KMS_DRIVER_PATCHLEVEL
,
1232 static struct pci_driver amdgpu_kms_pci_driver
= {
1233 .name
= DRIVER_NAME
,
1234 .id_table
= pciidlist
,
1235 .probe
= amdgpu_pci_probe
,
1236 .remove
= amdgpu_pci_remove
,
1237 .shutdown
= amdgpu_pci_shutdown
,
1238 .driver
.pm
= &amdgpu_pm_ops
,
1243 static int __init
amdgpu_init(void)
1247 if (vgacon_text_force()) {
1248 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1252 r
= amdgpu_sync_init();
1256 r
= amdgpu_fence_slab_init();
1260 DRM_INFO("amdgpu kernel modesetting enabled.\n");
1261 kms_driver
.num_ioctls
= amdgpu_max_kms_ioctl
;
1262 amdgpu_register_atpx_handler();
1264 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
1265 amdgpu_amdkfd_init();
1267 /* let modprobe override vga console setting */
1268 return pci_register_driver(&amdgpu_kms_pci_driver
);
1277 static void __exit
amdgpu_exit(void)
1279 amdgpu_amdkfd_fini();
1280 pci_unregister_driver(&amdgpu_kms_pci_driver
);
1281 amdgpu_unregister_atpx_handler();
1283 amdgpu_fence_slab_fini();
1286 module_init(amdgpu_init
);
1287 module_exit(amdgpu_exit
);
1289 MODULE_AUTHOR(DRIVER_AUTHOR
);
1290 MODULE_DESCRIPTION(DRIVER_DESC
);
1291 MODULE_LICENSE("GPL and additional rights");