drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

   1 /*
   2  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/amdgpu_drm.h>
  27 #include <drm/drm_gem.h>
  28 #include "amdgpu_drv.h"
  29
  30 #include <drm/drm_pciids.h>
  31 #include <linux/console.h>
  32 #include <linux/module.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drm_crtc_helper.h>
  36
  37 #include "amdgpu.h"
  38 #include "amdgpu_irq.h"
  39 #include "amdgpu_gem.h"
  40
  41 #include "amdgpu_amdkfd.h"
  42
  43 /*
  44  * KMS wrapper.
  45  * - 3.0.0 - initial driver
  46  * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
  47  * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
  48  *           at the end of IBs.
  49  * - 3.3.0 - Add VM support for UVD on supported hardware.
  50  * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
  51  * - 3.5.0 - Add support for new UVD_NO_OP register.
  52  * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
  53  * - 3.7.0 - Add support for VCE clock list packet
  54  * - 3.8.0 - Add support raster config init in the kernel
  55  * - 3.9.0 - Add support for memory query info about VRAM and GTT.
  56  * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
  57  * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
  58  * - 3.12.0 - Add query for double offchip LDS buffers
  59  * - 3.13.0 - Add PRT support
  60  * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
  61  * - 3.15.0 - Export more gpu info for gfx9
  62  * - 3.16.0 - Add reserved vmid support
  63  * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
  64  * - 3.18.0 - Export gpu always on cu bitmap
  65  * - 3.19.0 - Add support for UVD MJPEG decode
  66  * - 3.20.0 - Add support for local BOs
  67  * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
  68  * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
  69  * - 3.23.0 - Add query for VRAM lost counter
  70  * - 3.24.0 - Add high priority compute support for gfx9
  71  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
  72  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
  73  * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
  74  */
  75 #define KMS_DRIVER_MAJOR        3
  76 #define KMS_DRIVER_MINOR        27
  77 #define KMS_DRIVER_PATCHLEVEL   0
  78
  79 int amdgpu_vram_limit = 0;
  80 int amdgpu_vis_vram_limit = 0;
  81 int amdgpu_gart_size = -1; /* auto */
  82 int amdgpu_gtt_size = -1; /* auto */
  83 int amdgpu_moverate = -1; /* auto */
  84 int amdgpu_benchmarking = 0;
  85 int amdgpu_testing = 0;
  86 int amdgpu_audio = -1;
  87 int amdgpu_disp_priority = 0;
  88 int amdgpu_hw_i2c = 0;
  89 int amdgpu_pcie_gen2 = -1;
  90 int amdgpu_msi = -1;
  91 int amdgpu_lockup_timeout = 10000;
  92 int amdgpu_dpm = -1;
  93 int amdgpu_fw_load_type = -1;
  94 int amdgpu_aspm = -1;
  95 int amdgpu_runtime_pm = -1;
  96 uint amdgpu_ip_block_mask = 0xffffffff;
  97 int amdgpu_bapm = -1;
  98 int amdgpu_deep_color = 0;
  99 int amdgpu_vm_size = -1;
 100 int amdgpu_vm_fragment_size = -1;
 101 int amdgpu_vm_block_size = -1;
 102 int amdgpu_vm_fault_stop = 0;
 103 int amdgpu_vm_debug = 0;
 104 int amdgpu_vram_page_split = 512;
 105 int amdgpu_vm_update_mode = -1;
 106 int amdgpu_exp_hw_support = 0;
 107 int amdgpu_dc = -1;
 108 int amdgpu_sched_jobs = 32;
 109 int amdgpu_sched_hw_submission = 2;
 110 uint amdgpu_pcie_gen_cap = 0;
 111 uint amdgpu_pcie_lane_cap = 0;
 112 uint amdgpu_cg_mask = 0xffffffff;
 113 uint amdgpu_pg_mask = 0xffffffff;
 114 uint amdgpu_sdma_phase_quantum = 32;
 115 char *amdgpu_disable_cu = NULL;
 116 char *amdgpu_virtual_display = NULL;
 117 /* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/
 118 uint amdgpu_pp_feature_mask = 0xfffd3fff;
 119 int amdgpu_ngg = 0;
 120 int amdgpu_prim_buf_per_se = 0;
 121 int amdgpu_pos_buf_per_se = 0;
 122 int amdgpu_cntl_sb_buf_per_se = 0;
 123 int amdgpu_param_buf_per_se = 0;
 124 int amdgpu_job_hang_limit = 0;
 125 int amdgpu_lbpw = -1;
 126 int amdgpu_compute_multipipe = -1;
 127 int amdgpu_gpu_recovery = -1; /* auto */
 128 int amdgpu_emu_mode = 0;
 129 uint amdgpu_smu_memory_pool_size = 0;
 130 struct amdgpu_mgpu_info mgpu_info = {
 131         .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
 132 };
 133
 134 /**
 135  * DOC: vramlimit (int)
 136  * Restrict the total amount of VRAM in MiB for testing.  The default is 0 (Use full VRAM).
 137  */
 138 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 139 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 140
 141 /**
 142  * DOC: vis_vramlimit (int)
 143  * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 0 (Use full CPU visible VRAM).
 144  */
 145 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
 146 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 147
 148 /**
 149  * DOC: gartsize (uint)
 150  * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
 151  */
 152 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
 153 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 154
 155 /**
 156  * DOC: gttsize (int)
 157  * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
 158  * otherwise 3/4 RAM size).
 159  */
 160 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 161 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 162
 163 /**
 164  * DOC: moverate (int)
 165  * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
 166  */
 167 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
 168 module_param_named(moverate, amdgpu_moverate, int, 0600);
 169
 170 /**
 171  * DOC: benchmark (int)
 172  * Run benchmarks. The default is 0 (Skip benchmarks).
 173  */
 174 MODULE_PARM_DESC(benchmark, "Run benchmark");
 175 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 176
 177 /**
 178  * DOC: test (int)
 179  * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
 180  */
 181 MODULE_PARM_DESC(test, "Run tests");
 182 module_param_named(test, amdgpu_testing, int, 0444);
 183
 184 /**
 185  * DOC: audio (int)
 186  * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
 187  */
 188 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 189 module_param_named(audio, amdgpu_audio, int, 0444);
 190
 191 /**
 192  * DOC: disp_priority (int)
 193  * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
 194  */
 195 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
 196 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 197
 198 /**
 199  * DOC: hw_i2c (int)
 200  * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
 201  */
 202 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 203 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 204
 205 /**
 206  * DOC: pcie_gen2 (int)
 207  * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
 208  */
 209 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
 210 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 211
 212 /**
 213  * DOC: msi (int)
 214  * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 215  */
 216 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 217 module_param_named(msi, amdgpu_msi, int, 0444);
 218
 219 /**
 220  * DOC: lockup_timeout (int)
 221  * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be adjusted to 10000.
 222  * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 10000.
 223  */
 224 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
 225 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
 226
 227 /**
 228  * DOC: dpm (int)
 229  * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto).
 230  */
 231 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
 232 module_param_named(dpm, amdgpu_dpm, int, 0444);
 233
 234 /**
 235  * DOC: fw_load_type (int)
 236  * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
 237  */
 238 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
 239 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
 240
 241 /**
 242  * DOC: aspm (int)
 243  * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 244  */
 245 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
 246 module_param_named(aspm, amdgpu_aspm, int, 0444);
 247
 248 /**
 249  * DOC: runpm (int)
 250  * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
 251  * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
 252  */
 253 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
 254 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
 255
 256 /**
 257  * DOC: ip_block_mask (uint)
 258  * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
 259  * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
 260  * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
 261  * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
 262  */
 263 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
 264 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
 265
 266 /**
 267  * DOC: bapm (int)
 268  * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
 269  * The default -1 (auto, enabled)
 270  */
 271 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
 272 module_param_named(bapm, amdgpu_bapm, int, 0444);
 273
 274 /**
 275  * DOC: deep_color (int)
 276  * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
 277  */
 278 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
 279 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
 280
 281 /**
 282  * DOC: vm_size (int)
 283  * Override the size of the GPU's per client virtual address space in GiB.  The default is -1 (automatic for each asic).
 284  */
 285 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
 286 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
 287
 288 /**
 289  * DOC: vm_fragment_size (int)
 290  * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
 291  */
 292 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
 293 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
 294
 295 /**
 296  * DOC: vm_block_size (int)
 297  * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
 298  */
 299 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
 300 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
 301
 302 /**
 303  * DOC: vm_fault_stop (int)
 304  * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
 305  */
 306 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
 307 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
 308
 309 /**
 310  * DOC: vm_debug (int)
 311  * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
 312  */
 313 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
 314 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
 315
 316 /**
 317  * DOC: vm_update_mode (int)
 318  * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
 319  * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
 320  */
 321 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
 322 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
 323
 324 /**
 325  * DOC: vram_page_split (int)
 326  * Override the number of pages after we split VRAM allocations (default 512, -1 = disable). The default is 512.
 327  */
 328 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
 329 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
 330
 331 /**
 332  * DOC: exp_hw_support (int)
 333  * Enable experimental hw support (1 = enable). The default is 0 (disabled).
 334  */
 335 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
 336 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
 337
 338 /**
 339  * DOC: dc (int)
 340  * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
 341  */
 342 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
 343 module_param_named(dc, amdgpu_dc, int, 0444);
 344
 345 /**
 346  * DOC: sched_jobs (int)
 347  * Override the max number of jobs supported in the sw queue. The default is 32.
 348  */
 349 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
 350 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
 351
 352 /**
 353  * DOC: sched_hw_submission (int)
 354  * Override the max number of HW submissions. The default is 2.
 355  */
 356 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
 357 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
 358
 359 /**
 360  * DOC: ppfeaturemask (uint)
 361  * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
 362  * The default is the current set of stable power features.
 363  */
 364 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
 365 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
 366
 367 /**
 368  * DOC: pcie_gen_cap (uint)
 369  * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
 370  * The default is 0 (automatic for each asic).
 371  */
 372 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
 373 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
 374
 375 /**
 376  * DOC: pcie_lane_cap (uint)
 377  * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
 378  * The default is 0 (automatic for each asic).
 379  */
 380 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
 381 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
 382
 383 /**
 384  * DOC: cg_mask (uint)
 385  * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
 386  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
 387  */
 388 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
 389 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
 390
 391 /**
 392  * DOC: pg_mask (uint)
 393  * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
 394  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
 395  */
 396 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
 397 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
 398
 399 /**
 400  * DOC: sdma_phase_quantum (uint)
 401  * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
 402  */
 403 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
 404 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
 405
 406 /**
 407  * DOC: disable_cu (charp)
 408  * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
 409  */
 410 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
 411 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
 412
 413 /**
 414  * DOC: virtual_display (charp)
 415  * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
 416  * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
 417  * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
 418  * device at 26:00.0. The default is NULL.
 419  */
 420 MODULE_PARM_DESC(virtual_display,
 421                  "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
 422 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
 423
 424 /**
 425  * DOC: ngg (int)
 426  * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
 427  */
 428 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
 429 module_param_named(ngg, amdgpu_ngg, int, 0444);
 430
 431 /**
 432  * DOC: prim_buf_per_se (int)
 433  * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
 434  */
 435 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
 436 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
 437
 438 /**
 439  * DOC: pos_buf_per_se (int)
 440  * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
 441  */
 442 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
 443 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
 444
 445 /**
 446  * DOC: cntl_sb_buf_per_se (int)
 447  * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
 448  */
 449 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
 450 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
 451
 452 /**
 453  * DOC: param_buf_per_se (int)
 454  * Override the size of Off-Chip Pramater Cache per Shader Engine in Byte. The default is 0 (depending on gfx).
 455  */
 456 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
 457 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
 458
 459 /**
 460  * DOC: job_hang_limit (int)
 461  * Set how much time allow a job hang and not drop it. The default is 0.
 462  */
 463 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
 464 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
 465
 466 /**
 467  * DOC: lbpw (int)
 468  * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 469  */
 470 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
 471 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
 472
 473 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
 474 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
 475
 476 /**
 477  * DOC: gpu_recovery (int)
 478  * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
 479  */
 480 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
 481 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
 482
 483 /**
 484  * DOC: emu_mode (int)
 485  * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
 486  */
 487 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
 488 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
 489
 490 /**
 491  * DOC: si_support (int)
 492  * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
 493  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 494  * otherwise using amdgpu driver.
 495  */
 496 #ifdef CONFIG_DRM_AMDGPU_SI
 497
 498 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
 499 int amdgpu_si_support = 0;
 500 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
 501 #else
 502 int amdgpu_si_support = 1;
 503 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
 504 #endif
 505
 506 module_param_named(si_support, amdgpu_si_support, int, 0444);
 507 #endif
 508
 509 /**
 510  * DOC: cik_support (int)
 511  * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
 512  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 513  * otherwise using amdgpu driver.
 514  */
 515 #ifdef CONFIG_DRM_AMDGPU_CIK
 516
 517 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
 518 int amdgpu_cik_support = 0;
 519 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
 520 #else
 521 int amdgpu_cik_support = 1;
 522 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
 523 #endif
 524
 525 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 526 #endif
 527
 528 /**
 529  * DOC: smu_memory_pool_size (uint)
 530  * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
 531  * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
 532  */
 533 MODULE_PARM_DESC(smu_memory_pool_size,
 534         "reserve gtt for smu debug usage, 0 = disable,"
 535                 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
 536 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
 537
 538 #ifdef CONFIG_HSA_AMD
 539 /**
 540  * DOC: sched_policy (int)
 541  * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
 542  * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
 543  * assigns queues to HQDs.
 544  */
 545 int sched_policy = KFD_SCHED_POLICY_HWS;
 546 module_param(sched_policy, int, 0444);
 547 MODULE_PARM_DESC(sched_policy,
 548         "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
 549
 550 /**
 551  * DOC: hws_max_conc_proc (int)
 552  * Maximum number of processes that HWS can schedule concurrently. The maximum is the
 553  * number of VMIDs assigned to the HWS, which is also the default.
 554  */
 555 int hws_max_conc_proc = 8;
 556 module_param(hws_max_conc_proc, int, 0444);
 557 MODULE_PARM_DESC(hws_max_conc_proc,
 558         "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
 559
 560 /**
 561  * DOC: cwsr_enable (int)
 562  * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
 563  * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
 564  * disables it.
 565  */
 566 int cwsr_enable = 1;
 567 module_param(cwsr_enable, int, 0444);
 568 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
 569
 570 /**
 571  * DOC: max_num_of_queues_per_device (int)
 572  * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
 573  * is 4096.
 574  */
 575 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
 576 module_param(max_num_of_queues_per_device, int, 0444);
 577 MODULE_PARM_DESC(max_num_of_queues_per_device,
 578         "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
 579
 580 /**
 581  * DOC: send_sigterm (int)
 582  * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
 583  * but just print errors on dmesg. Setting 1 enables sending sigterm.
 584  */
 585 int send_sigterm;
 586 module_param(send_sigterm, int, 0444);
 587 MODULE_PARM_DESC(send_sigterm,
 588         "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
 589
 590 /**
 591  * DOC: debug_largebar (int)
 592  * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
 593  * system. This limits the VRAM size reported to ROCm applications to the visible
 594  * size, usually 256MB.
 595  * Default value is 0, diabled.
 596  */
 597 int debug_largebar;
 598 module_param(debug_largebar, int, 0444);
 599 MODULE_PARM_DESC(debug_largebar,
 600         "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
 601
 602 /**
 603  * DOC: ignore_crat (int)
 604  * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
 605  * table to get information about AMD APUs. This option can serve as a workaround on
 606  * systems with a broken CRAT table.
 607  */
 608 int ignore_crat;
 609 module_param(ignore_crat, int, 0444);
 610 MODULE_PARM_DESC(ignore_crat,
 611         "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
 612
 613 /**
 614  * DOC: noretry (int)
 615  * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry.
 616  * Setting 1 disables retry.
 617  * Retry is needed for recoverable page faults.
 618  */
 619 int noretry;
 620 module_param(noretry, int, 0644);
 621 MODULE_PARM_DESC(noretry,
 622         "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)");
 623
 624 /**
 625  * DOC: halt_if_hws_hang (int)
 626  * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
 627  * Setting 1 enables halt on hang.
 628  */
 629 int halt_if_hws_hang;
 630 module_param(halt_if_hws_hang, int, 0644);
 631 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
 632 #endif
 633
 634 static const struct pci_device_id pciidlist[] = {
 635 #ifdef  CONFIG_DRM_AMDGPU_SI
 636         {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 637         {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 638         {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 639         {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 640         {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 641         {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 642         {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 643         {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 644         {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 645         {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 646         {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 647         {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 648         {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 649         {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
 650         {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
 651         {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
 652         {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 653         {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 654         {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 655         {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 656         {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 657         {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 658         {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 659         {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 660         {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 661         {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 662         {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 663         {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 664         {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 665         {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 666         {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 667         {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 668         {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 669         {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 670         {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 671         {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 672         {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 673         {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 674         {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 675         {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 676         {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 677         {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 678         {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 679         {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 680         {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 681         {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 682         {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 683         {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 684         {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 685         {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 686         {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 687         {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 688         {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 689         {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 690         {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 691         {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 692         {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 693         {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 694         {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 695         {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 696         {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 697         {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 698         {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 699         {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 700         {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 701         {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 702         {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 703         {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 704         {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 705         {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 706         {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 707         {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 708 #endif
 709 #ifdef CONFIG_DRM_AMDGPU_CIK
 710         /* Kaveri */
 711         {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 712         {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 713         {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 714         {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 715         {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 716         {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 717         {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 718         {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 719         {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 720         {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 721         {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 722         {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 723         {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 724         {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 725         {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 726         {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 727         {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 728         {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 729         {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 730         {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 731         {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 732         {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 733         /* Bonaire */
 734         {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 735         {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 736         {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 737         {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 738         {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 739         {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 740         {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 741         {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 742         {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 743         {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 744         {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 745         /* Hawaii */
 746         {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 747         {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 748         {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 749         {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 750         {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 751         {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 752         {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 753         {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 754         {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 755         {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 756         {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 757         {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 758         /* Kabini */
 759         {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 760         {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 761         {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 762         {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 763         {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 764         {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 765         {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 766         {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 767         {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 768         {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 769         {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 770         {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 771         {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 772         {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 773         {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 774         {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 775         /* mullins */
 776         {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 777         {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 778         {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 779         {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 780         {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 781         {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 782         {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 783         {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 784         {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 785         {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 786         {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 787         {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 788         {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 789         {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 790         {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 791         {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 792 #endif
 793         /* topaz */
 794         {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 795         {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 796         {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 797         {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 798         {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 799         /* tonga */
 800         {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 801         {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 802         {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 803         {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 804         {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 805         {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 806         {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 807         {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 808         {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 809         /* fiji */
 810         {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
 811         {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
 812         /* carrizo */
 813         {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 814         {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 815         {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 816         {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 817         {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 818         /* stoney */
 819         {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
 820         /* Polaris11 */
 821         {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 822         {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 823         {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 824         {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 825         {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 826         {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 827         {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 828         {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 829         {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 830         /* Polaris10 */
 831         {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 832         {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 833         {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 834         {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 835         {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 836         {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 837         {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 838         {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 839         {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 840         {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 841         {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 842         {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 843         {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 844         /* Polaris12 */
 845         {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 846         {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 847         {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 848         {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 849         {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 850         {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 851         {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 852         {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 853         /* VEGAM */
 854         {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
 855         {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
 856         /* Vega 10 */
 857         {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 858         {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 859         {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 860         {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 861         {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 862         {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 863         {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 864         {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 865         {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 866         /* Vega 12 */
 867         {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 868         {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 869         {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 870         {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 871         {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 872         /* Vega 20 */
 873         {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 874         {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 875         {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 876         {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 877         {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 878         {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 879         /* Raven */
 880         {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
 881         {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
 882
 883         {0, 0, 0}
 884 };
 885
 886 MODULE_DEVICE_TABLE(pci, pciidlist);
 887
 888 static struct drm_driver kms_driver;
 889
 890 static int amdgpu_pci_probe(struct pci_dev *pdev,
 891                             const struct pci_device_id *ent)
 892 {
 893         struct drm_device *dev;
 894         unsigned long flags = ent->driver_data;
 895         int ret, retry = 0;
 896         bool supports_atomic = false;
 897
 898         if (!amdgpu_virtual_display &&
 899             amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
 900                 supports_atomic = true;
 901
 902         if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
 903                 DRM_INFO("This hardware requires experimental hardware support.\n"
 904                          "See modparam exp_hw_support\n");
 905                 return -ENODEV;
 906         }
 907
 908         /* Get rid of things like offb */
 909         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb");
 910         if (ret)
 911                 return ret;
 912
 913         dev = drm_dev_alloc(&kms_driver, &pdev->dev);
 914         if (IS_ERR(dev))
 915                 return PTR_ERR(dev);
 916
 917         if (!supports_atomic)
 918                 dev->driver_features &= ~DRIVER_ATOMIC;
 919
 920         ret = pci_enable_device(pdev);
 921         if (ret)
 922                 goto err_free;
 923
 924         dev->pdev = pdev;
 925
 926         pci_set_drvdata(pdev, dev);
 927
 928 retry_init:
 929         ret = drm_dev_register(dev, ent->driver_data);
 930         if (ret == -EAGAIN && ++retry <= 3) {
 931                 DRM_INFO("retry init %d\n", retry);
 932                 /* Don't request EX mode too frequently which is attacking */
 933                 msleep(5000);
 934                 goto retry_init;
 935         } else if (ret)
 936                 goto err_pci;
 937
 938         return 0;
 939
 940 err_pci:
 941         pci_disable_device(pdev);
 942 err_free:
 943         drm_dev_put(dev);
 944         return ret;
 945 }
 946
 947 static void
 948 amdgpu_pci_remove(struct pci_dev *pdev)
 949 {
 950         struct drm_device *dev = pci_get_drvdata(pdev);
 951
 952         DRM_ERROR("Device removal is currently not supported outside of fbcon\n");
 953         drm_dev_unplug(dev);
 954         pci_disable_device(pdev);
 955         pci_set_drvdata(pdev, NULL);
 956 }
 957
 958 static void
 959 amdgpu_pci_shutdown(struct pci_dev *pdev)
 960 {
 961         struct drm_device *dev = pci_get_drvdata(pdev);
 962         struct amdgpu_device *adev = dev->dev_private;
 963
 964         /* if we are running in a VM, make sure the device
 965          * torn down properly on reboot/shutdown.
 966          * unfortunately we can't detect certain
 967          * hypervisors so just do this all the time.
 968          */
 969         amdgpu_device_ip_suspend(adev);
 970 }
 971
 972 static int amdgpu_pmops_suspend(struct device *dev)
 973 {
 974         struct pci_dev *pdev = to_pci_dev(dev);
 975
 976         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 977         return amdgpu_device_suspend(drm_dev, true, true);
 978 }
 979
 980 static int amdgpu_pmops_resume(struct device *dev)
 981 {
 982         struct pci_dev *pdev = to_pci_dev(dev);
 983         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 984
 985         /* GPU comes up enabled by the bios on resume */
 986         if (amdgpu_device_is_px(drm_dev)) {
 987                 pm_runtime_disable(dev);
 988                 pm_runtime_set_active(dev);
 989                 pm_runtime_enable(dev);
 990         }
 991
 992         return amdgpu_device_resume(drm_dev, true, true);
 993 }
 994
 995 static int amdgpu_pmops_freeze(struct device *dev)
 996 {
 997         struct pci_dev *pdev = to_pci_dev(dev);
 998
 999         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1000         return amdgpu_device_suspend(drm_dev, false, true);
1001 }
1002
1003 static int amdgpu_pmops_thaw(struct device *dev)
1004 {
1005         struct pci_dev *pdev = to_pci_dev(dev);
1006
1007         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1008         return amdgpu_device_resume(drm_dev, false, true);
1009 }
1010
1011 static int amdgpu_pmops_poweroff(struct device *dev)
1012 {
1013         struct pci_dev *pdev = to_pci_dev(dev);
1014
1015         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1016         return amdgpu_device_suspend(drm_dev, true, true);
1017 }
1018
1019 static int amdgpu_pmops_restore(struct device *dev)
1020 {
1021         struct pci_dev *pdev = to_pci_dev(dev);
1022
1023         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1024         return amdgpu_device_resume(drm_dev, false, true);
1025 }
1026
1027 static int amdgpu_pmops_runtime_suspend(struct device *dev)
1028 {
1029         struct pci_dev *pdev = to_pci_dev(dev);
1030         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1031         int ret;
1032
1033         if (!amdgpu_device_is_px(drm_dev)) {
1034                 pm_runtime_forbid(dev);
1035                 return -EBUSY;
1036         }
1037
1038         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1039         drm_kms_helper_poll_disable(drm_dev);
1040
1041         ret = amdgpu_device_suspend(drm_dev, false, false);
1042         pci_save_state(pdev);
1043         pci_disable_device(pdev);
1044         pci_ignore_hotplug(pdev);
1045         if (amdgpu_is_atpx_hybrid())
1046                 pci_set_power_state(pdev, PCI_D3cold);
1047         else if (!amdgpu_has_atpx_dgpu_power_cntl())
1048                 pci_set_power_state(pdev, PCI_D3hot);
1049         drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1050
1051         return 0;
1052 }
1053
1054 static int amdgpu_pmops_runtime_resume(struct device *dev)
1055 {
1056         struct pci_dev *pdev = to_pci_dev(dev);
1057         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1058         int ret;
1059
1060         if (!amdgpu_device_is_px(drm_dev))
1061                 return -EINVAL;
1062
1063         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1064
1065         if (amdgpu_is_atpx_hybrid() ||
1066             !amdgpu_has_atpx_dgpu_power_cntl())
1067                 pci_set_power_state(pdev, PCI_D0);
1068         pci_restore_state(pdev);
1069         ret = pci_enable_device(pdev);
1070         if (ret)
1071                 return ret;
1072         pci_set_master(pdev);
1073
1074         ret = amdgpu_device_resume(drm_dev, false, false);
1075         drm_kms_helper_poll_enable(drm_dev);
1076         drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1077         return 0;
1078 }
1079
1080 static int amdgpu_pmops_runtime_idle(struct device *dev)
1081 {
1082         struct pci_dev *pdev = to_pci_dev(dev);
1083         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1084         struct drm_crtc *crtc;
1085
1086         if (!amdgpu_device_is_px(drm_dev)) {
1087                 pm_runtime_forbid(dev);
1088                 return -EBUSY;
1089         }
1090
1091         list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
1092                 if (crtc->enabled) {
1093                         DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1094                         return -EBUSY;
1095                 }
1096         }
1097
1098         pm_runtime_mark_last_busy(dev);
1099         pm_runtime_autosuspend(dev);
1100         /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1101         return 1;
1102 }
1103
1104 long amdgpu_drm_ioctl(struct file *filp,
1105                       unsigned int cmd, unsigned long arg)
1106 {
1107         struct drm_file *file_priv = filp->private_data;
1108         struct drm_device *dev;
1109         long ret;
1110         dev = file_priv->minor->dev;
1111         ret = pm_runtime_get_sync(dev->dev);
1112         if (ret < 0)
1113                 return ret;
1114
1115         ret = drm_ioctl(filp, cmd, arg);
1116
1117         pm_runtime_mark_last_busy(dev->dev);
1118         pm_runtime_put_autosuspend(dev->dev);
1119         return ret;
1120 }
1121
1122 static const struct dev_pm_ops amdgpu_pm_ops = {
1123         .suspend = amdgpu_pmops_suspend,
1124         .resume = amdgpu_pmops_resume,
1125         .freeze = amdgpu_pmops_freeze,
1126         .thaw = amdgpu_pmops_thaw,
1127         .poweroff = amdgpu_pmops_poweroff,
1128         .restore = amdgpu_pmops_restore,
1129         .runtime_suspend = amdgpu_pmops_runtime_suspend,
1130         .runtime_resume = amdgpu_pmops_runtime_resume,
1131         .runtime_idle = amdgpu_pmops_runtime_idle,
1132 };
1133
1134 static int amdgpu_flush(struct file *f, fl_owner_t id)
1135 {
1136         struct drm_file *file_priv = f->private_data;
1137         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1138
1139         amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr);
1140
1141         return 0;
1142 }
1143
1144
1145 static const struct file_operations amdgpu_driver_kms_fops = {
1146         .owner = THIS_MODULE,
1147         .open = drm_open,
1148         .flush = amdgpu_flush,
1149         .release = drm_release,
1150         .unlocked_ioctl = amdgpu_drm_ioctl,
1151         .mmap = amdgpu_mmap,
1152         .poll = drm_poll,
1153         .read = drm_read,
1154 #ifdef CONFIG_COMPAT
1155         .compat_ioctl = amdgpu_kms_compat_ioctl,
1156 #endif
1157 };
1158
1159 static bool
1160 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
1161                                  bool in_vblank_irq, int *vpos, int *hpos,
1162                                  ktime_t *stime, ktime_t *etime,
1163                                  const struct drm_display_mode *mode)
1164 {
1165         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1166                                                   stime, etime, mode);
1167 }
1168
1169 static struct drm_driver kms_driver = {
1170         .driver_features =
1171             DRIVER_USE_AGP | DRIVER_ATOMIC |
1172             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
1173             DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
1174         .load = amdgpu_driver_load_kms,
1175         .open = amdgpu_driver_open_kms,
1176         .postclose = amdgpu_driver_postclose_kms,
1177         .lastclose = amdgpu_driver_lastclose_kms,
1178         .unload = amdgpu_driver_unload_kms,
1179         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
1180         .enable_vblank = amdgpu_enable_vblank_kms,
1181         .disable_vblank = amdgpu_disable_vblank_kms,
1182         .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
1183         .get_scanout_position = amdgpu_get_crtc_scanout_position,
1184         .irq_handler = amdgpu_irq_handler,
1185         .ioctls = amdgpu_ioctls_kms,
1186         .gem_free_object_unlocked = amdgpu_gem_object_free,
1187         .gem_open_object = amdgpu_gem_object_open,
1188         .gem_close_object = amdgpu_gem_object_close,
1189         .dumb_create = amdgpu_mode_dumb_create,
1190         .dumb_map_offset = amdgpu_mode_dumb_mmap,
1191         .fops = &amdgpu_driver_kms_fops,
1192
1193         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1194         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1195         .gem_prime_export = amdgpu_gem_prime_export,
1196         .gem_prime_import = amdgpu_gem_prime_import,
1197         .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
1198         .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
1199         .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
1200         .gem_prime_vmap = amdgpu_gem_prime_vmap,
1201         .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
1202         .gem_prime_mmap = amdgpu_gem_prime_mmap,
1203
1204         .name = DRIVER_NAME,
1205         .desc = DRIVER_DESC,
1206         .date = DRIVER_DATE,
1207         .major = KMS_DRIVER_MAJOR,
1208         .minor = KMS_DRIVER_MINOR,
1209         .patchlevel = KMS_DRIVER_PATCHLEVEL,
1210 };
1211
1212 static struct drm_driver *driver;
1213 static struct pci_driver *pdriver;
1214
1215 static struct pci_driver amdgpu_kms_pci_driver = {
1216         .name = DRIVER_NAME,
1217         .id_table = pciidlist,
1218         .probe = amdgpu_pci_probe,
1219         .remove = amdgpu_pci_remove,
1220         .shutdown = amdgpu_pci_shutdown,
1221         .driver.pm = &amdgpu_pm_ops,
1222 };
1223
1224
1225
1226 static int __init amdgpu_init(void)
1227 {
1228         int r;
1229
1230         if (vgacon_text_force()) {
1231                 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1232                 return -EINVAL;
1233         }
1234
1235         r = amdgpu_sync_init();
1236         if (r)
1237                 goto error_sync;
1238
1239         r = amdgpu_fence_slab_init();
1240         if (r)
1241                 goto error_fence;
1242
1243         DRM_INFO("amdgpu kernel modesetting enabled.\n");
1244         driver = &kms_driver;
1245         pdriver = &amdgpu_kms_pci_driver;
1246         driver->num_ioctls = amdgpu_max_kms_ioctl;
1247         amdgpu_register_atpx_handler();
1248
1249         /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
1250         amdgpu_amdkfd_init();
1251
1252         /* let modprobe override vga console setting */
1253         return pci_register_driver(pdriver);
1254
1255 error_fence:
1256         amdgpu_sync_fini();
1257
1258 error_sync:
1259         return r;
1260 }
1261
1262 static void __exit amdgpu_exit(void)
1263 {
1264         amdgpu_amdkfd_fini();
1265         pci_unregister_driver(pdriver);
1266         amdgpu_unregister_atpx_handler();
1267         amdgpu_sync_fini();
1268         amdgpu_fence_slab_fini();
1269 }
1270
1271 module_init(amdgpu_init);
1272 module_exit(amdgpu_exit);
1273
1274 MODULE_AUTHOR(DRIVER_AUTHOR);
1275 MODULE_DESCRIPTION(DRIVER_DESC);
1276 MODULE_LICENSE("GPL and additional rights");