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[people/ms/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_psp.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26 #include <linux/firmware.h>
27 #include <drm/drm_drv.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_xgmi.h"
33 #include "soc15_common.h"
34 #include "psp_v3_1.h"
35 #include "psp_v10_0.h"
36 #include "psp_v11_0.h"
37 #include "psp_v11_0_8.h"
38 #include "psp_v12_0.h"
39 #include "psp_v13_0.h"
40 #include "psp_v13_0_4.h"
41
42 #include "amdgpu_ras.h"
43 #include "amdgpu_securedisplay.h"
44 #include "amdgpu_atomfirmware.h"
45
46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3)
47
48 static int psp_sysfs_init(struct amdgpu_device *adev);
49 static void psp_sysfs_fini(struct amdgpu_device *adev);
50
51 static int psp_load_smu_fw(struct psp_context *psp);
52 static int psp_rap_terminate(struct psp_context *psp);
53 static int psp_securedisplay_terminate(struct psp_context *psp);
54
55 /*
56 * Due to DF Cstate management centralized to PMFW, the firmware
57 * loading sequence will be updated as below:
58 * - Load KDB
59 * - Load SYS_DRV
60 * - Load tOS
61 * - Load PMFW
62 * - Setup TMR
63 * - Load other non-psp fw
64 * - Load ASD
65 * - Load XGMI/RAS/HDCP/DTM TA if any
66 *
67 * This new sequence is required for
68 * - Arcturus and onwards
69 */
70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
71 {
72 struct amdgpu_device *adev = psp->adev;
73
74 if (amdgpu_sriov_vf(adev)) {
75 psp->pmfw_centralized_cstate_management = false;
76 return;
77 }
78
79 switch (adev->ip_versions[MP0_HWIP][0]) {
80 case IP_VERSION(11, 0, 0):
81 case IP_VERSION(11, 0, 4):
82 case IP_VERSION(11, 0, 5):
83 case IP_VERSION(11, 0, 7):
84 case IP_VERSION(11, 0, 9):
85 case IP_VERSION(11, 0, 11):
86 case IP_VERSION(11, 0, 12):
87 case IP_VERSION(11, 0, 13):
88 case IP_VERSION(13, 0, 0):
89 case IP_VERSION(13, 0, 2):
90 case IP_VERSION(13, 0, 7):
91 psp->pmfw_centralized_cstate_management = true;
92 break;
93 default:
94 psp->pmfw_centralized_cstate_management = false;
95 break;
96 }
97 }
98
99 static int psp_early_init(void *handle)
100 {
101 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
102 struct psp_context *psp = &adev->psp;
103
104 switch (adev->ip_versions[MP0_HWIP][0]) {
105 case IP_VERSION(9, 0, 0):
106 psp_v3_1_set_psp_funcs(psp);
107 psp->autoload_supported = false;
108 break;
109 case IP_VERSION(10, 0, 0):
110 case IP_VERSION(10, 0, 1):
111 psp_v10_0_set_psp_funcs(psp);
112 psp->autoload_supported = false;
113 break;
114 case IP_VERSION(11, 0, 2):
115 case IP_VERSION(11, 0, 4):
116 psp_v11_0_set_psp_funcs(psp);
117 psp->autoload_supported = false;
118 break;
119 case IP_VERSION(11, 0, 0):
120 case IP_VERSION(11, 0, 5):
121 case IP_VERSION(11, 0, 9):
122 case IP_VERSION(11, 0, 7):
123 case IP_VERSION(11, 0, 11):
124 case IP_VERSION(11, 5, 0):
125 case IP_VERSION(11, 0, 12):
126 case IP_VERSION(11, 0, 13):
127 psp_v11_0_set_psp_funcs(psp);
128 psp->autoload_supported = true;
129 break;
130 case IP_VERSION(11, 0, 3):
131 case IP_VERSION(12, 0, 1):
132 psp_v12_0_set_psp_funcs(psp);
133 break;
134 case IP_VERSION(13, 0, 2):
135 psp_v13_0_set_psp_funcs(psp);
136 break;
137 case IP_VERSION(13, 0, 1):
138 case IP_VERSION(13, 0, 3):
139 case IP_VERSION(13, 0, 5):
140 case IP_VERSION(13, 0, 8):
141 psp_v13_0_set_psp_funcs(psp);
142 psp->autoload_supported = true;
143 break;
144 case IP_VERSION(11, 0, 8):
145 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
146 psp_v11_0_8_set_psp_funcs(psp);
147 psp->autoload_supported = false;
148 }
149 break;
150 case IP_VERSION(13, 0, 0):
151 case IP_VERSION(13, 0, 7):
152 psp_v13_0_set_psp_funcs(psp);
153 psp->autoload_supported = true;
154 break;
155 case IP_VERSION(13, 0, 4):
156 psp_v13_0_4_set_psp_funcs(psp);
157 psp->autoload_supported = true;
158 break;
159 default:
160 return -EINVAL;
161 }
162
163 psp->adev = adev;
164
165 psp_check_pmfw_centralized_cstate_management(psp);
166
167 return 0;
168 }
169
170 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
171 {
172 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
173 &mem_ctx->shared_buf);
174 }
175
176 static void psp_free_shared_bufs(struct psp_context *psp)
177 {
178 void *tmr_buf;
179 void **pptr;
180
181 /* free TMR memory buffer */
182 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
183 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
184
185 /* free xgmi shared memory */
186 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
187
188 /* free ras shared memory */
189 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
190
191 /* free hdcp shared memory */
192 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
193
194 /* free dtm shared memory */
195 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
196
197 /* free rap shared memory */
198 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
199
200 /* free securedisplay shared memory */
201 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
202
203
204 }
205
206 static void psp_memory_training_fini(struct psp_context *psp)
207 {
208 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
209
210 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
211 kfree(ctx->sys_cache);
212 ctx->sys_cache = NULL;
213 }
214
215 static int psp_memory_training_init(struct psp_context *psp)
216 {
217 int ret;
218 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
219
220 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
221 DRM_DEBUG("memory training is not supported!\n");
222 return 0;
223 }
224
225 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
226 if (ctx->sys_cache == NULL) {
227 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
228 ret = -ENOMEM;
229 goto Err_out;
230 }
231
232 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
233 ctx->train_data_size,
234 ctx->p2c_train_data_offset,
235 ctx->c2p_train_data_offset);
236 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
237 return 0;
238
239 Err_out:
240 psp_memory_training_fini(psp);
241 return ret;
242 }
243
244 /*
245 * Helper funciton to query psp runtime database entry
246 *
247 * @adev: amdgpu_device pointer
248 * @entry_type: the type of psp runtime database entry
249 * @db_entry: runtime database entry pointer
250 *
251 * Return false if runtime database doesn't exit or entry is invalid
252 * or true if the specific database entry is found, and copy to @db_entry
253 */
254 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
255 enum psp_runtime_entry_type entry_type,
256 void *db_entry)
257 {
258 uint64_t db_header_pos, db_dir_pos;
259 struct psp_runtime_data_header db_header = {0};
260 struct psp_runtime_data_directory db_dir = {0};
261 bool ret = false;
262 int i;
263
264 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
265 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
266
267 /* read runtime db header from vram */
268 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
269 sizeof(struct psp_runtime_data_header), false);
270
271 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
272 /* runtime db doesn't exist, exit */
273 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
274 return false;
275 }
276
277 /* read runtime database entry from vram */
278 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
279 sizeof(struct psp_runtime_data_directory), false);
280
281 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
282 /* invalid db entry count, exit */
283 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
284 return false;
285 }
286
287 /* look up for requested entry type */
288 for (i = 0; i < db_dir.entry_count && !ret; i++) {
289 if (db_dir.entry_list[i].entry_type == entry_type) {
290 switch (entry_type) {
291 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
292 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
293 /* invalid db entry size */
294 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
295 return false;
296 }
297 /* read runtime database entry */
298 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
299 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
300 ret = true;
301 break;
302 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
303 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
304 /* invalid db entry size */
305 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
306 return false;
307 }
308 /* read runtime database entry */
309 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
310 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
311 ret = true;
312 break;
313 default:
314 ret = false;
315 break;
316 }
317 }
318 }
319
320 return ret;
321 }
322
323 static int psp_init_sriov_microcode(struct psp_context *psp)
324 {
325 struct amdgpu_device *adev = psp->adev;
326 int ret = 0;
327
328 switch (adev->ip_versions[MP0_HWIP][0]) {
329 case IP_VERSION(9, 0, 0):
330 ret = psp_init_cap_microcode(psp, "vega10");
331 break;
332 case IP_VERSION(11, 0, 9):
333 ret = psp_init_cap_microcode(psp, "navi12");
334 break;
335 case IP_VERSION(11, 0, 7):
336 ret = psp_init_cap_microcode(psp, "sienna_cichlid");
337 break;
338 case IP_VERSION(13, 0, 2):
339 ret = psp_init_cap_microcode(psp, "aldebaran");
340 ret &= psp_init_ta_microcode(psp, "aldebaran");
341 break;
342 default:
343 BUG();
344 break;
345 }
346
347 return ret;
348 }
349
350 static int psp_sw_init(void *handle)
351 {
352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
353 struct psp_context *psp = &adev->psp;
354 int ret;
355 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
356 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
357 struct psp_runtime_scpm_entry scpm_entry;
358
359 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
360 if (!psp->cmd) {
361 DRM_ERROR("Failed to allocate memory to command buffer!\n");
362 ret = -ENOMEM;
363 }
364
365 if (amdgpu_sriov_vf(adev))
366 ret = psp_init_sriov_microcode(psp);
367 else
368 ret = psp_init_microcode(psp);
369 if (ret) {
370 DRM_ERROR("Failed to load psp firmware!\n");
371 return ret;
372 }
373
374 adev->psp.xgmi_context.supports_extended_data =
375 !adev->gmc.xgmi.connected_to_cpu &&
376 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
377
378 memset(&scpm_entry, 0, sizeof(scpm_entry));
379 if ((psp_get_runtime_db_entry(adev,
380 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
381 &scpm_entry)) &&
382 (SCPM_DISABLE != scpm_entry.scpm_status)) {
383 adev->scpm_enabled = true;
384 adev->scpm_status = scpm_entry.scpm_status;
385 } else {
386 adev->scpm_enabled = false;
387 adev->scpm_status = SCPM_DISABLE;
388 }
389
390 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
391
392 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
393 if (psp_get_runtime_db_entry(adev,
394 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
395 &boot_cfg_entry)) {
396 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
397 if ((psp->boot_cfg_bitmask) &
398 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
399 /* If psp runtime database exists, then
400 * only enable two stage memory training
401 * when TWO_STAGE_DRAM_TRAINING bit is set
402 * in runtime database */
403 mem_training_ctx->enable_mem_training = true;
404 }
405
406 } else {
407 /* If psp runtime database doesn't exist or
408 * is invalid, force enable two stage memory
409 * training */
410 mem_training_ctx->enable_mem_training = true;
411 }
412
413 if (mem_training_ctx->enable_mem_training) {
414 ret = psp_memory_training_init(psp);
415 if (ret) {
416 DRM_ERROR("Failed to initialize memory training!\n");
417 return ret;
418 }
419
420 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
421 if (ret) {
422 DRM_ERROR("Failed to process memory training!\n");
423 return ret;
424 }
425 }
426
427 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
428 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
429 ret= psp_sysfs_init(adev);
430 if (ret) {
431 return ret;
432 }
433 }
434
435 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
436 amdgpu_sriov_vf(adev) ?
437 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
438 &psp->fw_pri_bo,
439 &psp->fw_pri_mc_addr,
440 &psp->fw_pri_buf);
441 if (ret)
442 return ret;
443
444 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
445 AMDGPU_GEM_DOMAIN_VRAM,
446 &psp->fence_buf_bo,
447 &psp->fence_buf_mc_addr,
448 &psp->fence_buf);
449 if (ret)
450 goto failed1;
451
452 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
453 AMDGPU_GEM_DOMAIN_VRAM,
454 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
455 (void **)&psp->cmd_buf_mem);
456 if (ret)
457 goto failed2;
458
459 return 0;
460
461 failed2:
462 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
463 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
464 failed1:
465 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
466 &psp->fence_buf_mc_addr, &psp->fence_buf);
467 return ret;
468 }
469
470 static int psp_sw_fini(void *handle)
471 {
472 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
473 struct psp_context *psp = &adev->psp;
474 struct psp_gfx_cmd_resp *cmd = psp->cmd;
475
476 psp_memory_training_fini(psp);
477 if (psp->sos_fw) {
478 release_firmware(psp->sos_fw);
479 psp->sos_fw = NULL;
480 }
481 if (psp->asd_fw) {
482 release_firmware(psp->asd_fw);
483 psp->asd_fw = NULL;
484 }
485 if (psp->ta_fw) {
486 release_firmware(psp->ta_fw);
487 psp->ta_fw = NULL;
488 }
489 if (adev->psp.cap_fw) {
490 release_firmware(psp->cap_fw);
491 psp->cap_fw = NULL;
492 }
493
494 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
495 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
496 psp_sysfs_fini(adev);
497
498 kfree(cmd);
499 cmd = NULL;
500
501 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
502 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
503 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
504 &psp->fence_buf_mc_addr, &psp->fence_buf);
505 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
506 (void **)&psp->cmd_buf_mem);
507
508 return 0;
509 }
510
511 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
512 uint32_t reg_val, uint32_t mask, bool check_changed)
513 {
514 uint32_t val;
515 int i;
516 struct amdgpu_device *adev = psp->adev;
517
518 if (psp->adev->no_hw_access)
519 return 0;
520
521 for (i = 0; i < adev->usec_timeout; i++) {
522 val = RREG32(reg_index);
523 if (check_changed) {
524 if (val != reg_val)
525 return 0;
526 } else {
527 if ((val & mask) == reg_val)
528 return 0;
529 }
530 udelay(1);
531 }
532
533 return -ETIME;
534 }
535
536 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
537 {
538 switch (cmd_id) {
539 case GFX_CMD_ID_LOAD_TA:
540 return "LOAD_TA";
541 case GFX_CMD_ID_UNLOAD_TA:
542 return "UNLOAD_TA";
543 case GFX_CMD_ID_INVOKE_CMD:
544 return "INVOKE_CMD";
545 case GFX_CMD_ID_LOAD_ASD:
546 return "LOAD_ASD";
547 case GFX_CMD_ID_SETUP_TMR:
548 return "SETUP_TMR";
549 case GFX_CMD_ID_LOAD_IP_FW:
550 return "LOAD_IP_FW";
551 case GFX_CMD_ID_DESTROY_TMR:
552 return "DESTROY_TMR";
553 case GFX_CMD_ID_SAVE_RESTORE:
554 return "SAVE_RESTORE_IP_FW";
555 case GFX_CMD_ID_SETUP_VMR:
556 return "SETUP_VMR";
557 case GFX_CMD_ID_DESTROY_VMR:
558 return "DESTROY_VMR";
559 case GFX_CMD_ID_PROG_REG:
560 return "PROG_REG";
561 case GFX_CMD_ID_GET_FW_ATTESTATION:
562 return "GET_FW_ATTESTATION";
563 case GFX_CMD_ID_LOAD_TOC:
564 return "ID_LOAD_TOC";
565 case GFX_CMD_ID_AUTOLOAD_RLC:
566 return "AUTOLOAD_RLC";
567 case GFX_CMD_ID_BOOT_CFG:
568 return "BOOT_CFG";
569 default:
570 return "UNKNOWN CMD";
571 }
572 }
573
574 static int
575 psp_cmd_submit_buf(struct psp_context *psp,
576 struct amdgpu_firmware_info *ucode,
577 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
578 {
579 int ret;
580 int index, idx;
581 int timeout = 20000;
582 bool ras_intr = false;
583 bool skip_unsupport = false;
584
585 if (psp->adev->no_hw_access)
586 return 0;
587
588 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
589 return 0;
590
591 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
592
593 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
594
595 index = atomic_inc_return(&psp->fence_value);
596 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
597 if (ret) {
598 atomic_dec(&psp->fence_value);
599 goto exit;
600 }
601
602 amdgpu_device_invalidate_hdp(psp->adev, NULL);
603 while (*((unsigned int *)psp->fence_buf) != index) {
604 if (--timeout == 0)
605 break;
606 /*
607 * Shouldn't wait for timeout when err_event_athub occurs,
608 * because gpu reset thread triggered and lock resource should
609 * be released for psp resume sequence.
610 */
611 ras_intr = amdgpu_ras_intr_triggered();
612 if (ras_intr)
613 break;
614 usleep_range(10, 100);
615 amdgpu_device_invalidate_hdp(psp->adev, NULL);
616 }
617
618 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
619 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
620 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
621
622 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
623
624 /* In some cases, psp response status is not 0 even there is no
625 * problem while the command is submitted. Some version of PSP FW
626 * doesn't write 0 to that field.
627 * So here we would like to only print a warning instead of an error
628 * during psp initialization to avoid breaking hw_init and it doesn't
629 * return -EINVAL.
630 */
631 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
632 if (ucode)
633 DRM_WARN("failed to load ucode %s(0x%X) ",
634 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
635 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
636 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
637 psp->cmd_buf_mem->resp.status);
638 /* If any firmware (including CAP) load fails under SRIOV, it should
639 * return failure to stop the VF from initializing.
640 * Also return failure in case of timeout
641 */
642 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
643 ret = -EINVAL;
644 goto exit;
645 }
646 }
647
648 if (ucode) {
649 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
650 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
651 }
652
653 exit:
654 drm_dev_exit(idx);
655 return ret;
656 }
657
658 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
659 {
660 struct psp_gfx_cmd_resp *cmd = psp->cmd;
661
662 mutex_lock(&psp->mutex);
663
664 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
665
666 return cmd;
667 }
668
669 static void release_psp_cmd_buf(struct psp_context *psp)
670 {
671 mutex_unlock(&psp->mutex);
672 }
673
674 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
675 struct psp_gfx_cmd_resp *cmd,
676 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
677 {
678 struct amdgpu_device *adev = psp->adev;
679 uint32_t size = amdgpu_bo_size(tmr_bo);
680 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
681
682 if (amdgpu_sriov_vf(psp->adev))
683 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
684 else
685 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
686 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
687 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
688 cmd->cmd.cmd_setup_tmr.buf_size = size;
689 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
690 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
691 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
692 }
693
694 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
695 uint64_t pri_buf_mc, uint32_t size)
696 {
697 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
698 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
699 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
700 cmd->cmd.cmd_load_toc.toc_size = size;
701 }
702
703 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
704 static int psp_load_toc(struct psp_context *psp,
705 uint32_t *tmr_size)
706 {
707 int ret;
708 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
709
710 /* Copy toc to psp firmware private buffer */
711 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
712
713 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
714
715 ret = psp_cmd_submit_buf(psp, NULL, cmd,
716 psp->fence_buf_mc_addr);
717 if (!ret)
718 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
719
720 release_psp_cmd_buf(psp);
721
722 return ret;
723 }
724
725 /* Set up Trusted Memory Region */
726 static int psp_tmr_init(struct psp_context *psp)
727 {
728 int ret;
729 int tmr_size;
730 void *tmr_buf;
731 void **pptr;
732
733 /*
734 * According to HW engineer, they prefer the TMR address be "naturally
735 * aligned" , e.g. the start address be an integer divide of TMR size.
736 *
737 * Note: this memory need be reserved till the driver
738 * uninitializes.
739 */
740 tmr_size = PSP_TMR_SIZE(psp->adev);
741
742 /* For ASICs support RLC autoload, psp will parse the toc
743 * and calculate the total size of TMR needed */
744 if (!amdgpu_sriov_vf(psp->adev) &&
745 psp->toc.start_addr &&
746 psp->toc.size_bytes &&
747 psp->fw_pri_buf) {
748 ret = psp_load_toc(psp, &tmr_size);
749 if (ret) {
750 DRM_ERROR("Failed to load toc\n");
751 return ret;
752 }
753 }
754
755 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
756 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
757 AMDGPU_GEM_DOMAIN_VRAM,
758 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
759
760 return ret;
761 }
762
763 static bool psp_skip_tmr(struct psp_context *psp)
764 {
765 switch (psp->adev->ip_versions[MP0_HWIP][0]) {
766 case IP_VERSION(11, 0, 9):
767 case IP_VERSION(11, 0, 7):
768 case IP_VERSION(13, 0, 2):
769 return true;
770 default:
771 return false;
772 }
773 }
774
775 static int psp_tmr_load(struct psp_context *psp)
776 {
777 int ret;
778 struct psp_gfx_cmd_resp *cmd;
779
780 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
781 * Already set up by host driver.
782 */
783 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
784 return 0;
785
786 cmd = acquire_psp_cmd_buf(psp);
787
788 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
789 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
790 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
791
792 ret = psp_cmd_submit_buf(psp, NULL, cmd,
793 psp->fence_buf_mc_addr);
794
795 release_psp_cmd_buf(psp);
796
797 return ret;
798 }
799
800 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
801 struct psp_gfx_cmd_resp *cmd)
802 {
803 if (amdgpu_sriov_vf(psp->adev))
804 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
805 else
806 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
807 }
808
809 static int psp_tmr_unload(struct psp_context *psp)
810 {
811 int ret;
812 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
813
814 psp_prep_tmr_unload_cmd_buf(psp, cmd);
815 DRM_INFO("free PSP TMR buffer\n");
816
817 ret = psp_cmd_submit_buf(psp, NULL, cmd,
818 psp->fence_buf_mc_addr);
819
820 release_psp_cmd_buf(psp);
821
822 return ret;
823 }
824
825 static int psp_tmr_terminate(struct psp_context *psp)
826 {
827 return psp_tmr_unload(psp);
828 }
829
830 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
831 uint64_t *output_ptr)
832 {
833 int ret;
834 struct psp_gfx_cmd_resp *cmd;
835
836 if (!output_ptr)
837 return -EINVAL;
838
839 if (amdgpu_sriov_vf(psp->adev))
840 return 0;
841
842 cmd = acquire_psp_cmd_buf(psp);
843
844 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
845
846 ret = psp_cmd_submit_buf(psp, NULL, cmd,
847 psp->fence_buf_mc_addr);
848
849 if (!ret) {
850 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
851 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
852 }
853
854 release_psp_cmd_buf(psp);
855
856 return ret;
857 }
858
859 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
860 {
861 struct psp_context *psp = &adev->psp;
862 struct psp_gfx_cmd_resp *cmd;
863 int ret;
864
865 if (amdgpu_sriov_vf(adev))
866 return 0;
867
868 cmd = acquire_psp_cmd_buf(psp);
869
870 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
871 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
872
873 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
874 if (!ret) {
875 *boot_cfg =
876 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
877 }
878
879 release_psp_cmd_buf(psp);
880
881 return ret;
882 }
883
884 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
885 {
886 int ret;
887 struct psp_context *psp = &adev->psp;
888 struct psp_gfx_cmd_resp *cmd;
889
890 if (amdgpu_sriov_vf(adev))
891 return 0;
892
893 cmd = acquire_psp_cmd_buf(psp);
894
895 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
896 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
897 cmd->cmd.boot_cfg.boot_config = boot_cfg;
898 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
899
900 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
901
902 release_psp_cmd_buf(psp);
903
904 return ret;
905 }
906
907 static int psp_rl_load(struct amdgpu_device *adev)
908 {
909 int ret;
910 struct psp_context *psp = &adev->psp;
911 struct psp_gfx_cmd_resp *cmd;
912
913 if (!is_psp_fw_valid(psp->rl))
914 return 0;
915
916 cmd = acquire_psp_cmd_buf(psp);
917
918 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
919 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
920
921 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
922 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
923 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
924 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
925 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
926
927 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
928
929 release_psp_cmd_buf(psp);
930
931 return ret;
932 }
933
934 static int psp_asd_initialize(struct psp_context *psp)
935 {
936 int ret;
937
938 /* If PSP version doesn't match ASD version, asd loading will be failed.
939 * add workaround to bypass it for sriov now.
940 * TODO: add version check to make it common
941 */
942 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
943 return 0;
944
945 psp->asd_context.mem_context.shared_mc_addr = 0;
946 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
947 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD;
948
949 ret = psp_ta_load(psp, &psp->asd_context);
950 if (!ret)
951 psp->asd_context.initialized = true;
952
953 return ret;
954 }
955
956 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
957 uint32_t session_id)
958 {
959 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
960 cmd->cmd.cmd_unload_ta.session_id = session_id;
961 }
962
963 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
964 {
965 int ret;
966 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
967
968 psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
969
970 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
971
972 release_psp_cmd_buf(psp);
973
974 return ret;
975 }
976
977 static int psp_asd_terminate(struct psp_context *psp)
978 {
979 int ret;
980
981 if (amdgpu_sriov_vf(psp->adev))
982 return 0;
983
984 if (!psp->asd_context.initialized)
985 return 0;
986
987 ret = psp_ta_unload(psp, &psp->asd_context);
988 if (!ret)
989 psp->asd_context.initialized = false;
990
991 return ret;
992 }
993
994 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
995 uint32_t id, uint32_t value)
996 {
997 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
998 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
999 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1000 }
1001
1002 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1003 uint32_t value)
1004 {
1005 struct psp_gfx_cmd_resp *cmd;
1006 int ret = 0;
1007
1008 if (reg >= PSP_REG_LAST)
1009 return -EINVAL;
1010
1011 cmd = acquire_psp_cmd_buf(psp);
1012
1013 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1014 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1015 if (ret)
1016 DRM_ERROR("PSP failed to program reg id %d", reg);
1017
1018 release_psp_cmd_buf(psp);
1019
1020 return ret;
1021 }
1022
1023 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1024 uint64_t ta_bin_mc,
1025 struct ta_context *context)
1026 {
1027 cmd->cmd_id = context->ta_load_type;
1028 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
1029 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
1030 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;
1031
1032 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1033 lower_32_bits(context->mem_context.shared_mc_addr);
1034 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1035 upper_32_bits(context->mem_context.shared_mc_addr);
1036 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1037 }
1038
1039 int psp_ta_init_shared_buf(struct psp_context *psp,
1040 struct ta_mem_context *mem_ctx)
1041 {
1042 /*
1043 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1044 * physical) for ta to host memory
1045 */
1046 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1047 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1048 &mem_ctx->shared_bo,
1049 &mem_ctx->shared_mc_addr,
1050 &mem_ctx->shared_buf);
1051 }
1052
1053 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1054 uint32_t ta_cmd_id,
1055 struct ta_context *context)
1056 {
1057 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1058 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id;
1059 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1060
1061 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1;
1062 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size;
1063 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size;
1064 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo =
1065 lower_32_bits(context->mem_context.shared_mc_addr);
1066 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi =
1067 upper_32_bits(context->mem_context.shared_mc_addr);
1068 }
1069
1070 int psp_ta_invoke_indirect(struct psp_context *psp,
1071 uint32_t ta_cmd_id,
1072 struct ta_context *context)
1073 {
1074 int ret;
1075 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1076
1077 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context);
1078
1079 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1080 psp->fence_buf_mc_addr);
1081
1082 context->resp_status = cmd->resp.status;
1083
1084 release_psp_cmd_buf(psp);
1085
1086 return ret;
1087 }
1088
1089 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1090 uint32_t ta_cmd_id,
1091 uint32_t session_id)
1092 {
1093 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1094 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
1095 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1096 }
1097
1098 int psp_ta_invoke(struct psp_context *psp,
1099 uint32_t ta_cmd_id,
1100 struct ta_context *context)
1101 {
1102 int ret;
1103 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1104
1105 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1106
1107 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1108 psp->fence_buf_mc_addr);
1109
1110 context->resp_status = cmd->resp.status;
1111
1112 release_psp_cmd_buf(psp);
1113
1114 return ret;
1115 }
1116
1117 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1118 {
1119 int ret;
1120 struct psp_gfx_cmd_resp *cmd;
1121
1122 cmd = acquire_psp_cmd_buf(psp);
1123
1124 psp_copy_fw(psp, context->bin_desc.start_addr,
1125 context->bin_desc.size_bytes);
1126
1127 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1128
1129 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1130 psp->fence_buf_mc_addr);
1131
1132 context->resp_status = cmd->resp.status;
1133
1134 if (!ret) {
1135 context->session_id = cmd->resp.session_id;
1136 }
1137
1138 release_psp_cmd_buf(psp);
1139
1140 return ret;
1141 }
1142
1143 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1144 {
1145 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1146 }
1147
1148 int psp_xgmi_terminate(struct psp_context *psp)
1149 {
1150 int ret;
1151 struct amdgpu_device *adev = psp->adev;
1152
1153 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1154 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1155 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1156 adev->gmc.xgmi.connected_to_cpu))
1157 return 0;
1158
1159 if (!psp->xgmi_context.context.initialized)
1160 return 0;
1161
1162 ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1163
1164 psp->xgmi_context.context.initialized = false;
1165
1166 return ret;
1167 }
1168
1169 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1170 {
1171 struct ta_xgmi_shared_memory *xgmi_cmd;
1172 int ret;
1173
1174 if (!psp->ta_fw ||
1175 !psp->xgmi_context.context.bin_desc.size_bytes ||
1176 !psp->xgmi_context.context.bin_desc.start_addr)
1177 return -ENOENT;
1178
1179 if (!load_ta)
1180 goto invoke;
1181
1182 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1183 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1184
1185 if (!psp->xgmi_context.context.mem_context.shared_buf) {
1186 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1187 if (ret)
1188 return ret;
1189 }
1190
1191 /* Load XGMI TA */
1192 ret = psp_ta_load(psp, &psp->xgmi_context.context);
1193 if (!ret)
1194 psp->xgmi_context.context.initialized = true;
1195 else
1196 return ret;
1197
1198 invoke:
1199 /* Initialize XGMI session */
1200 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1201 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1202 xgmi_cmd->flag_extend_link_record = set_extended_data;
1203 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1204
1205 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1206
1207 return ret;
1208 }
1209
1210 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1211 {
1212 struct ta_xgmi_shared_memory *xgmi_cmd;
1213 int ret;
1214
1215 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1216 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1217
1218 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1219
1220 /* Invoke xgmi ta to get hive id */
1221 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1222 if (ret)
1223 return ret;
1224
1225 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1226
1227 return 0;
1228 }
1229
1230 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1231 {
1232 struct ta_xgmi_shared_memory *xgmi_cmd;
1233 int ret;
1234
1235 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1236 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1237
1238 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1239
1240 /* Invoke xgmi ta to get the node id */
1241 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1242 if (ret)
1243 return ret;
1244
1245 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1246
1247 return 0;
1248 }
1249
1250 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1251 {
1252 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1253 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1254 }
1255
1256 /*
1257 * Chips that support extended topology information require the driver to
1258 * reflect topology information in the opposite direction. This is
1259 * because the TA has already exceeded its link record limit and if the
1260 * TA holds bi-directional information, the driver would have to do
1261 * multiple fetches instead of just two.
1262 */
1263 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1264 struct psp_xgmi_node_info node_info)
1265 {
1266 struct amdgpu_device *mirror_adev;
1267 struct amdgpu_hive_info *hive;
1268 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1269 uint64_t dst_node_id = node_info.node_id;
1270 uint8_t dst_num_hops = node_info.num_hops;
1271 uint8_t dst_num_links = node_info.num_links;
1272
1273 hive = amdgpu_get_xgmi_hive(psp->adev);
1274 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1275 struct psp_xgmi_topology_info *mirror_top_info;
1276 int j;
1277
1278 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1279 continue;
1280
1281 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1282 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1283 if (mirror_top_info->nodes[j].node_id != src_node_id)
1284 continue;
1285
1286 mirror_top_info->nodes[j].num_hops = dst_num_hops;
1287 /*
1288 * prevent 0 num_links value re-reflection since reflection
1289 * criteria is based on num_hops (direct or indirect).
1290 *
1291 */
1292 if (dst_num_links)
1293 mirror_top_info->nodes[j].num_links = dst_num_links;
1294
1295 break;
1296 }
1297
1298 break;
1299 }
1300
1301 amdgpu_put_xgmi_hive(hive);
1302 }
1303
1304 int psp_xgmi_get_topology_info(struct psp_context *psp,
1305 int number_devices,
1306 struct psp_xgmi_topology_info *topology,
1307 bool get_extended_data)
1308 {
1309 struct ta_xgmi_shared_memory *xgmi_cmd;
1310 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1311 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1312 int i;
1313 int ret;
1314
1315 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1316 return -EINVAL;
1317
1318 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1319 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1320 xgmi_cmd->flag_extend_link_record = get_extended_data;
1321
1322 /* Fill in the shared memory with topology information as input */
1323 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1324 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1325 topology_info_input->num_nodes = number_devices;
1326
1327 for (i = 0; i < topology_info_input->num_nodes; i++) {
1328 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1329 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1330 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1331 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1332 }
1333
1334 /* Invoke xgmi ta to get the topology information */
1335 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1336 if (ret)
1337 return ret;
1338
1339 /* Read the output topology information from the shared memory */
1340 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1341 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1342 for (i = 0; i < topology->num_nodes; i++) {
1343 /* extended data will either be 0 or equal to non-extended data */
1344 if (topology_info_output->nodes[i].num_hops)
1345 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1346
1347 /* non-extended data gets everything here so no need to update */
1348 if (!get_extended_data) {
1349 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1350 topology->nodes[i].is_sharing_enabled =
1351 topology_info_output->nodes[i].is_sharing_enabled;
1352 topology->nodes[i].sdma_engine =
1353 topology_info_output->nodes[i].sdma_engine;
1354 }
1355
1356 }
1357
1358 /* Invoke xgmi ta again to get the link information */
1359 if (psp_xgmi_peer_link_info_supported(psp)) {
1360 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1361
1362 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1363
1364 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1365
1366 if (ret)
1367 return ret;
1368
1369 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1370 for (i = 0; i < topology->num_nodes; i++) {
1371 /* accumulate num_links on extended data */
1372 topology->nodes[i].num_links = get_extended_data ?
1373 topology->nodes[i].num_links +
1374 link_info_output->nodes[i].num_links :
1375 link_info_output->nodes[i].num_links;
1376
1377 /* reflect the topology information for bi-directionality */
1378 if (psp->xgmi_context.supports_extended_data &&
1379 get_extended_data && topology->nodes[i].num_hops)
1380 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1381 }
1382 }
1383
1384 return 0;
1385 }
1386
1387 int psp_xgmi_set_topology_info(struct psp_context *psp,
1388 int number_devices,
1389 struct psp_xgmi_topology_info *topology)
1390 {
1391 struct ta_xgmi_shared_memory *xgmi_cmd;
1392 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1393 int i;
1394
1395 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1396 return -EINVAL;
1397
1398 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1399 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1400
1401 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1402 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1403 topology_info_input->num_nodes = number_devices;
1404
1405 for (i = 0; i < topology_info_input->num_nodes; i++) {
1406 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1407 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1408 topology_info_input->nodes[i].is_sharing_enabled = 1;
1409 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1410 }
1411
1412 /* Invoke xgmi ta to set topology information */
1413 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1414 }
1415
1416 // ras begin
1417 static void psp_ras_ta_check_status(struct psp_context *psp)
1418 {
1419 struct ta_ras_shared_memory *ras_cmd =
1420 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1421
1422 switch (ras_cmd->ras_status) {
1423 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1424 dev_warn(psp->adev->dev,
1425 "RAS WARNING: cmd failed due to unsupported ip\n");
1426 break;
1427 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1428 dev_warn(psp->adev->dev,
1429 "RAS WARNING: cmd failed due to unsupported error injection\n");
1430 break;
1431 case TA_RAS_STATUS__SUCCESS:
1432 break;
1433 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1434 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1435 dev_warn(psp->adev->dev,
1436 "RAS WARNING: Inject error to critical region is not allowed\n");
1437 break;
1438 default:
1439 dev_warn(psp->adev->dev,
1440 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1441 break;
1442 }
1443 }
1444
1445 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1446 {
1447 struct ta_ras_shared_memory *ras_cmd;
1448 int ret;
1449
1450 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1451
1452 /*
1453 * TODO: bypass the loading in sriov for now
1454 */
1455 if (amdgpu_sriov_vf(psp->adev))
1456 return 0;
1457
1458 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1459
1460 if (amdgpu_ras_intr_triggered())
1461 return ret;
1462
1463 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1464 {
1465 DRM_WARN("RAS: Unsupported Interface");
1466 return -EINVAL;
1467 }
1468
1469 if (!ret) {
1470 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1471 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1472
1473 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1474 }
1475 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1476 dev_warn(psp->adev->dev,
1477 "RAS internal register access blocked\n");
1478
1479 psp_ras_ta_check_status(psp);
1480 }
1481
1482 return ret;
1483 }
1484
1485 int psp_ras_enable_features(struct psp_context *psp,
1486 union ta_ras_cmd_input *info, bool enable)
1487 {
1488 struct ta_ras_shared_memory *ras_cmd;
1489 int ret;
1490
1491 if (!psp->ras_context.context.initialized)
1492 return -EINVAL;
1493
1494 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1495 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1496
1497 if (enable)
1498 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1499 else
1500 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1501
1502 ras_cmd->ras_in_message = *info;
1503
1504 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1505 if (ret)
1506 return -EINVAL;
1507
1508 return 0;
1509 }
1510
1511 int psp_ras_terminate(struct psp_context *psp)
1512 {
1513 int ret;
1514
1515 /*
1516 * TODO: bypass the terminate in sriov for now
1517 */
1518 if (amdgpu_sriov_vf(psp->adev))
1519 return 0;
1520
1521 if (!psp->ras_context.context.initialized)
1522 return 0;
1523
1524 ret = psp_ta_unload(psp, &psp->ras_context.context);
1525
1526 psp->ras_context.context.initialized = false;
1527
1528 return ret;
1529 }
1530
1531 static int psp_ras_initialize(struct psp_context *psp)
1532 {
1533 int ret;
1534 uint32_t boot_cfg = 0xFF;
1535 struct amdgpu_device *adev = psp->adev;
1536 struct ta_ras_shared_memory *ras_cmd;
1537
1538 /*
1539 * TODO: bypass the initialize in sriov for now
1540 */
1541 if (amdgpu_sriov_vf(adev))
1542 return 0;
1543
1544 if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1545 !adev->psp.ras_context.context.bin_desc.start_addr) {
1546 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1547 return 0;
1548 }
1549
1550 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1551 /* query GECC enablement status from boot config
1552 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1553 */
1554 ret = psp_boot_config_get(adev, &boot_cfg);
1555 if (ret)
1556 dev_warn(adev->dev, "PSP get boot config failed\n");
1557
1558 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1559 if (!boot_cfg) {
1560 dev_info(adev->dev, "GECC is disabled\n");
1561 } else {
1562 /* disable GECC in next boot cycle if ras is
1563 * disabled by module parameter amdgpu_ras_enable
1564 * and/or amdgpu_ras_mask, or boot_config_get call
1565 * is failed
1566 */
1567 ret = psp_boot_config_set(adev, 0);
1568 if (ret)
1569 dev_warn(adev->dev, "PSP set boot config failed\n");
1570 else
1571 dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1572 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1573 }
1574 } else {
1575 if (1 == boot_cfg) {
1576 dev_info(adev->dev, "GECC is enabled\n");
1577 } else {
1578 /* enable GECC in next boot cycle if it is disabled
1579 * in boot config, or force enable GECC if failed to
1580 * get boot configuration
1581 */
1582 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1583 if (ret)
1584 dev_warn(adev->dev, "PSP set boot config failed\n");
1585 else
1586 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1587 }
1588 }
1589 }
1590
1591 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1592 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1593
1594 if (!psp->ras_context.context.initialized) {
1595 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1596 if (ret)
1597 return ret;
1598 }
1599
1600 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1601 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1602
1603 if (amdgpu_ras_is_poison_mode_supported(adev))
1604 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1605 if (!adev->gmc.xgmi.connected_to_cpu)
1606 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1607
1608 ret = psp_ta_load(psp, &psp->ras_context.context);
1609
1610 if (!ret && !ras_cmd->ras_status)
1611 psp->ras_context.context.initialized = true;
1612 else {
1613 if (ras_cmd->ras_status)
1614 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1615 amdgpu_ras_fini(psp->adev);
1616 }
1617
1618 return ret;
1619 }
1620
1621 int psp_ras_trigger_error(struct psp_context *psp,
1622 struct ta_ras_trigger_error_input *info)
1623 {
1624 struct ta_ras_shared_memory *ras_cmd;
1625 int ret;
1626
1627 if (!psp->ras_context.context.initialized)
1628 return -EINVAL;
1629
1630 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1631 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1632
1633 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1634 ras_cmd->ras_in_message.trigger_error = *info;
1635
1636 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1637 if (ret)
1638 return -EINVAL;
1639
1640 /* If err_event_athub occurs error inject was successful, however
1641 return status from TA is no long reliable */
1642 if (amdgpu_ras_intr_triggered())
1643 return 0;
1644
1645 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1646 return -EACCES;
1647 else if (ras_cmd->ras_status)
1648 return -EINVAL;
1649
1650 return 0;
1651 }
1652 // ras end
1653
1654 // HDCP start
1655 static int psp_hdcp_initialize(struct psp_context *psp)
1656 {
1657 int ret;
1658
1659 /*
1660 * TODO: bypass the initialize in sriov for now
1661 */
1662 if (amdgpu_sriov_vf(psp->adev))
1663 return 0;
1664
1665 if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1666 !psp->hdcp_context.context.bin_desc.start_addr) {
1667 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1668 return 0;
1669 }
1670
1671 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1672 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1673
1674 if (!psp->hdcp_context.context.initialized) {
1675 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1676 if (ret)
1677 return ret;
1678 }
1679
1680 ret = psp_ta_load(psp, &psp->hdcp_context.context);
1681 if (!ret) {
1682 psp->hdcp_context.context.initialized = true;
1683 mutex_init(&psp->hdcp_context.mutex);
1684 }
1685
1686 return ret;
1687 }
1688
1689 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1690 {
1691 /*
1692 * TODO: bypass the loading in sriov for now
1693 */
1694 if (amdgpu_sriov_vf(psp->adev))
1695 return 0;
1696
1697 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1698 }
1699
1700 static int psp_hdcp_terminate(struct psp_context *psp)
1701 {
1702 int ret;
1703
1704 /*
1705 * TODO: bypass the terminate in sriov for now
1706 */
1707 if (amdgpu_sriov_vf(psp->adev))
1708 return 0;
1709
1710 if (!psp->hdcp_context.context.initialized)
1711 return 0;
1712
1713 ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1714
1715 psp->hdcp_context.context.initialized = false;
1716
1717 return ret;
1718 }
1719 // HDCP end
1720
1721 // DTM start
1722 static int psp_dtm_initialize(struct psp_context *psp)
1723 {
1724 int ret;
1725
1726 /*
1727 * TODO: bypass the initialize in sriov for now
1728 */
1729 if (amdgpu_sriov_vf(psp->adev))
1730 return 0;
1731
1732 if (!psp->dtm_context.context.bin_desc.size_bytes ||
1733 !psp->dtm_context.context.bin_desc.start_addr) {
1734 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1735 return 0;
1736 }
1737
1738 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1739 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1740
1741 if (!psp->dtm_context.context.initialized) {
1742 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1743 if (ret)
1744 return ret;
1745 }
1746
1747 ret = psp_ta_load(psp, &psp->dtm_context.context);
1748 if (!ret) {
1749 psp->dtm_context.context.initialized = true;
1750 mutex_init(&psp->dtm_context.mutex);
1751 }
1752
1753 return ret;
1754 }
1755
1756 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1757 {
1758 /*
1759 * TODO: bypass the loading in sriov for now
1760 */
1761 if (amdgpu_sriov_vf(psp->adev))
1762 return 0;
1763
1764 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1765 }
1766
1767 static int psp_dtm_terminate(struct psp_context *psp)
1768 {
1769 int ret;
1770
1771 /*
1772 * TODO: bypass the terminate in sriov for now
1773 */
1774 if (amdgpu_sriov_vf(psp->adev))
1775 return 0;
1776
1777 if (!psp->dtm_context.context.initialized)
1778 return 0;
1779
1780 ret = psp_ta_unload(psp, &psp->dtm_context.context);
1781
1782 psp->dtm_context.context.initialized = false;
1783
1784 return ret;
1785 }
1786 // DTM end
1787
1788 // RAP start
1789 static int psp_rap_initialize(struct psp_context *psp)
1790 {
1791 int ret;
1792 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1793
1794 /*
1795 * TODO: bypass the initialize in sriov for now
1796 */
1797 if (amdgpu_sriov_vf(psp->adev))
1798 return 0;
1799
1800 if (!psp->rap_context.context.bin_desc.size_bytes ||
1801 !psp->rap_context.context.bin_desc.start_addr) {
1802 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1803 return 0;
1804 }
1805
1806 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1807 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1808
1809 if (!psp->rap_context.context.initialized) {
1810 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1811 if (ret)
1812 return ret;
1813 }
1814
1815 ret = psp_ta_load(psp, &psp->rap_context.context);
1816 if (!ret) {
1817 psp->rap_context.context.initialized = true;
1818 mutex_init(&psp->rap_context.mutex);
1819 } else
1820 return ret;
1821
1822 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1823 if (ret || status != TA_RAP_STATUS__SUCCESS) {
1824 psp_rap_terminate(psp);
1825 /* free rap shared memory */
1826 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1827
1828 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1829 ret, status);
1830
1831 return ret;
1832 }
1833
1834 return 0;
1835 }
1836
1837 static int psp_rap_terminate(struct psp_context *psp)
1838 {
1839 int ret;
1840
1841 if (!psp->rap_context.context.initialized)
1842 return 0;
1843
1844 ret = psp_ta_unload(psp, &psp->rap_context.context);
1845
1846 psp->rap_context.context.initialized = false;
1847
1848 return ret;
1849 }
1850
1851 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1852 {
1853 struct ta_rap_shared_memory *rap_cmd;
1854 int ret = 0;
1855
1856 if (!psp->rap_context.context.initialized)
1857 return 0;
1858
1859 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1860 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1861 return -EINVAL;
1862
1863 mutex_lock(&psp->rap_context.mutex);
1864
1865 rap_cmd = (struct ta_rap_shared_memory *)
1866 psp->rap_context.context.mem_context.shared_buf;
1867 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1868
1869 rap_cmd->cmd_id = ta_cmd_id;
1870 rap_cmd->validation_method_id = METHOD_A;
1871
1872 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1873 if (ret)
1874 goto out_unlock;
1875
1876 if (status)
1877 *status = rap_cmd->rap_status;
1878
1879 out_unlock:
1880 mutex_unlock(&psp->rap_context.mutex);
1881
1882 return ret;
1883 }
1884 // RAP end
1885
1886 /* securedisplay start */
1887 static int psp_securedisplay_initialize(struct psp_context *psp)
1888 {
1889 int ret;
1890 struct securedisplay_cmd *securedisplay_cmd;
1891
1892 /*
1893 * TODO: bypass the initialize in sriov for now
1894 */
1895 if (amdgpu_sriov_vf(psp->adev))
1896 return 0;
1897
1898 if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1899 !psp->securedisplay_context.context.bin_desc.start_addr) {
1900 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1901 return 0;
1902 }
1903
1904 psp->securedisplay_context.context.mem_context.shared_mem_size =
1905 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1906 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1907
1908 if (!psp->securedisplay_context.context.initialized) {
1909 ret = psp_ta_init_shared_buf(psp,
1910 &psp->securedisplay_context.context.mem_context);
1911 if (ret)
1912 return ret;
1913 }
1914
1915 ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1916 if (!ret) {
1917 psp->securedisplay_context.context.initialized = true;
1918 mutex_init(&psp->securedisplay_context.mutex);
1919 } else
1920 return ret;
1921
1922 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1923 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1924
1925 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1926 if (ret) {
1927 psp_securedisplay_terminate(psp);
1928 /* free securedisplay shared memory */
1929 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1930 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1931 return -EINVAL;
1932 }
1933
1934 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1935 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1936 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1937 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1938 }
1939
1940 return 0;
1941 }
1942
1943 static int psp_securedisplay_terminate(struct psp_context *psp)
1944 {
1945 int ret;
1946
1947 /*
1948 * TODO:bypass the terminate in sriov for now
1949 */
1950 if (amdgpu_sriov_vf(psp->adev))
1951 return 0;
1952
1953 if (!psp->securedisplay_context.context.initialized)
1954 return 0;
1955
1956 ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1957
1958 psp->securedisplay_context.context.initialized = false;
1959
1960 return ret;
1961 }
1962
1963 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1964 {
1965 int ret;
1966
1967 if (!psp->securedisplay_context.context.initialized)
1968 return -EINVAL;
1969
1970 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1971 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1972 return -EINVAL;
1973
1974 mutex_lock(&psp->securedisplay_context.mutex);
1975
1976 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1977
1978 mutex_unlock(&psp->securedisplay_context.mutex);
1979
1980 return ret;
1981 }
1982 /* SECUREDISPLAY end */
1983
1984 static int psp_hw_start(struct psp_context *psp)
1985 {
1986 struct amdgpu_device *adev = psp->adev;
1987 int ret;
1988
1989 if (!amdgpu_sriov_vf(adev)) {
1990 if ((is_psp_fw_valid(psp->kdb)) &&
1991 (psp->funcs->bootloader_load_kdb != NULL)) {
1992 ret = psp_bootloader_load_kdb(psp);
1993 if (ret) {
1994 DRM_ERROR("PSP load kdb failed!\n");
1995 return ret;
1996 }
1997 }
1998
1999 if ((is_psp_fw_valid(psp->spl)) &&
2000 (psp->funcs->bootloader_load_spl != NULL)) {
2001 ret = psp_bootloader_load_spl(psp);
2002 if (ret) {
2003 DRM_ERROR("PSP load spl failed!\n");
2004 return ret;
2005 }
2006 }
2007
2008 if ((is_psp_fw_valid(psp->sys)) &&
2009 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2010 ret = psp_bootloader_load_sysdrv(psp);
2011 if (ret) {
2012 DRM_ERROR("PSP load sys drv failed!\n");
2013 return ret;
2014 }
2015 }
2016
2017 if ((is_psp_fw_valid(psp->soc_drv)) &&
2018 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2019 ret = psp_bootloader_load_soc_drv(psp);
2020 if (ret) {
2021 DRM_ERROR("PSP load soc drv failed!\n");
2022 return ret;
2023 }
2024 }
2025
2026 if ((is_psp_fw_valid(psp->intf_drv)) &&
2027 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2028 ret = psp_bootloader_load_intf_drv(psp);
2029 if (ret) {
2030 DRM_ERROR("PSP load intf drv failed!\n");
2031 return ret;
2032 }
2033 }
2034
2035 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2036 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2037 ret = psp_bootloader_load_dbg_drv(psp);
2038 if (ret) {
2039 DRM_ERROR("PSP load dbg drv failed!\n");
2040 return ret;
2041 }
2042 }
2043
2044 if ((is_psp_fw_valid(psp->sos)) &&
2045 (psp->funcs->bootloader_load_sos != NULL)) {
2046 ret = psp_bootloader_load_sos(psp);
2047 if (ret) {
2048 DRM_ERROR("PSP load sos failed!\n");
2049 return ret;
2050 }
2051 }
2052 }
2053
2054 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2055 if (ret) {
2056 DRM_ERROR("PSP create ring failed!\n");
2057 return ret;
2058 }
2059
2060 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2061 goto skip_pin_bo;
2062
2063 ret = psp_tmr_init(psp);
2064 if (ret) {
2065 DRM_ERROR("PSP tmr init failed!\n");
2066 return ret;
2067 }
2068
2069 skip_pin_bo:
2070 /*
2071 * For ASICs with DF Cstate management centralized
2072 * to PMFW, TMR setup should be performed after PMFW
2073 * loaded and before other non-psp firmware loaded.
2074 */
2075 if (psp->pmfw_centralized_cstate_management) {
2076 ret = psp_load_smu_fw(psp);
2077 if (ret)
2078 return ret;
2079 }
2080
2081 ret = psp_tmr_load(psp);
2082 if (ret) {
2083 DRM_ERROR("PSP load tmr failed!\n");
2084 return ret;
2085 }
2086
2087 return 0;
2088 }
2089
2090 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2091 enum psp_gfx_fw_type *type)
2092 {
2093 switch (ucode->ucode_id) {
2094 case AMDGPU_UCODE_ID_CAP:
2095 *type = GFX_FW_TYPE_CAP;
2096 break;
2097 case AMDGPU_UCODE_ID_SDMA0:
2098 *type = GFX_FW_TYPE_SDMA0;
2099 break;
2100 case AMDGPU_UCODE_ID_SDMA1:
2101 *type = GFX_FW_TYPE_SDMA1;
2102 break;
2103 case AMDGPU_UCODE_ID_SDMA2:
2104 *type = GFX_FW_TYPE_SDMA2;
2105 break;
2106 case AMDGPU_UCODE_ID_SDMA3:
2107 *type = GFX_FW_TYPE_SDMA3;
2108 break;
2109 case AMDGPU_UCODE_ID_SDMA4:
2110 *type = GFX_FW_TYPE_SDMA4;
2111 break;
2112 case AMDGPU_UCODE_ID_SDMA5:
2113 *type = GFX_FW_TYPE_SDMA5;
2114 break;
2115 case AMDGPU_UCODE_ID_SDMA6:
2116 *type = GFX_FW_TYPE_SDMA6;
2117 break;
2118 case AMDGPU_UCODE_ID_SDMA7:
2119 *type = GFX_FW_TYPE_SDMA7;
2120 break;
2121 case AMDGPU_UCODE_ID_CP_MES:
2122 *type = GFX_FW_TYPE_CP_MES;
2123 break;
2124 case AMDGPU_UCODE_ID_CP_MES_DATA:
2125 *type = GFX_FW_TYPE_MES_STACK;
2126 break;
2127 case AMDGPU_UCODE_ID_CP_MES1:
2128 *type = GFX_FW_TYPE_CP_MES_KIQ;
2129 break;
2130 case AMDGPU_UCODE_ID_CP_MES1_DATA:
2131 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2132 break;
2133 case AMDGPU_UCODE_ID_CP_CE:
2134 *type = GFX_FW_TYPE_CP_CE;
2135 break;
2136 case AMDGPU_UCODE_ID_CP_PFP:
2137 *type = GFX_FW_TYPE_CP_PFP;
2138 break;
2139 case AMDGPU_UCODE_ID_CP_ME:
2140 *type = GFX_FW_TYPE_CP_ME;
2141 break;
2142 case AMDGPU_UCODE_ID_CP_MEC1:
2143 *type = GFX_FW_TYPE_CP_MEC;
2144 break;
2145 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2146 *type = GFX_FW_TYPE_CP_MEC_ME1;
2147 break;
2148 case AMDGPU_UCODE_ID_CP_MEC2:
2149 *type = GFX_FW_TYPE_CP_MEC;
2150 break;
2151 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2152 *type = GFX_FW_TYPE_CP_MEC_ME2;
2153 break;
2154 case AMDGPU_UCODE_ID_RLC_P:
2155 *type = GFX_FW_TYPE_RLC_P;
2156 break;
2157 case AMDGPU_UCODE_ID_RLC_V:
2158 *type = GFX_FW_TYPE_RLC_V;
2159 break;
2160 case AMDGPU_UCODE_ID_RLC_G:
2161 *type = GFX_FW_TYPE_RLC_G;
2162 break;
2163 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2164 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2165 break;
2166 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2167 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2168 break;
2169 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2170 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2171 break;
2172 case AMDGPU_UCODE_ID_RLC_IRAM:
2173 *type = GFX_FW_TYPE_RLC_IRAM;
2174 break;
2175 case AMDGPU_UCODE_ID_RLC_DRAM:
2176 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2177 break;
2178 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2179 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2180 break;
2181 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2182 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2183 break;
2184 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2185 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2186 break;
2187 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2188 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2189 break;
2190 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2191 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2192 break;
2193 case AMDGPU_UCODE_ID_SMC:
2194 *type = GFX_FW_TYPE_SMU;
2195 break;
2196 case AMDGPU_UCODE_ID_PPTABLE:
2197 *type = GFX_FW_TYPE_PPTABLE;
2198 break;
2199 case AMDGPU_UCODE_ID_UVD:
2200 *type = GFX_FW_TYPE_UVD;
2201 break;
2202 case AMDGPU_UCODE_ID_UVD1:
2203 *type = GFX_FW_TYPE_UVD1;
2204 break;
2205 case AMDGPU_UCODE_ID_VCE:
2206 *type = GFX_FW_TYPE_VCE;
2207 break;
2208 case AMDGPU_UCODE_ID_VCN:
2209 *type = GFX_FW_TYPE_VCN;
2210 break;
2211 case AMDGPU_UCODE_ID_VCN1:
2212 *type = GFX_FW_TYPE_VCN1;
2213 break;
2214 case AMDGPU_UCODE_ID_DMCU_ERAM:
2215 *type = GFX_FW_TYPE_DMCU_ERAM;
2216 break;
2217 case AMDGPU_UCODE_ID_DMCU_INTV:
2218 *type = GFX_FW_TYPE_DMCU_ISR;
2219 break;
2220 case AMDGPU_UCODE_ID_VCN0_RAM:
2221 *type = GFX_FW_TYPE_VCN0_RAM;
2222 break;
2223 case AMDGPU_UCODE_ID_VCN1_RAM:
2224 *type = GFX_FW_TYPE_VCN1_RAM;
2225 break;
2226 case AMDGPU_UCODE_ID_DMCUB:
2227 *type = GFX_FW_TYPE_DMUB;
2228 break;
2229 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2230 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2231 break;
2232 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2233 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2234 break;
2235 case AMDGPU_UCODE_ID_IMU_I:
2236 *type = GFX_FW_TYPE_IMU_I;
2237 break;
2238 case AMDGPU_UCODE_ID_IMU_D:
2239 *type = GFX_FW_TYPE_IMU_D;
2240 break;
2241 case AMDGPU_UCODE_ID_CP_RS64_PFP:
2242 *type = GFX_FW_TYPE_RS64_PFP;
2243 break;
2244 case AMDGPU_UCODE_ID_CP_RS64_ME:
2245 *type = GFX_FW_TYPE_RS64_ME;
2246 break;
2247 case AMDGPU_UCODE_ID_CP_RS64_MEC:
2248 *type = GFX_FW_TYPE_RS64_MEC;
2249 break;
2250 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2251 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2252 break;
2253 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2254 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2255 break;
2256 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2257 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2258 break;
2259 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2260 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2261 break;
2262 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2263 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2264 break;
2265 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2266 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2267 break;
2268 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2269 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2270 break;
2271 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2272 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2273 break;
2274 case AMDGPU_UCODE_ID_MAXIMUM:
2275 default:
2276 return -EINVAL;
2277 }
2278
2279 return 0;
2280 }
2281
2282 static void psp_print_fw_hdr(struct psp_context *psp,
2283 struct amdgpu_firmware_info *ucode)
2284 {
2285 struct amdgpu_device *adev = psp->adev;
2286 struct common_firmware_header *hdr;
2287
2288 switch (ucode->ucode_id) {
2289 case AMDGPU_UCODE_ID_SDMA0:
2290 case AMDGPU_UCODE_ID_SDMA1:
2291 case AMDGPU_UCODE_ID_SDMA2:
2292 case AMDGPU_UCODE_ID_SDMA3:
2293 case AMDGPU_UCODE_ID_SDMA4:
2294 case AMDGPU_UCODE_ID_SDMA5:
2295 case AMDGPU_UCODE_ID_SDMA6:
2296 case AMDGPU_UCODE_ID_SDMA7:
2297 hdr = (struct common_firmware_header *)
2298 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2299 amdgpu_ucode_print_sdma_hdr(hdr);
2300 break;
2301 case AMDGPU_UCODE_ID_CP_CE:
2302 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2303 amdgpu_ucode_print_gfx_hdr(hdr);
2304 break;
2305 case AMDGPU_UCODE_ID_CP_PFP:
2306 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2307 amdgpu_ucode_print_gfx_hdr(hdr);
2308 break;
2309 case AMDGPU_UCODE_ID_CP_ME:
2310 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2311 amdgpu_ucode_print_gfx_hdr(hdr);
2312 break;
2313 case AMDGPU_UCODE_ID_CP_MEC1:
2314 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2315 amdgpu_ucode_print_gfx_hdr(hdr);
2316 break;
2317 case AMDGPU_UCODE_ID_RLC_G:
2318 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2319 amdgpu_ucode_print_rlc_hdr(hdr);
2320 break;
2321 case AMDGPU_UCODE_ID_SMC:
2322 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2323 amdgpu_ucode_print_smc_hdr(hdr);
2324 break;
2325 default:
2326 break;
2327 }
2328 }
2329
2330 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2331 struct psp_gfx_cmd_resp *cmd)
2332 {
2333 int ret;
2334 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2335
2336 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2337 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2338 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2339 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2340
2341 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2342 if (ret)
2343 DRM_ERROR("Unknown firmware type\n");
2344
2345 return ret;
2346 }
2347
2348 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2349 struct amdgpu_firmware_info *ucode)
2350 {
2351 int ret = 0;
2352 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2353
2354 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2355 if (!ret) {
2356 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2357 psp->fence_buf_mc_addr);
2358 }
2359
2360 release_psp_cmd_buf(psp);
2361
2362 return ret;
2363 }
2364
2365 static int psp_load_smu_fw(struct psp_context *psp)
2366 {
2367 int ret;
2368 struct amdgpu_device *adev = psp->adev;
2369 struct amdgpu_firmware_info *ucode =
2370 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2371 struct amdgpu_ras *ras = psp->ras_context.ras;
2372
2373 /*
2374 * Skip SMU FW reloading in case of using BACO for runpm only,
2375 * as SMU is always alive.
2376 */
2377 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2378 return 0;
2379
2380 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2381 return 0;
2382
2383 if ((amdgpu_in_reset(adev) &&
2384 ras && adev->ras_enabled &&
2385 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2386 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2387 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2388 if (ret) {
2389 DRM_WARN("Failed to set MP1 state prepare for reload\n");
2390 }
2391 }
2392
2393 ret = psp_execute_non_psp_fw_load(psp, ucode);
2394
2395 if (ret)
2396 DRM_ERROR("PSP load smu failed!\n");
2397
2398 return ret;
2399 }
2400
2401 static bool fw_load_skip_check(struct psp_context *psp,
2402 struct amdgpu_firmware_info *ucode)
2403 {
2404 if (!ucode->fw || !ucode->ucode_size)
2405 return true;
2406
2407 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2408 (psp_smu_reload_quirk(psp) ||
2409 psp->autoload_supported ||
2410 psp->pmfw_centralized_cstate_management))
2411 return true;
2412
2413 if (amdgpu_sriov_vf(psp->adev) &&
2414 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2415 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2416 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2417 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2418 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2419 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2420 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2421 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2422 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2423 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2424 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2425 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2426 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2427 /*skip ucode loading in SRIOV VF */
2428 return true;
2429
2430 if (psp->autoload_supported &&
2431 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2432 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2433 /* skip mec JT when autoload is enabled */
2434 return true;
2435
2436 return false;
2437 }
2438
2439 int psp_load_fw_list(struct psp_context *psp,
2440 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2441 {
2442 int ret = 0, i;
2443 struct amdgpu_firmware_info *ucode;
2444
2445 for (i = 0; i < ucode_count; ++i) {
2446 ucode = ucode_list[i];
2447 psp_print_fw_hdr(psp, ucode);
2448 ret = psp_execute_non_psp_fw_load(psp, ucode);
2449 if (ret)
2450 return ret;
2451 }
2452 return ret;
2453 }
2454
2455 static int psp_load_non_psp_fw(struct psp_context *psp)
2456 {
2457 int i, ret;
2458 struct amdgpu_firmware_info *ucode;
2459 struct amdgpu_device *adev = psp->adev;
2460
2461 if (psp->autoload_supported &&
2462 !psp->pmfw_centralized_cstate_management) {
2463 ret = psp_load_smu_fw(psp);
2464 if (ret)
2465 return ret;
2466 }
2467
2468 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2469 ucode = &adev->firmware.ucode[i];
2470
2471 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2472 !fw_load_skip_check(psp, ucode)) {
2473 ret = psp_load_smu_fw(psp);
2474 if (ret)
2475 return ret;
2476 continue;
2477 }
2478
2479 if (fw_load_skip_check(psp, ucode))
2480 continue;
2481
2482 if (psp->autoload_supported &&
2483 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2484 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2485 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2486 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2487 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2488 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2489 /* PSP only receive one SDMA fw for sienna_cichlid,
2490 * as all four sdma fw are same */
2491 continue;
2492
2493 psp_print_fw_hdr(psp, ucode);
2494
2495 ret = psp_execute_non_psp_fw_load(psp, ucode);
2496 if (ret)
2497 return ret;
2498
2499 /* Start rlc autoload after psp recieved all the gfx firmware */
2500 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2501 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2502 ret = psp_rlc_autoload_start(psp);
2503 if (ret) {
2504 DRM_ERROR("Failed to start rlc autoload\n");
2505 return ret;
2506 }
2507 }
2508 }
2509
2510 return 0;
2511 }
2512
2513 static int psp_load_fw(struct amdgpu_device *adev)
2514 {
2515 int ret;
2516 struct psp_context *psp = &adev->psp;
2517
2518 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2519 /* should not destroy ring, only stop */
2520 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2521 } else {
2522 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2523
2524 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2525 if (ret) {
2526 DRM_ERROR("PSP ring init failed!\n");
2527 goto failed;
2528 }
2529 }
2530
2531 ret = psp_hw_start(psp);
2532 if (ret)
2533 goto failed;
2534
2535 ret = psp_load_non_psp_fw(psp);
2536 if (ret)
2537 goto failed1;
2538
2539 ret = psp_asd_initialize(psp);
2540 if (ret) {
2541 DRM_ERROR("PSP load asd failed!\n");
2542 goto failed1;
2543 }
2544
2545 ret = psp_rl_load(adev);
2546 if (ret) {
2547 DRM_ERROR("PSP load RL failed!\n");
2548 goto failed1;
2549 }
2550
2551 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2552 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2553 ret = psp_xgmi_initialize(psp, false, true);
2554 /* Warning the XGMI seesion initialize failure
2555 * Instead of stop driver initialization
2556 */
2557 if (ret)
2558 dev_err(psp->adev->dev,
2559 "XGMI: Failed to initialize XGMI session\n");
2560 }
2561 }
2562
2563 if (psp->ta_fw) {
2564 ret = psp_ras_initialize(psp);
2565 if (ret)
2566 dev_err(psp->adev->dev,
2567 "RAS: Failed to initialize RAS\n");
2568
2569 ret = psp_hdcp_initialize(psp);
2570 if (ret)
2571 dev_err(psp->adev->dev,
2572 "HDCP: Failed to initialize HDCP\n");
2573
2574 ret = psp_dtm_initialize(psp);
2575 if (ret)
2576 dev_err(psp->adev->dev,
2577 "DTM: Failed to initialize DTM\n");
2578
2579 ret = psp_rap_initialize(psp);
2580 if (ret)
2581 dev_err(psp->adev->dev,
2582 "RAP: Failed to initialize RAP\n");
2583
2584 ret = psp_securedisplay_initialize(psp);
2585 if (ret)
2586 dev_err(psp->adev->dev,
2587 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2588 }
2589
2590 return 0;
2591
2592 failed1:
2593 psp_free_shared_bufs(psp);
2594 failed:
2595 /*
2596 * all cleanup jobs (xgmi terminate, ras terminate,
2597 * ring destroy, cmd/fence/fw buffers destory,
2598 * psp->cmd destory) are delayed to psp_hw_fini
2599 */
2600 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2601 return ret;
2602 }
2603
2604 static int psp_hw_init(void *handle)
2605 {
2606 int ret;
2607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2608
2609 mutex_lock(&adev->firmware.mutex);
2610 /*
2611 * This sequence is just used on hw_init only once, no need on
2612 * resume.
2613 */
2614 ret = amdgpu_ucode_init_bo(adev);
2615 if (ret)
2616 goto failed;
2617
2618 ret = psp_load_fw(adev);
2619 if (ret) {
2620 DRM_ERROR("PSP firmware loading failed\n");
2621 goto failed;
2622 }
2623
2624 mutex_unlock(&adev->firmware.mutex);
2625 return 0;
2626
2627 failed:
2628 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2629 mutex_unlock(&adev->firmware.mutex);
2630 return -EINVAL;
2631 }
2632
2633 static int psp_hw_fini(void *handle)
2634 {
2635 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2636 struct psp_context *psp = &adev->psp;
2637
2638 if (psp->ta_fw) {
2639 psp_ras_terminate(psp);
2640 psp_securedisplay_terminate(psp);
2641 psp_rap_terminate(psp);
2642 psp_dtm_terminate(psp);
2643 psp_hdcp_terminate(psp);
2644
2645 if (adev->gmc.xgmi.num_physical_nodes > 1)
2646 psp_xgmi_terminate(psp);
2647 }
2648
2649 psp_asd_terminate(psp);
2650 psp_tmr_terminate(psp);
2651
2652 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2653
2654 psp_free_shared_bufs(psp);
2655
2656 return 0;
2657 }
2658
2659 static int psp_suspend(void *handle)
2660 {
2661 int ret = 0;
2662 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2663 struct psp_context *psp = &adev->psp;
2664
2665 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2666 psp->xgmi_context.context.initialized) {
2667 ret = psp_xgmi_terminate(psp);
2668 if (ret) {
2669 DRM_ERROR("Failed to terminate xgmi ta\n");
2670 goto out;
2671 }
2672 }
2673
2674 if (psp->ta_fw) {
2675 ret = psp_ras_terminate(psp);
2676 if (ret) {
2677 DRM_ERROR("Failed to terminate ras ta\n");
2678 goto out;
2679 }
2680 ret = psp_hdcp_terminate(psp);
2681 if (ret) {
2682 DRM_ERROR("Failed to terminate hdcp ta\n");
2683 goto out;
2684 }
2685 ret = psp_dtm_terminate(psp);
2686 if (ret) {
2687 DRM_ERROR("Failed to terminate dtm ta\n");
2688 goto out;
2689 }
2690 ret = psp_rap_terminate(psp);
2691 if (ret) {
2692 DRM_ERROR("Failed to terminate rap ta\n");
2693 goto out;
2694 }
2695 ret = psp_securedisplay_terminate(psp);
2696 if (ret) {
2697 DRM_ERROR("Failed to terminate securedisplay ta\n");
2698 goto out;
2699 }
2700 }
2701
2702 ret = psp_asd_terminate(psp);
2703 if (ret) {
2704 DRM_ERROR("Failed to terminate asd\n");
2705 goto out;
2706 }
2707
2708 ret = psp_tmr_terminate(psp);
2709 if (ret) {
2710 DRM_ERROR("Failed to terminate tmr\n");
2711 goto out;
2712 }
2713
2714 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2715 if (ret) {
2716 DRM_ERROR("PSP ring stop failed\n");
2717 }
2718
2719 out:
2720 psp_free_shared_bufs(psp);
2721
2722 return ret;
2723 }
2724
2725 static int psp_resume(void *handle)
2726 {
2727 int ret;
2728 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2729 struct psp_context *psp = &adev->psp;
2730
2731 DRM_INFO("PSP is resuming...\n");
2732
2733 if (psp->mem_train_ctx.enable_mem_training) {
2734 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2735 if (ret) {
2736 DRM_ERROR("Failed to process memory training!\n");
2737 return ret;
2738 }
2739 }
2740
2741 mutex_lock(&adev->firmware.mutex);
2742
2743 ret = psp_hw_start(psp);
2744 if (ret)
2745 goto failed;
2746
2747 ret = psp_load_non_psp_fw(psp);
2748 if (ret)
2749 goto failed;
2750
2751 ret = psp_asd_initialize(psp);
2752 if (ret) {
2753 DRM_ERROR("PSP load asd failed!\n");
2754 goto failed;
2755 }
2756
2757 ret = psp_rl_load(adev);
2758 if (ret) {
2759 dev_err(adev->dev, "PSP load RL failed!\n");
2760 goto failed;
2761 }
2762
2763 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2764 ret = psp_xgmi_initialize(psp, false, true);
2765 /* Warning the XGMI seesion initialize failure
2766 * Instead of stop driver initialization
2767 */
2768 if (ret)
2769 dev_err(psp->adev->dev,
2770 "XGMI: Failed to initialize XGMI session\n");
2771 }
2772
2773 if (psp->ta_fw) {
2774 ret = psp_ras_initialize(psp);
2775 if (ret)
2776 dev_err(psp->adev->dev,
2777 "RAS: Failed to initialize RAS\n");
2778
2779 ret = psp_hdcp_initialize(psp);
2780 if (ret)
2781 dev_err(psp->adev->dev,
2782 "HDCP: Failed to initialize HDCP\n");
2783
2784 ret = psp_dtm_initialize(psp);
2785 if (ret)
2786 dev_err(psp->adev->dev,
2787 "DTM: Failed to initialize DTM\n");
2788
2789 ret = psp_rap_initialize(psp);
2790 if (ret)
2791 dev_err(psp->adev->dev,
2792 "RAP: Failed to initialize RAP\n");
2793
2794 ret = psp_securedisplay_initialize(psp);
2795 if (ret)
2796 dev_err(psp->adev->dev,
2797 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2798 }
2799
2800 mutex_unlock(&adev->firmware.mutex);
2801
2802 return 0;
2803
2804 failed:
2805 DRM_ERROR("PSP resume failed\n");
2806 mutex_unlock(&adev->firmware.mutex);
2807 return ret;
2808 }
2809
2810 int psp_gpu_reset(struct amdgpu_device *adev)
2811 {
2812 int ret;
2813
2814 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2815 return 0;
2816
2817 mutex_lock(&adev->psp.mutex);
2818 ret = psp_mode1_reset(&adev->psp);
2819 mutex_unlock(&adev->psp.mutex);
2820
2821 return ret;
2822 }
2823
2824 int psp_rlc_autoload_start(struct psp_context *psp)
2825 {
2826 int ret;
2827 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2828
2829 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2830
2831 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2832 psp->fence_buf_mc_addr);
2833
2834 release_psp_cmd_buf(psp);
2835
2836 return ret;
2837 }
2838
2839 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2840 uint64_t cmd_gpu_addr, int cmd_size)
2841 {
2842 struct amdgpu_firmware_info ucode = {0};
2843
2844 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2845 AMDGPU_UCODE_ID_VCN0_RAM;
2846 ucode.mc_addr = cmd_gpu_addr;
2847 ucode.ucode_size = cmd_size;
2848
2849 return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2850 }
2851
2852 int psp_ring_cmd_submit(struct psp_context *psp,
2853 uint64_t cmd_buf_mc_addr,
2854 uint64_t fence_mc_addr,
2855 int index)
2856 {
2857 unsigned int psp_write_ptr_reg = 0;
2858 struct psp_gfx_rb_frame *write_frame;
2859 struct psp_ring *ring = &psp->km_ring;
2860 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2861 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2862 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2863 struct amdgpu_device *adev = psp->adev;
2864 uint32_t ring_size_dw = ring->ring_size / 4;
2865 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2866
2867 /* KM (GPCOM) prepare write pointer */
2868 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2869
2870 /* Update KM RB frame pointer to new frame */
2871 /* write_frame ptr increments by size of rb_frame in bytes */
2872 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2873 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2874 write_frame = ring_buffer_start;
2875 else
2876 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2877 /* Check invalid write_frame ptr address */
2878 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2879 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2880 ring_buffer_start, ring_buffer_end, write_frame);
2881 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2882 return -EINVAL;
2883 }
2884
2885 /* Initialize KM RB frame */
2886 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2887
2888 /* Update KM RB frame */
2889 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2890 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2891 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2892 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2893 write_frame->fence_value = index;
2894 amdgpu_device_flush_hdp(adev, NULL);
2895
2896 /* Update the write Pointer in DWORDs */
2897 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2898 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2899 return 0;
2900 }
2901
2902 int psp_init_asd_microcode(struct psp_context *psp,
2903 const char *chip_name)
2904 {
2905 struct amdgpu_device *adev = psp->adev;
2906 char fw_name[PSP_FW_NAME_LEN];
2907 const struct psp_firmware_header_v1_0 *asd_hdr;
2908 int err = 0;
2909
2910 if (!chip_name) {
2911 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2912 return -EINVAL;
2913 }
2914
2915 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2916 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2917 if (err)
2918 goto out;
2919
2920 err = amdgpu_ucode_validate(adev->psp.asd_fw);
2921 if (err)
2922 goto out;
2923
2924 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2925 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2926 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2927 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2928 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2929 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2930 return 0;
2931 out:
2932 dev_err(adev->dev, "fail to initialize asd microcode\n");
2933 release_firmware(adev->psp.asd_fw);
2934 adev->psp.asd_fw = NULL;
2935 return err;
2936 }
2937
2938 int psp_init_toc_microcode(struct psp_context *psp,
2939 const char *chip_name)
2940 {
2941 struct amdgpu_device *adev = psp->adev;
2942 char fw_name[PSP_FW_NAME_LEN];
2943 const struct psp_firmware_header_v1_0 *toc_hdr;
2944 int err = 0;
2945
2946 if (!chip_name) {
2947 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2948 return -EINVAL;
2949 }
2950
2951 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2952 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2953 if (err)
2954 goto out;
2955
2956 err = amdgpu_ucode_validate(adev->psp.toc_fw);
2957 if (err)
2958 goto out;
2959
2960 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2961 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2962 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2963 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2964 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2965 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2966 return 0;
2967 out:
2968 dev_err(adev->dev, "fail to request/validate toc microcode\n");
2969 release_firmware(adev->psp.toc_fw);
2970 adev->psp.toc_fw = NULL;
2971 return err;
2972 }
2973
2974 static int parse_sos_bin_descriptor(struct psp_context *psp,
2975 const struct psp_fw_bin_desc *desc,
2976 const struct psp_firmware_header_v2_0 *sos_hdr)
2977 {
2978 uint8_t *ucode_start_addr = NULL;
2979
2980 if (!psp || !desc || !sos_hdr)
2981 return -EINVAL;
2982
2983 ucode_start_addr = (uint8_t *)sos_hdr +
2984 le32_to_cpu(desc->offset_bytes) +
2985 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2986
2987 switch (desc->fw_type) {
2988 case PSP_FW_TYPE_PSP_SOS:
2989 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
2990 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
2991 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
2992 psp->sos.start_addr = ucode_start_addr;
2993 break;
2994 case PSP_FW_TYPE_PSP_SYS_DRV:
2995 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
2996 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
2997 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
2998 psp->sys.start_addr = ucode_start_addr;
2999 break;
3000 case PSP_FW_TYPE_PSP_KDB:
3001 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3002 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3003 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3004 psp->kdb.start_addr = ucode_start_addr;
3005 break;
3006 case PSP_FW_TYPE_PSP_TOC:
3007 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3008 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3009 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3010 psp->toc.start_addr = ucode_start_addr;
3011 break;
3012 case PSP_FW_TYPE_PSP_SPL:
3013 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3014 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3015 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3016 psp->spl.start_addr = ucode_start_addr;
3017 break;
3018 case PSP_FW_TYPE_PSP_RL:
3019 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3020 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3021 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3022 psp->rl.start_addr = ucode_start_addr;
3023 break;
3024 case PSP_FW_TYPE_PSP_SOC_DRV:
3025 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3026 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3027 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3028 psp->soc_drv.start_addr = ucode_start_addr;
3029 break;
3030 case PSP_FW_TYPE_PSP_INTF_DRV:
3031 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3032 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3033 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3034 psp->intf_drv.start_addr = ucode_start_addr;
3035 break;
3036 case PSP_FW_TYPE_PSP_DBG_DRV:
3037 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3038 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3039 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3040 psp->dbg_drv.start_addr = ucode_start_addr;
3041 break;
3042 default:
3043 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3044 break;
3045 }
3046
3047 return 0;
3048 }
3049
3050 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3051 {
3052 const struct psp_firmware_header_v1_0 *sos_hdr;
3053 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3054 uint8_t *ucode_array_start_addr;
3055
3056 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3057 ucode_array_start_addr = (uint8_t *)sos_hdr +
3058 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3059
3060 if (adev->gmc.xgmi.connected_to_cpu ||
3061 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3062 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3063 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3064
3065 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3066 adev->psp.sys.start_addr = ucode_array_start_addr;
3067
3068 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3069 adev->psp.sos.start_addr = ucode_array_start_addr +
3070 le32_to_cpu(sos_hdr->sos.offset_bytes);
3071 } else {
3072 /* Load alternate PSP SOS FW */
3073 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3074
3075 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3076 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3077
3078 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3079 adev->psp.sys.start_addr = ucode_array_start_addr +
3080 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3081
3082 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3083 adev->psp.sos.start_addr = ucode_array_start_addr +
3084 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3085 }
3086
3087 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3088 dev_warn(adev->dev, "PSP SOS FW not available");
3089 return -EINVAL;
3090 }
3091
3092 return 0;
3093 }
3094
3095 int psp_init_sos_microcode(struct psp_context *psp,
3096 const char *chip_name)
3097 {
3098 struct amdgpu_device *adev = psp->adev;
3099 char fw_name[PSP_FW_NAME_LEN];
3100 const struct psp_firmware_header_v1_0 *sos_hdr;
3101 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3102 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3103 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3104 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3105 int err = 0;
3106 uint8_t *ucode_array_start_addr;
3107 int fw_index = 0;
3108
3109 if (!chip_name) {
3110 dev_err(adev->dev, "invalid chip name for sos microcode\n");
3111 return -EINVAL;
3112 }
3113
3114 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3115 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3116 if (err)
3117 goto out;
3118
3119 err = amdgpu_ucode_validate(adev->psp.sos_fw);
3120 if (err)
3121 goto out;
3122
3123 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3124 ucode_array_start_addr = (uint8_t *)sos_hdr +
3125 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3126 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3127
3128 switch (sos_hdr->header.header_version_major) {
3129 case 1:
3130 err = psp_init_sos_base_fw(adev);
3131 if (err)
3132 goto out;
3133
3134 if (sos_hdr->header.header_version_minor == 1) {
3135 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3136 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3137 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3138 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3139 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3140 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3141 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3142 }
3143 if (sos_hdr->header.header_version_minor == 2) {
3144 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3145 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3146 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3147 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3148 }
3149 if (sos_hdr->header.header_version_minor == 3) {
3150 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3151 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3152 adev->psp.toc.start_addr = ucode_array_start_addr +
3153 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3154 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3155 adev->psp.kdb.start_addr = ucode_array_start_addr +
3156 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3157 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3158 adev->psp.spl.start_addr = ucode_array_start_addr +
3159 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3160 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3161 adev->psp.rl.start_addr = ucode_array_start_addr +
3162 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3163 }
3164 break;
3165 case 2:
3166 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3167
3168 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3169 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3170 err = -EINVAL;
3171 goto out;
3172 }
3173
3174 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3175 err = parse_sos_bin_descriptor(psp,
3176 &sos_hdr_v2_0->psp_fw_bin[fw_index],
3177 sos_hdr_v2_0);
3178 if (err)
3179 goto out;
3180 }
3181 break;
3182 default:
3183 dev_err(adev->dev,
3184 "unsupported psp sos firmware\n");
3185 err = -EINVAL;
3186 goto out;
3187 }
3188
3189 return 0;
3190 out:
3191 dev_err(adev->dev,
3192 "failed to init sos firmware\n");
3193 release_firmware(adev->psp.sos_fw);
3194 adev->psp.sos_fw = NULL;
3195
3196 return err;
3197 }
3198
3199 static int parse_ta_bin_descriptor(struct psp_context *psp,
3200 const struct psp_fw_bin_desc *desc,
3201 const struct ta_firmware_header_v2_0 *ta_hdr)
3202 {
3203 uint8_t *ucode_start_addr = NULL;
3204
3205 if (!psp || !desc || !ta_hdr)
3206 return -EINVAL;
3207
3208 ucode_start_addr = (uint8_t *)ta_hdr +
3209 le32_to_cpu(desc->offset_bytes) +
3210 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3211
3212 switch (desc->fw_type) {
3213 case TA_FW_TYPE_PSP_ASD:
3214 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3215 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version);
3216 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3217 psp->asd_context.bin_desc.start_addr = ucode_start_addr;
3218 break;
3219 case TA_FW_TYPE_PSP_XGMI:
3220 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3221 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3222 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;
3223 break;
3224 case TA_FW_TYPE_PSP_RAS:
3225 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3226 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3227 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;
3228 break;
3229 case TA_FW_TYPE_PSP_HDCP:
3230 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3231 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3232 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;
3233 break;
3234 case TA_FW_TYPE_PSP_DTM:
3235 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3236 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3237 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;
3238 break;
3239 case TA_FW_TYPE_PSP_RAP:
3240 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3241 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3242 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;
3243 break;
3244 case TA_FW_TYPE_PSP_SECUREDISPLAY:
3245 psp->securedisplay_context.context.bin_desc.fw_version =
3246 le32_to_cpu(desc->fw_version);
3247 psp->securedisplay_context.context.bin_desc.size_bytes =
3248 le32_to_cpu(desc->size_bytes);
3249 psp->securedisplay_context.context.bin_desc.start_addr =
3250 ucode_start_addr;
3251 break;
3252 default:
3253 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3254 break;
3255 }
3256
3257 return 0;
3258 }
3259
3260 int psp_init_ta_microcode(struct psp_context *psp,
3261 const char *chip_name)
3262 {
3263 struct amdgpu_device *adev = psp->adev;
3264 char fw_name[PSP_FW_NAME_LEN];
3265 const struct ta_firmware_header_v2_0 *ta_hdr;
3266 int err = 0;
3267 int ta_index = 0;
3268
3269 if (!chip_name) {
3270 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3271 return -EINVAL;
3272 }
3273
3274 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3275 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3276 if (err)
3277 goto out;
3278
3279 err = amdgpu_ucode_validate(adev->psp.ta_fw);
3280 if (err)
3281 goto out;
3282
3283 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3284
3285 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3286 dev_err(adev->dev, "unsupported TA header version\n");
3287 err = -EINVAL;
3288 goto out;
3289 }
3290
3291 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3292 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3293 err = -EINVAL;
3294 goto out;
3295 }
3296
3297 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3298 err = parse_ta_bin_descriptor(psp,
3299 &ta_hdr->ta_fw_bin[ta_index],
3300 ta_hdr);
3301 if (err)
3302 goto out;
3303 }
3304
3305 return 0;
3306 out:
3307 dev_err(adev->dev, "fail to initialize ta microcode\n");
3308 release_firmware(adev->psp.ta_fw);
3309 adev->psp.ta_fw = NULL;
3310 return err;
3311 }
3312
3313 int psp_init_cap_microcode(struct psp_context *psp,
3314 const char *chip_name)
3315 {
3316 struct amdgpu_device *adev = psp->adev;
3317 char fw_name[PSP_FW_NAME_LEN];
3318 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3319 struct amdgpu_firmware_info *info = NULL;
3320 int err = 0;
3321
3322 if (!chip_name) {
3323 dev_err(adev->dev, "invalid chip name for cap microcode\n");
3324 return -EINVAL;
3325 }
3326
3327 if (!amdgpu_sriov_vf(adev)) {
3328 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3329 return -EINVAL;
3330 }
3331
3332 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3333 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);
3334 if (err) {
3335 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3336 err = 0;
3337 goto out;
3338 }
3339
3340 err = amdgpu_ucode_validate(adev->psp.cap_fw);
3341 if (err) {
3342 dev_err(adev->dev, "fail to initialize cap microcode\n");
3343 goto out;
3344 }
3345
3346 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3347 info->ucode_id = AMDGPU_UCODE_ID_CAP;
3348 info->fw = adev->psp.cap_fw;
3349 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3350 adev->psp.cap_fw->data;
3351 adev->firmware.fw_size += ALIGN(
3352 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3353 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3354 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3355 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3356
3357 return 0;
3358
3359 out:
3360 release_firmware(adev->psp.cap_fw);
3361 adev->psp.cap_fw = NULL;
3362 return err;
3363 }
3364
3365 static int psp_set_clockgating_state(void *handle,
3366 enum amd_clockgating_state state)
3367 {
3368 return 0;
3369 }
3370
3371 static int psp_set_powergating_state(void *handle,
3372 enum amd_powergating_state state)
3373 {
3374 return 0;
3375 }
3376
3377 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3378 struct device_attribute *attr,
3379 char *buf)
3380 {
3381 struct drm_device *ddev = dev_get_drvdata(dev);
3382 struct amdgpu_device *adev = drm_to_adev(ddev);
3383 uint32_t fw_ver;
3384 int ret;
3385
3386 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3387 DRM_INFO("PSP block is not ready yet.");
3388 return -EBUSY;
3389 }
3390
3391 mutex_lock(&adev->psp.mutex);
3392 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3393 mutex_unlock(&adev->psp.mutex);
3394
3395 if (ret) {
3396 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3397 return ret;
3398 }
3399
3400 return sysfs_emit(buf, "%x\n", fw_ver);
3401 }
3402
3403 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3404 struct device_attribute *attr,
3405 const char *buf,
3406 size_t count)
3407 {
3408 struct drm_device *ddev = dev_get_drvdata(dev);
3409 struct amdgpu_device *adev = drm_to_adev(ddev);
3410 int ret, idx;
3411 char fw_name[100];
3412 const struct firmware *usbc_pd_fw;
3413 struct amdgpu_bo *fw_buf_bo = NULL;
3414 uint64_t fw_pri_mc_addr;
3415 void *fw_pri_cpu_addr;
3416
3417 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3418 DRM_INFO("PSP block is not ready yet.");
3419 return -EBUSY;
3420 }
3421
3422 if (!drm_dev_enter(ddev, &idx))
3423 return -ENODEV;
3424
3425 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3426 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3427 if (ret)
3428 goto fail;
3429
3430 /* LFB address which is aligned to 1MB boundary per PSP request */
3431 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3432 AMDGPU_GEM_DOMAIN_VRAM,
3433 &fw_buf_bo,
3434 &fw_pri_mc_addr,
3435 &fw_pri_cpu_addr);
3436 if (ret)
3437 goto rel_buf;
3438
3439 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3440
3441 mutex_lock(&adev->psp.mutex);
3442 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3443 mutex_unlock(&adev->psp.mutex);
3444
3445 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3446
3447 rel_buf:
3448 release_firmware(usbc_pd_fw);
3449 fail:
3450 if (ret) {
3451 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3452 count = ret;
3453 }
3454
3455 drm_dev_exit(idx);
3456 return count;
3457 }
3458
3459 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3460 {
3461 int idx;
3462
3463 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3464 return;
3465
3466 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3467 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3468
3469 drm_dev_exit(idx);
3470 }
3471
3472 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3473 psp_usbc_pd_fw_sysfs_read,
3474 psp_usbc_pd_fw_sysfs_write);
3475
3476 int is_psp_fw_valid(struct psp_bin_desc bin)
3477 {
3478 return bin.size_bytes;
3479 }
3480
3481 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3482 struct bin_attribute *bin_attr,
3483 char *buffer, loff_t pos, size_t count)
3484 {
3485 struct device *dev = kobj_to_dev(kobj);
3486 struct drm_device *ddev = dev_get_drvdata(dev);
3487 struct amdgpu_device *adev = drm_to_adev(ddev);
3488
3489 adev->psp.vbflash_done = false;
3490
3491 /* Safeguard against memory drain */
3492 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3493 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3494 kvfree(adev->psp.vbflash_tmp_buf);
3495 adev->psp.vbflash_tmp_buf = NULL;
3496 adev->psp.vbflash_image_size = 0;
3497 return -ENOMEM;
3498 }
3499
3500 /* TODO Just allocate max for now and optimize to realloc later if needed */
3501 if (!adev->psp.vbflash_tmp_buf) {
3502 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3503 if (!adev->psp.vbflash_tmp_buf)
3504 return -ENOMEM;
3505 }
3506
3507 mutex_lock(&adev->psp.mutex);
3508 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3509 adev->psp.vbflash_image_size += count;
3510 mutex_unlock(&adev->psp.mutex);
3511
3512 dev_info(adev->dev, "VBIOS flash write PSP done");
3513
3514 return count;
3515 }
3516
3517 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3518 struct bin_attribute *bin_attr, char *buffer,
3519 loff_t pos, size_t count)
3520 {
3521 struct device *dev = kobj_to_dev(kobj);
3522 struct drm_device *ddev = dev_get_drvdata(dev);
3523 struct amdgpu_device *adev = drm_to_adev(ddev);
3524 struct amdgpu_bo *fw_buf_bo = NULL;
3525 uint64_t fw_pri_mc_addr;
3526 void *fw_pri_cpu_addr;
3527 int ret;
3528
3529 dev_info(adev->dev, "VBIOS flash to PSP started");
3530
3531 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3532 AMDGPU_GPU_PAGE_SIZE,
3533 AMDGPU_GEM_DOMAIN_VRAM,
3534 &fw_buf_bo,
3535 &fw_pri_mc_addr,
3536 &fw_pri_cpu_addr);
3537 if (ret)
3538 goto rel_buf;
3539
3540 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3541
3542 mutex_lock(&adev->psp.mutex);
3543 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3544 mutex_unlock(&adev->psp.mutex);
3545
3546 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3547
3548 rel_buf:
3549 kvfree(adev->psp.vbflash_tmp_buf);
3550 adev->psp.vbflash_tmp_buf = NULL;
3551 adev->psp.vbflash_image_size = 0;
3552
3553 if (ret) {
3554 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3555 return ret;
3556 }
3557
3558 dev_info(adev->dev, "VBIOS flash to PSP done");
3559 return 0;
3560 }
3561
3562 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3563 struct device_attribute *attr,
3564 char *buf)
3565 {
3566 struct drm_device *ddev = dev_get_drvdata(dev);
3567 struct amdgpu_device *adev = drm_to_adev(ddev);
3568 uint32_t vbflash_status;
3569
3570 vbflash_status = psp_vbflash_status(&adev->psp);
3571 if (!adev->psp.vbflash_done)
3572 vbflash_status = 0;
3573 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3574 vbflash_status = 1;
3575
3576 return sysfs_emit(buf, "0x%x\n", vbflash_status);
3577 }
3578
3579 static const struct bin_attribute psp_vbflash_bin_attr = {
3580 .attr = {.name = "psp_vbflash", .mode = 0664},
3581 .size = 0,
3582 .write = amdgpu_psp_vbflash_write,
3583 .read = amdgpu_psp_vbflash_read,
3584 };
3585
3586 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
3587
3588 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3589 {
3590 int ret = 0;
3591 struct psp_context *psp = &adev->psp;
3592
3593 if (amdgpu_sriov_vf(adev))
3594 return -EINVAL;
3595
3596 switch (adev->ip_versions[MP0_HWIP][0]) {
3597 case IP_VERSION(13, 0, 0):
3598 case IP_VERSION(13, 0, 7):
3599 if (!psp->adev) {
3600 psp->adev = adev;
3601 psp_v13_0_set_psp_funcs(psp);
3602 }
3603 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3604 if (ret)
3605 dev_err(adev->dev, "Failed to create device file psp_vbflash");
3606 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3607 if (ret)
3608 dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3609 return ret;
3610 default:
3611 return 0;
3612 }
3613 }
3614
3615 const struct amd_ip_funcs psp_ip_funcs = {
3616 .name = "psp",
3617 .early_init = psp_early_init,
3618 .late_init = NULL,
3619 .sw_init = psp_sw_init,
3620 .sw_fini = psp_sw_fini,
3621 .hw_init = psp_hw_init,
3622 .hw_fini = psp_hw_fini,
3623 .suspend = psp_suspend,
3624 .resume = psp_resume,
3625 .is_idle = NULL,
3626 .check_soft_reset = NULL,
3627 .wait_for_idle = NULL,
3628 .soft_reset = NULL,
3629 .set_clockgating_state = psp_set_clockgating_state,
3630 .set_powergating_state = psp_set_powergating_state,
3631 };
3632
3633 static int psp_sysfs_init(struct amdgpu_device *adev)
3634 {
3635 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3636
3637 if (ret)
3638 DRM_ERROR("Failed to create USBC PD FW control file!");
3639
3640 return ret;
3641 }
3642
3643 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3644 {
3645 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3646 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3647 }
3648
3649 static void psp_sysfs_fini(struct amdgpu_device *adev)
3650 {
3651 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3652 }
3653
3654 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3655 {
3656 .type = AMD_IP_BLOCK_TYPE_PSP,
3657 .major = 3,
3658 .minor = 1,
3659 .rev = 0,
3660 .funcs = &psp_ip_funcs,
3661 };
3662
3663 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3664 {
3665 .type = AMD_IP_BLOCK_TYPE_PSP,
3666 .major = 10,
3667 .minor = 0,
3668 .rev = 0,
3669 .funcs = &psp_ip_funcs,
3670 };
3671
3672 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3673 {
3674 .type = AMD_IP_BLOCK_TYPE_PSP,
3675 .major = 11,
3676 .minor = 0,
3677 .rev = 0,
3678 .funcs = &psp_ip_funcs,
3679 };
3680
3681 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3682 .type = AMD_IP_BLOCK_TYPE_PSP,
3683 .major = 11,
3684 .minor = 0,
3685 .rev = 8,
3686 .funcs = &psp_ip_funcs,
3687 };
3688
3689 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3690 {
3691 .type = AMD_IP_BLOCK_TYPE_PSP,
3692 .major = 12,
3693 .minor = 0,
3694 .rev = 0,
3695 .funcs = &psp_ip_funcs,
3696 };
3697
3698 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3699 .type = AMD_IP_BLOCK_TYPE_PSP,
3700 .major = 13,
3701 .minor = 0,
3702 .rev = 0,
3703 .funcs = &psp_ip_funcs,
3704 };
3705
3706 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3707 .type = AMD_IP_BLOCK_TYPE_PSP,
3708 .major = 13,
3709 .minor = 0,
3710 .rev = 4,
3711 .funcs = &psp_ip_funcs,
3712 };
Michael's Linux tree.