2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <drm/ttm/ttm_bo_api.h>
33 #include <drm/ttm/ttm_bo_driver.h>
34 #include <drm/ttm/ttm_placement.h>
35 #include <drm/ttm/ttm_module.h>
36 #include <drm/ttm/ttm_page_alloc.h>
38 #include <drm/amdgpu_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swiotlb.h>
42 #include <linux/swap.h>
43 #include <linux/pagemap.h>
44 #include <linux/debugfs.h>
45 #include <linux/iommu.h>
46 #include <linux/hmm.h>
48 #include "amdgpu_object.h"
49 #include "amdgpu_trace.h"
50 #include "amdgpu_amdkfd.h"
51 #include "amdgpu_sdma.h"
52 #include "bif/bif_4_1_d.h"
54 static int amdgpu_map_buffer(struct ttm_buffer_object
*bo
,
55 struct ttm_mem_reg
*mem
, unsigned num_pages
,
56 uint64_t offset
, unsigned window
,
57 struct amdgpu_ring
*ring
,
60 static int amdgpu_ttm_debugfs_init(struct amdgpu_device
*adev
);
61 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device
*adev
);
63 static int amdgpu_invalidate_caches(struct ttm_bo_device
*bdev
, uint32_t flags
)
69 * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
72 * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
73 * @type: The type of memory requested
74 * @man: The memory type manager for each domain
76 * This is called by ttm_bo_init_mm() when a buffer object is being
79 static int amdgpu_init_mem_type(struct ttm_bo_device
*bdev
, uint32_t type
,
80 struct ttm_mem_type_manager
*man
)
82 struct amdgpu_device
*adev
;
84 adev
= amdgpu_ttm_adev(bdev
);
89 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
90 man
->available_caching
= TTM_PL_MASK_CACHING
;
91 man
->default_caching
= TTM_PL_FLAG_CACHED
;
95 man
->func
= &amdgpu_gtt_mgr_func
;
96 man
->gpu_offset
= adev
->gmc
.gart_start
;
97 man
->available_caching
= TTM_PL_MASK_CACHING
;
98 man
->default_caching
= TTM_PL_FLAG_CACHED
;
99 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
| TTM_MEMTYPE_FLAG_CMA
;
102 /* "On-card" video ram */
103 man
->func
= &amdgpu_vram_mgr_func
;
104 man
->gpu_offset
= adev
->gmc
.vram_start
;
105 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
|
106 TTM_MEMTYPE_FLAG_MAPPABLE
;
107 man
->available_caching
= TTM_PL_FLAG_UNCACHED
| TTM_PL_FLAG_WC
;
108 man
->default_caching
= TTM_PL_FLAG_WC
;
113 /* On-chip GDS memory*/
114 man
->func
= &ttm_bo_manager_func
;
116 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
| TTM_MEMTYPE_FLAG_CMA
;
117 man
->available_caching
= TTM_PL_FLAG_UNCACHED
;
118 man
->default_caching
= TTM_PL_FLAG_UNCACHED
;
121 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type
);
128 * amdgpu_evict_flags - Compute placement flags
130 * @bo: The buffer object to evict
131 * @placement: Possible destination(s) for evicted BO
133 * Fill in placement data when ttm_bo_evict() is called
135 static void amdgpu_evict_flags(struct ttm_buffer_object
*bo
,
136 struct ttm_placement
*placement
)
138 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->bdev
);
139 struct amdgpu_bo
*abo
;
140 static const struct ttm_place placements
= {
143 .flags
= TTM_PL_MASK_CACHING
| TTM_PL_FLAG_SYSTEM
146 /* Don't handle scatter gather BOs */
147 if (bo
->type
== ttm_bo_type_sg
) {
148 placement
->num_placement
= 0;
149 placement
->num_busy_placement
= 0;
153 /* Object isn't an AMDGPU object so ignore */
154 if (!amdgpu_bo_is_amdgpu_bo(bo
)) {
155 placement
->placement
= &placements
;
156 placement
->busy_placement
= &placements
;
157 placement
->num_placement
= 1;
158 placement
->num_busy_placement
= 1;
162 abo
= ttm_to_amdgpu_bo(bo
);
163 switch (bo
->mem
.mem_type
) {
167 placement
->num_placement
= 0;
168 placement
->num_busy_placement
= 0;
172 if (!adev
->mman
.buffer_funcs_enabled
) {
173 /* Move to system memory */
174 amdgpu_bo_placement_from_domain(abo
, AMDGPU_GEM_DOMAIN_CPU
);
175 } else if (!amdgpu_gmc_vram_full_visible(&adev
->gmc
) &&
176 !(abo
->flags
& AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
) &&
177 amdgpu_bo_in_cpu_visible_vram(abo
)) {
179 /* Try evicting to the CPU inaccessible part of VRAM
180 * first, but only set GTT as busy placement, so this
181 * BO will be evicted to GTT rather than causing other
182 * BOs to be evicted from VRAM
184 amdgpu_bo_placement_from_domain(abo
, AMDGPU_GEM_DOMAIN_VRAM
|
185 AMDGPU_GEM_DOMAIN_GTT
);
186 abo
->placements
[0].fpfn
= adev
->gmc
.visible_vram_size
>> PAGE_SHIFT
;
187 abo
->placements
[0].lpfn
= 0;
188 abo
->placement
.busy_placement
= &abo
->placements
[1];
189 abo
->placement
.num_busy_placement
= 1;
191 /* Move to GTT memory */
192 amdgpu_bo_placement_from_domain(abo
, AMDGPU_GEM_DOMAIN_GTT
);
197 amdgpu_bo_placement_from_domain(abo
, AMDGPU_GEM_DOMAIN_CPU
);
200 *placement
= abo
->placement
;
204 * amdgpu_verify_access - Verify access for a mmap call
206 * @bo: The buffer object to map
207 * @filp: The file pointer from the process performing the mmap
209 * This is called by ttm_bo_mmap() to verify whether a process
210 * has the right to mmap a BO to their process space.
212 static int amdgpu_verify_access(struct ttm_buffer_object
*bo
, struct file
*filp
)
214 struct amdgpu_bo
*abo
= ttm_to_amdgpu_bo(bo
);
217 * Don't verify access for KFD BOs. They don't have a GEM
218 * object associated with them.
223 if (amdgpu_ttm_tt_get_usermm(bo
->ttm
))
225 return drm_vma_node_verify_access(&abo
->gem_base
.vma_node
,
230 * amdgpu_move_null - Register memory for a buffer object
232 * @bo: The bo to assign the memory to
233 * @new_mem: The memory to be assigned.
235 * Assign the memory from new_mem to the memory of the buffer object bo.
237 static void amdgpu_move_null(struct ttm_buffer_object
*bo
,
238 struct ttm_mem_reg
*new_mem
)
240 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
242 BUG_ON(old_mem
->mm_node
!= NULL
);
244 new_mem
->mm_node
= NULL
;
248 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
250 * @bo: The bo to assign the memory to.
251 * @mm_node: Memory manager node for drm allocator.
252 * @mem: The region where the bo resides.
255 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object
*bo
,
256 struct drm_mm_node
*mm_node
,
257 struct ttm_mem_reg
*mem
)
261 if (mm_node
->start
!= AMDGPU_BO_INVALID_OFFSET
) {
262 addr
= mm_node
->start
<< PAGE_SHIFT
;
263 addr
+= bo
->bdev
->man
[mem
->mem_type
].gpu_offset
;
269 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
270 * @offset. It also modifies the offset to be within the drm_mm_node returned
272 * @mem: The region where the bo resides.
273 * @offset: The offset that drm_mm_node is used for finding.
276 static struct drm_mm_node
*amdgpu_find_mm_node(struct ttm_mem_reg
*mem
,
277 unsigned long *offset
)
279 struct drm_mm_node
*mm_node
= mem
->mm_node
;
281 while (*offset
>= (mm_node
->size
<< PAGE_SHIFT
)) {
282 *offset
-= (mm_node
->size
<< PAGE_SHIFT
);
289 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
291 * The function copies @size bytes from {src->mem + src->offset} to
292 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
293 * move and different for a BO to BO copy.
295 * @f: Returns the last fence if multiple jobs are submitted.
297 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device
*adev
,
298 struct amdgpu_copy_mem
*src
,
299 struct amdgpu_copy_mem
*dst
,
301 struct reservation_object
*resv
,
302 struct dma_fence
**f
)
304 struct amdgpu_ring
*ring
= adev
->mman
.buffer_funcs_ring
;
305 struct drm_mm_node
*src_mm
, *dst_mm
;
306 uint64_t src_node_start
, dst_node_start
, src_node_size
,
307 dst_node_size
, src_page_offset
, dst_page_offset
;
308 struct dma_fence
*fence
= NULL
;
310 const uint64_t GTT_MAX_BYTES
= (AMDGPU_GTT_MAX_TRANSFER_SIZE
*
311 AMDGPU_GPU_PAGE_SIZE
);
313 if (!adev
->mman
.buffer_funcs_enabled
) {
314 DRM_ERROR("Trying to move memory with ring turned off.\n");
318 src_mm
= amdgpu_find_mm_node(src
->mem
, &src
->offset
);
319 src_node_start
= amdgpu_mm_node_addr(src
->bo
, src_mm
, src
->mem
) +
321 src_node_size
= (src_mm
->size
<< PAGE_SHIFT
) - src
->offset
;
322 src_page_offset
= src_node_start
& (PAGE_SIZE
- 1);
324 dst_mm
= amdgpu_find_mm_node(dst
->mem
, &dst
->offset
);
325 dst_node_start
= amdgpu_mm_node_addr(dst
->bo
, dst_mm
, dst
->mem
) +
327 dst_node_size
= (dst_mm
->size
<< PAGE_SHIFT
) - dst
->offset
;
328 dst_page_offset
= dst_node_start
& (PAGE_SIZE
- 1);
330 mutex_lock(&adev
->mman
.gtt_window_lock
);
333 unsigned long cur_size
;
334 uint64_t from
= src_node_start
, to
= dst_node_start
;
335 struct dma_fence
*next
;
337 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
338 * begins at an offset, then adjust the size accordingly
340 cur_size
= min3(min(src_node_size
, dst_node_size
), size
,
342 if (cur_size
+ src_page_offset
> GTT_MAX_BYTES
||
343 cur_size
+ dst_page_offset
> GTT_MAX_BYTES
)
344 cur_size
-= max(src_page_offset
, dst_page_offset
);
346 /* Map only what needs to be accessed. Map src to window 0 and
349 if (src
->mem
->start
== AMDGPU_BO_INVALID_OFFSET
) {
350 r
= amdgpu_map_buffer(src
->bo
, src
->mem
,
351 PFN_UP(cur_size
+ src_page_offset
),
352 src_node_start
, 0, ring
,
356 /* Adjust the offset because amdgpu_map_buffer returns
357 * start of mapped page
359 from
+= src_page_offset
;
362 if (dst
->mem
->start
== AMDGPU_BO_INVALID_OFFSET
) {
363 r
= amdgpu_map_buffer(dst
->bo
, dst
->mem
,
364 PFN_UP(cur_size
+ dst_page_offset
),
365 dst_node_start
, 1, ring
,
369 to
+= dst_page_offset
;
372 r
= amdgpu_copy_buffer(ring
, from
, to
, cur_size
,
373 resv
, &next
, false, true);
377 dma_fence_put(fence
);
384 src_node_size
-= cur_size
;
385 if (!src_node_size
) {
386 src_node_start
= amdgpu_mm_node_addr(src
->bo
, ++src_mm
,
388 src_node_size
= (src_mm
->size
<< PAGE_SHIFT
);
390 src_node_start
+= cur_size
;
391 src_page_offset
= src_node_start
& (PAGE_SIZE
- 1);
393 dst_node_size
-= cur_size
;
394 if (!dst_node_size
) {
395 dst_node_start
= amdgpu_mm_node_addr(dst
->bo
, ++dst_mm
,
397 dst_node_size
= (dst_mm
->size
<< PAGE_SHIFT
);
399 dst_node_start
+= cur_size
;
400 dst_page_offset
= dst_node_start
& (PAGE_SIZE
- 1);
404 mutex_unlock(&adev
->mman
.gtt_window_lock
);
406 *f
= dma_fence_get(fence
);
407 dma_fence_put(fence
);
412 * amdgpu_move_blit - Copy an entire buffer to another buffer
414 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
415 * help move buffers to and from VRAM.
417 static int amdgpu_move_blit(struct ttm_buffer_object
*bo
,
418 bool evict
, bool no_wait_gpu
,
419 struct ttm_mem_reg
*new_mem
,
420 struct ttm_mem_reg
*old_mem
)
422 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->bdev
);
423 struct amdgpu_copy_mem src
, dst
;
424 struct dma_fence
*fence
= NULL
;
434 r
= amdgpu_ttm_copy_mem_to_mem(adev
, &src
, &dst
,
435 new_mem
->num_pages
<< PAGE_SHIFT
,
440 /* Always block for VM page tables before committing the new location */
441 if (bo
->type
== ttm_bo_type_kernel
)
442 r
= ttm_bo_move_accel_cleanup(bo
, fence
, true, new_mem
);
444 r
= ttm_bo_pipeline_move(bo
, fence
, evict
, new_mem
);
445 dma_fence_put(fence
);
450 dma_fence_wait(fence
, false);
451 dma_fence_put(fence
);
456 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
458 * Called by amdgpu_bo_move().
460 static int amdgpu_move_vram_ram(struct ttm_buffer_object
*bo
, bool evict
,
461 struct ttm_operation_ctx
*ctx
,
462 struct ttm_mem_reg
*new_mem
)
464 struct amdgpu_device
*adev
;
465 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
466 struct ttm_mem_reg tmp_mem
;
467 struct ttm_place placements
;
468 struct ttm_placement placement
;
471 adev
= amdgpu_ttm_adev(bo
->bdev
);
473 /* create space/pages for new_mem in GTT space */
475 tmp_mem
.mm_node
= NULL
;
476 placement
.num_placement
= 1;
477 placement
.placement
= &placements
;
478 placement
.num_busy_placement
= 1;
479 placement
.busy_placement
= &placements
;
482 placements
.flags
= TTM_PL_MASK_CACHING
| TTM_PL_FLAG_TT
;
483 r
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, ctx
);
488 /* set caching flags */
489 r
= ttm_tt_set_placement_caching(bo
->ttm
, tmp_mem
.placement
);
494 /* Bind the memory to the GTT space */
495 r
= ttm_tt_bind(bo
->ttm
, &tmp_mem
, ctx
);
500 /* blit VRAM to GTT */
501 r
= amdgpu_move_blit(bo
, evict
, ctx
->no_wait_gpu
, &tmp_mem
, old_mem
);
506 /* move BO (in tmp_mem) to new_mem */
507 r
= ttm_bo_move_ttm(bo
, ctx
, new_mem
);
509 ttm_bo_mem_put(bo
, &tmp_mem
);
514 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
516 * Called by amdgpu_bo_move().
518 static int amdgpu_move_ram_vram(struct ttm_buffer_object
*bo
, bool evict
,
519 struct ttm_operation_ctx
*ctx
,
520 struct ttm_mem_reg
*new_mem
)
522 struct amdgpu_device
*adev
;
523 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
524 struct ttm_mem_reg tmp_mem
;
525 struct ttm_placement placement
;
526 struct ttm_place placements
;
529 adev
= amdgpu_ttm_adev(bo
->bdev
);
531 /* make space in GTT for old_mem buffer */
533 tmp_mem
.mm_node
= NULL
;
534 placement
.num_placement
= 1;
535 placement
.placement
= &placements
;
536 placement
.num_busy_placement
= 1;
537 placement
.busy_placement
= &placements
;
540 placements
.flags
= TTM_PL_MASK_CACHING
| TTM_PL_FLAG_TT
;
541 r
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, ctx
);
546 /* move/bind old memory to GTT space */
547 r
= ttm_bo_move_ttm(bo
, ctx
, &tmp_mem
);
553 r
= amdgpu_move_blit(bo
, evict
, ctx
->no_wait_gpu
, new_mem
, old_mem
);
558 ttm_bo_mem_put(bo
, &tmp_mem
);
563 * amdgpu_bo_move - Move a buffer object to a new memory location
565 * Called by ttm_bo_handle_move_mem()
567 static int amdgpu_bo_move(struct ttm_buffer_object
*bo
, bool evict
,
568 struct ttm_operation_ctx
*ctx
,
569 struct ttm_mem_reg
*new_mem
)
571 struct amdgpu_device
*adev
;
572 struct amdgpu_bo
*abo
;
573 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
576 /* Can't move a pinned BO */
577 abo
= ttm_to_amdgpu_bo(bo
);
578 if (WARN_ON_ONCE(abo
->pin_count
> 0))
581 adev
= amdgpu_ttm_adev(bo
->bdev
);
583 if (old_mem
->mem_type
== TTM_PL_SYSTEM
&& bo
->ttm
== NULL
) {
584 amdgpu_move_null(bo
, new_mem
);
587 if ((old_mem
->mem_type
== TTM_PL_TT
&&
588 new_mem
->mem_type
== TTM_PL_SYSTEM
) ||
589 (old_mem
->mem_type
== TTM_PL_SYSTEM
&&
590 new_mem
->mem_type
== TTM_PL_TT
)) {
592 amdgpu_move_null(bo
, new_mem
);
595 if (old_mem
->mem_type
== AMDGPU_PL_GDS
||
596 old_mem
->mem_type
== AMDGPU_PL_GWS
||
597 old_mem
->mem_type
== AMDGPU_PL_OA
||
598 new_mem
->mem_type
== AMDGPU_PL_GDS
||
599 new_mem
->mem_type
== AMDGPU_PL_GWS
||
600 new_mem
->mem_type
== AMDGPU_PL_OA
) {
601 /* Nothing to save here */
602 amdgpu_move_null(bo
, new_mem
);
606 if (!adev
->mman
.buffer_funcs_enabled
)
609 if (old_mem
->mem_type
== TTM_PL_VRAM
&&
610 new_mem
->mem_type
== TTM_PL_SYSTEM
) {
611 r
= amdgpu_move_vram_ram(bo
, evict
, ctx
, new_mem
);
612 } else if (old_mem
->mem_type
== TTM_PL_SYSTEM
&&
613 new_mem
->mem_type
== TTM_PL_VRAM
) {
614 r
= amdgpu_move_ram_vram(bo
, evict
, ctx
, new_mem
);
616 r
= amdgpu_move_blit(bo
, evict
, ctx
->no_wait_gpu
,
622 r
= ttm_bo_move_memcpy(bo
, ctx
, new_mem
);
628 if (bo
->type
== ttm_bo_type_device
&&
629 new_mem
->mem_type
== TTM_PL_VRAM
&&
630 old_mem
->mem_type
!= TTM_PL_VRAM
) {
631 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
632 * accesses the BO after it's moved.
634 abo
->flags
&= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
637 /* update statistics */
638 atomic64_add((u64
)bo
->num_pages
<< PAGE_SHIFT
, &adev
->num_bytes_moved
);
643 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
645 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
647 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
649 struct ttm_mem_type_manager
*man
= &bdev
->man
[mem
->mem_type
];
650 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bdev
);
651 struct drm_mm_node
*mm_node
= mem
->mm_node
;
653 mem
->bus
.addr
= NULL
;
655 mem
->bus
.size
= mem
->num_pages
<< PAGE_SHIFT
;
657 mem
->bus
.is_iomem
= false;
658 if (!(man
->flags
& TTM_MEMTYPE_FLAG_MAPPABLE
))
660 switch (mem
->mem_type
) {
667 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
668 /* check if it's visible */
669 if ((mem
->bus
.offset
+ mem
->bus
.size
) > adev
->gmc
.visible_vram_size
)
671 /* Only physically contiguous buffers apply. In a contiguous
672 * buffer, size of the first mm_node would match the number of
673 * pages in ttm_mem_reg.
675 if (adev
->mman
.aper_base_kaddr
&&
676 (mm_node
->size
== mem
->num_pages
))
677 mem
->bus
.addr
= (u8
*)adev
->mman
.aper_base_kaddr
+
680 mem
->bus
.base
= adev
->gmc
.aper_base
;
681 mem
->bus
.is_iomem
= true;
689 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
693 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object
*bo
,
694 unsigned long page_offset
)
696 struct drm_mm_node
*mm
;
697 unsigned long offset
= (page_offset
<< PAGE_SHIFT
);
699 mm
= amdgpu_find_mm_node(&bo
->mem
, &offset
);
700 return (bo
->mem
.bus
.base
>> PAGE_SHIFT
) + mm
->start
+
701 (offset
>> PAGE_SHIFT
);
705 * TTM backend functions.
707 struct amdgpu_ttm_tt
{
708 struct ttm_dma_tt ttm
;
711 struct task_struct
*usertask
;
713 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
714 struct hmm_range range
;
719 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
720 * memory and start HMM tracking CPU page table update
722 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
723 * once afterwards to stop HMM tracking
725 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
726 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt
*ttm
, struct page
**pages
)
728 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
729 struct mm_struct
*mm
= gtt
->usertask
->mm
;
730 unsigned long end
= gtt
->userptr
+ ttm
->num_pages
* PAGE_SIZE
;
731 struct hmm_range
*range
= >t
->range
;
734 if (!mm
) /* Happens during process shutdown */
737 amdgpu_hmm_init_range(range
);
739 down_read(&mm
->mmap_sem
);
741 range
->vma
= find_vma(mm
, gtt
->userptr
);
742 if (!range_in_vma(range
->vma
, gtt
->userptr
, end
))
744 else if ((gtt
->userflags
& AMDGPU_GEM_USERPTR_ANONONLY
) &&
750 range
->pfns
= kvmalloc_array(ttm
->num_pages
, sizeof(uint64_t),
752 if (range
->pfns
== NULL
) {
756 range
->start
= gtt
->userptr
;
759 range
->pfns
[0] = range
->flags
[HMM_PFN_VALID
];
760 range
->pfns
[0] |= amdgpu_ttm_tt_is_readonly(ttm
) ?
761 0 : range
->flags
[HMM_PFN_WRITE
];
762 for (i
= 1; i
< ttm
->num_pages
; i
++)
763 range
->pfns
[i
] = range
->pfns
[0];
765 /* This may trigger page table update */
766 r
= hmm_vma_fault(range
, true);
770 up_read(&mm
->mmap_sem
);
772 for (i
= 0; i
< ttm
->num_pages
; i
++)
773 pages
[i
] = hmm_pfn_to_page(range
, range
->pfns
[i
]);
781 up_read(&mm
->mmap_sem
);
786 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
787 * Check if the pages backing this ttm range have been invalidated
789 * Returns: true if pages are still valid
791 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt
*ttm
)
793 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
796 if (!gtt
|| !gtt
->userptr
)
799 WARN_ONCE(!gtt
->range
.pfns
, "No user pages to check\n");
800 if (gtt
->range
.pfns
) {
801 r
= hmm_vma_range_done(>t
->range
);
802 kvfree(gtt
->range
.pfns
);
803 gtt
->range
.pfns
= NULL
;
811 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
813 * Called by amdgpu_cs_list_validate(). This creates the page list
814 * that backs user memory and will ultimately be mapped into the device
817 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt
*ttm
, struct page
**pages
)
821 for (i
= 0; i
< ttm
->num_pages
; ++i
)
822 ttm
->pages
[i
] = pages
? pages
[i
] : NULL
;
826 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
828 * Called by amdgpu_ttm_backend_bind()
830 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt
*ttm
)
832 struct amdgpu_device
*adev
= amdgpu_ttm_adev(ttm
->bdev
);
833 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
837 int write
= !(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
838 enum dma_data_direction direction
= write
?
839 DMA_BIDIRECTIONAL
: DMA_TO_DEVICE
;
841 /* Allocate an SG array and squash pages into it */
842 r
= sg_alloc_table_from_pages(ttm
->sg
, ttm
->pages
, ttm
->num_pages
, 0,
843 ttm
->num_pages
<< PAGE_SHIFT
,
848 /* Map SG to device */
850 nents
= dma_map_sg(adev
->dev
, ttm
->sg
->sgl
, ttm
->sg
->nents
, direction
);
851 if (nents
!= ttm
->sg
->nents
)
854 /* convert SG to linear array of pages and dma addresses */
855 drm_prime_sg_to_page_addr_arrays(ttm
->sg
, ttm
->pages
,
856 gtt
->ttm
.dma_address
, ttm
->num_pages
);
866 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
868 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt
*ttm
)
870 struct amdgpu_device
*adev
= amdgpu_ttm_adev(ttm
->bdev
);
871 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
873 int write
= !(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
874 enum dma_data_direction direction
= write
?
875 DMA_BIDIRECTIONAL
: DMA_TO_DEVICE
;
877 /* double check that we don't free the table twice */
881 /* unmap the pages mapped to the device */
882 dma_unmap_sg(adev
->dev
, ttm
->sg
->sgl
, ttm
->sg
->nents
, direction
);
884 sg_free_table(ttm
->sg
);
886 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
887 if (gtt
->range
.pfns
&&
888 ttm
->pages
[0] == hmm_pfn_to_page(>t
->range
, gtt
->range
.pfns
[0]))
889 WARN_ONCE(1, "Missing get_user_page_done\n");
893 int amdgpu_ttm_gart_bind(struct amdgpu_device
*adev
,
894 struct ttm_buffer_object
*tbo
,
897 struct amdgpu_bo
*abo
= ttm_to_amdgpu_bo(tbo
);
898 struct ttm_tt
*ttm
= tbo
->ttm
;
899 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
902 if (abo
->flags
& AMDGPU_GEM_CREATE_MQD_GFX9
) {
903 uint64_t page_idx
= 1;
905 r
= amdgpu_gart_bind(adev
, gtt
->offset
, page_idx
,
906 ttm
->pages
, gtt
->ttm
.dma_address
, flags
);
910 /* Patch mtype of the second part BO */
911 flags
&= ~AMDGPU_PTE_MTYPE_MASK
;
912 flags
|= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC
);
914 r
= amdgpu_gart_bind(adev
,
915 gtt
->offset
+ (page_idx
<< PAGE_SHIFT
),
916 ttm
->num_pages
- page_idx
,
917 &ttm
->pages
[page_idx
],
918 &(gtt
->ttm
.dma_address
[page_idx
]), flags
);
920 r
= amdgpu_gart_bind(adev
, gtt
->offset
, ttm
->num_pages
,
921 ttm
->pages
, gtt
->ttm
.dma_address
, flags
);
926 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
927 ttm
->num_pages
, gtt
->offset
);
933 * amdgpu_ttm_backend_bind - Bind GTT memory
935 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
936 * This handles binding GTT memory to the device address space.
938 static int amdgpu_ttm_backend_bind(struct ttm_tt
*ttm
,
939 struct ttm_mem_reg
*bo_mem
)
941 struct amdgpu_device
*adev
= amdgpu_ttm_adev(ttm
->bdev
);
942 struct amdgpu_ttm_tt
*gtt
= (void*)ttm
;
947 r
= amdgpu_ttm_tt_pin_userptr(ttm
);
949 DRM_ERROR("failed to pin userptr\n");
953 if (!ttm
->num_pages
) {
954 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
955 ttm
->num_pages
, bo_mem
, ttm
);
958 if (bo_mem
->mem_type
== AMDGPU_PL_GDS
||
959 bo_mem
->mem_type
== AMDGPU_PL_GWS
||
960 bo_mem
->mem_type
== AMDGPU_PL_OA
)
963 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem
)) {
964 gtt
->offset
= AMDGPU_BO_INVALID_OFFSET
;
968 /* compute PTE flags relevant to this BO memory */
969 flags
= amdgpu_ttm_tt_pte_flags(adev
, ttm
, bo_mem
);
971 /* bind pages into GART page tables */
972 gtt
->offset
= (u64
)bo_mem
->start
<< PAGE_SHIFT
;
973 r
= amdgpu_gart_bind(adev
, gtt
->offset
, ttm
->num_pages
,
974 ttm
->pages
, gtt
->ttm
.dma_address
, flags
);
977 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
978 ttm
->num_pages
, gtt
->offset
);
983 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
985 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object
*bo
)
987 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->bdev
);
988 struct ttm_operation_ctx ctx
= { false, false };
989 struct amdgpu_ttm_tt
*gtt
= (void*)bo
->ttm
;
990 struct ttm_mem_reg tmp
;
991 struct ttm_placement placement
;
992 struct ttm_place placements
;
993 uint64_t addr
, flags
;
996 if (bo
->mem
.start
!= AMDGPU_BO_INVALID_OFFSET
)
999 addr
= amdgpu_gmc_agp_addr(bo
);
1000 if (addr
!= AMDGPU_BO_INVALID_OFFSET
) {
1001 bo
->mem
.start
= addr
>> PAGE_SHIFT
;
1004 /* allocate GART space */
1007 placement
.num_placement
= 1;
1008 placement
.placement
= &placements
;
1009 placement
.num_busy_placement
= 1;
1010 placement
.busy_placement
= &placements
;
1011 placements
.fpfn
= 0;
1012 placements
.lpfn
= adev
->gmc
.gart_size
>> PAGE_SHIFT
;
1013 placements
.flags
= (bo
->mem
.placement
& ~TTM_PL_MASK_MEM
) |
1016 r
= ttm_bo_mem_space(bo
, &placement
, &tmp
, &ctx
);
1020 /* compute PTE flags for this buffer object */
1021 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo
->ttm
, &tmp
);
1024 gtt
->offset
= (u64
)tmp
.start
<< PAGE_SHIFT
;
1025 r
= amdgpu_ttm_gart_bind(adev
, bo
, flags
);
1027 ttm_bo_mem_put(bo
, &tmp
);
1031 ttm_bo_mem_put(bo
, &bo
->mem
);
1035 bo
->offset
= (bo
->mem
.start
<< PAGE_SHIFT
) +
1036 bo
->bdev
->man
[bo
->mem
.mem_type
].gpu_offset
;
1042 * amdgpu_ttm_recover_gart - Rebind GTT pages
1044 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1045 * rebind GTT pages during a GPU reset.
1047 int amdgpu_ttm_recover_gart(struct ttm_buffer_object
*tbo
)
1049 struct amdgpu_device
*adev
= amdgpu_ttm_adev(tbo
->bdev
);
1056 flags
= amdgpu_ttm_tt_pte_flags(adev
, tbo
->ttm
, &tbo
->mem
);
1057 r
= amdgpu_ttm_gart_bind(adev
, tbo
, flags
);
1063 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1065 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1068 static int amdgpu_ttm_backend_unbind(struct ttm_tt
*ttm
)
1070 struct amdgpu_device
*adev
= amdgpu_ttm_adev(ttm
->bdev
);
1071 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
1074 /* if the pages have userptr pinning then clear that first */
1076 amdgpu_ttm_tt_unpin_userptr(ttm
);
1078 if (gtt
->offset
== AMDGPU_BO_INVALID_OFFSET
)
1081 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1082 r
= amdgpu_gart_unbind(adev
, gtt
->offset
, ttm
->num_pages
);
1084 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1085 gtt
->ttm
.ttm
.num_pages
, gtt
->offset
);
1089 static void amdgpu_ttm_backend_destroy(struct ttm_tt
*ttm
)
1091 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
1094 put_task_struct(gtt
->usertask
);
1096 ttm_dma_tt_fini(>t
->ttm
);
1100 static struct ttm_backend_func amdgpu_backend_func
= {
1101 .bind
= &amdgpu_ttm_backend_bind
,
1102 .unbind
= &amdgpu_ttm_backend_unbind
,
1103 .destroy
= &amdgpu_ttm_backend_destroy
,
1107 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1109 * @bo: The buffer object to create a GTT ttm_tt object around
1111 * Called by ttm_tt_create().
1113 static struct ttm_tt
*amdgpu_ttm_tt_create(struct ttm_buffer_object
*bo
,
1114 uint32_t page_flags
)
1116 struct amdgpu_device
*adev
;
1117 struct amdgpu_ttm_tt
*gtt
;
1119 adev
= amdgpu_ttm_adev(bo
->bdev
);
1121 gtt
= kzalloc(sizeof(struct amdgpu_ttm_tt
), GFP_KERNEL
);
1125 gtt
->ttm
.ttm
.func
= &amdgpu_backend_func
;
1127 /* allocate space for the uninitialized page entries */
1128 if (ttm_sg_tt_init(>t
->ttm
, bo
, page_flags
)) {
1132 return >t
->ttm
.ttm
;
1136 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1138 * Map the pages of a ttm_tt object to an address space visible
1139 * to the underlying device.
1141 static int amdgpu_ttm_tt_populate(struct ttm_tt
*ttm
,
1142 struct ttm_operation_ctx
*ctx
)
1144 struct amdgpu_device
*adev
= amdgpu_ttm_adev(ttm
->bdev
);
1145 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
1146 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
1148 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1149 if (gtt
&& gtt
->userptr
) {
1150 ttm
->sg
= kzalloc(sizeof(struct sg_table
), GFP_KERNEL
);
1154 ttm
->page_flags
|= TTM_PAGE_FLAG_SG
;
1155 ttm
->state
= tt_unbound
;
1159 if (slave
&& ttm
->sg
) {
1160 drm_prime_sg_to_page_addr_arrays(ttm
->sg
, ttm
->pages
,
1161 gtt
->ttm
.dma_address
,
1163 ttm
->state
= tt_unbound
;
1167 #ifdef CONFIG_SWIOTLB
1168 if (adev
->need_swiotlb
&& swiotlb_nr_tbl()) {
1169 return ttm_dma_populate(>t
->ttm
, adev
->dev
, ctx
);
1173 /* fall back to generic helper to populate the page array
1174 * and map them to the device */
1175 return ttm_populate_and_map_pages(adev
->dev
, >t
->ttm
, ctx
);
1179 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1181 * Unmaps pages of a ttm_tt object from the device address space and
1182 * unpopulates the page array backing it.
1184 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt
*ttm
)
1186 struct amdgpu_device
*adev
;
1187 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
1188 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
1190 if (gtt
&& gtt
->userptr
) {
1191 amdgpu_ttm_tt_set_user_pages(ttm
, NULL
);
1193 ttm
->page_flags
&= ~TTM_PAGE_FLAG_SG
;
1200 adev
= amdgpu_ttm_adev(ttm
->bdev
);
1202 #ifdef CONFIG_SWIOTLB
1203 if (adev
->need_swiotlb
&& swiotlb_nr_tbl()) {
1204 ttm_dma_unpopulate(>t
->ttm
, adev
->dev
);
1209 /* fall back to generic helper to unmap and unpopulate array */
1210 ttm_unmap_and_unpopulate_pages(adev
->dev
, >t
->ttm
);
1214 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1217 * @ttm: The ttm_tt object to bind this userptr object to
1218 * @addr: The address in the current tasks VM space to use
1219 * @flags: Requirements of userptr object.
1221 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1224 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
1227 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
1232 gtt
->userptr
= addr
;
1233 gtt
->userflags
= flags
;
1236 put_task_struct(gtt
->usertask
);
1237 gtt
->usertask
= current
->group_leader
;
1238 get_task_struct(gtt
->usertask
);
1244 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1246 struct mm_struct
*amdgpu_ttm_tt_get_usermm(struct ttm_tt
*ttm
)
1248 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
1253 if (gtt
->usertask
== NULL
)
1256 return gtt
->usertask
->mm
;
1260 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1261 * address range for the current task.
1264 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt
*ttm
, unsigned long start
,
1267 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
1270 if (gtt
== NULL
|| !gtt
->userptr
)
1273 /* Return false if no part of the ttm_tt object lies within
1276 size
= (unsigned long)gtt
->ttm
.ttm
.num_pages
* PAGE_SIZE
;
1277 if (gtt
->userptr
> end
|| gtt
->userptr
+ size
<= start
)
1284 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1286 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt
*ttm
)
1288 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
1290 if (gtt
== NULL
|| !gtt
->userptr
)
1297 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1299 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
)
1301 struct amdgpu_ttm_tt
*gtt
= (void *)ttm
;
1306 return !!(gtt
->userflags
& AMDGPU_GEM_USERPTR_READONLY
);
1310 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1312 * @ttm: The ttm_tt object to compute the flags for
1313 * @mem: The memory registry backing this ttm_tt object
1315 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1317 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt
*ttm
, struct ttm_mem_reg
*mem
)
1321 if (mem
&& mem
->mem_type
!= TTM_PL_SYSTEM
)
1322 flags
|= AMDGPU_PTE_VALID
;
1324 if (mem
&& mem
->mem_type
== TTM_PL_TT
) {
1325 flags
|= AMDGPU_PTE_SYSTEM
;
1327 if (ttm
->caching_state
== tt_cached
)
1328 flags
|= AMDGPU_PTE_SNOOPED
;
1335 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1337 * @ttm: The ttm_tt object to compute the flags for
1338 * @mem: The memory registry backing this ttm_tt object
1340 * Figure out the flags to use for a VM PTE (Page Table Entry).
1342 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
1343 struct ttm_mem_reg
*mem
)
1345 uint64_t flags
= amdgpu_ttm_tt_pde_flags(ttm
, mem
);
1347 flags
|= adev
->gart
.gart_pte_flags
;
1348 flags
|= AMDGPU_PTE_READABLE
;
1350 if (!amdgpu_ttm_tt_is_readonly(ttm
))
1351 flags
|= AMDGPU_PTE_WRITEABLE
;
1357 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1360 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1361 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1362 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1363 * used to clean out a memory space.
1365 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object
*bo
,
1366 const struct ttm_place
*place
)
1368 unsigned long num_pages
= bo
->mem
.num_pages
;
1369 struct drm_mm_node
*node
= bo
->mem
.mm_node
;
1370 struct reservation_object_list
*flist
;
1371 struct dma_fence
*f
;
1374 /* If bo is a KFD BO, check if the bo belongs to the current process.
1375 * If true, then return false as any KFD process needs all its BOs to
1376 * be resident to run successfully
1378 flist
= reservation_object_get_list(bo
->resv
);
1380 for (i
= 0; i
< flist
->shared_count
; ++i
) {
1381 f
= rcu_dereference_protected(flist
->shared
[i
],
1382 reservation_object_held(bo
->resv
));
1383 if (amdkfd_fence_check_mm(f
, current
->mm
))
1388 switch (bo
->mem
.mem_type
) {
1393 /* Check each drm MM node individually */
1395 if (place
->fpfn
< (node
->start
+ node
->size
) &&
1396 !(place
->lpfn
&& place
->lpfn
<= node
->start
))
1399 num_pages
-= node
->size
;
1408 return ttm_bo_eviction_valuable(bo
, place
);
1412 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1414 * @bo: The buffer object to read/write
1415 * @offset: Offset into buffer object
1416 * @buf: Secondary buffer to write/read from
1417 * @len: Length in bytes of access
1418 * @write: true if writing
1420 * This is used to access VRAM that backs a buffer object via MMIO
1421 * access for debugging purposes.
1423 static int amdgpu_ttm_access_memory(struct ttm_buffer_object
*bo
,
1424 unsigned long offset
,
1425 void *buf
, int len
, int write
)
1427 struct amdgpu_bo
*abo
= ttm_to_amdgpu_bo(bo
);
1428 struct amdgpu_device
*adev
= amdgpu_ttm_adev(abo
->tbo
.bdev
);
1429 struct drm_mm_node
*nodes
;
1433 unsigned long flags
;
1435 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
)
1438 nodes
= amdgpu_find_mm_node(&abo
->tbo
.mem
, &offset
);
1439 pos
= (nodes
->start
<< PAGE_SHIFT
) + offset
;
1441 while (len
&& pos
< adev
->gmc
.mc_vram_size
) {
1442 uint64_t aligned_pos
= pos
& ~(uint64_t)3;
1443 uint32_t bytes
= 4 - (pos
& 3);
1444 uint32_t shift
= (pos
& 3) * 8;
1445 uint32_t mask
= 0xffffffff << shift
;
1448 mask
&= 0xffffffff >> (bytes
- len
) * 8;
1452 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
1453 WREG32_NO_KIQ(mmMM_INDEX
, ((uint32_t)aligned_pos
) | 0x80000000);
1454 WREG32_NO_KIQ(mmMM_INDEX_HI
, aligned_pos
>> 31);
1455 if (!write
|| mask
!= 0xffffffff)
1456 value
= RREG32_NO_KIQ(mmMM_DATA
);
1459 value
|= (*(uint32_t *)buf
<< shift
) & mask
;
1460 WREG32_NO_KIQ(mmMM_DATA
, value
);
1462 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
1464 value
= (value
& mask
) >> shift
;
1465 memcpy(buf
, &value
, bytes
);
1469 buf
= (uint8_t *)buf
+ bytes
;
1472 if (pos
>= (nodes
->start
+ nodes
->size
) << PAGE_SHIFT
) {
1474 pos
= (nodes
->start
<< PAGE_SHIFT
);
1481 static struct ttm_bo_driver amdgpu_bo_driver
= {
1482 .ttm_tt_create
= &amdgpu_ttm_tt_create
,
1483 .ttm_tt_populate
= &amdgpu_ttm_tt_populate
,
1484 .ttm_tt_unpopulate
= &amdgpu_ttm_tt_unpopulate
,
1485 .invalidate_caches
= &amdgpu_invalidate_caches
,
1486 .init_mem_type
= &amdgpu_init_mem_type
,
1487 .eviction_valuable
= amdgpu_ttm_bo_eviction_valuable
,
1488 .evict_flags
= &amdgpu_evict_flags
,
1489 .move
= &amdgpu_bo_move
,
1490 .verify_access
= &amdgpu_verify_access
,
1491 .move_notify
= &amdgpu_bo_move_notify
,
1492 .fault_reserve_notify
= &amdgpu_bo_fault_reserve_notify
,
1493 .io_mem_reserve
= &amdgpu_ttm_io_mem_reserve
,
1494 .io_mem_free
= &amdgpu_ttm_io_mem_free
,
1495 .io_mem_pfn
= amdgpu_ttm_io_mem_pfn
,
1496 .access_memory
= &amdgpu_ttm_access_memory
,
1497 .del_from_lru_notify
= &amdgpu_vm_del_from_lru_notify
1501 * Firmware Reservation functions
1504 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1506 * @adev: amdgpu_device pointer
1508 * free fw reserved vram if it has been reserved.
1510 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device
*adev
)
1512 amdgpu_bo_free_kernel(&adev
->fw_vram_usage
.reserved_bo
,
1513 NULL
, &adev
->fw_vram_usage
.va
);
1517 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1519 * @adev: amdgpu_device pointer
1521 * create bo vram reservation from fw.
1523 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device
*adev
)
1525 struct ttm_operation_ctx ctx
= { false, false };
1526 struct amdgpu_bo_param bp
;
1529 u64 vram_size
= adev
->gmc
.visible_vram_size
;
1530 u64 offset
= adev
->fw_vram_usage
.start_offset
;
1531 u64 size
= adev
->fw_vram_usage
.size
;
1532 struct amdgpu_bo
*bo
;
1534 memset(&bp
, 0, sizeof(bp
));
1535 bp
.size
= adev
->fw_vram_usage
.size
;
1536 bp
.byte_align
= PAGE_SIZE
;
1537 bp
.domain
= AMDGPU_GEM_DOMAIN_VRAM
;
1538 bp
.flags
= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
1539 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
;
1540 bp
.type
= ttm_bo_type_kernel
;
1542 adev
->fw_vram_usage
.va
= NULL
;
1543 adev
->fw_vram_usage
.reserved_bo
= NULL
;
1545 if (adev
->fw_vram_usage
.size
> 0 &&
1546 adev
->fw_vram_usage
.size
<= vram_size
) {
1548 r
= amdgpu_bo_create(adev
, &bp
,
1549 &adev
->fw_vram_usage
.reserved_bo
);
1553 r
= amdgpu_bo_reserve(adev
->fw_vram_usage
.reserved_bo
, false);
1557 /* remove the original mem node and create a new one at the
1560 bo
= adev
->fw_vram_usage
.reserved_bo
;
1561 offset
= ALIGN(offset
, PAGE_SIZE
);
1562 for (i
= 0; i
< bo
->placement
.num_placement
; ++i
) {
1563 bo
->placements
[i
].fpfn
= offset
>> PAGE_SHIFT
;
1564 bo
->placements
[i
].lpfn
= (offset
+ size
) >> PAGE_SHIFT
;
1567 ttm_bo_mem_put(&bo
->tbo
, &bo
->tbo
.mem
);
1568 r
= ttm_bo_mem_space(&bo
->tbo
, &bo
->placement
,
1569 &bo
->tbo
.mem
, &ctx
);
1573 r
= amdgpu_bo_pin_restricted(adev
->fw_vram_usage
.reserved_bo
,
1574 AMDGPU_GEM_DOMAIN_VRAM
,
1575 adev
->fw_vram_usage
.start_offset
,
1576 (adev
->fw_vram_usage
.start_offset
+
1577 adev
->fw_vram_usage
.size
));
1580 r
= amdgpu_bo_kmap(adev
->fw_vram_usage
.reserved_bo
,
1581 &adev
->fw_vram_usage
.va
);
1585 amdgpu_bo_unreserve(adev
->fw_vram_usage
.reserved_bo
);
1590 amdgpu_bo_unpin(adev
->fw_vram_usage
.reserved_bo
);
1592 amdgpu_bo_unreserve(adev
->fw_vram_usage
.reserved_bo
);
1594 amdgpu_bo_unref(&adev
->fw_vram_usage
.reserved_bo
);
1596 adev
->fw_vram_usage
.va
= NULL
;
1597 adev
->fw_vram_usage
.reserved_bo
= NULL
;
1601 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1602 * gtt/vram related fields.
1604 * This initializes all of the memory space pools that the TTM layer
1605 * will need such as the GTT space (system memory mapped to the device),
1606 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1607 * can be mapped per VMID.
1609 int amdgpu_ttm_init(struct amdgpu_device
*adev
)
1615 mutex_init(&adev
->mman
.gtt_window_lock
);
1617 /* No others user of address space so set it to 0 */
1618 r
= ttm_bo_device_init(&adev
->mman
.bdev
,
1620 adev
->ddev
->anon_inode
->i_mapping
,
1623 DRM_ERROR("failed initializing buffer object driver(%d).\n", r
);
1626 adev
->mman
.initialized
= true;
1628 /* We opt to avoid OOM on system pages allocations */
1629 adev
->mman
.bdev
.no_retry
= true;
1631 /* Initialize VRAM pool with all of VRAM divided into pages */
1632 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, TTM_PL_VRAM
,
1633 adev
->gmc
.real_vram_size
>> PAGE_SHIFT
);
1635 DRM_ERROR("Failed initializing VRAM heap.\n");
1639 /* Reduce size of CPU-visible VRAM if requested */
1640 vis_vram_limit
= (u64
)amdgpu_vis_vram_limit
* 1024 * 1024;
1641 if (amdgpu_vis_vram_limit
> 0 &&
1642 vis_vram_limit
<= adev
->gmc
.visible_vram_size
)
1643 adev
->gmc
.visible_vram_size
= vis_vram_limit
;
1645 /* Change the size here instead of the init above so only lpfn is affected */
1646 amdgpu_ttm_set_buffer_funcs_status(adev
, false);
1648 adev
->mman
.aper_base_kaddr
= ioremap_wc(adev
->gmc
.aper_base
,
1649 adev
->gmc
.visible_vram_size
);
1653 *The reserved vram for firmware must be pinned to the specified
1654 *place on the VRAM, so reserve it early.
1656 r
= amdgpu_ttm_fw_reserve_vram_init(adev
);
1661 /* allocate memory as required for VGA
1662 * This is used for VGA emulation and pre-OS scanout buffers to
1663 * avoid display artifacts while transitioning between pre-OS
1665 r
= amdgpu_bo_create_kernel(adev
, adev
->gmc
.stolen_size
, PAGE_SIZE
,
1666 AMDGPU_GEM_DOMAIN_VRAM
,
1667 &adev
->stolen_vga_memory
,
1671 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1672 (unsigned) (adev
->gmc
.real_vram_size
/ (1024 * 1024)));
1674 /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1675 * or whatever the user passed on module init */
1676 if (amdgpu_gtt_size
== -1) {
1680 gtt_size
= min(max((AMDGPU_DEFAULT_GTT_SIZE_MB
<< 20),
1681 adev
->gmc
.mc_vram_size
),
1682 ((uint64_t)si
.totalram
* si
.mem_unit
* 3/4));
1685 gtt_size
= (uint64_t)amdgpu_gtt_size
<< 20;
1687 /* Initialize GTT memory pool */
1688 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, TTM_PL_TT
, gtt_size
>> PAGE_SHIFT
);
1690 DRM_ERROR("Failed initializing GTT heap.\n");
1693 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1694 (unsigned)(gtt_size
/ (1024 * 1024)));
1696 /* Initialize various on-chip memory pools */
1697 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, AMDGPU_PL_GDS
,
1698 adev
->gds
.mem
.total_size
);
1700 DRM_ERROR("Failed initializing GDS heap.\n");
1704 r
= amdgpu_bo_create_kernel(adev
, adev
->gds
.mem
.gfx_partition_size
,
1705 4, AMDGPU_GEM_DOMAIN_GDS
,
1706 &adev
->gds
.gds_gfx_bo
, NULL
, NULL
);
1710 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, AMDGPU_PL_GWS
,
1711 adev
->gds
.gws
.total_size
);
1713 DRM_ERROR("Failed initializing gws heap.\n");
1717 r
= amdgpu_bo_create_kernel(adev
, adev
->gds
.gws
.gfx_partition_size
,
1718 1, AMDGPU_GEM_DOMAIN_GWS
,
1719 &adev
->gds
.gws_gfx_bo
, NULL
, NULL
);
1723 r
= ttm_bo_init_mm(&adev
->mman
.bdev
, AMDGPU_PL_OA
,
1724 adev
->gds
.oa
.total_size
);
1726 DRM_ERROR("Failed initializing oa heap.\n");
1730 r
= amdgpu_bo_create_kernel(adev
, adev
->gds
.oa
.gfx_partition_size
,
1731 1, AMDGPU_GEM_DOMAIN_OA
,
1732 &adev
->gds
.oa_gfx_bo
, NULL
, NULL
);
1736 /* Register debugfs entries for amdgpu_ttm */
1737 r
= amdgpu_ttm_debugfs_init(adev
);
1739 DRM_ERROR("Failed to init debugfs\n");
1746 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1748 void amdgpu_ttm_late_init(struct amdgpu_device
*adev
)
1750 /* return the VGA stolen memory (if any) back to VRAM */
1751 amdgpu_bo_free_kernel(&adev
->stolen_vga_memory
, NULL
, NULL
);
1755 * amdgpu_ttm_fini - De-initialize the TTM memory pools
1757 void amdgpu_ttm_fini(struct amdgpu_device
*adev
)
1759 if (!adev
->mman
.initialized
)
1762 amdgpu_ttm_debugfs_fini(adev
);
1763 amdgpu_ttm_fw_reserve_vram_fini(adev
);
1764 if (adev
->mman
.aper_base_kaddr
)
1765 iounmap(adev
->mman
.aper_base_kaddr
);
1766 adev
->mman
.aper_base_kaddr
= NULL
;
1768 ttm_bo_clean_mm(&adev
->mman
.bdev
, TTM_PL_VRAM
);
1769 ttm_bo_clean_mm(&adev
->mman
.bdev
, TTM_PL_TT
);
1770 ttm_bo_clean_mm(&adev
->mman
.bdev
, AMDGPU_PL_GDS
);
1771 ttm_bo_clean_mm(&adev
->mman
.bdev
, AMDGPU_PL_GWS
);
1772 ttm_bo_clean_mm(&adev
->mman
.bdev
, AMDGPU_PL_OA
);
1773 ttm_bo_device_release(&adev
->mman
.bdev
);
1774 adev
->mman
.initialized
= false;
1775 DRM_INFO("amdgpu: ttm finalized\n");
1779 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1781 * @adev: amdgpu_device pointer
1782 * @enable: true when we can use buffer functions.
1784 * Enable/disable use of buffer functions during suspend/resume. This should
1785 * only be called at bootup or when userspace isn't running.
1787 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device
*adev
, bool enable
)
1789 struct ttm_mem_type_manager
*man
= &adev
->mman
.bdev
.man
[TTM_PL_VRAM
];
1793 if (!adev
->mman
.initialized
|| adev
->in_gpu_reset
||
1794 adev
->mman
.buffer_funcs_enabled
== enable
)
1798 struct amdgpu_ring
*ring
;
1799 struct drm_sched_rq
*rq
;
1801 ring
= adev
->mman
.buffer_funcs_ring
;
1802 rq
= &ring
->sched
.sched_rq
[DRM_SCHED_PRIORITY_KERNEL
];
1803 r
= drm_sched_entity_init(&adev
->mman
.entity
, &rq
, 1, NULL
);
1805 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1810 drm_sched_entity_destroy(&adev
->mman
.entity
);
1811 dma_fence_put(man
->move
);
1815 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1817 size
= adev
->gmc
.real_vram_size
;
1819 size
= adev
->gmc
.visible_vram_size
;
1820 man
->size
= size
>> PAGE_SHIFT
;
1821 adev
->mman
.buffer_funcs_enabled
= enable
;
1824 int amdgpu_mmap(struct file
*filp
, struct vm_area_struct
*vma
)
1826 struct drm_file
*file_priv
= filp
->private_data
;
1827 struct amdgpu_device
*adev
= file_priv
->minor
->dev
->dev_private
;
1832 return ttm_bo_mmap(filp
, vma
, &adev
->mman
.bdev
);
1835 static int amdgpu_map_buffer(struct ttm_buffer_object
*bo
,
1836 struct ttm_mem_reg
*mem
, unsigned num_pages
,
1837 uint64_t offset
, unsigned window
,
1838 struct amdgpu_ring
*ring
,
1841 struct amdgpu_ttm_tt
*gtt
= (void *)bo
->ttm
;
1842 struct amdgpu_device
*adev
= ring
->adev
;
1843 struct ttm_tt
*ttm
= bo
->ttm
;
1844 struct amdgpu_job
*job
;
1845 unsigned num_dw
, num_bytes
;
1846 dma_addr_t
*dma_address
;
1847 struct dma_fence
*fence
;
1848 uint64_t src_addr
, dst_addr
;
1852 BUG_ON(adev
->mman
.buffer_funcs
->copy_max_bytes
<
1853 AMDGPU_GTT_MAX_TRANSFER_SIZE
* 8);
1855 *addr
= adev
->gmc
.gart_start
;
1856 *addr
+= (u64
)window
* AMDGPU_GTT_MAX_TRANSFER_SIZE
*
1857 AMDGPU_GPU_PAGE_SIZE
;
1859 num_dw
= adev
->mman
.buffer_funcs
->copy_num_dw
;
1860 while (num_dw
& 0x7)
1863 num_bytes
= num_pages
* 8;
1865 r
= amdgpu_job_alloc_with_ib(adev
, num_dw
* 4 + num_bytes
, &job
);
1869 src_addr
= num_dw
* 4;
1870 src_addr
+= job
->ibs
[0].gpu_addr
;
1872 dst_addr
= amdgpu_bo_gpu_offset(adev
->gart
.bo
);
1873 dst_addr
+= window
* AMDGPU_GTT_MAX_TRANSFER_SIZE
* 8;
1874 amdgpu_emit_copy_buffer(adev
, &job
->ibs
[0], src_addr
,
1875 dst_addr
, num_bytes
);
1877 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
1878 WARN_ON(job
->ibs
[0].length_dw
> num_dw
);
1880 dma_address
= >t
->ttm
.dma_address
[offset
>> PAGE_SHIFT
];
1881 flags
= amdgpu_ttm_tt_pte_flags(adev
, ttm
, mem
);
1882 r
= amdgpu_gart_map(adev
, 0, num_pages
, dma_address
, flags
,
1883 &job
->ibs
[0].ptr
[num_dw
]);
1887 r
= amdgpu_job_submit(job
, &adev
->mman
.entity
,
1888 AMDGPU_FENCE_OWNER_UNDEFINED
, &fence
);
1892 dma_fence_put(fence
);
1897 amdgpu_job_free(job
);
1901 int amdgpu_copy_buffer(struct amdgpu_ring
*ring
, uint64_t src_offset
,
1902 uint64_t dst_offset
, uint32_t byte_count
,
1903 struct reservation_object
*resv
,
1904 struct dma_fence
**fence
, bool direct_submit
,
1905 bool vm_needs_flush
)
1907 struct amdgpu_device
*adev
= ring
->adev
;
1908 struct amdgpu_job
*job
;
1911 unsigned num_loops
, num_dw
;
1915 if (direct_submit
&& !ring
->sched
.ready
) {
1916 DRM_ERROR("Trying to move memory with ring turned off.\n");
1920 max_bytes
= adev
->mman
.buffer_funcs
->copy_max_bytes
;
1921 num_loops
= DIV_ROUND_UP(byte_count
, max_bytes
);
1922 num_dw
= num_loops
* adev
->mman
.buffer_funcs
->copy_num_dw
;
1924 /* for IB padding */
1925 while (num_dw
& 0x7)
1928 r
= amdgpu_job_alloc_with_ib(adev
, num_dw
* 4, &job
);
1932 if (vm_needs_flush
) {
1933 job
->vm_pd_addr
= amdgpu_gmc_pd_addr(adev
->gart
.bo
);
1934 job
->vm_needs_flush
= true;
1937 r
= amdgpu_sync_resv(adev
, &job
->sync
, resv
,
1938 AMDGPU_FENCE_OWNER_UNDEFINED
,
1941 DRM_ERROR("sync failed (%d).\n", r
);
1946 for (i
= 0; i
< num_loops
; i
++) {
1947 uint32_t cur_size_in_bytes
= min(byte_count
, max_bytes
);
1949 amdgpu_emit_copy_buffer(adev
, &job
->ibs
[0], src_offset
,
1950 dst_offset
, cur_size_in_bytes
);
1952 src_offset
+= cur_size_in_bytes
;
1953 dst_offset
+= cur_size_in_bytes
;
1954 byte_count
-= cur_size_in_bytes
;
1957 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
1958 WARN_ON(job
->ibs
[0].length_dw
> num_dw
);
1960 r
= amdgpu_job_submit_direct(job
, ring
, fence
);
1962 r
= amdgpu_job_submit(job
, &adev
->mman
.entity
,
1963 AMDGPU_FENCE_OWNER_UNDEFINED
, fence
);
1970 amdgpu_job_free(job
);
1971 DRM_ERROR("Error scheduling IBs (%d)\n", r
);
1975 int amdgpu_fill_buffer(struct amdgpu_bo
*bo
,
1977 struct reservation_object
*resv
,
1978 struct dma_fence
**fence
)
1980 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
1981 uint32_t max_bytes
= adev
->mman
.buffer_funcs
->fill_max_bytes
;
1982 struct amdgpu_ring
*ring
= adev
->mman
.buffer_funcs_ring
;
1984 struct drm_mm_node
*mm_node
;
1985 unsigned long num_pages
;
1986 unsigned int num_loops
, num_dw
;
1988 struct amdgpu_job
*job
;
1991 if (!adev
->mman
.buffer_funcs_enabled
) {
1992 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1996 if (bo
->tbo
.mem
.mem_type
== TTM_PL_TT
) {
1997 r
= amdgpu_ttm_alloc_gart(&bo
->tbo
);
2002 num_pages
= bo
->tbo
.num_pages
;
2003 mm_node
= bo
->tbo
.mem
.mm_node
;
2006 uint32_t byte_count
= mm_node
->size
<< PAGE_SHIFT
;
2008 num_loops
+= DIV_ROUND_UP(byte_count
, max_bytes
);
2009 num_pages
-= mm_node
->size
;
2012 num_dw
= num_loops
* adev
->mman
.buffer_funcs
->fill_num_dw
;
2014 /* for IB padding */
2017 r
= amdgpu_job_alloc_with_ib(adev
, num_dw
* 4, &job
);
2022 r
= amdgpu_sync_resv(adev
, &job
->sync
, resv
,
2023 AMDGPU_FENCE_OWNER_UNDEFINED
, false);
2025 DRM_ERROR("sync failed (%d).\n", r
);
2030 num_pages
= bo
->tbo
.num_pages
;
2031 mm_node
= bo
->tbo
.mem
.mm_node
;
2034 uint32_t byte_count
= mm_node
->size
<< PAGE_SHIFT
;
2037 dst_addr
= amdgpu_mm_node_addr(&bo
->tbo
, mm_node
, &bo
->tbo
.mem
);
2038 while (byte_count
) {
2039 uint32_t cur_size_in_bytes
= min(byte_count
, max_bytes
);
2041 amdgpu_emit_fill_buffer(adev
, &job
->ibs
[0], src_data
,
2042 dst_addr
, cur_size_in_bytes
);
2044 dst_addr
+= cur_size_in_bytes
;
2045 byte_count
-= cur_size_in_bytes
;
2048 num_pages
-= mm_node
->size
;
2052 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
2053 WARN_ON(job
->ibs
[0].length_dw
> num_dw
);
2054 r
= amdgpu_job_submit(job
, &adev
->mman
.entity
,
2055 AMDGPU_FENCE_OWNER_UNDEFINED
, fence
);
2062 amdgpu_job_free(job
);
2066 #if defined(CONFIG_DEBUG_FS)
2068 static int amdgpu_mm_dump_table(struct seq_file
*m
, void *data
)
2070 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2071 unsigned ttm_pl
= (uintptr_t)node
->info_ent
->data
;
2072 struct drm_device
*dev
= node
->minor
->dev
;
2073 struct amdgpu_device
*adev
= dev
->dev_private
;
2074 struct ttm_mem_type_manager
*man
= &adev
->mman
.bdev
.man
[ttm_pl
];
2075 struct drm_printer p
= drm_seq_file_printer(m
);
2077 man
->func
->debug(man
, &p
);
2081 static const struct drm_info_list amdgpu_ttm_debugfs_list
[] = {
2082 {"amdgpu_vram_mm", amdgpu_mm_dump_table
, 0, (void *)TTM_PL_VRAM
},
2083 {"amdgpu_gtt_mm", amdgpu_mm_dump_table
, 0, (void *)TTM_PL_TT
},
2084 {"amdgpu_gds_mm", amdgpu_mm_dump_table
, 0, (void *)AMDGPU_PL_GDS
},
2085 {"amdgpu_gws_mm", amdgpu_mm_dump_table
, 0, (void *)AMDGPU_PL_GWS
},
2086 {"amdgpu_oa_mm", amdgpu_mm_dump_table
, 0, (void *)AMDGPU_PL_OA
},
2087 {"ttm_page_pool", ttm_page_alloc_debugfs
, 0, NULL
},
2088 #ifdef CONFIG_SWIOTLB
2089 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs
, 0, NULL
}
2094 * amdgpu_ttm_vram_read - Linear read access to VRAM
2096 * Accesses VRAM via MMIO for debugging purposes.
2098 static ssize_t
amdgpu_ttm_vram_read(struct file
*f
, char __user
*buf
,
2099 size_t size
, loff_t
*pos
)
2101 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2105 if (size
& 0x3 || *pos
& 0x3)
2108 if (*pos
>= adev
->gmc
.mc_vram_size
)
2112 unsigned long flags
;
2115 if (*pos
>= adev
->gmc
.mc_vram_size
)
2118 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
2119 WREG32_NO_KIQ(mmMM_INDEX
, ((uint32_t)*pos
) | 0x80000000);
2120 WREG32_NO_KIQ(mmMM_INDEX_HI
, *pos
>> 31);
2121 value
= RREG32_NO_KIQ(mmMM_DATA
);
2122 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
2124 r
= put_user(value
, (uint32_t *)buf
);
2138 * amdgpu_ttm_vram_write - Linear write access to VRAM
2140 * Accesses VRAM via MMIO for debugging purposes.
2142 static ssize_t
amdgpu_ttm_vram_write(struct file
*f
, const char __user
*buf
,
2143 size_t size
, loff_t
*pos
)
2145 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2149 if (size
& 0x3 || *pos
& 0x3)
2152 if (*pos
>= adev
->gmc
.mc_vram_size
)
2156 unsigned long flags
;
2159 if (*pos
>= adev
->gmc
.mc_vram_size
)
2162 r
= get_user(value
, (uint32_t *)buf
);
2166 spin_lock_irqsave(&adev
->mmio_idx_lock
, flags
);
2167 WREG32_NO_KIQ(mmMM_INDEX
, ((uint32_t)*pos
) | 0x80000000);
2168 WREG32_NO_KIQ(mmMM_INDEX_HI
, *pos
>> 31);
2169 WREG32_NO_KIQ(mmMM_DATA
, value
);
2170 spin_unlock_irqrestore(&adev
->mmio_idx_lock
, flags
);
2181 static const struct file_operations amdgpu_ttm_vram_fops
= {
2182 .owner
= THIS_MODULE
,
2183 .read
= amdgpu_ttm_vram_read
,
2184 .write
= amdgpu_ttm_vram_write
,
2185 .llseek
= default_llseek
,
2188 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2191 * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2193 static ssize_t
amdgpu_ttm_gtt_read(struct file
*f
, char __user
*buf
,
2194 size_t size
, loff_t
*pos
)
2196 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2201 loff_t p
= *pos
/ PAGE_SIZE
;
2202 unsigned off
= *pos
& ~PAGE_MASK
;
2203 size_t cur_size
= min_t(size_t, size
, PAGE_SIZE
- off
);
2207 if (p
>= adev
->gart
.num_cpu_pages
)
2210 page
= adev
->gart
.pages
[p
];
2215 r
= copy_to_user(buf
, ptr
, cur_size
);
2216 kunmap(adev
->gart
.pages
[p
]);
2218 r
= clear_user(buf
, cur_size
);
2232 static const struct file_operations amdgpu_ttm_gtt_fops
= {
2233 .owner
= THIS_MODULE
,
2234 .read
= amdgpu_ttm_gtt_read
,
2235 .llseek
= default_llseek
2241 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2243 * This function is used to read memory that has been mapped to the
2244 * GPU and the known addresses are not physical addresses but instead
2245 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2247 static ssize_t
amdgpu_iomem_read(struct file
*f
, char __user
*buf
,
2248 size_t size
, loff_t
*pos
)
2250 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2251 struct iommu_domain
*dom
;
2255 /* retrieve the IOMMU domain if any for this device */
2256 dom
= iommu_get_domain_for_dev(adev
->dev
);
2259 phys_addr_t addr
= *pos
& PAGE_MASK
;
2260 loff_t off
= *pos
& ~PAGE_MASK
;
2261 size_t bytes
= PAGE_SIZE
- off
;
2266 bytes
= bytes
< size
? bytes
: size
;
2268 /* Translate the bus address to a physical address. If
2269 * the domain is NULL it means there is no IOMMU active
2270 * and the address translation is the identity
2272 addr
= dom
? iommu_iova_to_phys(dom
, addr
) : addr
;
2274 pfn
= addr
>> PAGE_SHIFT
;
2275 if (!pfn_valid(pfn
))
2278 p
= pfn_to_page(pfn
);
2279 if (p
->mapping
!= adev
->mman
.bdev
.dev_mapping
)
2283 r
= copy_to_user(buf
, ptr
+ off
, bytes
);
2297 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2299 * This function is used to write memory that has been mapped to the
2300 * GPU and the known addresses are not physical addresses but instead
2301 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2303 static ssize_t
amdgpu_iomem_write(struct file
*f
, const char __user
*buf
,
2304 size_t size
, loff_t
*pos
)
2306 struct amdgpu_device
*adev
= file_inode(f
)->i_private
;
2307 struct iommu_domain
*dom
;
2311 dom
= iommu_get_domain_for_dev(adev
->dev
);
2314 phys_addr_t addr
= *pos
& PAGE_MASK
;
2315 loff_t off
= *pos
& ~PAGE_MASK
;
2316 size_t bytes
= PAGE_SIZE
- off
;
2321 bytes
= bytes
< size
? bytes
: size
;
2323 addr
= dom
? iommu_iova_to_phys(dom
, addr
) : addr
;
2325 pfn
= addr
>> PAGE_SHIFT
;
2326 if (!pfn_valid(pfn
))
2329 p
= pfn_to_page(pfn
);
2330 if (p
->mapping
!= adev
->mman
.bdev
.dev_mapping
)
2334 r
= copy_from_user(ptr
+ off
, buf
, bytes
);
2347 static const struct file_operations amdgpu_ttm_iomem_fops
= {
2348 .owner
= THIS_MODULE
,
2349 .read
= amdgpu_iomem_read
,
2350 .write
= amdgpu_iomem_write
,
2351 .llseek
= default_llseek
2354 static const struct {
2356 const struct file_operations
*fops
;
2358 } ttm_debugfs_entries
[] = {
2359 { "amdgpu_vram", &amdgpu_ttm_vram_fops
, TTM_PL_VRAM
},
2360 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2361 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops
, TTM_PL_TT
},
2363 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops
, TTM_PL_SYSTEM
},
2368 static int amdgpu_ttm_debugfs_init(struct amdgpu_device
*adev
)
2370 #if defined(CONFIG_DEBUG_FS)
2373 struct drm_minor
*minor
= adev
->ddev
->primary
;
2374 struct dentry
*ent
, *root
= minor
->debugfs_root
;
2376 for (count
= 0; count
< ARRAY_SIZE(ttm_debugfs_entries
); count
++) {
2377 ent
= debugfs_create_file(
2378 ttm_debugfs_entries
[count
].name
,
2379 S_IFREG
| S_IRUGO
, root
,
2381 ttm_debugfs_entries
[count
].fops
);
2383 return PTR_ERR(ent
);
2384 if (ttm_debugfs_entries
[count
].domain
== TTM_PL_VRAM
)
2385 i_size_write(ent
->d_inode
, adev
->gmc
.mc_vram_size
);
2386 else if (ttm_debugfs_entries
[count
].domain
== TTM_PL_TT
)
2387 i_size_write(ent
->d_inode
, adev
->gmc
.gart_size
);
2388 adev
->mman
.debugfs_entries
[count
] = ent
;
2391 count
= ARRAY_SIZE(amdgpu_ttm_debugfs_list
);
2393 #ifdef CONFIG_SWIOTLB
2394 if (!(adev
->need_swiotlb
&& swiotlb_nr_tbl()))
2398 return amdgpu_debugfs_add_files(adev
, amdgpu_ttm_debugfs_list
, count
);
2404 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device
*adev
)
2406 #if defined(CONFIG_DEBUG_FS)
2409 for (i
= 0; i
< ARRAY_SIZE(ttm_debugfs_entries
); i
++)
2410 debugfs_remove(adev
->mman
.debugfs_entries
[i
]);