drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __AMDGPU_UCODE_H__
  24 #define __AMDGPU_UCODE_H__
  25
  26 #include "amdgpu_socbb.h"
  27
  28 struct common_firmware_header {
  29         uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
  30         uint32_t header_size_bytes; /* size of just the header in bytes */
  31         uint16_t header_version_major; /* header version */
  32         uint16_t header_version_minor; /* header version */
  33         uint16_t ip_version_major; /* IP version */
  34         uint16_t ip_version_minor; /* IP version */
  35         uint32_t ucode_version;
  36         uint32_t ucode_size_bytes; /* size of ucode in bytes */
  37         uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
  38         uint32_t crc32;  /* crc32 checksum of the payload */
  39 };
  40
  41 /* version_major=1, version_minor=0 */
  42 struct mc_firmware_header_v1_0 {
  43         struct common_firmware_header header;
  44         uint32_t io_debug_size_bytes; /* size of debug array in dwords */
  45         uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
  46 };
  47
  48 /* version_major=1, version_minor=0 */
  49 struct smc_firmware_header_v1_0 {
  50         struct common_firmware_header header;
  51         uint32_t ucode_start_addr;
  52 };
  53
  54 /* version_major=2, version_minor=0 */
  55 struct smc_firmware_header_v2_0 {
  56         struct smc_firmware_header_v1_0 v1_0;
  57         uint32_t ppt_offset_bytes; /* soft pptable offset */
  58         uint32_t ppt_size_bytes; /* soft pptable size */
  59 };
  60
  61 struct smc_soft_pptable_entry {
  62         uint32_t id;
  63         uint32_t ppt_offset_bytes;
  64         uint32_t ppt_size_bytes;
  65 };
  66
  67 /* version_major=2, version_minor=1 */
  68 struct smc_firmware_header_v2_1 {
  69         struct smc_firmware_header_v1_0 v1_0;
  70         uint32_t pptable_count;
  71         uint32_t pptable_entry_offset;
  72 };
  73
  74 struct psp_fw_legacy_bin_desc {
  75         uint32_t fw_version;
  76         uint32_t offset_bytes;
  77         uint32_t size_bytes;
  78 };
  79
  80 /* version_major=1, version_minor=0 */
  81 struct psp_firmware_header_v1_0 {
  82         struct common_firmware_header header;
  83         struct psp_fw_legacy_bin_desc sos;
  84 };
  85
  86 /* version_major=1, version_minor=1 */
  87 struct psp_firmware_header_v1_1 {
  88         struct psp_firmware_header_v1_0 v1_0;
  89         struct psp_fw_legacy_bin_desc toc;
  90         struct psp_fw_legacy_bin_desc kdb;
  91 };
  92
  93 /* version_major=1, version_minor=2 */
  94 struct psp_firmware_header_v1_2 {
  95         struct psp_firmware_header_v1_0 v1_0;
  96         struct psp_fw_legacy_bin_desc res;
  97         struct psp_fw_legacy_bin_desc kdb;
  98 };
  99
 100 /* version_major=1, version_minor=3 */
 101 struct psp_firmware_header_v1_3 {
 102         struct psp_firmware_header_v1_1 v1_1;
 103         struct psp_fw_legacy_bin_desc spl;
 104         struct psp_fw_legacy_bin_desc rl;
 105         struct psp_fw_legacy_bin_desc sys_drv_aux;
 106         struct psp_fw_legacy_bin_desc sos_aux;
 107 };
 108
 109 struct psp_fw_bin_desc {
 110         uint32_t fw_type;
 111         uint32_t fw_version;
 112         uint32_t offset_bytes;
 113         uint32_t size_bytes;
 114 };
 115
 116 enum psp_fw_type {
 117         PSP_FW_TYPE_UNKOWN,
 118         PSP_FW_TYPE_PSP_SOS,
 119         PSP_FW_TYPE_PSP_SYS_DRV,
 120         PSP_FW_TYPE_PSP_KDB,
 121         PSP_FW_TYPE_PSP_TOC,
 122         PSP_FW_TYPE_PSP_SPL,
 123         PSP_FW_TYPE_PSP_RL,
 124         PSP_FW_TYPE_PSP_SOC_DRV,
 125         PSP_FW_TYPE_PSP_INTF_DRV,
 126         PSP_FW_TYPE_PSP_DBG_DRV,
 127 };
 128
 129 /* version_major=2, version_minor=0 */
 130 struct psp_firmware_header_v2_0 {
 131         struct common_firmware_header header;
 132         uint32_t psp_fw_bin_count;
 133         struct psp_fw_bin_desc psp_fw_bin[];
 134 };
 135
 136 /* version_major=1, version_minor=0 */
 137 struct ta_firmware_header_v1_0 {
 138         struct common_firmware_header header;
 139         struct psp_fw_legacy_bin_desc xgmi;
 140         struct psp_fw_legacy_bin_desc ras;
 141         struct psp_fw_legacy_bin_desc hdcp;
 142         struct psp_fw_legacy_bin_desc dtm;
 143         struct psp_fw_legacy_bin_desc securedisplay;
 144 };
 145
 146 enum ta_fw_type {
 147         TA_FW_TYPE_UNKOWN,
 148         TA_FW_TYPE_PSP_ASD,
 149         TA_FW_TYPE_PSP_XGMI,
 150         TA_FW_TYPE_PSP_RAS,
 151         TA_FW_TYPE_PSP_HDCP,
 152         TA_FW_TYPE_PSP_DTM,
 153         TA_FW_TYPE_PSP_RAP,
 154         TA_FW_TYPE_PSP_SECUREDISPLAY,
 155         TA_FW_TYPE_MAX_INDEX,
 156 };
 157
 158 /* version_major=2, version_minor=0 */
 159 struct ta_firmware_header_v2_0 {
 160         struct common_firmware_header header;
 161         uint32_t ta_fw_bin_count;
 162         struct psp_fw_bin_desc ta_fw_bin[];
 163 };
 164
 165 /* version_major=1, version_minor=0 */
 166 struct gfx_firmware_header_v1_0 {
 167         struct common_firmware_header header;
 168         uint32_t ucode_feature_version;
 169         uint32_t jt_offset; /* jt location */
 170         uint32_t jt_size;  /* size of jt */
 171 };
 172
 173 /* version_major=2, version_minor=0 */
 174 struct gfx_firmware_header_v2_0 {
 175         struct common_firmware_header header;
 176         uint32_t ucode_feature_version;
 177         uint32_t ucode_size_bytes;
 178         uint32_t ucode_offset_bytes;
 179         uint32_t data_size_bytes;
 180         uint32_t data_offset_bytes;
 181         uint32_t ucode_start_addr_lo;
 182         uint32_t ucode_start_addr_hi;
 183 };
 184
 185 /* version_major=1, version_minor=0 */
 186 struct mes_firmware_header_v1_0 {
 187         struct common_firmware_header header;
 188         uint32_t mes_ucode_version;
 189         uint32_t mes_ucode_size_bytes;
 190         uint32_t mes_ucode_offset_bytes;
 191         uint32_t mes_ucode_data_version;
 192         uint32_t mes_ucode_data_size_bytes;
 193         uint32_t mes_ucode_data_offset_bytes;
 194         uint32_t mes_uc_start_addr_lo;
 195         uint32_t mes_uc_start_addr_hi;
 196         uint32_t mes_data_start_addr_lo;
 197         uint32_t mes_data_start_addr_hi;
 198 };
 199
 200 /* version_major=1, version_minor=0 */
 201 struct rlc_firmware_header_v1_0 {
 202         struct common_firmware_header header;
 203         uint32_t ucode_feature_version;
 204         uint32_t save_and_restore_offset;
 205         uint32_t clear_state_descriptor_offset;
 206         uint32_t avail_scratch_ram_locations;
 207         uint32_t master_pkt_description_offset;
 208 };
 209
 210 /* version_major=2, version_minor=0 */
 211 struct rlc_firmware_header_v2_0 {
 212         struct common_firmware_header header;
 213         uint32_t ucode_feature_version;
 214         uint32_t jt_offset; /* jt location */
 215         uint32_t jt_size;  /* size of jt */
 216         uint32_t save_and_restore_offset;
 217         uint32_t clear_state_descriptor_offset;
 218         uint32_t avail_scratch_ram_locations;
 219         uint32_t reg_restore_list_size;
 220         uint32_t reg_list_format_start;
 221         uint32_t reg_list_format_separate_start;
 222         uint32_t starting_offsets_start;
 223         uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
 224         uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
 225         uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
 226         uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
 227         uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
 228         uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
 229         uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
 230         uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
 231 };
 232
 233 /* version_major=2, version_minor=1 */
 234 struct rlc_firmware_header_v2_1 {
 235         struct rlc_firmware_header_v2_0 v2_0;
 236         uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
 237         uint32_t save_restore_list_cntl_ucode_ver;
 238         uint32_t save_restore_list_cntl_feature_ver;
 239         uint32_t save_restore_list_cntl_size_bytes;
 240         uint32_t save_restore_list_cntl_offset_bytes;
 241         uint32_t save_restore_list_gpm_ucode_ver;
 242         uint32_t save_restore_list_gpm_feature_ver;
 243         uint32_t save_restore_list_gpm_size_bytes;
 244         uint32_t save_restore_list_gpm_offset_bytes;
 245         uint32_t save_restore_list_srm_ucode_ver;
 246         uint32_t save_restore_list_srm_feature_ver;
 247         uint32_t save_restore_list_srm_size_bytes;
 248         uint32_t save_restore_list_srm_offset_bytes;
 249 };
 250
 251 /* version_major=2, version_minor=2 */
 252 struct rlc_firmware_header_v2_2 {
 253         struct rlc_firmware_header_v2_1 v2_1;
 254         uint32_t rlc_iram_ucode_size_bytes;
 255         uint32_t rlc_iram_ucode_offset_bytes;
 256         uint32_t rlc_dram_ucode_size_bytes;
 257         uint32_t rlc_dram_ucode_offset_bytes;
 258 };
 259
 260 /* version_major=2, version_minor=3 */
 261 struct rlc_firmware_header_v2_3 {
 262     struct rlc_firmware_header_v2_2 v2_2;
 263     uint32_t rlcp_ucode_size_bytes;
 264     uint32_t rlcp_ucode_offset_bytes;
 265     uint32_t rlcv_ucode_size_bytes;
 266     uint32_t rlcv_ucode_offset_bytes;
 267 };
 268
 269 /* version_major=2, version_minor=4 */
 270 struct rlc_firmware_header_v2_4 {
 271     struct rlc_firmware_header_v2_3 v2_3;
 272     uint32_t global_tap_delays_ucode_size_bytes;
 273     uint32_t global_tap_delays_ucode_offset_bytes;
 274     uint32_t se0_tap_delays_ucode_size_bytes;
 275     uint32_t se0_tap_delays_ucode_offset_bytes;
 276     uint32_t se1_tap_delays_ucode_size_bytes;
 277     uint32_t se1_tap_delays_ucode_offset_bytes;
 278     uint32_t se2_tap_delays_ucode_size_bytes;
 279     uint32_t se2_tap_delays_ucode_offset_bytes;
 280     uint32_t se3_tap_delays_ucode_size_bytes;
 281     uint32_t se3_tap_delays_ucode_offset_bytes;
 282 };
 283
 284 /* version_major=1, version_minor=0 */
 285 struct sdma_firmware_header_v1_0 {
 286         struct common_firmware_header header;
 287         uint32_t ucode_feature_version;
 288         uint32_t ucode_change_version;
 289         uint32_t jt_offset; /* jt location */
 290         uint32_t jt_size; /* size of jt */
 291 };
 292
 293 /* version_major=1, version_minor=1 */
 294 struct sdma_firmware_header_v1_1 {
 295         struct sdma_firmware_header_v1_0 v1_0;
 296         uint32_t digest_size;
 297 };
 298
 299 /* version_major=2, version_minor=0 */
 300 struct sdma_firmware_header_v2_0 {
 301         struct common_firmware_header header;
 302         uint32_t ucode_feature_version;
 303         uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
 304         uint32_t ctx_jt_offset; /* context thread jt location */
 305         uint32_t ctx_jt_size; /* context thread size of jt */
 306         uint32_t ctl_ucode_offset;
 307         uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
 308         uint32_t ctl_jt_offset; /* control thread jt location */
 309         uint32_t ctl_jt_size; /* control thread size of jt */
 310 };
 311
 312 /* gpu info payload */
 313 struct gpu_info_firmware_v1_0 {
 314         uint32_t gc_num_se;
 315         uint32_t gc_num_cu_per_sh;
 316         uint32_t gc_num_sh_per_se;
 317         uint32_t gc_num_rb_per_se;
 318         uint32_t gc_num_tccs;
 319         uint32_t gc_num_gprs;
 320         uint32_t gc_num_max_gs_thds;
 321         uint32_t gc_gs_table_depth;
 322         uint32_t gc_gsprim_buff_depth;
 323         uint32_t gc_parameter_cache_depth;
 324         uint32_t gc_double_offchip_lds_buffer;
 325         uint32_t gc_wave_size;
 326         uint32_t gc_max_waves_per_simd;
 327         uint32_t gc_max_scratch_slots_per_cu;
 328         uint32_t gc_lds_size;
 329 };
 330
 331 struct gpu_info_firmware_v1_1 {
 332         struct gpu_info_firmware_v1_0 v1_0;
 333         uint32_t num_sc_per_sh;
 334         uint32_t num_packer_per_sc;
 335 };
 336
 337 /* gpu info payload
 338  * version_major=1, version_minor=1 */
 339 struct gpu_info_firmware_v1_2 {
 340         struct gpu_info_firmware_v1_1 v1_1;
 341         struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
 342 };
 343
 344 /* version_major=1, version_minor=0 */
 345 struct gpu_info_firmware_header_v1_0 {
 346         struct common_firmware_header header;
 347         uint16_t version_major; /* version */
 348         uint16_t version_minor; /* version */
 349 };
 350
 351 /* version_major=1, version_minor=0 */
 352 struct dmcu_firmware_header_v1_0 {
 353         struct common_firmware_header header;
 354         uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
 355         uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
 356 };
 357
 358 /* version_major=1, version_minor=0 */
 359 struct dmcub_firmware_header_v1_0 {
 360         struct common_firmware_header header;
 361         uint32_t inst_const_bytes; /* size of instruction region, in bytes */
 362         uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
 363 };
 364
 365 /* version_major=1, version_minor=0 */
 366 struct imu_firmware_header_v1_0 {
 367     struct common_firmware_header header;
 368     uint32_t imu_iram_ucode_size_bytes;
 369     uint32_t imu_iram_ucode_offset_bytes;
 370     uint32_t imu_dram_ucode_size_bytes;
 371     uint32_t imu_dram_ucode_offset_bytes;
 372 };
 373
 374 /* header is fixed size */
 375 union amdgpu_firmware_header {
 376         struct common_firmware_header common;
 377         struct mc_firmware_header_v1_0 mc;
 378         struct smc_firmware_header_v1_0 smc;
 379         struct smc_firmware_header_v2_0 smc_v2_0;
 380         struct psp_firmware_header_v1_0 psp;
 381         struct psp_firmware_header_v1_1 psp_v1_1;
 382         struct psp_firmware_header_v1_3 psp_v1_3;
 383         struct psp_firmware_header_v2_0 psp_v2_0;
 384         struct ta_firmware_header_v1_0 ta;
 385         struct ta_firmware_header_v2_0 ta_v2_0;
 386         struct gfx_firmware_header_v1_0 gfx;
 387         struct gfx_firmware_header_v2_0 gfx_v2_0;
 388         struct rlc_firmware_header_v1_0 rlc;
 389         struct rlc_firmware_header_v2_0 rlc_v2_0;
 390         struct rlc_firmware_header_v2_1 rlc_v2_1;
 391         struct rlc_firmware_header_v2_2 rlc_v2_2;
 392         struct rlc_firmware_header_v2_3 rlc_v2_3;
 393         struct rlc_firmware_header_v2_4 rlc_v2_4;
 394         struct sdma_firmware_header_v1_0 sdma;
 395         struct sdma_firmware_header_v1_1 sdma_v1_1;
 396         struct sdma_firmware_header_v2_0 sdma_v2_0;
 397         struct gpu_info_firmware_header_v1_0 gpu_info;
 398         struct dmcu_firmware_header_v1_0 dmcu;
 399         struct dmcub_firmware_header_v1_0 dmcub;
 400         struct imu_firmware_header_v1_0 imu;
 401         uint8_t raw[0x100];
 402 };
 403
 404 #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc))
 405
 406 /*
 407  * fw loading support
 408  */
 409 enum AMDGPU_UCODE_ID {
 410         AMDGPU_UCODE_ID_CAP = 0,
 411         AMDGPU_UCODE_ID_SDMA0,
 412         AMDGPU_UCODE_ID_SDMA1,
 413         AMDGPU_UCODE_ID_SDMA2,
 414         AMDGPU_UCODE_ID_SDMA3,
 415         AMDGPU_UCODE_ID_SDMA4,
 416         AMDGPU_UCODE_ID_SDMA5,
 417         AMDGPU_UCODE_ID_SDMA6,
 418         AMDGPU_UCODE_ID_SDMA7,
 419         AMDGPU_UCODE_ID_SDMA_UCODE_TH0,
 420         AMDGPU_UCODE_ID_SDMA_UCODE_TH1,
 421         AMDGPU_UCODE_ID_CP_CE,
 422         AMDGPU_UCODE_ID_CP_PFP,
 423         AMDGPU_UCODE_ID_CP_ME,
 424         AMDGPU_UCODE_ID_CP_RS64_PFP,
 425         AMDGPU_UCODE_ID_CP_RS64_ME,
 426         AMDGPU_UCODE_ID_CP_RS64_MEC,
 427         AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,
 428         AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,
 429         AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,
 430         AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,
 431         AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,
 432         AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,
 433         AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,
 434         AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,
 435         AMDGPU_UCODE_ID_CP_MEC1,
 436         AMDGPU_UCODE_ID_CP_MEC1_JT,
 437         AMDGPU_UCODE_ID_CP_MEC2,
 438         AMDGPU_UCODE_ID_CP_MEC2_JT,
 439         AMDGPU_UCODE_ID_CP_MES,
 440         AMDGPU_UCODE_ID_CP_MES_DATA,
 441         AMDGPU_UCODE_ID_CP_MES1,
 442         AMDGPU_UCODE_ID_CP_MES1_DATA,
 443         AMDGPU_UCODE_ID_IMU_I,
 444         AMDGPU_UCODE_ID_IMU_D,
 445         AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS,
 446         AMDGPU_UCODE_ID_SE0_TAP_DELAYS,
 447         AMDGPU_UCODE_ID_SE1_TAP_DELAYS,
 448         AMDGPU_UCODE_ID_SE2_TAP_DELAYS,
 449         AMDGPU_UCODE_ID_SE3_TAP_DELAYS,
 450         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
 451         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
 452         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
 453         AMDGPU_UCODE_ID_RLC_IRAM,
 454         AMDGPU_UCODE_ID_RLC_DRAM,
 455         AMDGPU_UCODE_ID_RLC_P,
 456         AMDGPU_UCODE_ID_RLC_V,
 457         AMDGPU_UCODE_ID_RLC_G,
 458         AMDGPU_UCODE_ID_STORAGE,
 459         AMDGPU_UCODE_ID_SMC,
 460         AMDGPU_UCODE_ID_PPTABLE,
 461         AMDGPU_UCODE_ID_UVD,
 462         AMDGPU_UCODE_ID_UVD1,
 463         AMDGPU_UCODE_ID_VCE,
 464         AMDGPU_UCODE_ID_VCN,
 465         AMDGPU_UCODE_ID_VCN1,
 466         AMDGPU_UCODE_ID_DMCU_ERAM,
 467         AMDGPU_UCODE_ID_DMCU_INTV,
 468         AMDGPU_UCODE_ID_VCN0_RAM,
 469         AMDGPU_UCODE_ID_VCN1_RAM,
 470         AMDGPU_UCODE_ID_DMCUB,
 471         AMDGPU_UCODE_ID_MAXIMUM,
 472 };
 473
 474 /* engine firmware status */
 475 enum AMDGPU_UCODE_STATUS {
 476         AMDGPU_UCODE_STATUS_INVALID,
 477         AMDGPU_UCODE_STATUS_NOT_LOADED,
 478         AMDGPU_UCODE_STATUS_LOADED,
 479 };
 480
 481 enum amdgpu_firmware_load_type {
 482         AMDGPU_FW_LOAD_DIRECT = 0,
 483         AMDGPU_FW_LOAD_PSP,
 484         AMDGPU_FW_LOAD_SMU,
 485         AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
 486 };
 487
 488 /* conform to smu_ucode_xfer_cz.h */
 489 #define AMDGPU_SDMA0_UCODE_LOADED       0x00000001
 490 #define AMDGPU_SDMA1_UCODE_LOADED       0x00000002
 491 #define AMDGPU_CPCE_UCODE_LOADED        0x00000004
 492 #define AMDGPU_CPPFP_UCODE_LOADED       0x00000008
 493 #define AMDGPU_CPME_UCODE_LOADED        0x00000010
 494 #define AMDGPU_CPMEC1_UCODE_LOADED      0x00000020
 495 #define AMDGPU_CPMEC2_UCODE_LOADED      0x00000040
 496 #define AMDGPU_CPRLC_UCODE_LOADED       0x00000100
 497
 498 /* amdgpu firmware info */
 499 struct amdgpu_firmware_info {
 500         /* ucode ID */
 501         enum AMDGPU_UCODE_ID ucode_id;
 502         /* request_firmware */
 503         const struct firmware *fw;
 504         /* starting mc address */
 505         uint64_t mc_addr;
 506         /* kernel linear address */
 507         void *kaddr;
 508         /* ucode_size_bytes */
 509         uint32_t ucode_size;
 510         /* starting tmr mc address */
 511         uint32_t tmr_mc_addr_lo;
 512         uint32_t tmr_mc_addr_hi;
 513 };
 514
 515 struct amdgpu_firmware {
 516         struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
 517         enum amdgpu_firmware_load_type load_type;
 518         struct amdgpu_bo *fw_buf;
 519         unsigned int fw_size;
 520         unsigned int max_ucodes;
 521         /* firmwares are loaded by psp instead of smu from vega10 */
 522         const struct amdgpu_psp_funcs *funcs;
 523         struct amdgpu_bo *rbuf;
 524         struct mutex mutex;
 525
 526         /* gpu info firmware data pointer */
 527         const struct firmware *gpu_info_fw;
 528
 529         void *fw_buf_ptr;
 530         uint64_t fw_buf_mc;
 531 };
 532
 533 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
 534 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
 535 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
 536 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
 537 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
 538 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
 539 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
 540 int amdgpu_ucode_validate(const struct firmware *fw);
 541 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 542                                 uint16_t hdr_major, uint16_t hdr_minor);
 543
 544 int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
 545 int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
 546 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
 547 void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
 548 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
 549
 550 enum amdgpu_firmware_load_type
 551 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
 552
 553 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
 554
 555 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);
 556
 557 #endif