]>
git.ipfire.org Git - thirdparty/kernel/stable.git/blob - drivers/gpu/drm/amd/amdgpu/atom.c
2 * Copyright 2008 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Author: Stanislaw Skowronek
25 #include <linux/module.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <asm/unaligned.h>
33 #include "atom-names.h"
34 #include "atom-bits.h"
37 #define ATOM_COND_ABOVE 0
38 #define ATOM_COND_ABOVEOREQUAL 1
39 #define ATOM_COND_ALWAYS 2
40 #define ATOM_COND_BELOW 3
41 #define ATOM_COND_BELOWOREQUAL 4
42 #define ATOM_COND_EQUAL 5
43 #define ATOM_COND_NOTEQUAL 6
45 #define ATOM_PORT_ATI 0
46 #define ATOM_PORT_PCI 1
47 #define ATOM_PORT_SYSIO 2
49 #define ATOM_UNIT_MICROSEC 0
50 #define ATOM_UNIT_MILLISEC 1
56 struct atom_context
*ctx
;
61 unsigned long last_jump_jiffies
;
65 int amdgpu_atom_debug
= 0;
66 static int amdgpu_atom_execute_table_locked(struct atom_context
*ctx
, int index
, uint32_t * params
);
67 int amdgpu_atom_execute_table(struct atom_context
*ctx
, int index
, uint32_t * params
);
69 static uint32_t atom_arg_mask
[8] =
70 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
72 static int atom_arg_shift
[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
74 static int atom_dst_to_src
[8][4] = {
75 /* translate destination alignment field to the source alignment encoding */
85 static int atom_def_dst
[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
87 static int debug_depth
= 0;
89 static void debug_print_spaces(int n
)
95 #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
96 #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
98 #define DEBUG(...) do { } while (0)
99 #define SDEBUG(...) do { } while (0)
102 static uint32_t atom_iio_execute(struct atom_context
*ctx
, int base
,
103 uint32_t index
, uint32_t data
)
105 uint32_t temp
= 0xCDCDCDCD;
113 temp
= ctx
->card
->ioreg_read(ctx
->card
, CU16(base
+ 1));
117 ctx
->card
->ioreg_write(ctx
->card
, CU16(base
+ 1), temp
);
122 ~((0xFFFFFFFF >> (32 - CU8(base
+ 1))) <<
128 (0xFFFFFFFF >> (32 - CU8(base
+ 1))) << CU8(base
+
132 case ATOM_IIO_MOVE_INDEX
:
134 ~((0xFFFFFFFF >> (32 - CU8(base
+ 1))) <<
137 ((index
>> CU8(base
+ 2)) &
138 (0xFFFFFFFF >> (32 - CU8(base
+ 1)))) << CU8(base
+
142 case ATOM_IIO_MOVE_DATA
:
144 ~((0xFFFFFFFF >> (32 - CU8(base
+ 1))) <<
147 ((data
>> CU8(base
+ 2)) &
148 (0xFFFFFFFF >> (32 - CU8(base
+ 1)))) << CU8(base
+
152 case ATOM_IIO_MOVE_ATTR
:
154 ~((0xFFFFFFFF >> (32 - CU8(base
+ 1))) <<
158 io_attr
>> CU8(base
+ 2)) & (0xFFFFFFFF >> (32 -
169 pr_info("Unknown IIO opcode\n");
174 static uint32_t atom_get_src_int(atom_exec_context
*ctx
, uint8_t attr
,
175 int *ptr
, uint32_t *saved
, int print
)
177 uint32_t idx
, val
= 0xCDCDCDCD, align
, arg
;
178 struct atom_context
*gctx
= ctx
->ctx
;
180 align
= (attr
>> 3) & 7;
186 DEBUG("REG[0x%04X]", idx
);
187 idx
+= gctx
->reg_block
;
188 switch (gctx
->io_mode
) {
190 val
= gctx
->card
->reg_read(gctx
->card
, idx
);
193 pr_info("PCI registers are not implemented\n");
196 pr_info("SYSIO registers are not implemented\n");
199 if (!(gctx
->io_mode
& 0x80)) {
200 pr_info("Bad IO mode\n");
203 if (!gctx
->iio
[gctx
->io_mode
& 0x7F]) {
204 pr_info("Undefined indirect IO read method %d\n",
205 gctx
->io_mode
& 0x7F);
209 atom_iio_execute(gctx
,
210 gctx
->iio
[gctx
->io_mode
& 0x7F],
217 /* get_unaligned_le32 avoids unaligned accesses from atombios
218 * tables, noticed on a DEC Alpha. */
219 val
= get_unaligned_le32((u32
*)&ctx
->ps
[idx
]);
221 DEBUG("PS[0x%02X,0x%04X]", idx
, val
);
227 DEBUG("WS[0x%02X]", idx
);
229 case ATOM_WS_QUOTIENT
:
230 val
= gctx
->divmul
[0];
232 case ATOM_WS_REMAINDER
:
233 val
= gctx
->divmul
[1];
235 case ATOM_WS_DATAPTR
:
236 val
= gctx
->data_block
;
241 case ATOM_WS_OR_MASK
:
242 val
= 1 << gctx
->shift
;
244 case ATOM_WS_AND_MASK
:
245 val
= ~(1 << gctx
->shift
);
247 case ATOM_WS_FB_WINDOW
:
250 case ATOM_WS_ATTRIBUTES
:
254 val
= gctx
->reg_block
;
264 if (gctx
->data_block
)
265 DEBUG("ID[0x%04X+%04X]", idx
, gctx
->data_block
);
267 DEBUG("ID[0x%04X]", idx
);
269 val
= U32(idx
+ gctx
->data_block
);
274 if ((gctx
->fb_base
+ (idx
* 4)) > gctx
->scratch_size_bytes
) {
275 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
276 gctx
->fb_base
+ (idx
* 4), gctx
->scratch_size_bytes
);
279 val
= gctx
->scratch
[(gctx
->fb_base
/ 4) + idx
];
281 DEBUG("FB[0x%02X]", idx
);
289 DEBUG("IMM 0x%08X\n", val
);
293 case ATOM_SRC_WORD16
:
297 DEBUG("IMM 0x%04X\n", val
);
301 case ATOM_SRC_BYTE16
:
302 case ATOM_SRC_BYTE24
:
306 DEBUG("IMM 0x%02X\n", val
);
314 DEBUG("PLL[0x%02X]", idx
);
315 val
= gctx
->card
->pll_read(gctx
->card
, idx
);
321 DEBUG("MC[0x%02X]", idx
);
322 val
= gctx
->card
->mc_read(gctx
->card
, idx
);
327 val
&= atom_arg_mask
[align
];
328 val
>>= atom_arg_shift
[align
];
332 DEBUG(".[31:0] -> 0x%08X\n", val
);
335 DEBUG(".[15:0] -> 0x%04X\n", val
);
338 DEBUG(".[23:8] -> 0x%04X\n", val
);
340 case ATOM_SRC_WORD16
:
341 DEBUG(".[31:16] -> 0x%04X\n", val
);
344 DEBUG(".[7:0] -> 0x%02X\n", val
);
347 DEBUG(".[15:8] -> 0x%02X\n", val
);
349 case ATOM_SRC_BYTE16
:
350 DEBUG(".[23:16] -> 0x%02X\n", val
);
352 case ATOM_SRC_BYTE24
:
353 DEBUG(".[31:24] -> 0x%02X\n", val
);
359 static void atom_skip_src_int(atom_exec_context
*ctx
, uint8_t attr
, int *ptr
)
361 uint32_t align
= (attr
>> 3) & 7, arg
= attr
& 7;
381 case ATOM_SRC_WORD16
:
386 case ATOM_SRC_BYTE16
:
387 case ATOM_SRC_BYTE24
:
395 static uint32_t atom_get_src(atom_exec_context
*ctx
, uint8_t attr
, int *ptr
)
397 return atom_get_src_int(ctx
, attr
, ptr
, NULL
, 1);
400 static uint32_t atom_get_src_direct(atom_exec_context
*ctx
, uint8_t align
, int *ptr
)
402 uint32_t val
= 0xCDCDCDCD;
411 case ATOM_SRC_WORD16
:
417 case ATOM_SRC_BYTE16
:
418 case ATOM_SRC_BYTE24
:
426 static uint32_t atom_get_dst(atom_exec_context
*ctx
, int arg
, uint8_t attr
,
427 int *ptr
, uint32_t *saved
, int print
)
429 return atom_get_src_int(ctx
,
430 arg
| atom_dst_to_src
[(attr
>> 3) &
431 7][(attr
>> 6) & 3] << 3,
435 static void atom_skip_dst(atom_exec_context
*ctx
, int arg
, uint8_t attr
, int *ptr
)
437 atom_skip_src_int(ctx
,
438 arg
| atom_dst_to_src
[(attr
>> 3) & 7][(attr
>> 6) &
442 static void atom_put_dst(atom_exec_context
*ctx
, int arg
, uint8_t attr
,
443 int *ptr
, uint32_t val
, uint32_t saved
)
446 atom_dst_to_src
[(attr
>> 3) & 7][(attr
>> 6) & 3], old_val
=
448 struct atom_context
*gctx
= ctx
->ctx
;
449 old_val
&= atom_arg_mask
[align
] >> atom_arg_shift
[align
];
450 val
<<= atom_arg_shift
[align
];
451 val
&= atom_arg_mask
[align
];
452 saved
&= ~atom_arg_mask
[align
];
458 DEBUG("REG[0x%04X]", idx
);
459 idx
+= gctx
->reg_block
;
460 switch (gctx
->io_mode
) {
463 gctx
->card
->reg_write(gctx
->card
, idx
,
466 gctx
->card
->reg_write(gctx
->card
, idx
, val
);
469 pr_info("PCI registers are not implemented\n");
472 pr_info("SYSIO registers are not implemented\n");
475 if (!(gctx
->io_mode
& 0x80)) {
476 pr_info("Bad IO mode\n");
479 if (!gctx
->iio
[gctx
->io_mode
& 0xFF]) {
480 pr_info("Undefined indirect IO write method %d\n",
481 gctx
->io_mode
& 0x7F);
484 atom_iio_execute(gctx
, gctx
->iio
[gctx
->io_mode
& 0xFF],
491 DEBUG("PS[0x%02X]", idx
);
492 ctx
->ps
[idx
] = cpu_to_le32(val
);
497 DEBUG("WS[0x%02X]", idx
);
499 case ATOM_WS_QUOTIENT
:
500 gctx
->divmul
[0] = val
;
502 case ATOM_WS_REMAINDER
:
503 gctx
->divmul
[1] = val
;
505 case ATOM_WS_DATAPTR
:
506 gctx
->data_block
= val
;
511 case ATOM_WS_OR_MASK
:
512 case ATOM_WS_AND_MASK
:
514 case ATOM_WS_FB_WINDOW
:
517 case ATOM_WS_ATTRIBUTES
:
521 gctx
->reg_block
= val
;
530 if ((gctx
->fb_base
+ (idx
* 4)) > gctx
->scratch_size_bytes
) {
531 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
532 gctx
->fb_base
+ (idx
* 4), gctx
->scratch_size_bytes
);
534 gctx
->scratch
[(gctx
->fb_base
/ 4) + idx
] = val
;
535 DEBUG("FB[0x%02X]", idx
);
540 DEBUG("PLL[0x%02X]", idx
);
541 gctx
->card
->pll_write(gctx
->card
, idx
, val
);
546 DEBUG("MC[0x%02X]", idx
);
547 gctx
->card
->mc_write(gctx
->card
, idx
, val
);
552 DEBUG(".[31:0] <- 0x%08X\n", old_val
);
555 DEBUG(".[15:0] <- 0x%04X\n", old_val
);
558 DEBUG(".[23:8] <- 0x%04X\n", old_val
);
560 case ATOM_SRC_WORD16
:
561 DEBUG(".[31:16] <- 0x%04X\n", old_val
);
564 DEBUG(".[7:0] <- 0x%02X\n", old_val
);
567 DEBUG(".[15:8] <- 0x%02X\n", old_val
);
569 case ATOM_SRC_BYTE16
:
570 DEBUG(".[23:16] <- 0x%02X\n", old_val
);
572 case ATOM_SRC_BYTE24
:
573 DEBUG(".[31:24] <- 0x%02X\n", old_val
);
578 static void atom_op_add(atom_exec_context
*ctx
, int *ptr
, int arg
)
580 uint8_t attr
= U8((*ptr
)++);
581 uint32_t dst
, src
, saved
;
584 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
586 src
= atom_get_src(ctx
, attr
, ptr
);
589 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
592 static void atom_op_and(atom_exec_context
*ctx
, int *ptr
, int arg
)
594 uint8_t attr
= U8((*ptr
)++);
595 uint32_t dst
, src
, saved
;
598 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
600 src
= atom_get_src(ctx
, attr
, ptr
);
603 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
606 static void atom_op_beep(atom_exec_context
*ctx
, int *ptr
, int arg
)
608 printk("ATOM BIOS beeped!\n");
611 static void atom_op_calltable(atom_exec_context
*ctx
, int *ptr
, int arg
)
613 int idx
= U8((*ptr
)++);
616 if (idx
< ATOM_TABLE_NAMES_CNT
)
617 SDEBUG(" table: %d (%s)\n", idx
, atom_table_names
[idx
]);
619 SDEBUG(" table: %d\n", idx
);
620 if (U16(ctx
->ctx
->cmd_table
+ 4 + 2 * idx
))
621 r
= amdgpu_atom_execute_table_locked(ctx
->ctx
, idx
, ctx
->ps
+ ctx
->ps_shift
);
627 static void atom_op_clear(atom_exec_context
*ctx
, int *ptr
, int arg
)
629 uint8_t attr
= U8((*ptr
)++);
633 attr
|= atom_def_dst
[attr
>> 3] << 6;
634 atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 0);
636 atom_put_dst(ctx
, arg
, attr
, &dptr
, 0, saved
);
639 static void atom_op_compare(atom_exec_context
*ctx
, int *ptr
, int arg
)
641 uint8_t attr
= U8((*ptr
)++);
644 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, NULL
, 1);
646 src
= atom_get_src(ctx
, attr
, ptr
);
647 ctx
->ctx
->cs_equal
= (dst
== src
);
648 ctx
->ctx
->cs_above
= (dst
> src
);
649 SDEBUG(" result: %s %s\n", ctx
->ctx
->cs_equal
? "EQ" : "NE",
650 ctx
->ctx
->cs_above
? "GT" : "LE");
653 static void atom_op_delay(atom_exec_context
*ctx
, int *ptr
, int arg
)
655 unsigned count
= U8((*ptr
)++);
656 SDEBUG(" count: %d\n", count
);
657 if (arg
== ATOM_UNIT_MICROSEC
)
659 else if (!drm_can_sleep())
665 static void atom_op_div(atom_exec_context
*ctx
, int *ptr
, int arg
)
667 uint8_t attr
= U8((*ptr
)++);
670 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, NULL
, 1);
672 src
= atom_get_src(ctx
, attr
, ptr
);
674 ctx
->ctx
->divmul
[0] = dst
/ src
;
675 ctx
->ctx
->divmul
[1] = dst
% src
;
677 ctx
->ctx
->divmul
[0] = 0;
678 ctx
->ctx
->divmul
[1] = 0;
682 static void atom_op_div32(atom_exec_context
*ctx
, int *ptr
, int arg
)
685 uint8_t attr
= U8((*ptr
)++);
688 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, NULL
, 1);
690 src
= atom_get_src(ctx
, attr
, ptr
);
693 val64
|= ((uint64_t)ctx
->ctx
->divmul
[1]) << 32;
695 ctx
->ctx
->divmul
[0] = lower_32_bits(val64
);
696 ctx
->ctx
->divmul
[1] = upper_32_bits(val64
);
698 ctx
->ctx
->divmul
[0] = 0;
699 ctx
->ctx
->divmul
[1] = 0;
703 static void atom_op_eot(atom_exec_context
*ctx
, int *ptr
, int arg
)
705 /* functionally, a nop */
708 static void atom_op_jump(atom_exec_context
*ctx
, int *ptr
, int arg
)
710 int execute
= 0, target
= U16(*ptr
);
711 unsigned long cjiffies
;
715 case ATOM_COND_ABOVE
:
716 execute
= ctx
->ctx
->cs_above
;
718 case ATOM_COND_ABOVEOREQUAL
:
719 execute
= ctx
->ctx
->cs_above
|| ctx
->ctx
->cs_equal
;
721 case ATOM_COND_ALWAYS
:
724 case ATOM_COND_BELOW
:
725 execute
= !(ctx
->ctx
->cs_above
|| ctx
->ctx
->cs_equal
);
727 case ATOM_COND_BELOWOREQUAL
:
728 execute
= !ctx
->ctx
->cs_above
;
730 case ATOM_COND_EQUAL
:
731 execute
= ctx
->ctx
->cs_equal
;
733 case ATOM_COND_NOTEQUAL
:
734 execute
= !ctx
->ctx
->cs_equal
;
737 if (arg
!= ATOM_COND_ALWAYS
)
738 SDEBUG(" taken: %s\n", execute
? "yes" : "no");
739 SDEBUG(" target: 0x%04X\n", target
);
741 if (ctx
->last_jump
== (ctx
->start
+ target
)) {
743 if (time_after(cjiffies
, ctx
->last_jump_jiffies
)) {
744 cjiffies
-= ctx
->last_jump_jiffies
;
745 if ((jiffies_to_msecs(cjiffies
) > 5000)) {
746 DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n");
750 /* jiffies wrap around we will just wait a little longer */
751 ctx
->last_jump_jiffies
= jiffies
;
754 ctx
->last_jump
= ctx
->start
+ target
;
755 ctx
->last_jump_jiffies
= jiffies
;
757 *ptr
= ctx
->start
+ target
;
761 static void atom_op_mask(atom_exec_context
*ctx
, int *ptr
, int arg
)
763 uint8_t attr
= U8((*ptr
)++);
764 uint32_t dst
, mask
, src
, saved
;
767 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
768 mask
= atom_get_src_direct(ctx
, ((attr
>> 3) & 7), ptr
);
769 SDEBUG(" mask: 0x%08x", mask
);
771 src
= atom_get_src(ctx
, attr
, ptr
);
775 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
778 static void atom_op_move(atom_exec_context
*ctx
, int *ptr
, int arg
)
780 uint8_t attr
= U8((*ptr
)++);
783 if (((attr
>> 3) & 7) != ATOM_SRC_DWORD
)
784 atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 0);
786 atom_skip_dst(ctx
, arg
, attr
, ptr
);
790 src
= atom_get_src(ctx
, attr
, ptr
);
792 atom_put_dst(ctx
, arg
, attr
, &dptr
, src
, saved
);
795 static void atom_op_mul(atom_exec_context
*ctx
, int *ptr
, int arg
)
797 uint8_t attr
= U8((*ptr
)++);
800 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, NULL
, 1);
802 src
= atom_get_src(ctx
, attr
, ptr
);
803 ctx
->ctx
->divmul
[0] = dst
* src
;
806 static void atom_op_mul32(atom_exec_context
*ctx
, int *ptr
, int arg
)
809 uint8_t attr
= U8((*ptr
)++);
812 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, NULL
, 1);
814 src
= atom_get_src(ctx
, attr
, ptr
);
815 val64
= (uint64_t)dst
* (uint64_t)src
;
816 ctx
->ctx
->divmul
[0] = lower_32_bits(val64
);
817 ctx
->ctx
->divmul
[1] = upper_32_bits(val64
);
820 static void atom_op_nop(atom_exec_context
*ctx
, int *ptr
, int arg
)
825 static void atom_op_or(atom_exec_context
*ctx
, int *ptr
, int arg
)
827 uint8_t attr
= U8((*ptr
)++);
828 uint32_t dst
, src
, saved
;
831 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
833 src
= atom_get_src(ctx
, attr
, ptr
);
836 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
839 static void atom_op_postcard(atom_exec_context
*ctx
, int *ptr
, int arg
)
841 uint8_t val
= U8((*ptr
)++);
842 SDEBUG("POST card output: 0x%02X\n", val
);
845 static void atom_op_repeat(atom_exec_context
*ctx
, int *ptr
, int arg
)
847 pr_info("unimplemented!\n");
850 static void atom_op_restorereg(atom_exec_context
*ctx
, int *ptr
, int arg
)
852 pr_info("unimplemented!\n");
855 static void atom_op_savereg(atom_exec_context
*ctx
, int *ptr
, int arg
)
857 pr_info("unimplemented!\n");
860 static void atom_op_setdatablock(atom_exec_context
*ctx
, int *ptr
, int arg
)
864 SDEBUG(" block: %d\n", idx
);
866 ctx
->ctx
->data_block
= 0;
868 ctx
->ctx
->data_block
= ctx
->start
;
870 ctx
->ctx
->data_block
= U16(ctx
->ctx
->data_table
+ 4 + 2 * idx
);
871 SDEBUG(" base: 0x%04X\n", ctx
->ctx
->data_block
);
874 static void atom_op_setfbbase(atom_exec_context
*ctx
, int *ptr
, int arg
)
876 uint8_t attr
= U8((*ptr
)++);
877 SDEBUG(" fb_base: ");
878 ctx
->ctx
->fb_base
= atom_get_src(ctx
, attr
, ptr
);
881 static void atom_op_setport(atom_exec_context
*ctx
, int *ptr
, int arg
)
887 if (port
< ATOM_IO_NAMES_CNT
)
888 SDEBUG(" port: %d (%s)\n", port
, atom_io_names
[port
]);
890 SDEBUG(" port: %d\n", port
);
892 ctx
->ctx
->io_mode
= ATOM_IO_MM
;
894 ctx
->ctx
->io_mode
= ATOM_IO_IIO
| port
;
898 ctx
->ctx
->io_mode
= ATOM_IO_PCI
;
901 case ATOM_PORT_SYSIO
:
902 ctx
->ctx
->io_mode
= ATOM_IO_SYSIO
;
908 static void atom_op_setregblock(atom_exec_context
*ctx
, int *ptr
, int arg
)
910 ctx
->ctx
->reg_block
= U16(*ptr
);
912 SDEBUG(" base: 0x%04X\n", ctx
->ctx
->reg_block
);
915 static void atom_op_shift_left(atom_exec_context
*ctx
, int *ptr
, int arg
)
917 uint8_t attr
= U8((*ptr
)++), shift
;
921 attr
|= atom_def_dst
[attr
>> 3] << 6;
923 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
924 shift
= atom_get_src_direct(ctx
, ATOM_SRC_BYTE0
, ptr
);
925 SDEBUG(" shift: %d\n", shift
);
928 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
931 static void atom_op_shift_right(atom_exec_context
*ctx
, int *ptr
, int arg
)
933 uint8_t attr
= U8((*ptr
)++), shift
;
937 attr
|= atom_def_dst
[attr
>> 3] << 6;
939 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
940 shift
= atom_get_src_direct(ctx
, ATOM_SRC_BYTE0
, ptr
);
941 SDEBUG(" shift: %d\n", shift
);
944 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
947 static void atom_op_shl(atom_exec_context
*ctx
, int *ptr
, int arg
)
949 uint8_t attr
= U8((*ptr
)++), shift
;
952 uint32_t dst_align
= atom_dst_to_src
[(attr
>> 3) & 7][(attr
>> 6) & 3];
954 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
955 /* op needs to full dst value */
957 shift
= atom_get_src(ctx
, attr
, ptr
);
958 SDEBUG(" shift: %d\n", shift
);
960 dst
&= atom_arg_mask
[dst_align
];
961 dst
>>= atom_arg_shift
[dst_align
];
963 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
966 static void atom_op_shr(atom_exec_context
*ctx
, int *ptr
, int arg
)
968 uint8_t attr
= U8((*ptr
)++), shift
;
971 uint32_t dst_align
= atom_dst_to_src
[(attr
>> 3) & 7][(attr
>> 6) & 3];
973 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
974 /* op needs to full dst value */
976 shift
= atom_get_src(ctx
, attr
, ptr
);
977 SDEBUG(" shift: %d\n", shift
);
979 dst
&= atom_arg_mask
[dst_align
];
980 dst
>>= atom_arg_shift
[dst_align
];
982 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
985 static void atom_op_sub(atom_exec_context
*ctx
, int *ptr
, int arg
)
987 uint8_t attr
= U8((*ptr
)++);
988 uint32_t dst
, src
, saved
;
991 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
993 src
= atom_get_src(ctx
, attr
, ptr
);
996 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
999 static void atom_op_switch(atom_exec_context
*ctx
, int *ptr
, int arg
)
1001 uint8_t attr
= U8((*ptr
)++);
1002 uint32_t src
, val
, target
;
1003 SDEBUG(" switch: ");
1004 src
= atom_get_src(ctx
, attr
, ptr
);
1005 while (U16(*ptr
) != ATOM_CASE_END
)
1006 if (U8(*ptr
) == ATOM_CASE_MAGIC
) {
1010 atom_get_src(ctx
, (attr
& 0x38) | ATOM_ARG_IMM
,
1014 SDEBUG(" target: %04X\n", target
);
1015 *ptr
= ctx
->start
+ target
;
1020 pr_info("Bad case\n");
1026 static void atom_op_test(atom_exec_context
*ctx
, int *ptr
, int arg
)
1028 uint8_t attr
= U8((*ptr
)++);
1031 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, NULL
, 1);
1033 src
= atom_get_src(ctx
, attr
, ptr
);
1034 ctx
->ctx
->cs_equal
= ((dst
& src
) == 0);
1035 SDEBUG(" result: %s\n", ctx
->ctx
->cs_equal
? "EQ" : "NE");
1038 static void atom_op_xor(atom_exec_context
*ctx
, int *ptr
, int arg
)
1040 uint8_t attr
= U8((*ptr
)++);
1041 uint32_t dst
, src
, saved
;
1044 dst
= atom_get_dst(ctx
, arg
, attr
, ptr
, &saved
, 1);
1046 src
= atom_get_src(ctx
, attr
, ptr
);
1049 atom_put_dst(ctx
, arg
, attr
, &dptr
, dst
, saved
);
1052 static void atom_op_debug(atom_exec_context
*ctx
, int *ptr
, int arg
)
1054 uint8_t val
= U8((*ptr
)++);
1055 SDEBUG("DEBUG output: 0x%02X\n", val
);
1058 static void atom_op_processds(atom_exec_context
*ctx
, int *ptr
, int arg
)
1060 uint16_t val
= U16(*ptr
);
1062 SDEBUG("PROCESSDS output: 0x%02X\n", val
);
1066 void (*func
) (atom_exec_context
*, int *, int);
1068 } opcode_table
[ATOM_OP_CNT
] = {
1071 atom_op_move
, ATOM_ARG_REG
}, {
1072 atom_op_move
, ATOM_ARG_PS
}, {
1073 atom_op_move
, ATOM_ARG_WS
}, {
1074 atom_op_move
, ATOM_ARG_FB
}, {
1075 atom_op_move
, ATOM_ARG_PLL
}, {
1076 atom_op_move
, ATOM_ARG_MC
}, {
1077 atom_op_and
, ATOM_ARG_REG
}, {
1078 atom_op_and
, ATOM_ARG_PS
}, {
1079 atom_op_and
, ATOM_ARG_WS
}, {
1080 atom_op_and
, ATOM_ARG_FB
}, {
1081 atom_op_and
, ATOM_ARG_PLL
}, {
1082 atom_op_and
, ATOM_ARG_MC
}, {
1083 atom_op_or
, ATOM_ARG_REG
}, {
1084 atom_op_or
, ATOM_ARG_PS
}, {
1085 atom_op_or
, ATOM_ARG_WS
}, {
1086 atom_op_or
, ATOM_ARG_FB
}, {
1087 atom_op_or
, ATOM_ARG_PLL
}, {
1088 atom_op_or
, ATOM_ARG_MC
}, {
1089 atom_op_shift_left
, ATOM_ARG_REG
}, {
1090 atom_op_shift_left
, ATOM_ARG_PS
}, {
1091 atom_op_shift_left
, ATOM_ARG_WS
}, {
1092 atom_op_shift_left
, ATOM_ARG_FB
}, {
1093 atom_op_shift_left
, ATOM_ARG_PLL
}, {
1094 atom_op_shift_left
, ATOM_ARG_MC
}, {
1095 atom_op_shift_right
, ATOM_ARG_REG
}, {
1096 atom_op_shift_right
, ATOM_ARG_PS
}, {
1097 atom_op_shift_right
, ATOM_ARG_WS
}, {
1098 atom_op_shift_right
, ATOM_ARG_FB
}, {
1099 atom_op_shift_right
, ATOM_ARG_PLL
}, {
1100 atom_op_shift_right
, ATOM_ARG_MC
}, {
1101 atom_op_mul
, ATOM_ARG_REG
}, {
1102 atom_op_mul
, ATOM_ARG_PS
}, {
1103 atom_op_mul
, ATOM_ARG_WS
}, {
1104 atom_op_mul
, ATOM_ARG_FB
}, {
1105 atom_op_mul
, ATOM_ARG_PLL
}, {
1106 atom_op_mul
, ATOM_ARG_MC
}, {
1107 atom_op_div
, ATOM_ARG_REG
}, {
1108 atom_op_div
, ATOM_ARG_PS
}, {
1109 atom_op_div
, ATOM_ARG_WS
}, {
1110 atom_op_div
, ATOM_ARG_FB
}, {
1111 atom_op_div
, ATOM_ARG_PLL
}, {
1112 atom_op_div
, ATOM_ARG_MC
}, {
1113 atom_op_add
, ATOM_ARG_REG
}, {
1114 atom_op_add
, ATOM_ARG_PS
}, {
1115 atom_op_add
, ATOM_ARG_WS
}, {
1116 atom_op_add
, ATOM_ARG_FB
}, {
1117 atom_op_add
, ATOM_ARG_PLL
}, {
1118 atom_op_add
, ATOM_ARG_MC
}, {
1119 atom_op_sub
, ATOM_ARG_REG
}, {
1120 atom_op_sub
, ATOM_ARG_PS
}, {
1121 atom_op_sub
, ATOM_ARG_WS
}, {
1122 atom_op_sub
, ATOM_ARG_FB
}, {
1123 atom_op_sub
, ATOM_ARG_PLL
}, {
1124 atom_op_sub
, ATOM_ARG_MC
}, {
1125 atom_op_setport
, ATOM_PORT_ATI
}, {
1126 atom_op_setport
, ATOM_PORT_PCI
}, {
1127 atom_op_setport
, ATOM_PORT_SYSIO
}, {
1128 atom_op_setregblock
, 0}, {
1129 atom_op_setfbbase
, 0}, {
1130 atom_op_compare
, ATOM_ARG_REG
}, {
1131 atom_op_compare
, ATOM_ARG_PS
}, {
1132 atom_op_compare
, ATOM_ARG_WS
}, {
1133 atom_op_compare
, ATOM_ARG_FB
}, {
1134 atom_op_compare
, ATOM_ARG_PLL
}, {
1135 atom_op_compare
, ATOM_ARG_MC
}, {
1136 atom_op_switch
, 0}, {
1137 atom_op_jump
, ATOM_COND_ALWAYS
}, {
1138 atom_op_jump
, ATOM_COND_EQUAL
}, {
1139 atom_op_jump
, ATOM_COND_BELOW
}, {
1140 atom_op_jump
, ATOM_COND_ABOVE
}, {
1141 atom_op_jump
, ATOM_COND_BELOWOREQUAL
}, {
1142 atom_op_jump
, ATOM_COND_ABOVEOREQUAL
}, {
1143 atom_op_jump
, ATOM_COND_NOTEQUAL
}, {
1144 atom_op_test
, ATOM_ARG_REG
}, {
1145 atom_op_test
, ATOM_ARG_PS
}, {
1146 atom_op_test
, ATOM_ARG_WS
}, {
1147 atom_op_test
, ATOM_ARG_FB
}, {
1148 atom_op_test
, ATOM_ARG_PLL
}, {
1149 atom_op_test
, ATOM_ARG_MC
}, {
1150 atom_op_delay
, ATOM_UNIT_MILLISEC
}, {
1151 atom_op_delay
, ATOM_UNIT_MICROSEC
}, {
1152 atom_op_calltable
, 0}, {
1153 atom_op_repeat
, 0}, {
1154 atom_op_clear
, ATOM_ARG_REG
}, {
1155 atom_op_clear
, ATOM_ARG_PS
}, {
1156 atom_op_clear
, ATOM_ARG_WS
}, {
1157 atom_op_clear
, ATOM_ARG_FB
}, {
1158 atom_op_clear
, ATOM_ARG_PLL
}, {
1159 atom_op_clear
, ATOM_ARG_MC
}, {
1162 atom_op_mask
, ATOM_ARG_REG
}, {
1163 atom_op_mask
, ATOM_ARG_PS
}, {
1164 atom_op_mask
, ATOM_ARG_WS
}, {
1165 atom_op_mask
, ATOM_ARG_FB
}, {
1166 atom_op_mask
, ATOM_ARG_PLL
}, {
1167 atom_op_mask
, ATOM_ARG_MC
}, {
1168 atom_op_postcard
, 0}, {
1170 atom_op_savereg
, 0}, {
1171 atom_op_restorereg
, 0}, {
1172 atom_op_setdatablock
, 0}, {
1173 atom_op_xor
, ATOM_ARG_REG
}, {
1174 atom_op_xor
, ATOM_ARG_PS
}, {
1175 atom_op_xor
, ATOM_ARG_WS
}, {
1176 atom_op_xor
, ATOM_ARG_FB
}, {
1177 atom_op_xor
, ATOM_ARG_PLL
}, {
1178 atom_op_xor
, ATOM_ARG_MC
}, {
1179 atom_op_shl
, ATOM_ARG_REG
}, {
1180 atom_op_shl
, ATOM_ARG_PS
}, {
1181 atom_op_shl
, ATOM_ARG_WS
}, {
1182 atom_op_shl
, ATOM_ARG_FB
}, {
1183 atom_op_shl
, ATOM_ARG_PLL
}, {
1184 atom_op_shl
, ATOM_ARG_MC
}, {
1185 atom_op_shr
, ATOM_ARG_REG
}, {
1186 atom_op_shr
, ATOM_ARG_PS
}, {
1187 atom_op_shr
, ATOM_ARG_WS
}, {
1188 atom_op_shr
, ATOM_ARG_FB
}, {
1189 atom_op_shr
, ATOM_ARG_PLL
}, {
1190 atom_op_shr
, ATOM_ARG_MC
}, {
1191 atom_op_debug
, 0}, {
1192 atom_op_processds
, 0}, {
1193 atom_op_mul32
, ATOM_ARG_PS
}, {
1194 atom_op_mul32
, ATOM_ARG_WS
}, {
1195 atom_op_div32
, ATOM_ARG_PS
}, {
1196 atom_op_div32
, ATOM_ARG_WS
},
1199 static int amdgpu_atom_execute_table_locked(struct atom_context
*ctx
, int index
, uint32_t * params
)
1201 int base
= CU16(ctx
->cmd_table
+ 4 + 2 * index
);
1202 int len
, ws
, ps
, ptr
;
1204 atom_exec_context ectx
;
1210 len
= CU16(base
+ ATOM_CT_SIZE_PTR
);
1211 ws
= CU8(base
+ ATOM_CT_WS_PTR
);
1212 ps
= CU8(base
+ ATOM_CT_PS_PTR
) & ATOM_CT_PS_MASK
;
1213 ptr
= base
+ ATOM_CT_CODE_PTR
;
1215 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base
, len
, ws
, ps
);
1218 ectx
.ps_shift
= ps
/ 4;
1224 ectx
.ws
= kcalloc(4, ws
, GFP_KERNEL
);
1231 if (op
< ATOM_OP_NAMES_CNT
)
1232 SDEBUG("%s @ 0x%04X\n", atom_op_names
[op
], ptr
- 1);
1234 SDEBUG("[%d] @ 0x%04X\n", op
, ptr
- 1);
1236 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
1237 base
, len
, ws
, ps
, ptr
- 1);
1242 if (op
< ATOM_OP_CNT
&& op
> 0)
1243 opcode_table
[op
].func(&ectx
, &ptr
,
1244 opcode_table
[op
].arg
);
1248 if (op
== ATOM_OP_EOT
)
1260 int amdgpu_atom_execute_table(struct atom_context
*ctx
, int index
, uint32_t * params
)
1264 mutex_lock(&ctx
->mutex
);
1265 /* reset data block */
1266 ctx
->data_block
= 0;
1267 /* reset reg block */
1269 /* reset fb window */
1272 ctx
->io_mode
= ATOM_IO_MM
;
1276 r
= amdgpu_atom_execute_table_locked(ctx
, index
, params
);
1277 mutex_unlock(&ctx
->mutex
);
1281 static int atom_iio_len
[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
1283 static void atom_index_iio(struct atom_context
*ctx
, int base
)
1285 ctx
->iio
= kzalloc(2 * 256, GFP_KERNEL
);
1288 while (CU8(base
) == ATOM_IIO_START
) {
1289 ctx
->iio
[CU8(base
+ 1)] = base
+ 2;
1291 while (CU8(base
) != ATOM_IIO_END
)
1292 base
+= atom_iio_len
[CU8(base
)];
1297 struct atom_context
*amdgpu_atom_parse(struct card_info
*card
, void *bios
)
1300 struct atom_context
*ctx
=
1301 kzalloc(sizeof(struct atom_context
), GFP_KERNEL
);
1311 if (CU16(0) != ATOM_BIOS_MAGIC
) {
1312 pr_info("Invalid BIOS magic\n");
1317 (CSTR(ATOM_ATI_MAGIC_PTR
), ATOM_ATI_MAGIC
,
1318 strlen(ATOM_ATI_MAGIC
))) {
1319 pr_info("Invalid ATI magic\n");
1324 base
= CU16(ATOM_ROM_TABLE_PTR
);
1326 (CSTR(base
+ ATOM_ROM_MAGIC_PTR
), ATOM_ROM_MAGIC
,
1327 strlen(ATOM_ROM_MAGIC
))) {
1328 pr_info("Invalid ATOM magic\n");
1333 ctx
->cmd_table
= CU16(base
+ ATOM_ROM_CMD_PTR
);
1334 ctx
->data_table
= CU16(base
+ ATOM_ROM_DATA_PTR
);
1335 atom_index_iio(ctx
, CU16(ctx
->data_table
+ ATOM_DATA_IIO_PTR
) + 4);
1337 amdgpu_atom_destroy(ctx
);
1341 idx
= CU16(ATOM_ROM_PART_NUMBER_PTR
);
1347 pr_info("ATOM BIOS: %s\n", str
);
1348 strlcpy(ctx
->vbios_version
, str
, sizeof(ctx
->vbios_version
));
1355 int amdgpu_atom_asic_init(struct atom_context
*ctx
)
1357 int hwi
= CU16(ctx
->data_table
+ ATOM_DATA_FWI_PTR
);
1363 ps
[0] = cpu_to_le32(CU32(hwi
+ ATOM_FWI_DEFSCLK_PTR
));
1364 ps
[1] = cpu_to_le32(CU32(hwi
+ ATOM_FWI_DEFMCLK_PTR
));
1365 if (!ps
[0] || !ps
[1])
1368 if (!CU16(ctx
->cmd_table
+ 4 + 2 * ATOM_CMD_INIT
))
1370 ret
= amdgpu_atom_execute_table(ctx
, ATOM_CMD_INIT
, ps
);
1379 void amdgpu_atom_destroy(struct atom_context
*ctx
)
1385 bool amdgpu_atom_parse_data_header(struct atom_context
*ctx
, int index
,
1386 uint16_t * size
, uint8_t * frev
, uint8_t * crev
,
1387 uint16_t * data_start
)
1389 int offset
= index
* 2 + 4;
1390 int idx
= CU16(ctx
->data_table
+ offset
);
1391 u16
*mdt
= (u16
*)(ctx
->bios
+ ctx
->data_table
+ 4);
1399 *frev
= CU8(idx
+ 2);
1401 *crev
= CU8(idx
+ 3);
1406 bool amdgpu_atom_parse_cmd_header(struct atom_context
*ctx
, int index
, uint8_t * frev
,
1409 int offset
= index
* 2 + 4;
1410 int idx
= CU16(ctx
->cmd_table
+ offset
);
1411 u16
*mct
= (u16
*)(ctx
->bios
+ ctx
->cmd_table
+ 4);
1417 *frev
= CU8(idx
+ 2);
1419 *crev
= CU8(idx
+ 3);