2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
31 #include "amdgpu_gfx.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_pm.h"
37 #include "gc/gc_9_0_offset.h"
38 #include "gc/gc_9_0_sh_mask.h"
40 #include "vega10_enum.h"
41 #include "hdp/hdp_4_0_offset.h"
43 #include "soc15_common.h"
44 #include "clearstate_gfx9.h"
45 #include "v9_structs.h"
47 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
49 #include "amdgpu_ras.h"
53 #define GFX9_NUM_GFX_RINGS 1
54 #define GFX9_MEC_HPD_SIZE 4096
55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
56 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
58 #define mmPWR_MISC_CNTL_STATUS 0x0183
59 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
60 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
61 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
62 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
63 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
65 #define mmGCEA_PROBE_MAP 0x070c
66 #define mmGCEA_PROBE_MAP_BASE_IDX 0
68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
70 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
77 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
84 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
89 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
91 MODULE_FIRMWARE("amdgpu/raven_me.bin");
92 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
98 MODULE_FIRMWARE("amdgpu/picasso_me.bin");
99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");
104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
106 MODULE_FIRMWARE("amdgpu/raven2_me.bin");
107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
113 MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
114 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
116 MODULE_FIRMWARE("amdgpu/renoir_ce.bin");
117 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin");
118 MODULE_FIRMWARE("amdgpu/renoir_me.bin");
119 MODULE_FIRMWARE("amdgpu/renoir_mec.bin");
120 MODULE_FIRMWARE("amdgpu/renoir_mec2.bin");
121 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
123 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03
124 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0
125 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04
126 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0
127 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09
128 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0
129 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a
130 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0
131 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b
132 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0
133 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c
134 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0
136 enum ta_ras_gfx_subblock
{
138 TA_RAS_BLOCK__GFX_CPC_INDEX_START
= 0,
139 TA_RAS_BLOCK__GFX_CPC_SCRATCH
= TA_RAS_BLOCK__GFX_CPC_INDEX_START
,
140 TA_RAS_BLOCK__GFX_CPC_UCODE
,
141 TA_RAS_BLOCK__GFX_DC_STATE_ME1
,
142 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1
,
143 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1
,
144 TA_RAS_BLOCK__GFX_DC_STATE_ME2
,
145 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2
,
146 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2
,
147 TA_RAS_BLOCK__GFX_CPC_INDEX_END
= TA_RAS_BLOCK__GFX_DC_RESTORE_ME2
,
149 TA_RAS_BLOCK__GFX_CPF_INDEX_START
,
150 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2
= TA_RAS_BLOCK__GFX_CPF_INDEX_START
,
151 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1
,
152 TA_RAS_BLOCK__GFX_CPF_TAG
,
153 TA_RAS_BLOCK__GFX_CPF_INDEX_END
= TA_RAS_BLOCK__GFX_CPF_TAG
,
155 TA_RAS_BLOCK__GFX_CPG_INDEX_START
,
156 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ
= TA_RAS_BLOCK__GFX_CPG_INDEX_START
,
157 TA_RAS_BLOCK__GFX_CPG_DMA_TAG
,
158 TA_RAS_BLOCK__GFX_CPG_TAG
,
159 TA_RAS_BLOCK__GFX_CPG_INDEX_END
= TA_RAS_BLOCK__GFX_CPG_TAG
,
161 TA_RAS_BLOCK__GFX_GDS_INDEX_START
,
162 TA_RAS_BLOCK__GFX_GDS_MEM
= TA_RAS_BLOCK__GFX_GDS_INDEX_START
,
163 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE
,
164 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM
,
165 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM
,
166 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM
,
167 TA_RAS_BLOCK__GFX_GDS_INDEX_END
= TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM
,
169 TA_RAS_BLOCK__GFX_SPI_SR_MEM
,
171 TA_RAS_BLOCK__GFX_SQ_INDEX_START
,
172 TA_RAS_BLOCK__GFX_SQ_SGPR
= TA_RAS_BLOCK__GFX_SQ_INDEX_START
,
173 TA_RAS_BLOCK__GFX_SQ_LDS_D
,
174 TA_RAS_BLOCK__GFX_SQ_LDS_I
,
175 TA_RAS_BLOCK__GFX_SQ_VGPR
, /* VGPR = SP*/
176 TA_RAS_BLOCK__GFX_SQ_INDEX_END
= TA_RAS_BLOCK__GFX_SQ_VGPR
,
178 TA_RAS_BLOCK__GFX_SQC_INDEX_START
,
180 TA_RAS_BLOCK__GFX_SQC_INDEX0_START
= TA_RAS_BLOCK__GFX_SQC_INDEX_START
,
181 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO
=
182 TA_RAS_BLOCK__GFX_SQC_INDEX0_START
,
183 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF
,
184 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO
,
185 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF
,
186 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO
,
187 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF
,
188 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO
,
189 TA_RAS_BLOCK__GFX_SQC_INDEX0_END
=
190 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO
,
192 TA_RAS_BLOCK__GFX_SQC_INDEX1_START
,
193 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM
=
194 TA_RAS_BLOCK__GFX_SQC_INDEX1_START
,
195 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO
,
196 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO
,
197 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM
,
198 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM
,
199 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO
,
200 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO
,
201 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM
,
202 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM
,
203 TA_RAS_BLOCK__GFX_SQC_INDEX1_END
=
204 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM
,
206 TA_RAS_BLOCK__GFX_SQC_INDEX2_START
,
207 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM
=
208 TA_RAS_BLOCK__GFX_SQC_INDEX2_START
,
209 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO
,
210 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO
,
211 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM
,
212 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM
,
213 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO
,
214 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO
,
215 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM
,
216 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM
,
217 TA_RAS_BLOCK__GFX_SQC_INDEX2_END
=
218 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM
,
219 TA_RAS_BLOCK__GFX_SQC_INDEX_END
= TA_RAS_BLOCK__GFX_SQC_INDEX2_END
,
221 TA_RAS_BLOCK__GFX_TA_INDEX_START
,
222 TA_RAS_BLOCK__GFX_TA_FS_DFIFO
= TA_RAS_BLOCK__GFX_TA_INDEX_START
,
223 TA_RAS_BLOCK__GFX_TA_FS_AFIFO
,
224 TA_RAS_BLOCK__GFX_TA_FL_LFIFO
,
225 TA_RAS_BLOCK__GFX_TA_FX_LFIFO
,
226 TA_RAS_BLOCK__GFX_TA_FS_CFIFO
,
227 TA_RAS_BLOCK__GFX_TA_INDEX_END
= TA_RAS_BLOCK__GFX_TA_FS_CFIFO
,
229 TA_RAS_BLOCK__GFX_TCA_INDEX_START
,
230 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO
= TA_RAS_BLOCK__GFX_TCA_INDEX_START
,
231 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO
,
232 TA_RAS_BLOCK__GFX_TCA_INDEX_END
= TA_RAS_BLOCK__GFX_TCA_REQ_FIFO
,
233 /* TCC (5 sub-ranges)*/
234 TA_RAS_BLOCK__GFX_TCC_INDEX_START
,
236 TA_RAS_BLOCK__GFX_TCC_INDEX0_START
= TA_RAS_BLOCK__GFX_TCC_INDEX_START
,
237 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA
= TA_RAS_BLOCK__GFX_TCC_INDEX0_START
,
238 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1
,
239 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0
,
240 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1
,
241 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0
,
242 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1
,
243 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG
,
244 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG
,
245 TA_RAS_BLOCK__GFX_TCC_INDEX0_END
= TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG
,
247 TA_RAS_BLOCK__GFX_TCC_INDEX1_START
,
248 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC
= TA_RAS_BLOCK__GFX_TCC_INDEX1_START
,
249 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER
,
250 TA_RAS_BLOCK__GFX_TCC_INDEX1_END
=
251 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER
,
253 TA_RAS_BLOCK__GFX_TCC_INDEX2_START
,
254 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA
= TA_RAS_BLOCK__GFX_TCC_INDEX2_START
,
255 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL
,
256 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO
,
257 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN
,
258 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ
,
259 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO
,
260 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM
,
261 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO
,
262 TA_RAS_BLOCK__GFX_TCC_INDEX2_END
=
263 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO
,
265 TA_RAS_BLOCK__GFX_TCC_INDEX3_START
,
266 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO
= TA_RAS_BLOCK__GFX_TCC_INDEX3_START
,
267 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM
,
268 TA_RAS_BLOCK__GFX_TCC_INDEX3_END
=
269 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM
,
271 TA_RAS_BLOCK__GFX_TCC_INDEX4_START
,
272 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN
=
273 TA_RAS_BLOCK__GFX_TCC_INDEX4_START
,
274 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER
,
275 TA_RAS_BLOCK__GFX_TCC_INDEX4_END
=
276 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER
,
277 TA_RAS_BLOCK__GFX_TCC_INDEX_END
= TA_RAS_BLOCK__GFX_TCC_INDEX4_END
,
279 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM
,
281 TA_RAS_BLOCK__GFX_TCP_INDEX_START
,
282 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM
= TA_RAS_BLOCK__GFX_TCP_INDEX_START
,
283 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM
,
284 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO
,
285 TA_RAS_BLOCK__GFX_TCP_VM_FIFO
,
286 TA_RAS_BLOCK__GFX_TCP_DB_RAM
,
287 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0
,
288 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1
,
289 TA_RAS_BLOCK__GFX_TCP_INDEX_END
= TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1
,
291 TA_RAS_BLOCK__GFX_TD_INDEX_START
,
292 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO
= TA_RAS_BLOCK__GFX_TD_INDEX_START
,
293 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI
,
294 TA_RAS_BLOCK__GFX_TD_CS_FIFO
,
295 TA_RAS_BLOCK__GFX_TD_INDEX_END
= TA_RAS_BLOCK__GFX_TD_CS_FIFO
,
296 /* EA (3 sub-ranges)*/
297 TA_RAS_BLOCK__GFX_EA_INDEX_START
,
299 TA_RAS_BLOCK__GFX_EA_INDEX0_START
= TA_RAS_BLOCK__GFX_EA_INDEX_START
,
300 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM
= TA_RAS_BLOCK__GFX_EA_INDEX0_START
,
301 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM
,
302 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM
,
303 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM
,
304 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM
,
305 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM
,
306 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM
,
307 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM
,
308 TA_RAS_BLOCK__GFX_EA_INDEX0_END
= TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM
,
310 TA_RAS_BLOCK__GFX_EA_INDEX1_START
,
311 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM
= TA_RAS_BLOCK__GFX_EA_INDEX1_START
,
312 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM
,
313 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM
,
314 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM
,
315 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM
,
316 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM
,
317 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM
,
318 TA_RAS_BLOCK__GFX_EA_INDEX1_END
= TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM
,
320 TA_RAS_BLOCK__GFX_EA_INDEX2_START
,
321 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM
= TA_RAS_BLOCK__GFX_EA_INDEX2_START
,
322 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM
,
323 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM
,
324 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM
,
325 TA_RAS_BLOCK__GFX_EA_INDEX2_END
= TA_RAS_BLOCK__GFX_EA_MAM_D3MEM
,
326 TA_RAS_BLOCK__GFX_EA_INDEX_END
= TA_RAS_BLOCK__GFX_EA_INDEX2_END
,
328 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE
,
330 TA_RAS_BLOCK__UTC_VML2_WALKER
,
331 /* UTC ATC L2 2MB cache*/
332 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK
,
333 /* UTC ATC L2 4KB cache*/
334 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK
,
335 TA_RAS_BLOCK__GFX_MAX
338 struct ras_gfx_subblock
{
341 int hw_supported_error_type
;
342 int sw_supported_error_type
;
345 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \
346 [AMDGPU_RAS_BLOCK__##subblock] = { \
348 TA_RAS_BLOCK__##subblock, \
349 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \
350 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \
353 static const struct ras_gfx_subblock ras_gfx_subblocks
[] = {
354 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH
, 0, 1, 1, 1, 1, 0, 0, 1),
355 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE
, 0, 1, 1, 1, 1, 0, 0, 1),
356 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1
, 1, 0, 0, 1, 0, 0, 1, 0),
357 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1
, 1, 0, 0, 1, 0, 0, 0, 0),
358 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1
, 1, 0, 0, 1, 0, 0, 0, 0),
359 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2
, 1, 0, 0, 1, 0, 0, 0, 0),
360 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2
, 1, 0, 0, 1, 0, 0, 0, 0),
361 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2
, 1, 0, 0, 1, 0, 0, 0, 0),
362 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2
, 1, 0, 0, 1, 0, 0, 0, 0),
363 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1
, 1, 0, 0, 1, 0, 0, 1, 0),
364 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG
, 0, 1, 1, 1, 1, 0, 0, 1),
365 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ
, 1, 0, 0, 1, 0, 0, 1, 0),
366 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG
, 0, 1, 1, 1, 0, 1, 0, 1),
367 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG
, 0, 1, 1, 1, 1, 1, 0, 1),
368 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM
, 0, 1, 1, 1, 0, 0, 0, 0),
369 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE
, 1, 0, 0, 1, 0, 0, 0, 0),
370 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM
, 0, 1, 1, 1, 0, 0, 0,
372 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM
, 1, 0, 0, 1, 0, 0, 0,
374 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM
, 0, 1, 1, 1, 0, 0, 0, 0),
375 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM
, 1, 0, 0, 1, 0, 0, 0, 0),
376 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR
, 0, 1, 1, 1, 0, 0, 0, 0),
377 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D
, 0, 1, 1, 1, 1, 0, 0, 1),
378 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I
, 0, 1, 1, 1, 0, 0, 0, 0),
379 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR
, 0, 1, 1, 1, 0, 0, 0, 0),
380 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO
, 0, 1, 1, 1, 0, 0, 0, 1),
381 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF
, 0, 1, 1, 1, 0, 0,
383 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO
, 0, 1, 1, 1, 0, 0, 0,
385 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF
, 0, 1, 1, 1, 0, 0,
387 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO
, 0, 1, 1, 1, 1, 0, 0,
389 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF
, 0, 1, 1, 1, 0, 0,
391 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO
, 0, 1, 1, 1, 0, 0, 0,
393 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM
, 0, 1, 1, 1, 1, 0, 0,
395 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO
, 1, 0, 0, 1, 0,
397 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO
, 1, 0, 0, 1, 0, 0, 0,
399 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM
, 0, 1, 1, 1, 0, 0, 0,
401 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM
, 0, 1, 1, 1, 0, 0, 0,
403 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO
, 1, 0, 0, 1, 0, 0, 0,
405 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO
, 1, 0, 0, 1, 0, 0, 0,
407 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM
, 1, 0, 0, 1, 0, 0,
409 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM
, 0, 1, 1, 1, 0, 0, 0,
411 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM
, 0, 1, 1, 1, 1, 0, 0,
413 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO
, 1, 0, 0, 1, 0,
415 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO
, 1, 0, 0, 1, 0, 0, 0,
417 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM
, 0, 1, 1, 1, 0, 0, 0,
419 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM
, 0, 1, 1, 1, 0, 0, 0,
421 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO
, 1, 0, 0, 1, 0, 0, 0,
423 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO
, 1, 0, 0, 1, 0, 0, 0,
425 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM
, 1, 0, 0, 1, 0, 0,
427 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM
, 0, 1, 1, 1, 0, 0, 0,
429 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO
, 0, 1, 1, 1, 1, 0, 0, 1),
430 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO
, 1, 0, 0, 1, 0, 0, 0, 0),
431 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO
, 1, 0, 0, 1, 0, 0, 0, 0),
432 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO
, 1, 0, 0, 1, 0, 0, 0, 0),
433 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO
, 1, 0, 0, 1, 0, 0, 0, 0),
434 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO
, 1, 0, 0, 1, 0, 1, 1, 0),
435 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO
, 1, 0, 0, 1, 0, 0, 0, 0),
436 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA
, 0, 1, 1, 1, 1, 0, 0, 1),
437 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1
, 0, 1, 1, 1, 1, 0, 0,
439 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0
, 0, 1, 1, 1, 1, 0, 0,
441 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1
, 0, 1, 1, 1, 1, 0, 0,
443 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0
, 0, 1, 1, 1, 0, 0, 0,
445 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1
, 0, 1, 1, 1, 0, 0, 0,
447 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG
, 0, 1, 1, 1, 0, 0, 0, 0),
448 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG
, 0, 1, 1, 1, 0, 0, 0, 0),
449 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC
, 1, 0, 0, 1, 0, 0, 0, 0),
450 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER
, 1, 0, 0, 1, 0, 0, 0, 0),
451 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA
, 1, 0, 0, 1, 0, 0, 0, 0),
452 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL
, 1, 0, 0, 1, 0, 0, 0, 0),
453 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO
, 1, 0, 0, 1, 0, 0, 0, 0),
454 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN
, 1, 0, 0, 1, 0, 1, 1, 0),
455 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ
, 1, 0, 0, 1, 0, 0, 0, 0),
456 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO
, 0, 1, 1, 1, 0, 0, 0, 0),
457 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM
, 1, 0, 0, 1, 0, 0, 1, 0),
458 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO
, 1, 0, 0, 1, 0, 0, 0,
460 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO
, 1, 0, 0, 1, 0, 0, 0, 0),
461 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM
, 1, 0, 0, 1, 0, 0, 0,
463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN
, 1, 0, 0, 1, 0, 0,
465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER
, 1, 0, 0, 1, 0, 0, 0,
467 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM
, 1, 0, 0, 1, 0, 0, 0, 0),
468 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM
, 0, 1, 1, 1, 1, 0, 0, 1),
469 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM
, 0, 1, 1, 1, 0, 0, 0, 0),
470 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO
, 1, 0, 0, 1, 0, 0, 0, 0),
471 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO
, 0, 1, 1, 1, 0, 0, 0, 0),
472 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM
, 1, 0, 0, 1, 0, 0, 0, 0),
473 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0
, 0, 1, 1, 1, 0, 0, 0, 0),
474 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1
, 0, 1, 1, 1, 0, 0, 0, 0),
475 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO
, 0, 1, 1, 1, 1, 0, 0, 1),
476 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI
, 0, 1, 1, 1, 0, 0, 0, 0),
477 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO
, 1, 0, 0, 1, 0, 0, 0, 0),
478 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM
, 0, 1, 1, 1, 1, 0, 0, 1),
479 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM
, 0, 1, 1, 1, 0, 0, 0, 0),
480 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM
, 0, 1, 1, 1, 0, 0, 0, 0),
481 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM
, 0, 1, 1, 1, 0, 0, 0, 0),
482 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM
, 0, 1, 1, 1, 0, 0, 0, 0),
483 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM
, 0, 1, 1, 1, 0, 0, 0, 0),
484 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM
, 0, 1, 1, 1, 0, 0, 0, 0),
485 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM
, 0, 1, 1, 1, 0, 0, 0, 0),
486 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM
, 1, 0, 0, 1, 0, 0, 0, 0),
487 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM
, 1, 0, 0, 1, 0, 0, 0, 0),
488 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM
, 1, 0, 0, 1, 0, 0, 0, 0),
489 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM
, 1, 0, 0, 1, 0, 0, 0, 0),
490 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM
, 1, 0, 0, 1, 0, 0, 0, 0),
491 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM
, 1, 0, 0, 1, 0, 0, 0, 0),
492 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM
, 1, 0, 0, 1, 0, 0, 0, 0),
493 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM
, 1, 0, 0, 1, 0, 0, 0, 0),
494 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM
, 1, 0, 0, 1, 0, 0, 0, 0),
495 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM
, 1, 0, 0, 1, 0, 0, 0, 0),
496 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM
, 1, 0, 0, 1, 0, 0, 0, 0),
497 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE
, 0, 1, 1, 1, 0, 0, 0, 0),
498 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER
, 0, 1, 1, 1, 0, 0, 0, 0),
499 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK
, 1, 0, 0, 1, 0, 0, 0, 0),
500 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK
, 0, 1, 1, 1, 0, 0, 0, 0),
503 static const struct soc15_reg_golden golden_settings_gc_9_0
[] =
505 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmDB_DEBUG2
, 0xf00fffff, 0x00000400),
506 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmDB_DEBUG3
, 0x80000000, 0x80000000),
507 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_GPU_ID
, 0x0000000f, 0x00000000),
508 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_BINNER_EVENT_CNTL_3
, 0x00000003, 0x82400024),
509 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE
, 0x3fffffff, 0x00000001),
510 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_LINE_STIPPLE_STATE
, 0x0000ff0f, 0x00000000),
511 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSH_MEM_CONFIG
, 0x00001000, 0x00001000),
512 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_RESOURCE_RESERVE_CU_0
, 0x0007ffff, 0x00000800),
513 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_RESOURCE_RESERVE_CU_1
, 0x0007ffff, 0x00000800),
514 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0
, 0x01ffffff, 0x0000ff87),
515 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1
, 0x01ffffff, 0x0000ff8f),
516 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSQC_CONFIG
, 0x03000000, 0x020a2000),
517 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTA_CNTL_AUX
, 0xfffffeef, 0x010b0000),
518 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_HI
, 0xffffffff, 0x4a2c0e68),
519 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_LO
, 0xffffffff, 0xb5d3f197),
520 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmVGT_CACHE_INVALIDATION
, 0x3fff3af3, 0x19200000),
521 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmVGT_GS_MAX_WAVE_ID
, 0x00000fff, 0x000003ff),
522 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_MEC1_F32_INT_DIS
, 0x00000800, 0x00000800),
523 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_MEC2_F32_INT_DIS
, 0x00000800, 0x00000800),
524 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_DEBUG
, 0x00008000, 0x00008000)
527 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10
[] =
529 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL
, 0x0000f000, 0x00012107),
530 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL_3
, 0x30000000, 0x10000000),
531 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCPC_UTCL1_CNTL
, 0x08000000, 0x08000080),
532 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCPF_UTCL1_CNTL
, 0x08000000, 0x08000080),
533 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCPG_UTCL1_CNTL
, 0x08000000, 0x08000080),
534 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG
, 0xffff77ff, 0x2a114042),
535 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG_READ
, 0xffff77ff, 0x2a114042),
536 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmIA_UTCL1_CNTL
, 0x08000000, 0x08000080),
537 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE_1
, 0x00008000, 0x00048000),
538 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_GPM_UTCL1_CNTL_0
, 0x08000000, 0x08000080),
539 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_GPM_UTCL1_CNTL_1
, 0x08000000, 0x08000080),
540 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_GPM_UTCL1_CNTL_2
, 0x08000000, 0x08000080),
541 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_PREWALKER_UTCL1_CNTL
, 0x08000000, 0x08000080),
542 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_SPM_UTCL1_CNTL
, 0x08000000, 0x08000080),
543 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRMI_UTCL1_CNTL2
, 0x00030000, 0x00020000),
544 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_CONFIG_CNTL_1
, 0x0000000f, 0x01000107),
545 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTD_CNTL
, 0x00001800, 0x00000800),
546 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmWD_UTCL1_CNTL
, 0x08000000, 0x08000080)
549 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20
[] =
551 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_DCC_CONFIG
, 0x0f000080, 0x04000080),
552 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL_2
, 0x0f000000, 0x0a000000),
553 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL_3
, 0x30000000, 0x10000000),
554 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG
, 0xf3e777ff, 0x22014042),
555 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG_READ
, 0xf3e777ff, 0x22014042),
556 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmDB_DEBUG2
, 0x00003e00, 0x00000400),
557 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE_1
, 0xff840000, 0x04040000),
558 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRMI_UTCL1_CNTL2
, 0x00030000, 0x00030000),
559 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_CONFIG_CNTL_1
, 0xffff010f, 0x01000107),
560 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTA_CNTL_AUX
, 0x000b0000, 0x000b0000),
561 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTD_CNTL
, 0x01000000, 0x01000000)
564 static const struct soc15_reg_golden golden_settings_gc_9_1
[] =
566 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL
, 0xfffdf3cf, 0x00014104),
567 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCPC_UTCL1_CNTL
, 0x08000000, 0x08000080),
568 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCPF_UTCL1_CNTL
, 0x08000000, 0x08000080),
569 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCPG_UTCL1_CNTL
, 0x08000000, 0x08000080),
570 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmDB_DEBUG2
, 0xf00fffff, 0x00000420),
571 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_GPU_ID
, 0x0000000f, 0x00000000),
572 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmIA_UTCL1_CNTL
, 0x08000000, 0x08000080),
573 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_BINNER_EVENT_CNTL_3
, 0x00000003, 0x82400024),
574 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE
, 0x3fffffff, 0x00000001),
575 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_LINE_STIPPLE_STATE
, 0x0000ff0f, 0x00000000),
576 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_GPM_UTCL1_CNTL_0
, 0x08000000, 0x08000080),
577 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_GPM_UTCL1_CNTL_1
, 0x08000000, 0x08000080),
578 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_GPM_UTCL1_CNTL_2
, 0x08000000, 0x08000080),
579 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_PREWALKER_UTCL1_CNTL
, 0x08000000, 0x08000080),
580 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_SPM_UTCL1_CNTL
, 0x08000000, 0x08000080),
581 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTA_CNTL_AUX
, 0xfffffeef, 0x010b0000),
582 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_HI
, 0xffffffff, 0x00000000),
583 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_LO
, 0xffffffff, 0x00003120),
584 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmVGT_CACHE_INVALIDATION
, 0x3fff3af3, 0x19200000),
585 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmVGT_GS_MAX_WAVE_ID
, 0x00000fff, 0x000000ff),
586 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmWD_UTCL1_CNTL
, 0x08000000, 0x08000080),
587 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_MEC1_F32_INT_DIS
, 0x00000800, 0x00000800),
588 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_MEC2_F32_INT_DIS
, 0x00000800, 0x00000800),
589 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_DEBUG
, 0x00008000, 0x00008000)
592 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1
[] =
594 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL_3
, 0x30000000, 0x10000000),
595 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG
, 0xffff77ff, 0x24000042),
596 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG_READ
, 0xffff77ff, 0x24000042),
597 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE_1
, 0xffffffff, 0x04048000),
598 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_MODE_CNTL_1
, 0x06000000, 0x06000000),
599 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRMI_UTCL1_CNTL2
, 0x00030000, 0x00020000),
600 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTD_CNTL
, 0x01bd9f33, 0x00000800)
603 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2
[] =
605 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_DCC_CONFIG
, 0xff7fffff, 0x04000000),
606 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL
, 0xfffdf3cf, 0x00014104),
607 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL_2
, 0xff7fffff, 0x0a000000),
608 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCPC_UTCL1_CNTL
, 0x7f0fffff, 0x08000080),
609 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCPF_UTCL1_CNTL
, 0xff8fffff, 0x08000080),
610 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCPG_UTCL1_CNTL
, 0x7f8fffff, 0x08000080),
611 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG
, 0xffff77ff, 0x26013041),
612 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG_READ
, 0xffff77ff, 0x26013041),
613 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmIA_UTCL1_CNTL
, 0x3f8fffff, 0x08000080),
614 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE_1
, 0xffffffff, 0x04040000),
615 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_GPM_UTCL1_CNTL_0
, 0xff0fffff, 0x08000080),
616 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_GPM_UTCL1_CNTL_1
, 0xff0fffff, 0x08000080),
617 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_GPM_UTCL1_CNTL_2
, 0xff0fffff, 0x08000080),
618 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_PREWALKER_UTCL1_CNTL
, 0xff0fffff, 0x08000080),
619 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmRLC_SPM_UTCL1_CNTL
, 0xff0fffff, 0x08000080),
620 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_HI
, 0xffffffff, 0x00000000),
621 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_LO
, 0xffffffff, 0x00000010),
622 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTD_CNTL
, 0x01bd9f33, 0x01000000),
623 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmWD_UTCL1_CNTL
, 0x3f8fffff, 0x08000080),
626 static const struct soc15_reg_golden golden_settings_gc_9_1_rn
[] =
628 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL
, 0xfffdf3cf, 0x00014104),
629 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL_2
, 0xff7fffff, 0x0a000000),
630 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmDB_DEBUG2
, 0xf00fffff, 0x00000400),
631 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG
, 0xf3e777ff, 0x24000042),
632 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG_READ
, 0xf3e777ff, 0x24000042),
633 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE
, 0x3fffffff, 0x00000001),
634 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE_1
, 0xffffffff, 0x04040000),
635 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_LINE_STIPPLE_STATE
, 0x0000ff0f, 0x00000000),
636 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTA_CNTL_AUX
, 0xfffffeef, 0x010b0000),
637 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_HI
, 0xffffffff, 0x00000000),
638 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_LO
, 0xffffffff, 0x00003120),
639 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGCEA_PROBE_MAP
, 0xffffffff, 0x0000cccc),
642 static const struct soc15_reg_golden golden_settings_gc_9_x_common
[] =
644 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_SD_CNTL
, 0xffffffff, 0x000001ff),
645 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGRBM_CAM_INDEX
, 0xffffffff, 0x00000000),
646 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGRBM_CAM_DATA
, 0xffffffff, 0x2544c382)
649 static const struct soc15_reg_golden golden_settings_gc_9_2_1
[] =
651 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmDB_DEBUG2
, 0xf00fffff, 0x00000420),
652 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_GPU_ID
, 0x0000000f, 0x00000000),
653 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_BINNER_EVENT_CNTL_3
, 0x00000003, 0x82400024),
654 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE
, 0x3fffffff, 0x00000001),
655 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_LINE_STIPPLE_STATE
, 0x0000ff0f, 0x00000000),
656 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSH_MEM_CONFIG
, 0x00001000, 0x00001000),
657 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_RESOURCE_RESERVE_CU_0
, 0x0007ffff, 0x00000800),
658 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_RESOURCE_RESERVE_CU_1
, 0x0007ffff, 0x00000800),
659 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0
, 0x01ffffff, 0x0000ff87),
660 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1
, 0x01ffffff, 0x0000ff8f),
661 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSQC_CONFIG
, 0x03000000, 0x020a2000),
662 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTA_CNTL_AUX
, 0xfffffeef, 0x010b0000),
663 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_HI
, 0xffffffff, 0x4a2c0e68),
664 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_LO
, 0xffffffff, 0xb5d3f197),
665 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmVGT_CACHE_INVALIDATION
, 0x3fff3af3, 0x19200000),
666 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmVGT_GS_MAX_WAVE_ID
, 0x00000fff, 0x000003ff)
669 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12
[] =
671 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_DCC_CONFIG
, 0x00000080, 0x04000080),
672 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL
, 0xfffdf3cf, 0x00014104),
673 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCB_HW_CONTROL_2
, 0x0f000000, 0x0a000000),
674 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG
, 0xffff77ff, 0x24104041),
675 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG_READ
, 0xffff77ff, 0x24104041),
676 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmPA_SC_ENHANCE_1
, 0xffffffff, 0x04040000),
677 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSPI_CONFIG_CNTL_1
, 0xffff03ff, 0x01000107),
678 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_HI
, 0xffffffff, 0x00000000),
679 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_LO
, 0xffffffff, 0x76325410),
680 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTD_CNTL
, 0x01bd9f33, 0x01000000),
681 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_MEC1_F32_INT_DIS
, 0x00000800, 0x00000800),
682 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_MEC2_F32_INT_DIS
, 0x00000800, 0x00000800),
683 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmCP_DEBUG
, 0x00008000, 0x00008000)
686 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct
[] =
688 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmGB_ADDR_CONFIG
, 0xffff77ff, 0x2a114042),
689 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTA_CNTL_AUX
, 0xfffffeef, 0x10b0000),
690 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_0_ARCT
, 0x3fffffff, 0x346f0a4e),
691 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_1_ARCT
, 0x3fffffff, 0x1c642ca),
692 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_2_ARCT
, 0x3fffffff, 0x26f45098),
693 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_3_ARCT
, 0x3fffffff, 0x2ebd9fe3),
694 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_4_ARCT
, 0x3fffffff, 0xb90f5b1),
695 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmTCP_CHAN_STEER_5_ARCT
, 0x3ff, 0x135),
696 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSQ_CONFIG
, 0xffffffff, 0x011A0000),
697 SOC15_REG_GOLDEN_VALUE(GC
, 0, mmSQ_FIFO_SIZES
, 0xffffffff, 0x00000f00),
700 static const struct soc15_reg_rlcg rlcg_access_gc_9_0
[] = {
701 {SOC15_REG_ENTRY(GC
, 0, mmGRBM_GFX_INDEX
)},
702 {SOC15_REG_ENTRY(GC
, 0, mmSQ_IND_INDEX
)},
705 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS
[] =
707 mmRLC_SRM_INDEX_CNTL_ADDR_0
- mmRLC_SRM_INDEX_CNTL_ADDR_0
,
708 mmRLC_SRM_INDEX_CNTL_ADDR_1
- mmRLC_SRM_INDEX_CNTL_ADDR_0
,
709 mmRLC_SRM_INDEX_CNTL_ADDR_2
- mmRLC_SRM_INDEX_CNTL_ADDR_0
,
710 mmRLC_SRM_INDEX_CNTL_ADDR_3
- mmRLC_SRM_INDEX_CNTL_ADDR_0
,
711 mmRLC_SRM_INDEX_CNTL_ADDR_4
- mmRLC_SRM_INDEX_CNTL_ADDR_0
,
712 mmRLC_SRM_INDEX_CNTL_ADDR_5
- mmRLC_SRM_INDEX_CNTL_ADDR_0
,
713 mmRLC_SRM_INDEX_CNTL_ADDR_6
- mmRLC_SRM_INDEX_CNTL_ADDR_0
,
714 mmRLC_SRM_INDEX_CNTL_ADDR_7
- mmRLC_SRM_INDEX_CNTL_ADDR_0
,
717 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS
[] =
719 mmRLC_SRM_INDEX_CNTL_DATA_0
- mmRLC_SRM_INDEX_CNTL_DATA_0
,
720 mmRLC_SRM_INDEX_CNTL_DATA_1
- mmRLC_SRM_INDEX_CNTL_DATA_0
,
721 mmRLC_SRM_INDEX_CNTL_DATA_2
- mmRLC_SRM_INDEX_CNTL_DATA_0
,
722 mmRLC_SRM_INDEX_CNTL_DATA_3
- mmRLC_SRM_INDEX_CNTL_DATA_0
,
723 mmRLC_SRM_INDEX_CNTL_DATA_4
- mmRLC_SRM_INDEX_CNTL_DATA_0
,
724 mmRLC_SRM_INDEX_CNTL_DATA_5
- mmRLC_SRM_INDEX_CNTL_DATA_0
,
725 mmRLC_SRM_INDEX_CNTL_DATA_6
- mmRLC_SRM_INDEX_CNTL_DATA_0
,
726 mmRLC_SRM_INDEX_CNTL_DATA_7
- mmRLC_SRM_INDEX_CNTL_DATA_0
,
729 void gfx_v9_0_rlcg_wreg(struct amdgpu_device
*adev
, u32 offset
, u32 v
)
731 static void *scratch_reg0
;
732 static void *scratch_reg1
;
733 static void *scratch_reg2
;
734 static void *scratch_reg3
;
735 static void *spare_int
;
736 static uint32_t grbm_cntl
;
737 static uint32_t grbm_idx
;
739 scratch_reg0
= adev
->rmmio
+ (adev
->reg_offset
[GC_HWIP
][0][mmSCRATCH_REG0_BASE_IDX
] + mmSCRATCH_REG0
)*4;
740 scratch_reg1
= adev
->rmmio
+ (adev
->reg_offset
[GC_HWIP
][0][mmSCRATCH_REG1_BASE_IDX
] + mmSCRATCH_REG1
)*4;
741 scratch_reg2
= adev
->rmmio
+ (adev
->reg_offset
[GC_HWIP
][0][mmSCRATCH_REG1_BASE_IDX
] + mmSCRATCH_REG2
)*4;
742 scratch_reg3
= adev
->rmmio
+ (adev
->reg_offset
[GC_HWIP
][0][mmSCRATCH_REG1_BASE_IDX
] + mmSCRATCH_REG3
)*4;
743 spare_int
= adev
->rmmio
+ (adev
->reg_offset
[GC_HWIP
][0][mmRLC_SPARE_INT_BASE_IDX
] + mmRLC_SPARE_INT
)*4;
745 grbm_cntl
= adev
->reg_offset
[GC_HWIP
][0][mmGRBM_GFX_CNTL_BASE_IDX
] + mmGRBM_GFX_CNTL
;
746 grbm_idx
= adev
->reg_offset
[GC_HWIP
][0][mmGRBM_GFX_INDEX_BASE_IDX
] + mmGRBM_GFX_INDEX
;
748 if (amdgpu_sriov_runtime(adev
)) {
749 pr_err("shouldn't call rlcg write register during runtime\n");
753 if (offset
== grbm_cntl
|| offset
== grbm_idx
) {
754 if (offset
== grbm_cntl
)
755 writel(v
, scratch_reg2
);
756 else if (offset
== grbm_idx
)
757 writel(v
, scratch_reg3
);
759 writel(v
, ((void __iomem
*)adev
->rmmio
) + (offset
* 4));
762 uint32_t retries
= 50000;
764 writel(v
, scratch_reg0
);
765 writel(offset
| 0x80000000, scratch_reg1
);
766 writel(1, spare_int
);
767 for (i
= 0; i
< retries
; i
++) {
770 tmp
= readl(scratch_reg1
);
771 if (!(tmp
& 0x80000000))
777 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset
);
782 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
783 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
784 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
785 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
787 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device
*adev
);
788 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device
*adev
);
789 static void gfx_v9_0_set_gds_init(struct amdgpu_device
*adev
);
790 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device
*adev
);
791 static int gfx_v9_0_get_cu_info(struct amdgpu_device
*adev
,
792 struct amdgpu_cu_info
*cu_info
);
793 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device
*adev
);
794 static void gfx_v9_0_select_se_sh(struct amdgpu_device
*adev
, u32 se_num
, u32 sh_num
, u32 instance
);
795 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring
*ring
);
796 static u64
gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring
*ring
);
797 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device
*adev
,
798 void *ras_error_status
);
799 static int gfx_v9_0_ras_error_inject(struct amdgpu_device
*adev
,
801 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device
*adev
);
803 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring
*kiq_ring
,
806 amdgpu_ring_write(kiq_ring
, PACKET3(PACKET3_SET_RESOURCES
, 6));
807 amdgpu_ring_write(kiq_ring
,
808 PACKET3_SET_RESOURCES_VMID_MASK(0) |
809 /* vmid_mask:0* queue_type:0 (KIQ) */
810 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
811 amdgpu_ring_write(kiq_ring
,
812 lower_32_bits(queue_mask
)); /* queue mask lo */
813 amdgpu_ring_write(kiq_ring
,
814 upper_32_bits(queue_mask
)); /* queue mask hi */
815 amdgpu_ring_write(kiq_ring
, 0); /* gws mask lo */
816 amdgpu_ring_write(kiq_ring
, 0); /* gws mask hi */
817 amdgpu_ring_write(kiq_ring
, 0); /* oac mask */
818 amdgpu_ring_write(kiq_ring
, 0); /* gds heap base:0, gds heap size:0 */
821 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring
*kiq_ring
,
822 struct amdgpu_ring
*ring
)
824 struct amdgpu_device
*adev
= kiq_ring
->adev
;
825 uint64_t mqd_addr
= amdgpu_bo_gpu_offset(ring
->mqd_obj
);
826 uint64_t wptr_addr
= adev
->wb
.gpu_addr
+ (ring
->wptr_offs
* 4);
827 uint32_t eng_sel
= ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
? 4 : 0;
829 amdgpu_ring_write(kiq_ring
, PACKET3(PACKET3_MAP_QUEUES
, 5));
830 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
831 amdgpu_ring_write(kiq_ring
, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
832 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
833 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
834 PACKET3_MAP_QUEUES_QUEUE(ring
->queue
) |
835 PACKET3_MAP_QUEUES_PIPE(ring
->pipe
) |
836 PACKET3_MAP_QUEUES_ME((ring
->me
== 1 ? 0 : 1)) |
837 /*queue_type: normal compute queue */
838 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
839 /* alloc format: all_on_one_pipe */
840 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
841 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel
) |
842 /* num_queues: must be 1 */
843 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
844 amdgpu_ring_write(kiq_ring
,
845 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring
->doorbell_index
));
846 amdgpu_ring_write(kiq_ring
, lower_32_bits(mqd_addr
));
847 amdgpu_ring_write(kiq_ring
, upper_32_bits(mqd_addr
));
848 amdgpu_ring_write(kiq_ring
, lower_32_bits(wptr_addr
));
849 amdgpu_ring_write(kiq_ring
, upper_32_bits(wptr_addr
));
852 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring
*kiq_ring
,
853 struct amdgpu_ring
*ring
,
854 enum amdgpu_unmap_queues_action action
,
855 u64 gpu_addr
, u64 seq
)
857 uint32_t eng_sel
= ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
? 4 : 0;
859 amdgpu_ring_write(kiq_ring
, PACKET3(PACKET3_UNMAP_QUEUES
, 4));
860 amdgpu_ring_write(kiq_ring
, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
861 PACKET3_UNMAP_QUEUES_ACTION(action
) |
862 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
863 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel
) |
864 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
865 amdgpu_ring_write(kiq_ring
,
866 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring
->doorbell_index
));
868 if (action
== PREEMPT_QUEUES_NO_UNMAP
) {
869 amdgpu_ring_write(kiq_ring
, lower_32_bits(gpu_addr
));
870 amdgpu_ring_write(kiq_ring
, upper_32_bits(gpu_addr
));
871 amdgpu_ring_write(kiq_ring
, seq
);
873 amdgpu_ring_write(kiq_ring
, 0);
874 amdgpu_ring_write(kiq_ring
, 0);
875 amdgpu_ring_write(kiq_ring
, 0);
879 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring
*kiq_ring
,
880 struct amdgpu_ring
*ring
,
884 uint32_t eng_sel
= ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
? 4 : 0;
886 amdgpu_ring_write(kiq_ring
, PACKET3(PACKET3_QUERY_STATUS
, 5));
887 amdgpu_ring_write(kiq_ring
,
888 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
889 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
890 PACKET3_QUERY_STATUS_COMMAND(2));
891 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
892 amdgpu_ring_write(kiq_ring
,
893 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring
->doorbell_index
) |
894 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel
));
895 amdgpu_ring_write(kiq_ring
, lower_32_bits(addr
));
896 amdgpu_ring_write(kiq_ring
, upper_32_bits(addr
));
897 amdgpu_ring_write(kiq_ring
, lower_32_bits(seq
));
898 amdgpu_ring_write(kiq_ring
, upper_32_bits(seq
));
901 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring
*kiq_ring
,
902 uint16_t pasid
, uint32_t flush_type
,
905 amdgpu_ring_write(kiq_ring
, PACKET3(PACKET3_INVALIDATE_TLBS
, 0));
906 amdgpu_ring_write(kiq_ring
,
907 PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
908 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub
) |
909 PACKET3_INVALIDATE_TLBS_PASID(pasid
) |
910 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type
));
913 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs
= {
914 .kiq_set_resources
= gfx_v9_0_kiq_set_resources
,
915 .kiq_map_queues
= gfx_v9_0_kiq_map_queues
,
916 .kiq_unmap_queues
= gfx_v9_0_kiq_unmap_queues
,
917 .kiq_query_status
= gfx_v9_0_kiq_query_status
,
918 .kiq_invalidate_tlbs
= gfx_v9_0_kiq_invalidate_tlbs
,
919 .set_resources_size
= 8,
920 .map_queues_size
= 7,
921 .unmap_queues_size
= 6,
922 .query_status_size
= 7,
923 .invalidate_tlbs_size
= 2,
926 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device
*adev
)
928 adev
->gfx
.kiq
.pmf
= &gfx_v9_0_kiq_pm4_funcs
;
931 static void gfx_v9_0_init_golden_registers(struct amdgpu_device
*adev
)
933 switch (adev
->asic_type
) {
935 soc15_program_register_sequence(adev
,
936 golden_settings_gc_9_0
,
937 ARRAY_SIZE(golden_settings_gc_9_0
));
938 soc15_program_register_sequence(adev
,
939 golden_settings_gc_9_0_vg10
,
940 ARRAY_SIZE(golden_settings_gc_9_0_vg10
));
943 soc15_program_register_sequence(adev
,
944 golden_settings_gc_9_2_1
,
945 ARRAY_SIZE(golden_settings_gc_9_2_1
));
946 soc15_program_register_sequence(adev
,
947 golden_settings_gc_9_2_1_vg12
,
948 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12
));
951 soc15_program_register_sequence(adev
,
952 golden_settings_gc_9_0
,
953 ARRAY_SIZE(golden_settings_gc_9_0
));
954 soc15_program_register_sequence(adev
,
955 golden_settings_gc_9_0_vg20
,
956 ARRAY_SIZE(golden_settings_gc_9_0_vg20
));
959 soc15_program_register_sequence(adev
,
960 golden_settings_gc_9_4_1_arct
,
961 ARRAY_SIZE(golden_settings_gc_9_4_1_arct
));
964 soc15_program_register_sequence(adev
, golden_settings_gc_9_1
,
965 ARRAY_SIZE(golden_settings_gc_9_1
));
966 if (adev
->rev_id
>= 8)
967 soc15_program_register_sequence(adev
,
968 golden_settings_gc_9_1_rv2
,
969 ARRAY_SIZE(golden_settings_gc_9_1_rv2
));
971 soc15_program_register_sequence(adev
,
972 golden_settings_gc_9_1_rv1
,
973 ARRAY_SIZE(golden_settings_gc_9_1_rv1
));
976 soc15_program_register_sequence(adev
,
977 golden_settings_gc_9_1_rn
,
978 ARRAY_SIZE(golden_settings_gc_9_1_rn
));
979 return; /* for renoir, don't need common goldensetting */
984 if (adev
->asic_type
!= CHIP_ARCTURUS
)
985 soc15_program_register_sequence(adev
, golden_settings_gc_9_x_common
,
986 (const u32
)ARRAY_SIZE(golden_settings_gc_9_x_common
));
989 static void gfx_v9_0_scratch_init(struct amdgpu_device
*adev
)
991 adev
->gfx
.scratch
.num_reg
= 8;
992 adev
->gfx
.scratch
.reg_base
= SOC15_REG_OFFSET(GC
, 0, mmSCRATCH_REG0
);
993 adev
->gfx
.scratch
.free_mask
= (1u << adev
->gfx
.scratch
.num_reg
) - 1;
996 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring
*ring
, int eng_sel
,
997 bool wc
, uint32_t reg
, uint32_t val
)
999 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
1000 amdgpu_ring_write(ring
, WRITE_DATA_ENGINE_SEL(eng_sel
) |
1001 WRITE_DATA_DST_SEL(0) |
1002 (wc
? WR_CONFIRM
: 0));
1003 amdgpu_ring_write(ring
, reg
);
1004 amdgpu_ring_write(ring
, 0);
1005 amdgpu_ring_write(ring
, val
);
1008 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring
*ring
, int eng_sel
,
1009 int mem_space
, int opt
, uint32_t addr0
,
1010 uint32_t addr1
, uint32_t ref
, uint32_t mask
,
1013 amdgpu_ring_write(ring
, PACKET3(PACKET3_WAIT_REG_MEM
, 5));
1014 amdgpu_ring_write(ring
,
1015 /* memory (1) or register (0) */
1016 (WAIT_REG_MEM_MEM_SPACE(mem_space
) |
1017 WAIT_REG_MEM_OPERATION(opt
) | /* wait */
1018 WAIT_REG_MEM_FUNCTION(3) | /* equal */
1019 WAIT_REG_MEM_ENGINE(eng_sel
)));
1022 BUG_ON(addr0
& 0x3); /* Dword align */
1023 amdgpu_ring_write(ring
, addr0
);
1024 amdgpu_ring_write(ring
, addr1
);
1025 amdgpu_ring_write(ring
, ref
);
1026 amdgpu_ring_write(ring
, mask
);
1027 amdgpu_ring_write(ring
, inv
); /* poll interval */
1030 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring
*ring
)
1032 struct amdgpu_device
*adev
= ring
->adev
;
1038 r
= amdgpu_gfx_scratch_get(adev
, &scratch
);
1042 WREG32(scratch
, 0xCAFEDEAD);
1043 r
= amdgpu_ring_alloc(ring
, 3);
1045 goto error_free_scratch
;
1047 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_UCONFIG_REG
, 1));
1048 amdgpu_ring_write(ring
, (scratch
- PACKET3_SET_UCONFIG_REG_START
));
1049 amdgpu_ring_write(ring
, 0xDEADBEEF);
1050 amdgpu_ring_commit(ring
);
1052 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1053 tmp
= RREG32(scratch
);
1054 if (tmp
== 0xDEADBEEF)
1059 if (i
>= adev
->usec_timeout
)
1063 amdgpu_gfx_scratch_free(adev
, scratch
);
1067 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
1069 struct amdgpu_device
*adev
= ring
->adev
;
1070 struct amdgpu_ib ib
;
1071 struct dma_fence
*f
= NULL
;
1078 r
= amdgpu_device_wb_get(adev
, &index
);
1082 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
1083 adev
->wb
.wb
[index
] = cpu_to_le32(0xCAFEDEAD);
1084 memset(&ib
, 0, sizeof(ib
));
1085 r
= amdgpu_ib_get(adev
, NULL
, 16, &ib
);
1089 ib
.ptr
[0] = PACKET3(PACKET3_WRITE_DATA
, 3);
1090 ib
.ptr
[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM
;
1091 ib
.ptr
[2] = lower_32_bits(gpu_addr
);
1092 ib
.ptr
[3] = upper_32_bits(gpu_addr
);
1093 ib
.ptr
[4] = 0xDEADBEEF;
1096 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, &f
);
1100 r
= dma_fence_wait_timeout(f
, false, timeout
);
1108 tmp
= adev
->wb
.wb
[index
];
1109 if (tmp
== 0xDEADBEEF)
1115 amdgpu_ib_free(adev
, &ib
, NULL
);
1118 amdgpu_device_wb_free(adev
, index
);
1123 static void gfx_v9_0_free_microcode(struct amdgpu_device
*adev
)
1125 release_firmware(adev
->gfx
.pfp_fw
);
1126 adev
->gfx
.pfp_fw
= NULL
;
1127 release_firmware(adev
->gfx
.me_fw
);
1128 adev
->gfx
.me_fw
= NULL
;
1129 release_firmware(adev
->gfx
.ce_fw
);
1130 adev
->gfx
.ce_fw
= NULL
;
1131 release_firmware(adev
->gfx
.rlc_fw
);
1132 adev
->gfx
.rlc_fw
= NULL
;
1133 release_firmware(adev
->gfx
.mec_fw
);
1134 adev
->gfx
.mec_fw
= NULL
;
1135 release_firmware(adev
->gfx
.mec2_fw
);
1136 adev
->gfx
.mec2_fw
= NULL
;
1138 kfree(adev
->gfx
.rlc
.register_list_format
);
1141 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device
*adev
)
1143 const struct rlc_firmware_header_v2_1
*rlc_hdr
;
1145 rlc_hdr
= (const struct rlc_firmware_header_v2_1
*)adev
->gfx
.rlc_fw
->data
;
1146 adev
->gfx
.rlc_srlc_fw_version
= le32_to_cpu(rlc_hdr
->save_restore_list_cntl_ucode_ver
);
1147 adev
->gfx
.rlc_srlc_feature_version
= le32_to_cpu(rlc_hdr
->save_restore_list_cntl_feature_ver
);
1148 adev
->gfx
.rlc
.save_restore_list_cntl_size_bytes
= le32_to_cpu(rlc_hdr
->save_restore_list_cntl_size_bytes
);
1149 adev
->gfx
.rlc
.save_restore_list_cntl
= (u8
*)rlc_hdr
+ le32_to_cpu(rlc_hdr
->save_restore_list_cntl_offset_bytes
);
1150 adev
->gfx
.rlc_srlg_fw_version
= le32_to_cpu(rlc_hdr
->save_restore_list_gpm_ucode_ver
);
1151 adev
->gfx
.rlc_srlg_feature_version
= le32_to_cpu(rlc_hdr
->save_restore_list_gpm_feature_ver
);
1152 adev
->gfx
.rlc
.save_restore_list_gpm_size_bytes
= le32_to_cpu(rlc_hdr
->save_restore_list_gpm_size_bytes
);
1153 adev
->gfx
.rlc
.save_restore_list_gpm
= (u8
*)rlc_hdr
+ le32_to_cpu(rlc_hdr
->save_restore_list_gpm_offset_bytes
);
1154 adev
->gfx
.rlc_srls_fw_version
= le32_to_cpu(rlc_hdr
->save_restore_list_srm_ucode_ver
);
1155 adev
->gfx
.rlc_srls_feature_version
= le32_to_cpu(rlc_hdr
->save_restore_list_srm_feature_ver
);
1156 adev
->gfx
.rlc
.save_restore_list_srm_size_bytes
= le32_to_cpu(rlc_hdr
->save_restore_list_srm_size_bytes
);
1157 adev
->gfx
.rlc
.save_restore_list_srm
= (u8
*)rlc_hdr
+ le32_to_cpu(rlc_hdr
->save_restore_list_srm_offset_bytes
);
1158 adev
->gfx
.rlc
.reg_list_format_direct_reg_list_length
=
1159 le32_to_cpu(rlc_hdr
->reg_list_format_direct_reg_list_length
);
1162 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device
*adev
)
1164 adev
->gfx
.me_fw_write_wait
= false;
1165 adev
->gfx
.mec_fw_write_wait
= false;
1167 if ((adev
->asic_type
!= CHIP_ARCTURUS
) &&
1168 ((adev
->gfx
.mec_fw_version
< 0x000001a5) ||
1169 (adev
->gfx
.mec_feature_version
< 46) ||
1170 (adev
->gfx
.pfp_fw_version
< 0x000000b7) ||
1171 (adev
->gfx
.pfp_feature_version
< 46)))
1172 DRM_WARN_ONCE("CP firmware version too old, please update!");
1174 switch (adev
->asic_type
) {
1176 if ((adev
->gfx
.me_fw_version
>= 0x0000009c) &&
1177 (adev
->gfx
.me_feature_version
>= 42) &&
1178 (adev
->gfx
.pfp_fw_version
>= 0x000000b1) &&
1179 (adev
->gfx
.pfp_feature_version
>= 42))
1180 adev
->gfx
.me_fw_write_wait
= true;
1182 if ((adev
->gfx
.mec_fw_version
>= 0x00000193) &&
1183 (adev
->gfx
.mec_feature_version
>= 42))
1184 adev
->gfx
.mec_fw_write_wait
= true;
1187 if ((adev
->gfx
.me_fw_version
>= 0x0000009c) &&
1188 (adev
->gfx
.me_feature_version
>= 44) &&
1189 (adev
->gfx
.pfp_fw_version
>= 0x000000b2) &&
1190 (adev
->gfx
.pfp_feature_version
>= 44))
1191 adev
->gfx
.me_fw_write_wait
= true;
1193 if ((adev
->gfx
.mec_fw_version
>= 0x00000196) &&
1194 (adev
->gfx
.mec_feature_version
>= 44))
1195 adev
->gfx
.mec_fw_write_wait
= true;
1198 if ((adev
->gfx
.me_fw_version
>= 0x0000009c) &&
1199 (adev
->gfx
.me_feature_version
>= 44) &&
1200 (adev
->gfx
.pfp_fw_version
>= 0x000000b2) &&
1201 (adev
->gfx
.pfp_feature_version
>= 44))
1202 adev
->gfx
.me_fw_write_wait
= true;
1204 if ((adev
->gfx
.mec_fw_version
>= 0x00000197) &&
1205 (adev
->gfx
.mec_feature_version
>= 44))
1206 adev
->gfx
.mec_fw_write_wait
= true;
1209 if ((adev
->gfx
.me_fw_version
>= 0x0000009c) &&
1210 (adev
->gfx
.me_feature_version
>= 42) &&
1211 (adev
->gfx
.pfp_fw_version
>= 0x000000b1) &&
1212 (adev
->gfx
.pfp_feature_version
>= 42))
1213 adev
->gfx
.me_fw_write_wait
= true;
1215 if ((adev
->gfx
.mec_fw_version
>= 0x00000192) &&
1216 (adev
->gfx
.mec_feature_version
>= 42))
1217 adev
->gfx
.mec_fw_write_wait
= true;
1220 adev
->gfx
.me_fw_write_wait
= true;
1221 adev
->gfx
.mec_fw_write_wait
= true;
1226 struct amdgpu_gfxoff_quirk
{
1234 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list
[] = {
1235 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */
1236 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1237 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */
1238 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 },
1239 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */
1240 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },
1244 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev
*pdev
)
1246 const struct amdgpu_gfxoff_quirk
*p
= amdgpu_gfxoff_quirk_list
;
1248 while (p
&& p
->chip_device
!= 0) {
1249 if (pdev
->vendor
== p
->chip_vendor
&&
1250 pdev
->device
== p
->chip_device
&&
1251 pdev
->subsystem_vendor
== p
->subsys_vendor
&&
1252 pdev
->subsystem_device
== p
->subsys_device
&&
1253 pdev
->revision
== p
->revision
) {
1261 static bool is_raven_kicker(struct amdgpu_device
*adev
)
1263 if (adev
->pm
.fw_version
>= 0x41e2b)
1269 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device
*adev
)
1271 if (gfx_v9_0_should_disable_gfxoff(adev
->pdev
))
1272 adev
->pm
.pp_feature
&= ~PP_GFXOFF_MASK
;
1274 switch (adev
->asic_type
) {
1280 if (!(adev
->rev_id
>= 0x8 || adev
->pdev
->device
== 0x15d8) &&
1281 ((!is_raven_kicker(adev
) &&
1282 adev
->gfx
.rlc_fw_version
< 531) ||
1283 (adev
->gfx
.rlc_feature_version
< 1) ||
1284 !adev
->gfx
.rlc
.is_rlc_v2_1
))
1285 adev
->pm
.pp_feature
&= ~PP_GFXOFF_MASK
;
1287 if (adev
->pm
.pp_feature
& PP_GFXOFF_MASK
)
1288 adev
->pg_flags
|= AMD_PG_SUPPORT_GFX_PG
|
1290 AMD_PG_SUPPORT_RLC_SMU_HS
;
1293 if (adev
->pm
.pp_feature
& PP_GFXOFF_MASK
)
1294 adev
->pg_flags
|= AMD_PG_SUPPORT_GFX_PG
|
1296 AMD_PG_SUPPORT_RLC_SMU_HS
;
1303 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device
*adev
,
1304 const char *chip_name
)
1308 struct amdgpu_firmware_info
*info
= NULL
;
1309 const struct common_firmware_header
*header
= NULL
;
1310 const struct gfx_firmware_header_v1_0
*cp_hdr
;
1312 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_pfp.bin", chip_name
);
1313 err
= request_firmware(&adev
->gfx
.pfp_fw
, fw_name
, adev
->dev
);
1316 err
= amdgpu_ucode_validate(adev
->gfx
.pfp_fw
);
1319 cp_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.pfp_fw
->data
;
1320 adev
->gfx
.pfp_fw_version
= le32_to_cpu(cp_hdr
->header
.ucode_version
);
1321 adev
->gfx
.pfp_feature_version
= le32_to_cpu(cp_hdr
->ucode_feature_version
);
1323 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_me.bin", chip_name
);
1324 err
= request_firmware(&adev
->gfx
.me_fw
, fw_name
, adev
->dev
);
1327 err
= amdgpu_ucode_validate(adev
->gfx
.me_fw
);
1330 cp_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.me_fw
->data
;
1331 adev
->gfx
.me_fw_version
= le32_to_cpu(cp_hdr
->header
.ucode_version
);
1332 adev
->gfx
.me_feature_version
= le32_to_cpu(cp_hdr
->ucode_feature_version
);
1334 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_ce.bin", chip_name
);
1335 err
= request_firmware(&adev
->gfx
.ce_fw
, fw_name
, adev
->dev
);
1338 err
= amdgpu_ucode_validate(adev
->gfx
.ce_fw
);
1341 cp_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.ce_fw
->data
;
1342 adev
->gfx
.ce_fw_version
= le32_to_cpu(cp_hdr
->header
.ucode_version
);
1343 adev
->gfx
.ce_feature_version
= le32_to_cpu(cp_hdr
->ucode_feature_version
);
1345 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
) {
1346 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_CP_PFP
];
1347 info
->ucode_id
= AMDGPU_UCODE_ID_CP_PFP
;
1348 info
->fw
= adev
->gfx
.pfp_fw
;
1349 header
= (const struct common_firmware_header
*)info
->fw
->data
;
1350 adev
->firmware
.fw_size
+=
1351 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
1353 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_CP_ME
];
1354 info
->ucode_id
= AMDGPU_UCODE_ID_CP_ME
;
1355 info
->fw
= adev
->gfx
.me_fw
;
1356 header
= (const struct common_firmware_header
*)info
->fw
->data
;
1357 adev
->firmware
.fw_size
+=
1358 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
1360 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_CP_CE
];
1361 info
->ucode_id
= AMDGPU_UCODE_ID_CP_CE
;
1362 info
->fw
= adev
->gfx
.ce_fw
;
1363 header
= (const struct common_firmware_header
*)info
->fw
->data
;
1364 adev
->firmware
.fw_size
+=
1365 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
1371 "gfx9: Failed to load firmware \"%s\"\n",
1373 release_firmware(adev
->gfx
.pfp_fw
);
1374 adev
->gfx
.pfp_fw
= NULL
;
1375 release_firmware(adev
->gfx
.me_fw
);
1376 adev
->gfx
.me_fw
= NULL
;
1377 release_firmware(adev
->gfx
.ce_fw
);
1378 adev
->gfx
.ce_fw
= NULL
;
1383 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device
*adev
,
1384 const char *chip_name
)
1388 struct amdgpu_firmware_info
*info
= NULL
;
1389 const struct common_firmware_header
*header
= NULL
;
1390 const struct rlc_firmware_header_v2_0
*rlc_hdr
;
1391 unsigned int *tmp
= NULL
;
1393 uint16_t version_major
;
1394 uint16_t version_minor
;
1395 uint32_t smu_version
;
1398 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
1399 * instead of picasso_rlc.bin.
1401 * PCO AM4: revision >= 0xC8 && revision <= 0xCF
1402 * or revision >= 0xD8 && revision <= 0xDF
1403 * otherwise is PCO FP5
1405 if (!strcmp(chip_name
, "picasso") &&
1406 (((adev
->pdev
->revision
>= 0xC8) && (adev
->pdev
->revision
<= 0xCF)) ||
1407 ((adev
->pdev
->revision
>= 0xD8) && (adev
->pdev
->revision
<= 0xDF))))
1408 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_rlc_am4.bin", chip_name
);
1409 else if (!strcmp(chip_name
, "raven") && (amdgpu_pm_load_smu_firmware(adev
, &smu_version
) == 0) &&
1410 (smu_version
>= 0x41e2b))
1412 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly.
1414 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_kicker_rlc.bin", chip_name
);
1416 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_rlc.bin", chip_name
);
1417 err
= request_firmware(&adev
->gfx
.rlc_fw
, fw_name
, adev
->dev
);
1420 err
= amdgpu_ucode_validate(adev
->gfx
.rlc_fw
);
1421 rlc_hdr
= (const struct rlc_firmware_header_v2_0
*)adev
->gfx
.rlc_fw
->data
;
1423 version_major
= le16_to_cpu(rlc_hdr
->header
.header_version_major
);
1424 version_minor
= le16_to_cpu(rlc_hdr
->header
.header_version_minor
);
1425 if (version_major
== 2 && version_minor
== 1)
1426 adev
->gfx
.rlc
.is_rlc_v2_1
= true;
1428 adev
->gfx
.rlc_fw_version
= le32_to_cpu(rlc_hdr
->header
.ucode_version
);
1429 adev
->gfx
.rlc_feature_version
= le32_to_cpu(rlc_hdr
->ucode_feature_version
);
1430 adev
->gfx
.rlc
.save_and_restore_offset
=
1431 le32_to_cpu(rlc_hdr
->save_and_restore_offset
);
1432 adev
->gfx
.rlc
.clear_state_descriptor_offset
=
1433 le32_to_cpu(rlc_hdr
->clear_state_descriptor_offset
);
1434 adev
->gfx
.rlc
.avail_scratch_ram_locations
=
1435 le32_to_cpu(rlc_hdr
->avail_scratch_ram_locations
);
1436 adev
->gfx
.rlc
.reg_restore_list_size
=
1437 le32_to_cpu(rlc_hdr
->reg_restore_list_size
);
1438 adev
->gfx
.rlc
.reg_list_format_start
=
1439 le32_to_cpu(rlc_hdr
->reg_list_format_start
);
1440 adev
->gfx
.rlc
.reg_list_format_separate_start
=
1441 le32_to_cpu(rlc_hdr
->reg_list_format_separate_start
);
1442 adev
->gfx
.rlc
.starting_offsets_start
=
1443 le32_to_cpu(rlc_hdr
->starting_offsets_start
);
1444 adev
->gfx
.rlc
.reg_list_format_size_bytes
=
1445 le32_to_cpu(rlc_hdr
->reg_list_format_size_bytes
);
1446 adev
->gfx
.rlc
.reg_list_size_bytes
=
1447 le32_to_cpu(rlc_hdr
->reg_list_size_bytes
);
1448 adev
->gfx
.rlc
.register_list_format
=
1449 kmalloc(adev
->gfx
.rlc
.reg_list_format_size_bytes
+
1450 adev
->gfx
.rlc
.reg_list_size_bytes
, GFP_KERNEL
);
1451 if (!adev
->gfx
.rlc
.register_list_format
) {
1456 tmp
= (unsigned int *)((uintptr_t)rlc_hdr
+
1457 le32_to_cpu(rlc_hdr
->reg_list_format_array_offset_bytes
));
1458 for (i
= 0 ; i
< (adev
->gfx
.rlc
.reg_list_format_size_bytes
>> 2); i
++)
1459 adev
->gfx
.rlc
.register_list_format
[i
] = le32_to_cpu(tmp
[i
]);
1461 adev
->gfx
.rlc
.register_restore
= adev
->gfx
.rlc
.register_list_format
+ i
;
1463 tmp
= (unsigned int *)((uintptr_t)rlc_hdr
+
1464 le32_to_cpu(rlc_hdr
->reg_list_array_offset_bytes
));
1465 for (i
= 0 ; i
< (adev
->gfx
.rlc
.reg_list_size_bytes
>> 2); i
++)
1466 adev
->gfx
.rlc
.register_restore
[i
] = le32_to_cpu(tmp
[i
]);
1468 if (adev
->gfx
.rlc
.is_rlc_v2_1
)
1469 gfx_v9_0_init_rlc_ext_microcode(adev
);
1471 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
) {
1472 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_RLC_G
];
1473 info
->ucode_id
= AMDGPU_UCODE_ID_RLC_G
;
1474 info
->fw
= adev
->gfx
.rlc_fw
;
1475 header
= (const struct common_firmware_header
*)info
->fw
->data
;
1476 adev
->firmware
.fw_size
+=
1477 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
1479 if (adev
->gfx
.rlc
.is_rlc_v2_1
&&
1480 adev
->gfx
.rlc
.save_restore_list_cntl_size_bytes
&&
1481 adev
->gfx
.rlc
.save_restore_list_gpm_size_bytes
&&
1482 adev
->gfx
.rlc
.save_restore_list_srm_size_bytes
) {
1483 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
];
1484 info
->ucode_id
= AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
;
1485 info
->fw
= adev
->gfx
.rlc_fw
;
1486 adev
->firmware
.fw_size
+=
1487 ALIGN(adev
->gfx
.rlc
.save_restore_list_cntl_size_bytes
, PAGE_SIZE
);
1489 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
];
1490 info
->ucode_id
= AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
;
1491 info
->fw
= adev
->gfx
.rlc_fw
;
1492 adev
->firmware
.fw_size
+=
1493 ALIGN(adev
->gfx
.rlc
.save_restore_list_gpm_size_bytes
, PAGE_SIZE
);
1495 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
];
1496 info
->ucode_id
= AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
;
1497 info
->fw
= adev
->gfx
.rlc_fw
;
1498 adev
->firmware
.fw_size
+=
1499 ALIGN(adev
->gfx
.rlc
.save_restore_list_srm_size_bytes
, PAGE_SIZE
);
1506 "gfx9: Failed to load firmware \"%s\"\n",
1508 release_firmware(adev
->gfx
.rlc_fw
);
1509 adev
->gfx
.rlc_fw
= NULL
;
1514 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device
*adev
,
1515 const char *chip_name
)
1519 struct amdgpu_firmware_info
*info
= NULL
;
1520 const struct common_firmware_header
*header
= NULL
;
1521 const struct gfx_firmware_header_v1_0
*cp_hdr
;
1523 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_mec.bin", chip_name
);
1524 err
= request_firmware(&adev
->gfx
.mec_fw
, fw_name
, adev
->dev
);
1527 err
= amdgpu_ucode_validate(adev
->gfx
.mec_fw
);
1530 cp_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec_fw
->data
;
1531 adev
->gfx
.mec_fw_version
= le32_to_cpu(cp_hdr
->header
.ucode_version
);
1532 adev
->gfx
.mec_feature_version
= le32_to_cpu(cp_hdr
->ucode_feature_version
);
1535 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_mec2.bin", chip_name
);
1536 err
= request_firmware(&adev
->gfx
.mec2_fw
, fw_name
, adev
->dev
);
1538 err
= amdgpu_ucode_validate(adev
->gfx
.mec2_fw
);
1541 cp_hdr
= (const struct gfx_firmware_header_v1_0
*)
1542 adev
->gfx
.mec2_fw
->data
;
1543 adev
->gfx
.mec2_fw_version
=
1544 le32_to_cpu(cp_hdr
->header
.ucode_version
);
1545 adev
->gfx
.mec2_feature_version
=
1546 le32_to_cpu(cp_hdr
->ucode_feature_version
);
1549 adev
->gfx
.mec2_fw
= NULL
;
1552 if (adev
->firmware
.load_type
== AMDGPU_FW_LOAD_PSP
) {
1553 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_CP_MEC1
];
1554 info
->ucode_id
= AMDGPU_UCODE_ID_CP_MEC1
;
1555 info
->fw
= adev
->gfx
.mec_fw
;
1556 header
= (const struct common_firmware_header
*)info
->fw
->data
;
1557 cp_hdr
= (const struct gfx_firmware_header_v1_0
*)info
->fw
->data
;
1558 adev
->firmware
.fw_size
+=
1559 ALIGN(le32_to_cpu(header
->ucode_size_bytes
) - le32_to_cpu(cp_hdr
->jt_size
) * 4, PAGE_SIZE
);
1561 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_CP_MEC1_JT
];
1562 info
->ucode_id
= AMDGPU_UCODE_ID_CP_MEC1_JT
;
1563 info
->fw
= adev
->gfx
.mec_fw
;
1564 adev
->firmware
.fw_size
+=
1565 ALIGN(le32_to_cpu(cp_hdr
->jt_size
) * 4, PAGE_SIZE
);
1567 if (adev
->gfx
.mec2_fw
) {
1568 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_CP_MEC2
];
1569 info
->ucode_id
= AMDGPU_UCODE_ID_CP_MEC2
;
1570 info
->fw
= adev
->gfx
.mec2_fw
;
1571 header
= (const struct common_firmware_header
*)info
->fw
->data
;
1572 cp_hdr
= (const struct gfx_firmware_header_v1_0
*)info
->fw
->data
;
1573 adev
->firmware
.fw_size
+=
1574 ALIGN(le32_to_cpu(header
->ucode_size_bytes
) - le32_to_cpu(cp_hdr
->jt_size
) * 4, PAGE_SIZE
);
1576 /* TODO: Determine if MEC2 JT FW loading can be removed
1577 for all GFX V9 asic and above */
1578 if (adev
->asic_type
!= CHIP_ARCTURUS
&&
1579 adev
->asic_type
!= CHIP_RENOIR
) {
1580 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_CP_MEC2_JT
];
1581 info
->ucode_id
= AMDGPU_UCODE_ID_CP_MEC2_JT
;
1582 info
->fw
= adev
->gfx
.mec2_fw
;
1583 adev
->firmware
.fw_size
+=
1584 ALIGN(le32_to_cpu(cp_hdr
->jt_size
) * 4,
1591 gfx_v9_0_check_if_need_gfxoff(adev
);
1592 gfx_v9_0_check_fw_write_wait(adev
);
1595 "gfx9: Failed to load firmware \"%s\"\n",
1597 release_firmware(adev
->gfx
.mec_fw
);
1598 adev
->gfx
.mec_fw
= NULL
;
1599 release_firmware(adev
->gfx
.mec2_fw
);
1600 adev
->gfx
.mec2_fw
= NULL
;
1605 static int gfx_v9_0_init_microcode(struct amdgpu_device
*adev
)
1607 const char *chip_name
;
1612 switch (adev
->asic_type
) {
1614 chip_name
= "vega10";
1617 chip_name
= "vega12";
1620 chip_name
= "vega20";
1623 if (adev
->rev_id
>= 8)
1624 chip_name
= "raven2";
1625 else if (adev
->pdev
->device
== 0x15d8)
1626 chip_name
= "picasso";
1628 chip_name
= "raven";
1631 chip_name
= "arcturus";
1634 chip_name
= "renoir";
1640 /* No CPG in Arcturus */
1641 if (adev
->asic_type
!= CHIP_ARCTURUS
) {
1642 r
= gfx_v9_0_init_cp_gfx_microcode(adev
, chip_name
);
1647 r
= gfx_v9_0_init_rlc_microcode(adev
, chip_name
);
1651 r
= gfx_v9_0_init_cp_compute_microcode(adev
, chip_name
);
1658 static u32
gfx_v9_0_get_csb_size(struct amdgpu_device
*adev
)
1661 const struct cs_section_def
*sect
= NULL
;
1662 const struct cs_extent_def
*ext
= NULL
;
1664 /* begin clear state */
1666 /* context control state */
1669 for (sect
= gfx9_cs_data
; sect
->section
!= NULL
; ++sect
) {
1670 for (ext
= sect
->section
; ext
->extent
!= NULL
; ++ext
) {
1671 if (sect
->id
== SECT_CONTEXT
)
1672 count
+= 2 + ext
->reg_count
;
1678 /* end clear state */
1686 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device
*adev
,
1687 volatile u32
*buffer
)
1690 const struct cs_section_def
*sect
= NULL
;
1691 const struct cs_extent_def
*ext
= NULL
;
1693 if (adev
->gfx
.rlc
.cs_data
== NULL
)
1698 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1699 buffer
[count
++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1701 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL
, 1));
1702 buffer
[count
++] = cpu_to_le32(0x80000000);
1703 buffer
[count
++] = cpu_to_le32(0x80000000);
1705 for (sect
= adev
->gfx
.rlc
.cs_data
; sect
->section
!= NULL
; ++sect
) {
1706 for (ext
= sect
->section
; ext
->extent
!= NULL
; ++ext
) {
1707 if (sect
->id
== SECT_CONTEXT
) {
1709 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG
, ext
->reg_count
));
1710 buffer
[count
++] = cpu_to_le32(ext
->reg_index
-
1711 PACKET3_SET_CONTEXT_REG_START
);
1712 for (i
= 0; i
< ext
->reg_count
; i
++)
1713 buffer
[count
++] = cpu_to_le32(ext
->extent
[i
]);
1720 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1721 buffer
[count
++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE
);
1723 buffer
[count
++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE
, 0));
1724 buffer
[count
++] = cpu_to_le32(0);
1727 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device
*adev
)
1729 struct amdgpu_cu_info
*cu_info
= &adev
->gfx
.cu_info
;
1730 uint32_t pg_always_on_cu_num
= 2;
1731 uint32_t always_on_cu_num
;
1733 uint32_t mask
, cu_bitmap
, counter
;
1735 if (adev
->flags
& AMD_IS_APU
)
1736 always_on_cu_num
= 4;
1737 else if (adev
->asic_type
== CHIP_VEGA12
)
1738 always_on_cu_num
= 8;
1740 always_on_cu_num
= 12;
1742 mutex_lock(&adev
->grbm_idx_mutex
);
1743 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
1744 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
1748 gfx_v9_0_select_se_sh(adev
, i
, j
, 0xffffffff);
1750 for (k
= 0; k
< adev
->gfx
.config
.max_cu_per_sh
; k
++) {
1751 if (cu_info
->bitmap
[i
][j
] & mask
) {
1752 if (counter
== pg_always_on_cu_num
)
1753 WREG32_SOC15(GC
, 0, mmRLC_PG_ALWAYS_ON_CU_MASK
, cu_bitmap
);
1754 if (counter
< always_on_cu_num
)
1763 WREG32_SOC15(GC
, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK
, cu_bitmap
);
1764 cu_info
->ao_cu_bitmap
[i
][j
] = cu_bitmap
;
1767 gfx_v9_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1768 mutex_unlock(&adev
->grbm_idx_mutex
);
1771 static void gfx_v9_0_init_lbpw(struct amdgpu_device
*adev
)
1775 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1776 WREG32_SOC15(GC
, 0, mmRLC_LB_THR_CONFIG_1
, 0x0000007F);
1777 WREG32_SOC15(GC
, 0, mmRLC_LB_THR_CONFIG_2
, 0x0333A5A7);
1778 WREG32_SOC15(GC
, 0, mmRLC_LB_THR_CONFIG_3
, 0x00000077);
1779 WREG32_SOC15(GC
, 0, mmRLC_LB_THR_CONFIG_4
, (0x30 | 0x40 << 8 | 0x02FA << 16));
1781 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1782 WREG32_SOC15(GC
, 0, mmRLC_LB_CNTR_INIT
, 0x00000000);
1784 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1785 WREG32_SOC15(GC
, 0, mmRLC_LB_CNTR_MAX
, 0x00000500);
1787 mutex_lock(&adev
->grbm_idx_mutex
);
1788 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1789 gfx_v9_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1790 WREG32_SOC15(GC
, 0, mmRLC_LB_INIT_CU_MASK
, 0xffffffff);
1792 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1793 data
= REG_SET_FIELD(0, RLC_LB_PARAMS
, FIFO_SAMPLES
, 0x0003);
1794 data
|= REG_SET_FIELD(data
, RLC_LB_PARAMS
, PG_IDLE_SAMPLES
, 0x0010);
1795 data
|= REG_SET_FIELD(data
, RLC_LB_PARAMS
, PG_IDLE_SAMPLE_INTERVAL
, 0x033F);
1796 WREG32_SOC15(GC
, 0, mmRLC_LB_PARAMS
, data
);
1798 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1799 data
= RREG32_SOC15(GC
, 0, mmRLC_GPM_GENERAL_7
);
1802 WREG32_SOC15(GC
, 0, mmRLC_GPM_GENERAL_7
, data
);
1805 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven),
1806 * programmed in gfx_v9_0_init_always_on_cu_mask()
1809 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1810 * but used for RLC_LB_CNTL configuration */
1811 data
= RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK
;
1812 data
|= REG_SET_FIELD(data
, RLC_LB_CNTL
, CU_MASK_USED_OFF_HYST
, 0x09);
1813 data
|= REG_SET_FIELD(data
, RLC_LB_CNTL
, RESERVED
, 0x80000);
1814 WREG32_SOC15(GC
, 0, mmRLC_LB_CNTL
, data
);
1815 mutex_unlock(&adev
->grbm_idx_mutex
);
1817 gfx_v9_0_init_always_on_cu_mask(adev
);
1820 static void gfx_v9_4_init_lbpw(struct amdgpu_device
*adev
)
1824 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1825 WREG32_SOC15(GC
, 0, mmRLC_LB_THR_CONFIG_1
, 0x0000007F);
1826 WREG32_SOC15(GC
, 0, mmRLC_LB_THR_CONFIG_2
, 0x033388F8);
1827 WREG32_SOC15(GC
, 0, mmRLC_LB_THR_CONFIG_3
, 0x00000077);
1828 WREG32_SOC15(GC
, 0, mmRLC_LB_THR_CONFIG_4
, (0x10 | 0x27 << 8 | 0x02FA << 16));
1830 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1831 WREG32_SOC15(GC
, 0, mmRLC_LB_CNTR_INIT
, 0x00000000);
1833 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1834 WREG32_SOC15(GC
, 0, mmRLC_LB_CNTR_MAX
, 0x00000800);
1836 mutex_lock(&adev
->grbm_idx_mutex
);
1837 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1838 gfx_v9_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
1839 WREG32_SOC15(GC
, 0, mmRLC_LB_INIT_CU_MASK
, 0xffffffff);
1841 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1842 data
= REG_SET_FIELD(0, RLC_LB_PARAMS
, FIFO_SAMPLES
, 0x0003);
1843 data
|= REG_SET_FIELD(data
, RLC_LB_PARAMS
, PG_IDLE_SAMPLES
, 0x0010);
1844 data
|= REG_SET_FIELD(data
, RLC_LB_PARAMS
, PG_IDLE_SAMPLE_INTERVAL
, 0x033F);
1845 WREG32_SOC15(GC
, 0, mmRLC_LB_PARAMS
, data
);
1847 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1848 data
= RREG32_SOC15(GC
, 0, mmRLC_GPM_GENERAL_7
);
1851 WREG32_SOC15(GC
, 0, mmRLC_GPM_GENERAL_7
, data
);
1854 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON),
1855 * programmed in gfx_v9_0_init_always_on_cu_mask()
1858 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1859 * but used for RLC_LB_CNTL configuration */
1860 data
= RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK
;
1861 data
|= REG_SET_FIELD(data
, RLC_LB_CNTL
, CU_MASK_USED_OFF_HYST
, 0x09);
1862 data
|= REG_SET_FIELD(data
, RLC_LB_CNTL
, RESERVED
, 0x80000);
1863 WREG32_SOC15(GC
, 0, mmRLC_LB_CNTL
, data
);
1864 mutex_unlock(&adev
->grbm_idx_mutex
);
1866 gfx_v9_0_init_always_on_cu_mask(adev
);
1869 static void gfx_v9_0_enable_lbpw(struct amdgpu_device
*adev
, bool enable
)
1871 WREG32_FIELD15(GC
, 0, RLC_LB_CNTL
, LOAD_BALANCE_ENABLE
, enable
? 1 : 0);
1874 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device
*adev
)
1879 static int gfx_v9_0_rlc_init(struct amdgpu_device
*adev
)
1881 const struct cs_section_def
*cs_data
;
1884 adev
->gfx
.rlc
.cs_data
= gfx9_cs_data
;
1886 cs_data
= adev
->gfx
.rlc
.cs_data
;
1889 /* init clear state block */
1890 r
= amdgpu_gfx_rlc_init_csb(adev
);
1895 if (adev
->asic_type
== CHIP_RAVEN
|| adev
->asic_type
== CHIP_RENOIR
) {
1896 /* TODO: double check the cp_table_size for RV */
1897 adev
->gfx
.rlc
.cp_table_size
= ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1898 r
= amdgpu_gfx_rlc_init_cpt(adev
);
1903 switch (adev
->asic_type
) {
1905 gfx_v9_0_init_lbpw(adev
);
1908 gfx_v9_4_init_lbpw(adev
);
1914 /* init spm vmid with 0xf */
1915 if (adev
->gfx
.rlc
.funcs
->update_spm_vmid
)
1916 adev
->gfx
.rlc
.funcs
->update_spm_vmid(adev
, 0xf);
1921 static void gfx_v9_0_mec_fini(struct amdgpu_device
*adev
)
1923 amdgpu_bo_free_kernel(&adev
->gfx
.mec
.hpd_eop_obj
, NULL
, NULL
);
1924 amdgpu_bo_free_kernel(&adev
->gfx
.mec
.mec_fw_obj
, NULL
, NULL
);
1927 static int gfx_v9_0_mec_init(struct amdgpu_device
*adev
)
1931 const __le32
*fw_data
;
1934 size_t mec_hpd_size
;
1936 const struct gfx_firmware_header_v1_0
*mec_hdr
;
1938 bitmap_zero(adev
->gfx
.mec
.queue_bitmap
, AMDGPU_MAX_COMPUTE_QUEUES
);
1940 /* take ownership of the relevant compute queues */
1941 amdgpu_gfx_compute_queue_acquire(adev
);
1942 mec_hpd_size
= adev
->gfx
.num_compute_rings
* GFX9_MEC_HPD_SIZE
;
1944 r
= amdgpu_bo_create_reserved(adev
, mec_hpd_size
, PAGE_SIZE
,
1945 AMDGPU_GEM_DOMAIN_VRAM
,
1946 &adev
->gfx
.mec
.hpd_eop_obj
,
1947 &adev
->gfx
.mec
.hpd_eop_gpu_addr
,
1950 dev_warn(adev
->dev
, "(%d) create HDP EOP bo failed\n", r
);
1951 gfx_v9_0_mec_fini(adev
);
1955 memset(hpd
, 0, mec_hpd_size
);
1957 amdgpu_bo_kunmap(adev
->gfx
.mec
.hpd_eop_obj
);
1958 amdgpu_bo_unreserve(adev
->gfx
.mec
.hpd_eop_obj
);
1960 mec_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec_fw
->data
;
1962 fw_data
= (const __le32
*)
1963 (adev
->gfx
.mec_fw
->data
+
1964 le32_to_cpu(mec_hdr
->header
.ucode_array_offset_bytes
));
1965 fw_size
= le32_to_cpu(mec_hdr
->header
.ucode_size_bytes
) / 4;
1967 r
= amdgpu_bo_create_reserved(adev
, mec_hdr
->header
.ucode_size_bytes
,
1968 PAGE_SIZE
, AMDGPU_GEM_DOMAIN_GTT
,
1969 &adev
->gfx
.mec
.mec_fw_obj
,
1970 &adev
->gfx
.mec
.mec_fw_gpu_addr
,
1973 dev_warn(adev
->dev
, "(%d) create mec firmware bo failed\n", r
);
1974 gfx_v9_0_mec_fini(adev
);
1978 memcpy(fw
, fw_data
, fw_size
);
1980 amdgpu_bo_kunmap(adev
->gfx
.mec
.mec_fw_obj
);
1981 amdgpu_bo_unreserve(adev
->gfx
.mec
.mec_fw_obj
);
1986 static uint32_t wave_read_ind(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t address
)
1988 WREG32_SOC15_RLC(GC
, 0, mmSQ_IND_INDEX
,
1989 (wave
<< SQ_IND_INDEX__WAVE_ID__SHIFT
) |
1990 (simd
<< SQ_IND_INDEX__SIMD_ID__SHIFT
) |
1991 (address
<< SQ_IND_INDEX__INDEX__SHIFT
) |
1992 (SQ_IND_INDEX__FORCE_READ_MASK
));
1993 return RREG32_SOC15(GC
, 0, mmSQ_IND_DATA
);
1996 static void wave_read_regs(struct amdgpu_device
*adev
, uint32_t simd
,
1997 uint32_t wave
, uint32_t thread
,
1998 uint32_t regno
, uint32_t num
, uint32_t *out
)
2000 WREG32_SOC15_RLC(GC
, 0, mmSQ_IND_INDEX
,
2001 (wave
<< SQ_IND_INDEX__WAVE_ID__SHIFT
) |
2002 (simd
<< SQ_IND_INDEX__SIMD_ID__SHIFT
) |
2003 (regno
<< SQ_IND_INDEX__INDEX__SHIFT
) |
2004 (thread
<< SQ_IND_INDEX__THREAD_ID__SHIFT
) |
2005 (SQ_IND_INDEX__FORCE_READ_MASK
) |
2006 (SQ_IND_INDEX__AUTO_INCR_MASK
));
2008 *(out
++) = RREG32_SOC15(GC
, 0, mmSQ_IND_DATA
);
2011 static void gfx_v9_0_read_wave_data(struct amdgpu_device
*adev
, uint32_t simd
, uint32_t wave
, uint32_t *dst
, int *no_fields
)
2013 /* type 1 wave data */
2014 dst
[(*no_fields
)++] = 1;
2015 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_STATUS
);
2016 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_PC_LO
);
2017 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_PC_HI
);
2018 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_EXEC_LO
);
2019 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_EXEC_HI
);
2020 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_HW_ID
);
2021 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_INST_DW0
);
2022 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_INST_DW1
);
2023 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_GPR_ALLOC
);
2024 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_LDS_ALLOC
);
2025 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_TRAPSTS
);
2026 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_IB_STS
);
2027 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_IB_DBG0
);
2028 dst
[(*no_fields
)++] = wave_read_ind(adev
, simd
, wave
, ixSQ_WAVE_M0
);
2031 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device
*adev
, uint32_t simd
,
2032 uint32_t wave
, uint32_t start
,
2033 uint32_t size
, uint32_t *dst
)
2036 adev
, simd
, wave
, 0,
2037 start
+ SQIND_WAVE_SGPRS_OFFSET
, size
, dst
);
2040 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device
*adev
, uint32_t simd
,
2041 uint32_t wave
, uint32_t thread
,
2042 uint32_t start
, uint32_t size
,
2046 adev
, simd
, wave
, thread
,
2047 start
+ SQIND_WAVE_VGPRS_OFFSET
, size
, dst
);
2050 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device
*adev
,
2051 u32 me
, u32 pipe
, u32 q
, u32 vm
)
2053 soc15_grbm_select(adev
, me
, pipe
, q
, vm
);
2056 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs
= {
2057 .get_gpu_clock_counter
= &gfx_v9_0_get_gpu_clock_counter
,
2058 .select_se_sh
= &gfx_v9_0_select_se_sh
,
2059 .read_wave_data
= &gfx_v9_0_read_wave_data
,
2060 .read_wave_sgprs
= &gfx_v9_0_read_wave_sgprs
,
2061 .read_wave_vgprs
= &gfx_v9_0_read_wave_vgprs
,
2062 .select_me_pipe_q
= &gfx_v9_0_select_me_pipe_q
,
2063 .ras_error_inject
= &gfx_v9_0_ras_error_inject
,
2064 .query_ras_error_count
= &gfx_v9_0_query_ras_error_count
,
2065 .reset_ras_error_count
= &gfx_v9_0_reset_ras_error_count
,
2068 static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs
= {
2069 .get_gpu_clock_counter
= &gfx_v9_0_get_gpu_clock_counter
,
2070 .select_se_sh
= &gfx_v9_0_select_se_sh
,
2071 .read_wave_data
= &gfx_v9_0_read_wave_data
,
2072 .read_wave_sgprs
= &gfx_v9_0_read_wave_sgprs
,
2073 .read_wave_vgprs
= &gfx_v9_0_read_wave_vgprs
,
2074 .select_me_pipe_q
= &gfx_v9_0_select_me_pipe_q
,
2075 .ras_error_inject
= &gfx_v9_4_ras_error_inject
,
2076 .query_ras_error_count
= &gfx_v9_4_query_ras_error_count
,
2077 .reset_ras_error_count
= &gfx_v9_4_reset_ras_error_count
,
2080 static int gfx_v9_0_gpu_early_init(struct amdgpu_device
*adev
)
2085 adev
->gfx
.funcs
= &gfx_v9_0_gfx_funcs
;
2087 switch (adev
->asic_type
) {
2089 adev
->gfx
.config
.max_hw_contexts
= 8;
2090 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
2091 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
2092 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
2093 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x4C0;
2094 gb_addr_config
= VEGA10_GB_ADDR_CONFIG_GOLDEN
;
2097 adev
->gfx
.config
.max_hw_contexts
= 8;
2098 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
2099 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
2100 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
2101 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x4C0;
2102 gb_addr_config
= VEGA12_GB_ADDR_CONFIG_GOLDEN
;
2103 DRM_INFO("fix gfx.config for vega12\n");
2106 adev
->gfx
.config
.max_hw_contexts
= 8;
2107 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
2108 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
2109 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
2110 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x4C0;
2111 gb_addr_config
= RREG32_SOC15(GC
, 0, mmGB_ADDR_CONFIG
);
2112 gb_addr_config
&= ~0xf3e777ff;
2113 gb_addr_config
|= 0x22014042;
2114 /* check vbios table if gpu info is not available */
2115 err
= amdgpu_atomfirmware_get_gfx_info(adev
);
2120 adev
->gfx
.config
.max_hw_contexts
= 8;
2121 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
2122 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
2123 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
2124 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x4C0;
2125 if (adev
->rev_id
>= 8)
2126 gb_addr_config
= RAVEN2_GB_ADDR_CONFIG_GOLDEN
;
2128 gb_addr_config
= RAVEN_GB_ADDR_CONFIG_GOLDEN
;
2131 adev
->gfx
.funcs
= &gfx_v9_4_gfx_funcs
;
2132 adev
->gfx
.config
.max_hw_contexts
= 8;
2133 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
2134 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
2135 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x30;
2136 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x4C0;
2137 gb_addr_config
= RREG32_SOC15(GC
, 0, mmGB_ADDR_CONFIG
);
2138 gb_addr_config
&= ~0xf3e777ff;
2139 gb_addr_config
|= 0x22014042;
2142 adev
->gfx
.config
.max_hw_contexts
= 8;
2143 adev
->gfx
.config
.sc_prim_fifo_size_frontend
= 0x20;
2144 adev
->gfx
.config
.sc_prim_fifo_size_backend
= 0x100;
2145 adev
->gfx
.config
.sc_hiz_tile_fifo_size
= 0x80;
2146 adev
->gfx
.config
.sc_earlyz_tile_fifo_size
= 0x4C0;
2147 gb_addr_config
= RREG32_SOC15(GC
, 0, mmGB_ADDR_CONFIG
);
2148 gb_addr_config
&= ~0xf3e777ff;
2149 gb_addr_config
|= 0x22010042;
2156 adev
->gfx
.config
.gb_addr_config
= gb_addr_config
;
2158 adev
->gfx
.config
.gb_addr_config_fields
.num_pipes
= 1 <<
2160 adev
->gfx
.config
.gb_addr_config
,
2164 adev
->gfx
.config
.max_tile_pipes
=
2165 adev
->gfx
.config
.gb_addr_config_fields
.num_pipes
;
2167 adev
->gfx
.config
.gb_addr_config_fields
.num_banks
= 1 <<
2169 adev
->gfx
.config
.gb_addr_config
,
2172 adev
->gfx
.config
.gb_addr_config_fields
.max_compress_frags
= 1 <<
2174 adev
->gfx
.config
.gb_addr_config
,
2176 MAX_COMPRESSED_FRAGS
);
2177 adev
->gfx
.config
.gb_addr_config_fields
.num_rb_per_se
= 1 <<
2179 adev
->gfx
.config
.gb_addr_config
,
2182 adev
->gfx
.config
.gb_addr_config_fields
.num_se
= 1 <<
2184 adev
->gfx
.config
.gb_addr_config
,
2186 NUM_SHADER_ENGINES
);
2187 adev
->gfx
.config
.gb_addr_config_fields
.pipe_interleave_size
= 1 << (8 +
2189 adev
->gfx
.config
.gb_addr_config
,
2191 PIPE_INTERLEAVE_SIZE
));
2196 static int gfx_v9_0_compute_ring_init(struct amdgpu_device
*adev
, int ring_id
,
2197 int mec
, int pipe
, int queue
)
2201 struct amdgpu_ring
*ring
= &adev
->gfx
.compute_ring
[ring_id
];
2203 ring
= &adev
->gfx
.compute_ring
[ring_id
];
2208 ring
->queue
= queue
;
2210 ring
->ring_obj
= NULL
;
2211 ring
->use_doorbell
= true;
2212 ring
->doorbell_index
= (adev
->doorbell_index
.mec_ring0
+ ring_id
) << 1;
2213 ring
->eop_gpu_addr
= adev
->gfx
.mec
.hpd_eop_gpu_addr
2214 + (ring_id
* GFX9_MEC_HPD_SIZE
);
2215 sprintf(ring
->name
, "comp_%d.%d.%d", ring
->me
, ring
->pipe
, ring
->queue
);
2217 irq_type
= AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
2218 + ((ring
->me
- 1) * adev
->gfx
.mec
.num_pipe_per_mec
)
2221 /* type-2 packets are deprecated on MEC, use type-3 instead */
2222 r
= amdgpu_ring_init(adev
, ring
, 1024,
2223 &adev
->gfx
.eop_irq
, irq_type
);
2231 static int gfx_v9_0_sw_init(void *handle
)
2233 int i
, j
, k
, r
, ring_id
;
2234 struct amdgpu_ring
*ring
;
2235 struct amdgpu_kiq
*kiq
;
2236 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2238 switch (adev
->asic_type
) {
2245 adev
->gfx
.mec
.num_mec
= 2;
2248 adev
->gfx
.mec
.num_mec
= 1;
2252 adev
->gfx
.mec
.num_pipe_per_mec
= 4;
2253 adev
->gfx
.mec
.num_queue_per_pipe
= 8;
2256 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_GRBM_CP
, GFX_9_0__SRCID__CP_EOP_INTERRUPT
, &adev
->gfx
.eop_irq
);
2260 /* Privileged reg */
2261 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_GRBM_CP
, GFX_9_0__SRCID__CP_PRIV_REG_FAULT
,
2262 &adev
->gfx
.priv_reg_irq
);
2266 /* Privileged inst */
2267 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_GRBM_CP
, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT
,
2268 &adev
->gfx
.priv_inst_irq
);
2273 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_GRBM_CP
, GFX_9_0__SRCID__CP_ECC_ERROR
,
2274 &adev
->gfx
.cp_ecc_error_irq
);
2279 r
= amdgpu_irq_add_id(adev
, SOC15_IH_CLIENTID_GRBM_CP
, GFX_9_0__SRCID__CP_FUE_ERROR
,
2280 &adev
->gfx
.cp_ecc_error_irq
);
2284 adev
->gfx
.gfx_current_status
= AMDGPU_GFX_NORMAL_MODE
;
2286 gfx_v9_0_scratch_init(adev
);
2288 r
= gfx_v9_0_init_microcode(adev
);
2290 DRM_ERROR("Failed to load gfx firmware!\n");
2294 r
= adev
->gfx
.rlc
.funcs
->init(adev
);
2296 DRM_ERROR("Failed to init rlc BOs!\n");
2300 r
= gfx_v9_0_mec_init(adev
);
2302 DRM_ERROR("Failed to init MEC BOs!\n");
2306 /* set up the gfx ring */
2307 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++) {
2308 ring
= &adev
->gfx
.gfx_ring
[i
];
2309 ring
->ring_obj
= NULL
;
2311 sprintf(ring
->name
, "gfx");
2313 sprintf(ring
->name
, "gfx_%d", i
);
2314 ring
->use_doorbell
= true;
2315 ring
->doorbell_index
= adev
->doorbell_index
.gfx_ring0
<< 1;
2316 r
= amdgpu_ring_init(adev
, ring
, 1024,
2317 &adev
->gfx
.eop_irq
, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP
);
2322 /* set up the compute queues - allocate horizontally across pipes */
2324 for (i
= 0; i
< adev
->gfx
.mec
.num_mec
; ++i
) {
2325 for (j
= 0; j
< adev
->gfx
.mec
.num_queue_per_pipe
; j
++) {
2326 for (k
= 0; k
< adev
->gfx
.mec
.num_pipe_per_mec
; k
++) {
2327 if (!amdgpu_gfx_is_mec_queue_enabled(adev
, i
, k
, j
))
2330 r
= gfx_v9_0_compute_ring_init(adev
,
2341 r
= amdgpu_gfx_kiq_init(adev
, GFX9_MEC_HPD_SIZE
);
2343 DRM_ERROR("Failed to init KIQ BOs!\n");
2347 kiq
= &adev
->gfx
.kiq
;
2348 r
= amdgpu_gfx_kiq_init_ring(adev
, &kiq
->ring
, &kiq
->irq
);
2352 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
2353 r
= amdgpu_gfx_mqd_sw_init(adev
, sizeof(struct v9_mqd_allocation
));
2357 adev
->gfx
.ce_ram_size
= 0x8000;
2359 r
= gfx_v9_0_gpu_early_init(adev
);
2367 static int gfx_v9_0_sw_fini(void *handle
)
2370 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2372 amdgpu_gfx_ras_fini(adev
);
2374 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
2375 amdgpu_ring_fini(&adev
->gfx
.gfx_ring
[i
]);
2376 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
2377 amdgpu_ring_fini(&adev
->gfx
.compute_ring
[i
]);
2379 amdgpu_gfx_mqd_sw_fini(adev
);
2380 amdgpu_gfx_kiq_free_ring(&adev
->gfx
.kiq
.ring
);
2381 amdgpu_gfx_kiq_fini(adev
);
2383 gfx_v9_0_mec_fini(adev
);
2384 amdgpu_bo_unref(&adev
->gfx
.rlc
.clear_state_obj
);
2385 if (adev
->asic_type
== CHIP_RAVEN
|| adev
->asic_type
== CHIP_RENOIR
) {
2386 amdgpu_bo_free_kernel(&adev
->gfx
.rlc
.cp_table_obj
,
2387 &adev
->gfx
.rlc
.cp_table_gpu_addr
,
2388 (void **)&adev
->gfx
.rlc
.cp_table_ptr
);
2390 gfx_v9_0_free_microcode(adev
);
2396 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device
*adev
)
2401 static void gfx_v9_0_select_se_sh(struct amdgpu_device
*adev
, u32 se_num
, u32 sh_num
, u32 instance
)
2405 if (instance
== 0xffffffff)
2406 data
= REG_SET_FIELD(0, GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
, 1);
2408 data
= REG_SET_FIELD(0, GRBM_GFX_INDEX
, INSTANCE_INDEX
, instance
);
2410 if (se_num
== 0xffffffff)
2411 data
= REG_SET_FIELD(data
, GRBM_GFX_INDEX
, SE_BROADCAST_WRITES
, 1);
2413 data
= REG_SET_FIELD(data
, GRBM_GFX_INDEX
, SE_INDEX
, se_num
);
2415 if (sh_num
== 0xffffffff)
2416 data
= REG_SET_FIELD(data
, GRBM_GFX_INDEX
, SH_BROADCAST_WRITES
, 1);
2418 data
= REG_SET_FIELD(data
, GRBM_GFX_INDEX
, SH_INDEX
, sh_num
);
2420 WREG32_SOC15_RLC_SHADOW(GC
, 0, mmGRBM_GFX_INDEX
, data
);
2423 static u32
gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device
*adev
)
2427 data
= RREG32_SOC15(GC
, 0, mmCC_RB_BACKEND_DISABLE
);
2428 data
|= RREG32_SOC15(GC
, 0, mmGC_USER_RB_BACKEND_DISABLE
);
2430 data
&= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK
;
2431 data
>>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT
;
2433 mask
= amdgpu_gfx_create_bitmask(adev
->gfx
.config
.max_backends_per_se
/
2434 adev
->gfx
.config
.max_sh_per_se
);
2436 return (~data
) & mask
;
2439 static void gfx_v9_0_setup_rb(struct amdgpu_device
*adev
)
2444 u32 rb_bitmap_width_per_sh
= adev
->gfx
.config
.max_backends_per_se
/
2445 adev
->gfx
.config
.max_sh_per_se
;
2447 mutex_lock(&adev
->grbm_idx_mutex
);
2448 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
2449 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
2450 gfx_v9_0_select_se_sh(adev
, i
, j
, 0xffffffff);
2451 data
= gfx_v9_0_get_rb_active_bitmap(adev
);
2452 active_rbs
|= data
<< ((i
* adev
->gfx
.config
.max_sh_per_se
+ j
) *
2453 rb_bitmap_width_per_sh
);
2456 gfx_v9_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
2457 mutex_unlock(&adev
->grbm_idx_mutex
);
2459 adev
->gfx
.config
.backend_enable_mask
= active_rbs
;
2460 adev
->gfx
.config
.num_rbs
= hweight32(active_rbs
);
2463 #define DEFAULT_SH_MEM_BASES (0x6000)
2464 #define FIRST_COMPUTE_VMID (8)
2465 #define LAST_COMPUTE_VMID (16)
2466 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device
*adev
)
2469 uint32_t sh_mem_config
;
2470 uint32_t sh_mem_bases
;
2473 * Configure apertures:
2474 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
2475 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
2476 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
2478 sh_mem_bases
= DEFAULT_SH_MEM_BASES
| (DEFAULT_SH_MEM_BASES
<< 16);
2480 sh_mem_config
= SH_MEM_ADDRESS_MODE_64
|
2481 SH_MEM_ALIGNMENT_MODE_UNALIGNED
<<
2482 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT
;
2484 mutex_lock(&adev
->srbm_mutex
);
2485 for (i
= FIRST_COMPUTE_VMID
; i
< LAST_COMPUTE_VMID
; i
++) {
2486 soc15_grbm_select(adev
, 0, 0, 0, i
);
2487 /* CP and shaders */
2488 WREG32_SOC15_RLC(GC
, 0, mmSH_MEM_CONFIG
, sh_mem_config
);
2489 WREG32_SOC15_RLC(GC
, 0, mmSH_MEM_BASES
, sh_mem_bases
);
2491 soc15_grbm_select(adev
, 0, 0, 0, 0);
2492 mutex_unlock(&adev
->srbm_mutex
);
2494 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
2495 acccess. These should be enabled by FW for target VMIDs. */
2496 for (i
= FIRST_COMPUTE_VMID
; i
< LAST_COMPUTE_VMID
; i
++) {
2497 WREG32_SOC15_OFFSET(GC
, 0, mmGDS_VMID0_BASE
, 2 * i
, 0);
2498 WREG32_SOC15_OFFSET(GC
, 0, mmGDS_VMID0_SIZE
, 2 * i
, 0);
2499 WREG32_SOC15_OFFSET(GC
, 0, mmGDS_GWS_VMID0
, i
, 0);
2500 WREG32_SOC15_OFFSET(GC
, 0, mmGDS_OA_VMID0
, i
, 0);
2504 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device
*adev
)
2509 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
2510 * access. Compute VMIDs should be enabled by FW for target VMIDs,
2511 * the driver can enable them for graphics. VMID0 should maintain
2512 * access so that HWS firmware can save/restore entries.
2514 for (vmid
= 1; vmid
< 16; vmid
++) {
2515 WREG32_SOC15_OFFSET(GC
, 0, mmGDS_VMID0_BASE
, 2 * vmid
, 0);
2516 WREG32_SOC15_OFFSET(GC
, 0, mmGDS_VMID0_SIZE
, 2 * vmid
, 0);
2517 WREG32_SOC15_OFFSET(GC
, 0, mmGDS_GWS_VMID0
, vmid
, 0);
2518 WREG32_SOC15_OFFSET(GC
, 0, mmGDS_OA_VMID0
, vmid
, 0);
2522 static void gfx_v9_0_init_sq_config(struct amdgpu_device
*adev
)
2526 switch (adev
->asic_type
) {
2528 tmp
= RREG32_SOC15(GC
, 0, mmSQ_CONFIG
);
2529 tmp
= REG_SET_FIELD(tmp
, SQ_CONFIG
,
2530 DISABLE_BARRIER_WAITCNT
, 1);
2531 WREG32_SOC15(GC
, 0, mmSQ_CONFIG
, tmp
);
2538 static void gfx_v9_0_constants_init(struct amdgpu_device
*adev
)
2543 WREG32_FIELD15_RLC(GC
, 0, GRBM_CNTL
, READ_TIMEOUT
, 0xff);
2545 gfx_v9_0_tiling_mode_table_init(adev
);
2547 gfx_v9_0_setup_rb(adev
);
2548 gfx_v9_0_get_cu_info(adev
, &adev
->gfx
.cu_info
);
2549 adev
->gfx
.config
.db_debug2
= RREG32_SOC15(GC
, 0, mmDB_DEBUG2
);
2551 /* XXX SH_MEM regs */
2552 /* where to put LDS, scratch, GPUVM in FSA64 space */
2553 mutex_lock(&adev
->srbm_mutex
);
2554 for (i
= 0; i
< adev
->vm_manager
.id_mgr
[AMDGPU_GFXHUB_0
].num_ids
; i
++) {
2555 soc15_grbm_select(adev
, 0, 0, 0, i
);
2556 /* CP and shaders */
2558 tmp
= REG_SET_FIELD(0, SH_MEM_CONFIG
, ALIGNMENT_MODE
,
2559 SH_MEM_ALIGNMENT_MODE_UNALIGNED
);
2560 tmp
= REG_SET_FIELD(tmp
, SH_MEM_CONFIG
, RETRY_DISABLE
,
2562 WREG32_SOC15_RLC(GC
, 0, mmSH_MEM_CONFIG
, tmp
);
2563 WREG32_SOC15_RLC(GC
, 0, mmSH_MEM_BASES
, 0);
2565 tmp
= REG_SET_FIELD(0, SH_MEM_CONFIG
, ALIGNMENT_MODE
,
2566 SH_MEM_ALIGNMENT_MODE_UNALIGNED
);
2567 tmp
= REG_SET_FIELD(tmp
, SH_MEM_CONFIG
, RETRY_DISABLE
,
2569 WREG32_SOC15_RLC(GC
, 0, mmSH_MEM_CONFIG
, tmp
);
2570 tmp
= REG_SET_FIELD(0, SH_MEM_BASES
, PRIVATE_BASE
,
2571 (adev
->gmc
.private_aperture_start
>> 48));
2572 tmp
= REG_SET_FIELD(tmp
, SH_MEM_BASES
, SHARED_BASE
,
2573 (adev
->gmc
.shared_aperture_start
>> 48));
2574 WREG32_SOC15_RLC(GC
, 0, mmSH_MEM_BASES
, tmp
);
2577 soc15_grbm_select(adev
, 0, 0, 0, 0);
2579 mutex_unlock(&adev
->srbm_mutex
);
2581 gfx_v9_0_init_compute_vmid(adev
);
2582 gfx_v9_0_init_gds_vmid(adev
);
2583 gfx_v9_0_init_sq_config(adev
);
2586 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device
*adev
)
2591 mutex_lock(&adev
->grbm_idx_mutex
);
2592 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
2593 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
2594 gfx_v9_0_select_se_sh(adev
, i
, j
, 0xffffffff);
2595 for (k
= 0; k
< adev
->usec_timeout
; k
++) {
2596 if (RREG32_SOC15(GC
, 0, mmRLC_SERDES_CU_MASTER_BUSY
) == 0)
2600 if (k
== adev
->usec_timeout
) {
2601 gfx_v9_0_select_se_sh(adev
, 0xffffffff,
2602 0xffffffff, 0xffffffff);
2603 mutex_unlock(&adev
->grbm_idx_mutex
);
2604 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
2610 gfx_v9_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
2611 mutex_unlock(&adev
->grbm_idx_mutex
);
2613 mask
= RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK
|
2614 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK
|
2615 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK
|
2616 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK
;
2617 for (k
= 0; k
< adev
->usec_timeout
; k
++) {
2618 if ((RREG32_SOC15(GC
, 0, mmRLC_SERDES_NONCU_MASTER_BUSY
) & mask
) == 0)
2624 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev
,
2627 u32 tmp
= RREG32_SOC15(GC
, 0, mmCP_INT_CNTL_RING0
);
2629 tmp
= REG_SET_FIELD(tmp
, CP_INT_CNTL_RING0
, CNTX_BUSY_INT_ENABLE
, enable
? 1 : 0);
2630 tmp
= REG_SET_FIELD(tmp
, CP_INT_CNTL_RING0
, CNTX_EMPTY_INT_ENABLE
, enable
? 1 : 0);
2631 tmp
= REG_SET_FIELD(tmp
, CP_INT_CNTL_RING0
, CMP_BUSY_INT_ENABLE
, enable
? 1 : 0);
2632 tmp
= REG_SET_FIELD(tmp
, CP_INT_CNTL_RING0
, GFX_IDLE_INT_ENABLE
, enable
? 1 : 0);
2634 WREG32_SOC15(GC
, 0, mmCP_INT_CNTL_RING0
, tmp
);
2637 static void gfx_v9_0_init_csb(struct amdgpu_device
*adev
)
2639 adev
->gfx
.rlc
.funcs
->get_csb_buffer(adev
, adev
->gfx
.rlc
.cs_ptr
);
2641 WREG32_RLC(SOC15_REG_OFFSET(GC
, 0, mmRLC_CSIB_ADDR_HI
),
2642 adev
->gfx
.rlc
.clear_state_gpu_addr
>> 32);
2643 WREG32_RLC(SOC15_REG_OFFSET(GC
, 0, mmRLC_CSIB_ADDR_LO
),
2644 adev
->gfx
.rlc
.clear_state_gpu_addr
& 0xfffffffc);
2645 WREG32_RLC(SOC15_REG_OFFSET(GC
, 0, mmRLC_CSIB_LENGTH
),
2646 adev
->gfx
.rlc
.clear_state_size
);
2649 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format
,
2650 int indirect_offset
,
2652 int *unique_indirect_regs
,
2653 int unique_indirect_reg_count
,
2654 int *indirect_start_offsets
,
2655 int *indirect_start_offsets_count
,
2656 int max_start_offsets_count
)
2660 for (; indirect_offset
< list_size
; indirect_offset
++) {
2661 WARN_ON(*indirect_start_offsets_count
>= max_start_offsets_count
);
2662 indirect_start_offsets
[*indirect_start_offsets_count
] = indirect_offset
;
2663 *indirect_start_offsets_count
= *indirect_start_offsets_count
+ 1;
2665 while (register_list_format
[indirect_offset
] != 0xFFFFFFFF) {
2666 indirect_offset
+= 2;
2668 /* look for the matching indice */
2669 for (idx
= 0; idx
< unique_indirect_reg_count
; idx
++) {
2670 if (unique_indirect_regs
[idx
] ==
2671 register_list_format
[indirect_offset
] ||
2672 !unique_indirect_regs
[idx
])
2676 BUG_ON(idx
>= unique_indirect_reg_count
);
2678 if (!unique_indirect_regs
[idx
])
2679 unique_indirect_regs
[idx
] = register_list_format
[indirect_offset
];
2686 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device
*adev
)
2688 int unique_indirect_regs
[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2689 int unique_indirect_reg_count
= 0;
2691 int indirect_start_offsets
[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2692 int indirect_start_offsets_count
= 0;
2698 u32
*register_list_format
=
2699 kmemdup(adev
->gfx
.rlc
.register_list_format
,
2700 adev
->gfx
.rlc
.reg_list_format_size_bytes
, GFP_KERNEL
);
2701 if (!register_list_format
)
2704 /* setup unique_indirect_regs array and indirect_start_offsets array */
2705 unique_indirect_reg_count
= ARRAY_SIZE(unique_indirect_regs
);
2706 gfx_v9_1_parse_ind_reg_list(register_list_format
,
2707 adev
->gfx
.rlc
.reg_list_format_direct_reg_list_length
,
2708 adev
->gfx
.rlc
.reg_list_format_size_bytes
>> 2,
2709 unique_indirect_regs
,
2710 unique_indirect_reg_count
,
2711 indirect_start_offsets
,
2712 &indirect_start_offsets_count
,
2713 ARRAY_SIZE(indirect_start_offsets
));
2715 /* enable auto inc in case it is disabled */
2716 tmp
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_SRM_CNTL
));
2717 tmp
|= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK
;
2718 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_SRM_CNTL
), tmp
);
2720 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2721 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_SRM_ARAM_ADDR
),
2722 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET
);
2723 for (i
= 0; i
< adev
->gfx
.rlc
.reg_list_size_bytes
>> 2; i
++)
2724 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_SRM_ARAM_DATA
),
2725 adev
->gfx
.rlc
.register_restore
[i
]);
2727 /* load indirect register */
2728 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_SCRATCH_ADDR
),
2729 adev
->gfx
.rlc
.reg_list_format_start
);
2731 /* direct register portion */
2732 for (i
= 0; i
< adev
->gfx
.rlc
.reg_list_format_direct_reg_list_length
; i
++)
2733 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_SCRATCH_DATA
),
2734 register_list_format
[i
]);
2736 /* indirect register portion */
2737 while (i
< (adev
->gfx
.rlc
.reg_list_format_size_bytes
>> 2)) {
2738 if (register_list_format
[i
] == 0xFFFFFFFF) {
2739 WREG32_SOC15(GC
, 0, mmRLC_GPM_SCRATCH_DATA
, register_list_format
[i
++]);
2743 WREG32_SOC15(GC
, 0, mmRLC_GPM_SCRATCH_DATA
, register_list_format
[i
++]);
2744 WREG32_SOC15(GC
, 0, mmRLC_GPM_SCRATCH_DATA
, register_list_format
[i
++]);
2746 for (j
= 0; j
< unique_indirect_reg_count
; j
++) {
2747 if (register_list_format
[i
] == unique_indirect_regs
[j
]) {
2748 WREG32_SOC15(GC
, 0, mmRLC_GPM_SCRATCH_DATA
, j
);
2753 BUG_ON(j
>= unique_indirect_reg_count
);
2758 /* set save/restore list size */
2759 list_size
= adev
->gfx
.rlc
.reg_list_size_bytes
>> 2;
2760 list_size
= list_size
>> 1;
2761 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_SCRATCH_ADDR
),
2762 adev
->gfx
.rlc
.reg_restore_list_size
);
2763 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_SCRATCH_DATA
), list_size
);
2765 /* write the starting offsets to RLC scratch ram */
2766 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_SCRATCH_ADDR
),
2767 adev
->gfx
.rlc
.starting_offsets_start
);
2768 for (i
= 0; i
< ARRAY_SIZE(indirect_start_offsets
); i
++)
2769 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_GPM_SCRATCH_DATA
),
2770 indirect_start_offsets
[i
]);
2772 /* load unique indirect regs*/
2773 for (i
= 0; i
< ARRAY_SIZE(unique_indirect_regs
); i
++) {
2774 if (unique_indirect_regs
[i
] != 0) {
2775 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0
)
2776 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS
[i
],
2777 unique_indirect_regs
[i
] & 0x3FFFF);
2779 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_SRM_INDEX_CNTL_DATA_0
)
2780 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS
[i
],
2781 unique_indirect_regs
[i
] >> 20);
2785 kfree(register_list_format
);
2789 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device
*adev
)
2791 WREG32_FIELD15(GC
, 0, RLC_SRM_CNTL
, SRM_ENABLE
, 1);
2794 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device
*adev
,
2798 uint32_t default_data
= 0;
2800 default_data
= data
= RREG32(SOC15_REG_OFFSET(PWR
, 0, mmPWR_MISC_CNTL_STATUS
));
2801 if (enable
== true) {
2802 /* enable GFXIP control over CGPG */
2803 data
|= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK
;
2804 if(default_data
!= data
)
2805 WREG32(SOC15_REG_OFFSET(PWR
, 0, mmPWR_MISC_CNTL_STATUS
), data
);
2808 data
&= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK
;
2809 data
|= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT
);
2810 if(default_data
!= data
)
2811 WREG32(SOC15_REG_OFFSET(PWR
, 0, mmPWR_MISC_CNTL_STATUS
), data
);
2813 /* restore GFXIP control over GCPG */
2814 data
&= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK
;
2815 if(default_data
!= data
)
2816 WREG32(SOC15_REG_OFFSET(PWR
, 0, mmPWR_MISC_CNTL_STATUS
), data
);
2820 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device
*adev
)
2824 if (adev
->pg_flags
& (AMD_PG_SUPPORT_GFX_PG
|
2825 AMD_PG_SUPPORT_GFX_SMG
|
2826 AMD_PG_SUPPORT_GFX_DMG
)) {
2827 /* init IDLE_POLL_COUNT = 60 */
2828 data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmCP_RB_WPTR_POLL_CNTL
));
2829 data
&= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK
;
2830 data
|= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
);
2831 WREG32(SOC15_REG_OFFSET(GC
, 0, mmCP_RB_WPTR_POLL_CNTL
), data
);
2833 /* init RLC PG Delay */
2835 data
|= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT
);
2836 data
|= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT
);
2837 data
|= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT
);
2838 data
|= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT
);
2839 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_DELAY
), data
);
2841 data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_DELAY_2
));
2842 data
&= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK
;
2843 data
|= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT
);
2844 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_DELAY_2
), data
);
2846 data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_DELAY_3
));
2847 data
&= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK
;
2848 data
|= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT
);
2849 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_DELAY_3
), data
);
2851 data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_AUTO_PG_CTRL
));
2852 data
&= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK
;
2854 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2855 data
|= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT
);
2856 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_AUTO_PG_CTRL
), data
);
2858 pwr_10_0_gfxip_control_over_cgpg(adev
, true);
2862 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device
*adev
,
2866 uint32_t default_data
= 0;
2868 default_data
= data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
));
2869 data
= REG_SET_FIELD(data
, RLC_PG_CNTL
,
2870 SMU_CLK_SLOWDOWN_ON_PU_ENABLE
,
2872 if (default_data
!= data
)
2873 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
), data
);
2876 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device
*adev
,
2880 uint32_t default_data
= 0;
2882 default_data
= data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
));
2883 data
= REG_SET_FIELD(data
, RLC_PG_CNTL
,
2884 SMU_CLK_SLOWDOWN_ON_PD_ENABLE
,
2886 if(default_data
!= data
)
2887 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
), data
);
2890 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device
*adev
,
2894 uint32_t default_data
= 0;
2896 default_data
= data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
));
2897 data
= REG_SET_FIELD(data
, RLC_PG_CNTL
,
2900 if(default_data
!= data
)
2901 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
), data
);
2904 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device
*adev
,
2907 uint32_t data
, default_data
;
2909 default_data
= data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
));
2910 data
= REG_SET_FIELD(data
, RLC_PG_CNTL
,
2911 GFX_POWER_GATING_ENABLE
,
2913 if(default_data
!= data
)
2914 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
), data
);
2917 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device
*adev
,
2920 uint32_t data
, default_data
;
2922 default_data
= data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
));
2923 data
= REG_SET_FIELD(data
, RLC_PG_CNTL
,
2924 GFX_PIPELINE_PG_ENABLE
,
2926 if(default_data
!= data
)
2927 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
), data
);
2930 /* read any GFX register to wake up GFX */
2931 data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmDB_RENDER_CONTROL
));
2934 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device
*adev
,
2937 uint32_t data
, default_data
;
2939 default_data
= data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
));
2940 data
= REG_SET_FIELD(data
, RLC_PG_CNTL
,
2941 STATIC_PER_CU_PG_ENABLE
,
2943 if(default_data
!= data
)
2944 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
), data
);
2947 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device
*adev
,
2950 uint32_t data
, default_data
;
2952 default_data
= data
= RREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
));
2953 data
= REG_SET_FIELD(data
, RLC_PG_CNTL
,
2954 DYN_PER_CU_PG_ENABLE
,
2956 if(default_data
!= data
)
2957 WREG32(SOC15_REG_OFFSET(GC
, 0, mmRLC_PG_CNTL
), data
);
2960 static void gfx_v9_0_init_pg(struct amdgpu_device
*adev
)
2962 gfx_v9_0_init_csb(adev
);
2965 * Rlc save restore list is workable since v2_1.
2966 * And it's needed by gfxoff feature.
2968 if (adev
->gfx
.rlc
.is_rlc_v2_1
) {
2969 if (adev
->asic_type
== CHIP_VEGA12
||
2970 (adev
->asic_type
== CHIP_RAVEN
&&
2972 gfx_v9_1_init_rlc_save_restore_list(adev
);
2973 gfx_v9_0_enable_save_restore_machine(adev
);
2976 if (adev
->pg_flags
& (AMD_PG_SUPPORT_GFX_PG
|
2977 AMD_PG_SUPPORT_GFX_SMG
|
2978 AMD_PG_SUPPORT_GFX_DMG
|
2980 AMD_PG_SUPPORT_GDS
|
2981 AMD_PG_SUPPORT_RLC_SMU_HS
)) {
2982 WREG32(mmRLC_JUMP_TABLE_RESTORE
,
2983 adev
->gfx
.rlc
.cp_table_gpu_addr
>> 8);
2984 gfx_v9_0_init_gfx_power_gating(adev
);
2988 void gfx_v9_0_rlc_stop(struct amdgpu_device
*adev
)
2990 WREG32_FIELD15(GC
, 0, RLC_CNTL
, RLC_ENABLE_F32
, 0);
2991 gfx_v9_0_enable_gui_idle_interrupt(adev
, false);
2992 gfx_v9_0_wait_for_rlc_serdes(adev
);
2995 static void gfx_v9_0_rlc_reset(struct amdgpu_device
*adev
)
2997 WREG32_FIELD15(GC
, 0, GRBM_SOFT_RESET
, SOFT_RESET_RLC
, 1);
2999 WREG32_FIELD15(GC
, 0, GRBM_SOFT_RESET
, SOFT_RESET_RLC
, 0);
3003 static void gfx_v9_0_rlc_start(struct amdgpu_device
*adev
)
3005 #ifdef AMDGPU_RLC_DEBUG_RETRY
3009 WREG32_FIELD15(GC
, 0, RLC_CNTL
, RLC_ENABLE_F32
, 1);
3012 /* carrizo do enable cp interrupt after cp inited */
3013 if (!(adev
->flags
& AMD_IS_APU
)) {
3014 gfx_v9_0_enable_gui_idle_interrupt(adev
, true);
3018 #ifdef AMDGPU_RLC_DEBUG_RETRY
3019 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
3020 rlc_ucode_ver
= RREG32_SOC15(GC
, 0, mmRLC_GPM_GENERAL_6
);
3021 if(rlc_ucode_ver
== 0x108) {
3022 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
3023 rlc_ucode_ver
, adev
->gfx
.rlc_fw_version
);
3024 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
3025 * default is 0x9C4 to create a 100us interval */
3026 WREG32_SOC15(GC
, 0, mmRLC_GPM_TIMER_INT_3
, 0x9C4);
3027 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
3028 * to disable the page fault retry interrupts, default is
3030 WREG32_SOC15(GC
, 0, mmRLC_GPM_GENERAL_12
, 0x100);
3035 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device
*adev
)
3037 const struct rlc_firmware_header_v2_0
*hdr
;
3038 const __le32
*fw_data
;
3039 unsigned i
, fw_size
;
3041 if (!adev
->gfx
.rlc_fw
)
3044 hdr
= (const struct rlc_firmware_header_v2_0
*)adev
->gfx
.rlc_fw
->data
;
3045 amdgpu_ucode_print_rlc_hdr(&hdr
->header
);
3047 fw_data
= (const __le32
*)(adev
->gfx
.rlc_fw
->data
+
3048 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
3049 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
3051 WREG32_SOC15(GC
, 0, mmRLC_GPM_UCODE_ADDR
,
3052 RLCG_UCODE_LOADING_START_ADDRESS
);
3053 for (i
= 0; i
< fw_size
; i
++)
3054 WREG32_SOC15(GC
, 0, mmRLC_GPM_UCODE_DATA
, le32_to_cpup(fw_data
++));
3055 WREG32_SOC15(GC
, 0, mmRLC_GPM_UCODE_ADDR
, adev
->gfx
.rlc_fw_version
);
3060 static int gfx_v9_0_rlc_resume(struct amdgpu_device
*adev
)
3064 if (amdgpu_sriov_vf(adev
)) {
3065 gfx_v9_0_init_csb(adev
);
3069 adev
->gfx
.rlc
.funcs
->stop(adev
);
3072 WREG32_SOC15(GC
, 0, mmRLC_CGCG_CGLS_CTRL
, 0);
3074 gfx_v9_0_init_pg(adev
);
3076 if (adev
->firmware
.load_type
!= AMDGPU_FW_LOAD_PSP
) {
3077 /* legacy rlc firmware loading */
3078 r
= gfx_v9_0_rlc_load_microcode(adev
);
3083 switch (adev
->asic_type
) {
3085 if (amdgpu_lbpw
== 0)
3086 gfx_v9_0_enable_lbpw(adev
, false);
3088 gfx_v9_0_enable_lbpw(adev
, true);
3091 if (amdgpu_lbpw
> 0)
3092 gfx_v9_0_enable_lbpw(adev
, true);
3094 gfx_v9_0_enable_lbpw(adev
, false);
3100 adev
->gfx
.rlc
.funcs
->start(adev
);
3105 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device
*adev
, bool enable
)
3108 u32 tmp
= RREG32_SOC15(GC
, 0, mmCP_ME_CNTL
);
3110 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, ME_HALT
, enable
? 0 : 1);
3111 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, PFP_HALT
, enable
? 0 : 1);
3112 tmp
= REG_SET_FIELD(tmp
, CP_ME_CNTL
, CE_HALT
, enable
? 0 : 1);
3114 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
3115 adev
->gfx
.gfx_ring
[i
].sched
.ready
= false;
3117 WREG32_SOC15_RLC(GC
, 0, mmCP_ME_CNTL
, tmp
);
3121 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device
*adev
)
3123 const struct gfx_firmware_header_v1_0
*pfp_hdr
;
3124 const struct gfx_firmware_header_v1_0
*ce_hdr
;
3125 const struct gfx_firmware_header_v1_0
*me_hdr
;
3126 const __le32
*fw_data
;
3127 unsigned i
, fw_size
;
3129 if (!adev
->gfx
.me_fw
|| !adev
->gfx
.pfp_fw
|| !adev
->gfx
.ce_fw
)
3132 pfp_hdr
= (const struct gfx_firmware_header_v1_0
*)
3133 adev
->gfx
.pfp_fw
->data
;
3134 ce_hdr
= (const struct gfx_firmware_header_v1_0
*)
3135 adev
->gfx
.ce_fw
->data
;
3136 me_hdr
= (const struct gfx_firmware_header_v1_0
*)
3137 adev
->gfx
.me_fw
->data
;
3139 amdgpu_ucode_print_gfx_hdr(&pfp_hdr
->header
);
3140 amdgpu_ucode_print_gfx_hdr(&ce_hdr
->header
);
3141 amdgpu_ucode_print_gfx_hdr(&me_hdr
->header
);
3143 gfx_v9_0_cp_gfx_enable(adev
, false);
3146 fw_data
= (const __le32
*)
3147 (adev
->gfx
.pfp_fw
->data
+
3148 le32_to_cpu(pfp_hdr
->header
.ucode_array_offset_bytes
));
3149 fw_size
= le32_to_cpu(pfp_hdr
->header
.ucode_size_bytes
) / 4;
3150 WREG32_SOC15(GC
, 0, mmCP_PFP_UCODE_ADDR
, 0);
3151 for (i
= 0; i
< fw_size
; i
++)
3152 WREG32_SOC15(GC
, 0, mmCP_PFP_UCODE_DATA
, le32_to_cpup(fw_data
++));
3153 WREG32_SOC15(GC
, 0, mmCP_PFP_UCODE_ADDR
, adev
->gfx
.pfp_fw_version
);
3156 fw_data
= (const __le32
*)
3157 (adev
->gfx
.ce_fw
->data
+
3158 le32_to_cpu(ce_hdr
->header
.ucode_array_offset_bytes
));
3159 fw_size
= le32_to_cpu(ce_hdr
->header
.ucode_size_bytes
) / 4;
3160 WREG32_SOC15(GC
, 0, mmCP_CE_UCODE_ADDR
, 0);
3161 for (i
= 0; i
< fw_size
; i
++)
3162 WREG32_SOC15(GC
, 0, mmCP_CE_UCODE_DATA
, le32_to_cpup(fw_data
++));
3163 WREG32_SOC15(GC
, 0, mmCP_CE_UCODE_ADDR
, adev
->gfx
.ce_fw_version
);
3166 fw_data
= (const __le32
*)
3167 (adev
->gfx
.me_fw
->data
+
3168 le32_to_cpu(me_hdr
->header
.ucode_array_offset_bytes
));
3169 fw_size
= le32_to_cpu(me_hdr
->header
.ucode_size_bytes
) / 4;
3170 WREG32_SOC15(GC
, 0, mmCP_ME_RAM_WADDR
, 0);
3171 for (i
= 0; i
< fw_size
; i
++)
3172 WREG32_SOC15(GC
, 0, mmCP_ME_RAM_DATA
, le32_to_cpup(fw_data
++));
3173 WREG32_SOC15(GC
, 0, mmCP_ME_RAM_WADDR
, adev
->gfx
.me_fw_version
);
3178 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device
*adev
)
3180 struct amdgpu_ring
*ring
= &adev
->gfx
.gfx_ring
[0];
3181 const struct cs_section_def
*sect
= NULL
;
3182 const struct cs_extent_def
*ext
= NULL
;
3186 WREG32_SOC15(GC
, 0, mmCP_MAX_CONTEXT
, adev
->gfx
.config
.max_hw_contexts
- 1);
3187 WREG32_SOC15(GC
, 0, mmCP_DEVICE_ID
, 1);
3189 gfx_v9_0_cp_gfx_enable(adev
, true);
3191 r
= amdgpu_ring_alloc(ring
, gfx_v9_0_get_csb_size(adev
) + 4 + 3);
3193 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r
);
3197 amdgpu_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
3198 amdgpu_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
3200 amdgpu_ring_write(ring
, PACKET3(PACKET3_CONTEXT_CONTROL
, 1));
3201 amdgpu_ring_write(ring
, 0x80000000);
3202 amdgpu_ring_write(ring
, 0x80000000);
3204 for (sect
= gfx9_cs_data
; sect
->section
!= NULL
; ++sect
) {
3205 for (ext
= sect
->section
; ext
->extent
!= NULL
; ++ext
) {
3206 if (sect
->id
== SECT_CONTEXT
) {
3207 amdgpu_ring_write(ring
,
3208 PACKET3(PACKET3_SET_CONTEXT_REG
,
3210 amdgpu_ring_write(ring
,
3211 ext
->reg_index
- PACKET3_SET_CONTEXT_REG_START
);
3212 for (i
= 0; i
< ext
->reg_count
; i
++)
3213 amdgpu_ring_write(ring
, ext
->extent
[i
]);
3218 amdgpu_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
3219 amdgpu_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
3221 amdgpu_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
3222 amdgpu_ring_write(ring
, 0);
3224 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_BASE
, 2));
3225 amdgpu_ring_write(ring
, PACKET3_BASE_INDEX(CE_PARTITION_BASE
));
3226 amdgpu_ring_write(ring
, 0x8000);
3227 amdgpu_ring_write(ring
, 0x8000);
3229 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_UCONFIG_REG
,1));
3230 tmp
= (PACKET3_SET_UCONFIG_REG_INDEX_TYPE
|
3231 (SOC15_REG_OFFSET(GC
, 0, mmVGT_INDEX_TYPE
) - PACKET3_SET_UCONFIG_REG_START
));
3232 amdgpu_ring_write(ring
, tmp
);
3233 amdgpu_ring_write(ring
, 0);
3235 amdgpu_ring_commit(ring
);
3240 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device
*adev
)
3242 struct amdgpu_ring
*ring
;
3245 u64 rb_addr
, rptr_addr
, wptr_gpu_addr
;
3247 /* Set the write pointer delay */
3248 WREG32_SOC15(GC
, 0, mmCP_RB_WPTR_DELAY
, 0);
3250 /* set the RB to use vmid 0 */
3251 WREG32_SOC15(GC
, 0, mmCP_RB_VMID
, 0);
3253 /* Set ring buffer size */
3254 ring
= &adev
->gfx
.gfx_ring
[0];
3255 rb_bufsz
= order_base_2(ring
->ring_size
/ 8);
3256 tmp
= REG_SET_FIELD(0, CP_RB0_CNTL
, RB_BUFSZ
, rb_bufsz
);
3257 tmp
= REG_SET_FIELD(tmp
, CP_RB0_CNTL
, RB_BLKSZ
, rb_bufsz
- 2);
3259 tmp
= REG_SET_FIELD(tmp
, CP_RB0_CNTL
, BUF_SWAP
, 1);
3261 WREG32_SOC15(GC
, 0, mmCP_RB0_CNTL
, tmp
);
3263 /* Initialize the ring buffer's write pointers */
3265 WREG32_SOC15(GC
, 0, mmCP_RB0_WPTR
, lower_32_bits(ring
->wptr
));
3266 WREG32_SOC15(GC
, 0, mmCP_RB0_WPTR_HI
, upper_32_bits(ring
->wptr
));
3268 /* set the wb address wether it's enabled or not */
3269 rptr_addr
= adev
->wb
.gpu_addr
+ (ring
->rptr_offs
* 4);
3270 WREG32_SOC15(GC
, 0, mmCP_RB0_RPTR_ADDR
, lower_32_bits(rptr_addr
));
3271 WREG32_SOC15(GC
, 0, mmCP_RB0_RPTR_ADDR_HI
, upper_32_bits(rptr_addr
) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK
);
3273 wptr_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->wptr_offs
* 4);
3274 WREG32_SOC15(GC
, 0, mmCP_RB_WPTR_POLL_ADDR_LO
, lower_32_bits(wptr_gpu_addr
));
3275 WREG32_SOC15(GC
, 0, mmCP_RB_WPTR_POLL_ADDR_HI
, upper_32_bits(wptr_gpu_addr
));
3278 WREG32_SOC15(GC
, 0, mmCP_RB0_CNTL
, tmp
);
3280 rb_addr
= ring
->gpu_addr
>> 8;
3281 WREG32_SOC15(GC
, 0, mmCP_RB0_BASE
, rb_addr
);
3282 WREG32_SOC15(GC
, 0, mmCP_RB0_BASE_HI
, upper_32_bits(rb_addr
));
3284 tmp
= RREG32_SOC15(GC
, 0, mmCP_RB_DOORBELL_CONTROL
);
3285 if (ring
->use_doorbell
) {
3286 tmp
= REG_SET_FIELD(tmp
, CP_RB_DOORBELL_CONTROL
,
3287 DOORBELL_OFFSET
, ring
->doorbell_index
);
3288 tmp
= REG_SET_FIELD(tmp
, CP_RB_DOORBELL_CONTROL
,
3291 tmp
= REG_SET_FIELD(tmp
, CP_RB_DOORBELL_CONTROL
, DOORBELL_EN
, 0);
3293 WREG32_SOC15(GC
, 0, mmCP_RB_DOORBELL_CONTROL
, tmp
);
3295 tmp
= REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER
,
3296 DOORBELL_RANGE_LOWER
, ring
->doorbell_index
);
3297 WREG32_SOC15(GC
, 0, mmCP_RB_DOORBELL_RANGE_LOWER
, tmp
);
3299 WREG32_SOC15(GC
, 0, mmCP_RB_DOORBELL_RANGE_UPPER
,
3300 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK
);
3303 /* start the ring */
3304 gfx_v9_0_cp_gfx_start(adev
);
3305 ring
->sched
.ready
= true;
3310 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device
*adev
, bool enable
)
3315 WREG32_SOC15_RLC(GC
, 0, mmCP_MEC_CNTL
, 0);
3317 WREG32_SOC15_RLC(GC
, 0, mmCP_MEC_CNTL
,
3318 (CP_MEC_CNTL__MEC_ME1_HALT_MASK
| CP_MEC_CNTL__MEC_ME2_HALT_MASK
));
3319 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
3320 adev
->gfx
.compute_ring
[i
].sched
.ready
= false;
3321 adev
->gfx
.kiq
.ring
.sched
.ready
= false;
3326 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device
*adev
)
3328 const struct gfx_firmware_header_v1_0
*mec_hdr
;
3329 const __le32
*fw_data
;
3333 if (!adev
->gfx
.mec_fw
)
3336 gfx_v9_0_cp_compute_enable(adev
, false);
3338 mec_hdr
= (const struct gfx_firmware_header_v1_0
*)adev
->gfx
.mec_fw
->data
;
3339 amdgpu_ucode_print_gfx_hdr(&mec_hdr
->header
);
3341 fw_data
= (const __le32
*)
3342 (adev
->gfx
.mec_fw
->data
+
3343 le32_to_cpu(mec_hdr
->header
.ucode_array_offset_bytes
));
3345 tmp
= REG_SET_FIELD(tmp
, CP_CPC_IC_BASE_CNTL
, VMID
, 0);
3346 tmp
= REG_SET_FIELD(tmp
, CP_CPC_IC_BASE_CNTL
, CACHE_POLICY
, 0);
3347 WREG32_SOC15(GC
, 0, mmCP_CPC_IC_BASE_CNTL
, tmp
);
3349 WREG32_SOC15(GC
, 0, mmCP_CPC_IC_BASE_LO
,
3350 adev
->gfx
.mec
.mec_fw_gpu_addr
& 0xFFFFF000);
3351 WREG32_SOC15(GC
, 0, mmCP_CPC_IC_BASE_HI
,
3352 upper_32_bits(adev
->gfx
.mec
.mec_fw_gpu_addr
));
3355 WREG32_SOC15(GC
, 0, mmCP_MEC_ME1_UCODE_ADDR
,
3356 mec_hdr
->jt_offset
);
3357 for (i
= 0; i
< mec_hdr
->jt_size
; i
++)
3358 WREG32_SOC15(GC
, 0, mmCP_MEC_ME1_UCODE_DATA
,
3359 le32_to_cpup(fw_data
+ mec_hdr
->jt_offset
+ i
));
3361 WREG32_SOC15(GC
, 0, mmCP_MEC_ME1_UCODE_ADDR
,
3362 adev
->gfx
.mec_fw_version
);
3363 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3369 static void gfx_v9_0_kiq_setting(struct amdgpu_ring
*ring
)
3372 struct amdgpu_device
*adev
= ring
->adev
;
3374 /* tell RLC which is KIQ queue */
3375 tmp
= RREG32_SOC15(GC
, 0, mmRLC_CP_SCHEDULERS
);
3377 tmp
|= (ring
->me
<< 5) | (ring
->pipe
<< 3) | (ring
->queue
);
3378 WREG32_SOC15_RLC(GC
, 0, mmRLC_CP_SCHEDULERS
, tmp
);
3380 WREG32_SOC15_RLC(GC
, 0, mmRLC_CP_SCHEDULERS
, tmp
);
3383 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring
*ring
, struct v9_mqd
*mqd
)
3385 struct amdgpu_device
*adev
= ring
->adev
;
3387 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_COMPUTE
) {
3388 if (amdgpu_gfx_is_high_priority_compute_queue(adev
, ring
->queue
)) {
3389 mqd
->cp_hqd_pipe_priority
= AMDGPU_GFX_PIPE_PRIO_HIGH
;
3390 ring
->has_high_prio
= true;
3391 mqd
->cp_hqd_queue_priority
=
3392 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM
;
3394 ring
->has_high_prio
= false;
3399 static int gfx_v9_0_mqd_init(struct amdgpu_ring
*ring
)
3401 struct amdgpu_device
*adev
= ring
->adev
;
3402 struct v9_mqd
*mqd
= ring
->mqd_ptr
;
3403 uint64_t hqd_gpu_addr
, wb_gpu_addr
, eop_base_addr
;
3406 mqd
->header
= 0xC0310800;
3407 mqd
->compute_pipelinestat_enable
= 0x00000001;
3408 mqd
->compute_static_thread_mgmt_se0
= 0xffffffff;
3409 mqd
->compute_static_thread_mgmt_se1
= 0xffffffff;
3410 mqd
->compute_static_thread_mgmt_se2
= 0xffffffff;
3411 mqd
->compute_static_thread_mgmt_se3
= 0xffffffff;
3412 mqd
->compute_static_thread_mgmt_se4
= 0xffffffff;
3413 mqd
->compute_static_thread_mgmt_se5
= 0xffffffff;
3414 mqd
->compute_static_thread_mgmt_se6
= 0xffffffff;
3415 mqd
->compute_static_thread_mgmt_se7
= 0xffffffff;
3416 mqd
->compute_misc_reserved
= 0x00000003;
3418 mqd
->dynamic_cu_mask_addr_lo
=
3419 lower_32_bits(ring
->mqd_gpu_addr
3420 + offsetof(struct v9_mqd_allocation
, dynamic_cu_mask
));
3421 mqd
->dynamic_cu_mask_addr_hi
=
3422 upper_32_bits(ring
->mqd_gpu_addr
3423 + offsetof(struct v9_mqd_allocation
, dynamic_cu_mask
));
3425 eop_base_addr
= ring
->eop_gpu_addr
>> 8;
3426 mqd
->cp_hqd_eop_base_addr_lo
= eop_base_addr
;
3427 mqd
->cp_hqd_eop_base_addr_hi
= upper_32_bits(eop_base_addr
);
3429 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3430 tmp
= RREG32_SOC15(GC
, 0, mmCP_HQD_EOP_CONTROL
);
3431 tmp
= REG_SET_FIELD(tmp
, CP_HQD_EOP_CONTROL
, EOP_SIZE
,
3432 (order_base_2(GFX9_MEC_HPD_SIZE
/ 4) - 1));
3434 mqd
->cp_hqd_eop_control
= tmp
;
3436 /* enable doorbell? */
3437 tmp
= RREG32_SOC15(GC
, 0, mmCP_HQD_PQ_DOORBELL_CONTROL
);
3439 if (ring
->use_doorbell
) {
3440 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_DOORBELL_CONTROL
,
3441 DOORBELL_OFFSET
, ring
->doorbell_index
);
3442 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_DOORBELL_CONTROL
,
3444 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_DOORBELL_CONTROL
,
3445 DOORBELL_SOURCE
, 0);
3446 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_DOORBELL_CONTROL
,
3449 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_DOORBELL_CONTROL
,
3453 mqd
->cp_hqd_pq_doorbell_control
= tmp
;
3455 /* disable the queue if it's active */
3457 mqd
->cp_hqd_dequeue_request
= 0;
3458 mqd
->cp_hqd_pq_rptr
= 0;
3459 mqd
->cp_hqd_pq_wptr_lo
= 0;
3460 mqd
->cp_hqd_pq_wptr_hi
= 0;
3462 /* set the pointer to the MQD */
3463 mqd
->cp_mqd_base_addr_lo
= ring
->mqd_gpu_addr
& 0xfffffffc;
3464 mqd
->cp_mqd_base_addr_hi
= upper_32_bits(ring
->mqd_gpu_addr
);
3466 /* set MQD vmid to 0 */
3467 tmp
= RREG32_SOC15(GC
, 0, mmCP_MQD_CONTROL
);
3468 tmp
= REG_SET_FIELD(tmp
, CP_MQD_CONTROL
, VMID
, 0);
3469 mqd
->cp_mqd_control
= tmp
;
3471 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3472 hqd_gpu_addr
= ring
->gpu_addr
>> 8;
3473 mqd
->cp_hqd_pq_base_lo
= hqd_gpu_addr
;
3474 mqd
->cp_hqd_pq_base_hi
= upper_32_bits(hqd_gpu_addr
);
3476 /* set up the HQD, this is similar to CP_RB0_CNTL */
3477 tmp
= RREG32_SOC15(GC
, 0, mmCP_HQD_PQ_CONTROL
);
3478 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_CONTROL
, QUEUE_SIZE
,
3479 (order_base_2(ring
->ring_size
/ 4) - 1));
3480 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_CONTROL
, RPTR_BLOCK_SIZE
,
3481 ((order_base_2(AMDGPU_GPU_PAGE_SIZE
/ 4) - 1) << 8));
3483 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_CONTROL
, ENDIAN_SWAP
, 1);
3485 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_CONTROL
, UNORD_DISPATCH
, 0);
3486 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_CONTROL
, ROQ_PQ_IB_FLIP
, 0);
3487 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_CONTROL
, PRIV_STATE
, 1);
3488 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_CONTROL
, KMD_QUEUE
, 1);
3489 mqd
->cp_hqd_pq_control
= tmp
;
3491 /* set the wb address whether it's enabled or not */
3492 wb_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->rptr_offs
* 4);
3493 mqd
->cp_hqd_pq_rptr_report_addr_lo
= wb_gpu_addr
& 0xfffffffc;
3494 mqd
->cp_hqd_pq_rptr_report_addr_hi
=
3495 upper_32_bits(wb_gpu_addr
) & 0xffff;
3497 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3498 wb_gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->wptr_offs
* 4);
3499 mqd
->cp_hqd_pq_wptr_poll_addr_lo
= wb_gpu_addr
& 0xfffffffc;
3500 mqd
->cp_hqd_pq_wptr_poll_addr_hi
= upper_32_bits(wb_gpu_addr
) & 0xffff;
3503 /* enable the doorbell if requested */
3504 if (ring
->use_doorbell
) {
3505 tmp
= RREG32_SOC15(GC
, 0, mmCP_HQD_PQ_DOORBELL_CONTROL
);
3506 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_DOORBELL_CONTROL
,
3507 DOORBELL_OFFSET
, ring
->doorbell_index
);
3509 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_DOORBELL_CONTROL
,
3511 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_DOORBELL_CONTROL
,
3512 DOORBELL_SOURCE
, 0);
3513 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PQ_DOORBELL_CONTROL
,
3517 mqd
->cp_hqd_pq_doorbell_control
= tmp
;
3519 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3521 mqd
->cp_hqd_pq_rptr
= RREG32_SOC15(GC
, 0, mmCP_HQD_PQ_RPTR
);
3523 /* set the vmid for the queue */
3524 mqd
->cp_hqd_vmid
= 0;
3526 tmp
= RREG32_SOC15(GC
, 0, mmCP_HQD_PERSISTENT_STATE
);
3527 tmp
= REG_SET_FIELD(tmp
, CP_HQD_PERSISTENT_STATE
, PRELOAD_SIZE
, 0x53);
3528 mqd
->cp_hqd_persistent_state
= tmp
;
3530 /* set MIN_IB_AVAIL_SIZE */
3531 tmp
= RREG32_SOC15(GC
, 0, mmCP_HQD_IB_CONTROL
);
3532 tmp
= REG_SET_FIELD(tmp
, CP_HQD_IB_CONTROL
, MIN_IB_AVAIL_SIZE
, 3);
3533 mqd
->cp_hqd_ib_control
= tmp
;
3535 /* set static priority for a queue/ring */
3536 gfx_v9_0_mqd_set_priority(ring
, mqd
);
3537 mqd
->cp_hqd_quantum
= RREG32(mmCP_HQD_QUANTUM
);
3539 /* map_queues packet doesn't need activate the queue,
3540 * so only kiq need set this field.
3542 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_KIQ
)
3543 mqd
->cp_hqd_active
= 1;
3548 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring
*ring
)
3550 struct amdgpu_device
*adev
= ring
->adev
;
3551 struct v9_mqd
*mqd
= ring
->mqd_ptr
;
3554 /* disable wptr polling */
3555 WREG32_FIELD15(GC
, 0, CP_PQ_WPTR_POLL_CNTL
, EN
, 0);
3557 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_EOP_BASE_ADDR
,
3558 mqd
->cp_hqd_eop_base_addr_lo
);
3559 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_EOP_BASE_ADDR_HI
,
3560 mqd
->cp_hqd_eop_base_addr_hi
);
3562 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3563 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_EOP_CONTROL
,
3564 mqd
->cp_hqd_eop_control
);
3566 /* enable doorbell? */
3567 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_DOORBELL_CONTROL
,
3568 mqd
->cp_hqd_pq_doorbell_control
);
3570 /* disable the queue if it's active */
3571 if (RREG32_SOC15(GC
, 0, mmCP_HQD_ACTIVE
) & 1) {
3572 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_DEQUEUE_REQUEST
, 1);
3573 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
3574 if (!(RREG32_SOC15(GC
, 0, mmCP_HQD_ACTIVE
) & 1))
3578 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_DEQUEUE_REQUEST
,
3579 mqd
->cp_hqd_dequeue_request
);
3580 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_RPTR
,
3581 mqd
->cp_hqd_pq_rptr
);
3582 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_WPTR_LO
,
3583 mqd
->cp_hqd_pq_wptr_lo
);
3584 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_WPTR_HI
,
3585 mqd
->cp_hqd_pq_wptr_hi
);
3588 /* set the pointer to the MQD */
3589 WREG32_SOC15_RLC(GC
, 0, mmCP_MQD_BASE_ADDR
,
3590 mqd
->cp_mqd_base_addr_lo
);
3591 WREG32_SOC15_RLC(GC
, 0, mmCP_MQD_BASE_ADDR_HI
,
3592 mqd
->cp_mqd_base_addr_hi
);
3594 /* set MQD vmid to 0 */
3595 WREG32_SOC15_RLC(GC
, 0, mmCP_MQD_CONTROL
,
3596 mqd
->cp_mqd_control
);
3598 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3599 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_BASE
,
3600 mqd
->cp_hqd_pq_base_lo
);
3601 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_BASE_HI
,
3602 mqd
->cp_hqd_pq_base_hi
);
3604 /* set up the HQD, this is similar to CP_RB0_CNTL */
3605 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_CONTROL
,
3606 mqd
->cp_hqd_pq_control
);
3608 /* set the wb address whether it's enabled or not */
3609 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR
,
3610 mqd
->cp_hqd_pq_rptr_report_addr_lo
);
3611 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI
,
3612 mqd
->cp_hqd_pq_rptr_report_addr_hi
);
3614 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3615 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR
,
3616 mqd
->cp_hqd_pq_wptr_poll_addr_lo
);
3617 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI
,
3618 mqd
->cp_hqd_pq_wptr_poll_addr_hi
);
3620 /* enable the doorbell if requested */
3621 if (ring
->use_doorbell
) {
3622 WREG32_SOC15(GC
, 0, mmCP_MEC_DOORBELL_RANGE_LOWER
,
3623 (adev
->doorbell_index
.kiq
* 2) << 2);
3624 WREG32_SOC15(GC
, 0, mmCP_MEC_DOORBELL_RANGE_UPPER
,
3625 (adev
->doorbell_index
.userqueue_end
* 2) << 2);
3628 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_DOORBELL_CONTROL
,
3629 mqd
->cp_hqd_pq_doorbell_control
);
3631 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3632 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_WPTR_LO
,
3633 mqd
->cp_hqd_pq_wptr_lo
);
3634 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_WPTR_HI
,
3635 mqd
->cp_hqd_pq_wptr_hi
);
3637 /* set the vmid for the queue */
3638 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_VMID
, mqd
->cp_hqd_vmid
);
3640 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PERSISTENT_STATE
,
3641 mqd
->cp_hqd_persistent_state
);
3643 /* activate the queue */
3644 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_ACTIVE
,
3645 mqd
->cp_hqd_active
);
3647 if (ring
->use_doorbell
)
3648 WREG32_FIELD15(GC
, 0, CP_PQ_STATUS
, DOORBELL_ENABLE
, 1);
3653 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring
*ring
)
3655 struct amdgpu_device
*adev
= ring
->adev
;
3658 /* disable the queue if it's active */
3659 if (RREG32_SOC15(GC
, 0, mmCP_HQD_ACTIVE
) & 1) {
3661 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_DEQUEUE_REQUEST
, 1);
3663 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
3664 if (!(RREG32_SOC15(GC
, 0, mmCP_HQD_ACTIVE
) & 1))
3669 if (j
== AMDGPU_MAX_USEC_TIMEOUT
) {
3670 DRM_DEBUG("KIQ dequeue request failed.\n");
3672 /* Manual disable if dequeue request times out */
3673 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_ACTIVE
, 0);
3676 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_DEQUEUE_REQUEST
,
3680 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_IQ_TIMER
, 0);
3681 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_IB_CONTROL
, 0);
3682 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PERSISTENT_STATE
, 0);
3683 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_DOORBELL_CONTROL
, 0x40000000);
3684 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_DOORBELL_CONTROL
, 0);
3685 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_RPTR
, 0);
3686 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_WPTR_HI
, 0);
3687 WREG32_SOC15_RLC(GC
, 0, mmCP_HQD_PQ_WPTR_LO
, 0);
3692 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring
*ring
)
3694 struct amdgpu_device
*adev
= ring
->adev
;
3695 struct v9_mqd
*mqd
= ring
->mqd_ptr
;
3696 int mqd_idx
= AMDGPU_MAX_COMPUTE_RINGS
;
3698 gfx_v9_0_kiq_setting(ring
);
3700 if (adev
->in_gpu_reset
) { /* for GPU_RESET case */
3701 /* reset MQD to a clean status */
3702 if (adev
->gfx
.mec
.mqd_backup
[mqd_idx
])
3703 memcpy(mqd
, adev
->gfx
.mec
.mqd_backup
[mqd_idx
], sizeof(struct v9_mqd_allocation
));
3705 /* reset ring buffer */
3707 amdgpu_ring_clear_ring(ring
);
3709 mutex_lock(&adev
->srbm_mutex
);
3710 soc15_grbm_select(adev
, ring
->me
, ring
->pipe
, ring
->queue
, 0);
3711 gfx_v9_0_kiq_init_register(ring
);
3712 soc15_grbm_select(adev
, 0, 0, 0, 0);
3713 mutex_unlock(&adev
->srbm_mutex
);
3715 memset((void *)mqd
, 0, sizeof(struct v9_mqd_allocation
));
3716 ((struct v9_mqd_allocation
*)mqd
)->dynamic_cu_mask
= 0xFFFFFFFF;
3717 ((struct v9_mqd_allocation
*)mqd
)->dynamic_rb_mask
= 0xFFFFFFFF;
3718 mutex_lock(&adev
->srbm_mutex
);
3719 soc15_grbm_select(adev
, ring
->me
, ring
->pipe
, ring
->queue
, 0);
3720 gfx_v9_0_mqd_init(ring
);
3721 gfx_v9_0_kiq_init_register(ring
);
3722 soc15_grbm_select(adev
, 0, 0, 0, 0);
3723 mutex_unlock(&adev
->srbm_mutex
);
3725 if (adev
->gfx
.mec
.mqd_backup
[mqd_idx
])
3726 memcpy(adev
->gfx
.mec
.mqd_backup
[mqd_idx
], mqd
, sizeof(struct v9_mqd_allocation
));
3732 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring
*ring
)
3734 struct amdgpu_device
*adev
= ring
->adev
;
3735 struct v9_mqd
*mqd
= ring
->mqd_ptr
;
3736 int mqd_idx
= ring
- &adev
->gfx
.compute_ring
[0];
3738 if (!adev
->in_gpu_reset
&& !adev
->in_suspend
) {
3739 memset((void *)mqd
, 0, sizeof(struct v9_mqd_allocation
));
3740 ((struct v9_mqd_allocation
*)mqd
)->dynamic_cu_mask
= 0xFFFFFFFF;
3741 ((struct v9_mqd_allocation
*)mqd
)->dynamic_rb_mask
= 0xFFFFFFFF;
3742 mutex_lock(&adev
->srbm_mutex
);
3743 soc15_grbm_select(adev
, ring
->me
, ring
->pipe
, ring
->queue
, 0);
3744 gfx_v9_0_mqd_init(ring
);
3745 soc15_grbm_select(adev
, 0, 0, 0, 0);
3746 mutex_unlock(&adev
->srbm_mutex
);
3748 if (adev
->gfx
.mec
.mqd_backup
[mqd_idx
])
3749 memcpy(adev
->gfx
.mec
.mqd_backup
[mqd_idx
], mqd
, sizeof(struct v9_mqd_allocation
));
3750 } else if (adev
->in_gpu_reset
) { /* for GPU_RESET case */
3751 /* reset MQD to a clean status */
3752 if (adev
->gfx
.mec
.mqd_backup
[mqd_idx
])
3753 memcpy(mqd
, adev
->gfx
.mec
.mqd_backup
[mqd_idx
], sizeof(struct v9_mqd_allocation
));
3755 /* reset ring buffer */
3757 atomic64_set((atomic64_t
*)&adev
->wb
.wb
[ring
->wptr_offs
], 0);
3758 amdgpu_ring_clear_ring(ring
);
3760 amdgpu_ring_clear_ring(ring
);
3766 static int gfx_v9_0_kiq_resume(struct amdgpu_device
*adev
)
3768 struct amdgpu_ring
*ring
;
3771 ring
= &adev
->gfx
.kiq
.ring
;
3773 r
= amdgpu_bo_reserve(ring
->mqd_obj
, false);
3774 if (unlikely(r
!= 0))
3777 r
= amdgpu_bo_kmap(ring
->mqd_obj
, (void **)&ring
->mqd_ptr
);
3778 if (unlikely(r
!= 0))
3781 gfx_v9_0_kiq_init_queue(ring
);
3782 amdgpu_bo_kunmap(ring
->mqd_obj
);
3783 ring
->mqd_ptr
= NULL
;
3784 amdgpu_bo_unreserve(ring
->mqd_obj
);
3785 ring
->sched
.ready
= true;
3789 static int gfx_v9_0_kcq_resume(struct amdgpu_device
*adev
)
3791 struct amdgpu_ring
*ring
= NULL
;
3794 gfx_v9_0_cp_compute_enable(adev
, true);
3796 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
3797 ring
= &adev
->gfx
.compute_ring
[i
];
3799 r
= amdgpu_bo_reserve(ring
->mqd_obj
, false);
3800 if (unlikely(r
!= 0))
3802 r
= amdgpu_bo_kmap(ring
->mqd_obj
, (void **)&ring
->mqd_ptr
);
3804 r
= gfx_v9_0_kcq_init_queue(ring
);
3805 amdgpu_bo_kunmap(ring
->mqd_obj
);
3806 ring
->mqd_ptr
= NULL
;
3808 amdgpu_bo_unreserve(ring
->mqd_obj
);
3813 r
= amdgpu_gfx_enable_kcq(adev
);
3818 static int gfx_v9_0_cp_resume(struct amdgpu_device
*adev
)
3821 struct amdgpu_ring
*ring
;
3823 if (!(adev
->flags
& AMD_IS_APU
))
3824 gfx_v9_0_enable_gui_idle_interrupt(adev
, false);
3826 if (adev
->firmware
.load_type
!= AMDGPU_FW_LOAD_PSP
) {
3827 if (adev
->asic_type
!= CHIP_ARCTURUS
) {
3828 /* legacy firmware loading */
3829 r
= gfx_v9_0_cp_gfx_load_microcode(adev
);
3834 r
= gfx_v9_0_cp_compute_load_microcode(adev
);
3839 r
= gfx_v9_0_kiq_resume(adev
);
3843 if (adev
->asic_type
!= CHIP_ARCTURUS
) {
3844 r
= gfx_v9_0_cp_gfx_resume(adev
);
3849 r
= gfx_v9_0_kcq_resume(adev
);
3853 if (adev
->asic_type
!= CHIP_ARCTURUS
) {
3854 ring
= &adev
->gfx
.gfx_ring
[0];
3855 r
= amdgpu_ring_test_helper(ring
);
3860 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
3861 ring
= &adev
->gfx
.compute_ring
[i
];
3862 amdgpu_ring_test_helper(ring
);
3865 gfx_v9_0_enable_gui_idle_interrupt(adev
, true);
3870 static void gfx_v9_0_init_tcp_config(struct amdgpu_device
*adev
)
3874 if (adev
->asic_type
!= CHIP_ARCTURUS
)
3877 tmp
= RREG32_SOC15(GC
, 0, mmTCP_ADDR_CONFIG
);
3878 tmp
= REG_SET_FIELD(tmp
, TCP_ADDR_CONFIG
, ENABLE64KHASH
,
3879 adev
->df
.hash_status
.hash_64k
);
3880 tmp
= REG_SET_FIELD(tmp
, TCP_ADDR_CONFIG
, ENABLE2MHASH
,
3881 adev
->df
.hash_status
.hash_2m
);
3882 tmp
= REG_SET_FIELD(tmp
, TCP_ADDR_CONFIG
, ENABLE1GHASH
,
3883 adev
->df
.hash_status
.hash_1g
);
3884 WREG32_SOC15(GC
, 0, mmTCP_ADDR_CONFIG
, tmp
);
3887 static void gfx_v9_0_cp_enable(struct amdgpu_device
*adev
, bool enable
)
3889 if (adev
->asic_type
!= CHIP_ARCTURUS
)
3890 gfx_v9_0_cp_gfx_enable(adev
, enable
);
3891 gfx_v9_0_cp_compute_enable(adev
, enable
);
3894 static int gfx_v9_0_hw_init(void *handle
)
3897 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3899 if (!amdgpu_sriov_vf(adev
))
3900 gfx_v9_0_init_golden_registers(adev
);
3902 gfx_v9_0_constants_init(adev
);
3904 gfx_v9_0_init_tcp_config(adev
);
3906 r
= adev
->gfx
.rlc
.funcs
->resume(adev
);
3910 r
= gfx_v9_0_cp_resume(adev
);
3917 static int gfx_v9_0_hw_fini(void *handle
)
3919 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3921 amdgpu_irq_put(adev
, &adev
->gfx
.cp_ecc_error_irq
, 0);
3922 amdgpu_irq_put(adev
, &adev
->gfx
.priv_reg_irq
, 0);
3923 amdgpu_irq_put(adev
, &adev
->gfx
.priv_inst_irq
, 0);
3925 /* DF freeze and kcq disable will fail */
3926 if (!amdgpu_ras_intr_triggered())
3927 /* disable KCQ to avoid CPC touch memory not valid anymore */
3928 amdgpu_gfx_disable_kcq(adev
);
3930 if (amdgpu_sriov_vf(adev
)) {
3931 gfx_v9_0_cp_gfx_enable(adev
, false);
3932 /* must disable polling for SRIOV when hw finished, otherwise
3933 * CPC engine may still keep fetching WB address which is already
3934 * invalid after sw finished and trigger DMAR reading error in
3937 WREG32_FIELD15(GC
, 0, CP_PQ_WPTR_POLL_CNTL
, EN
, 0);
3941 /* Use deinitialize sequence from CAIL when unbinding device from driver,
3942 * otherwise KIQ is hanging when binding back
3944 if (!adev
->in_gpu_reset
&& !adev
->in_suspend
) {
3945 mutex_lock(&adev
->srbm_mutex
);
3946 soc15_grbm_select(adev
, adev
->gfx
.kiq
.ring
.me
,
3947 adev
->gfx
.kiq
.ring
.pipe
,
3948 adev
->gfx
.kiq
.ring
.queue
, 0);
3949 gfx_v9_0_kiq_fini_register(&adev
->gfx
.kiq
.ring
);
3950 soc15_grbm_select(adev
, 0, 0, 0, 0);
3951 mutex_unlock(&adev
->srbm_mutex
);
3954 gfx_v9_0_cp_enable(adev
, false);
3955 adev
->gfx
.rlc
.funcs
->stop(adev
);
3960 static int gfx_v9_0_suspend(void *handle
)
3962 return gfx_v9_0_hw_fini(handle
);
3965 static int gfx_v9_0_resume(void *handle
)
3967 return gfx_v9_0_hw_init(handle
);
3970 static bool gfx_v9_0_is_idle(void *handle
)
3972 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3974 if (REG_GET_FIELD(RREG32_SOC15(GC
, 0, mmGRBM_STATUS
),
3975 GRBM_STATUS
, GUI_ACTIVE
))
3981 static int gfx_v9_0_wait_for_idle(void *handle
)
3984 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3986 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
3987 if (gfx_v9_0_is_idle(handle
))
3994 static int gfx_v9_0_soft_reset(void *handle
)
3996 u32 grbm_soft_reset
= 0;
3998 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4001 tmp
= RREG32_SOC15(GC
, 0, mmGRBM_STATUS
);
4002 if (tmp
& (GRBM_STATUS__PA_BUSY_MASK
| GRBM_STATUS__SC_BUSY_MASK
|
4003 GRBM_STATUS__BCI_BUSY_MASK
| GRBM_STATUS__SX_BUSY_MASK
|
4004 GRBM_STATUS__TA_BUSY_MASK
| GRBM_STATUS__VGT_BUSY_MASK
|
4005 GRBM_STATUS__DB_BUSY_MASK
| GRBM_STATUS__CB_BUSY_MASK
|
4006 GRBM_STATUS__GDS_BUSY_MASK
| GRBM_STATUS__SPI_BUSY_MASK
|
4007 GRBM_STATUS__IA_BUSY_MASK
| GRBM_STATUS__IA_BUSY_NO_DMA_MASK
)) {
4008 grbm_soft_reset
= REG_SET_FIELD(grbm_soft_reset
,
4009 GRBM_SOFT_RESET
, SOFT_RESET_CP
, 1);
4010 grbm_soft_reset
= REG_SET_FIELD(grbm_soft_reset
,
4011 GRBM_SOFT_RESET
, SOFT_RESET_GFX
, 1);
4014 if (tmp
& (GRBM_STATUS__CP_BUSY_MASK
| GRBM_STATUS__CP_COHERENCY_BUSY_MASK
)) {
4015 grbm_soft_reset
= REG_SET_FIELD(grbm_soft_reset
,
4016 GRBM_SOFT_RESET
, SOFT_RESET_CP
, 1);
4020 tmp
= RREG32_SOC15(GC
, 0, mmGRBM_STATUS2
);
4021 if (REG_GET_FIELD(tmp
, GRBM_STATUS2
, RLC_BUSY
))
4022 grbm_soft_reset
= REG_SET_FIELD(grbm_soft_reset
,
4023 GRBM_SOFT_RESET
, SOFT_RESET_RLC
, 1);
4026 if (grbm_soft_reset
) {
4028 adev
->gfx
.rlc
.funcs
->stop(adev
);
4030 if (adev
->asic_type
!= CHIP_ARCTURUS
)
4031 /* Disable GFX parsing/prefetching */
4032 gfx_v9_0_cp_gfx_enable(adev
, false);
4034 /* Disable MEC parsing/prefetching */
4035 gfx_v9_0_cp_compute_enable(adev
, false);
4037 if (grbm_soft_reset
) {
4038 tmp
= RREG32_SOC15(GC
, 0, mmGRBM_SOFT_RESET
);
4039 tmp
|= grbm_soft_reset
;
4040 dev_info(adev
->dev
, "GRBM_SOFT_RESET=0x%08X\n", tmp
);
4041 WREG32_SOC15(GC
, 0, mmGRBM_SOFT_RESET
, tmp
);
4042 tmp
= RREG32_SOC15(GC
, 0, mmGRBM_SOFT_RESET
);
4046 tmp
&= ~grbm_soft_reset
;
4047 WREG32_SOC15(GC
, 0, mmGRBM_SOFT_RESET
, tmp
);
4048 tmp
= RREG32_SOC15(GC
, 0, mmGRBM_SOFT_RESET
);
4051 /* Wait a little for things to settle down */
4057 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device
*adev
)
4059 signed long r
, cnt
= 0;
4060 unsigned long flags
;
4062 struct amdgpu_kiq
*kiq
= &adev
->gfx
.kiq
;
4063 struct amdgpu_ring
*ring
= &kiq
->ring
;
4065 BUG_ON(!ring
->funcs
->emit_rreg
);
4067 spin_lock_irqsave(&kiq
->ring_lock
, flags
);
4068 amdgpu_ring_alloc(ring
, 32);
4069 amdgpu_ring_write(ring
, PACKET3(PACKET3_COPY_DATA
, 4));
4070 amdgpu_ring_write(ring
, 9 | /* src: register*/
4071 (5 << 8) | /* dst: memory */
4072 (1 << 16) | /* count sel */
4073 (1 << 20)); /* write confirm */
4074 amdgpu_ring_write(ring
, 0);
4075 amdgpu_ring_write(ring
, 0);
4076 amdgpu_ring_write(ring
, lower_32_bits(adev
->wb
.gpu_addr
+
4077 kiq
->reg_val_offs
* 4));
4078 amdgpu_ring_write(ring
, upper_32_bits(adev
->wb
.gpu_addr
+
4079 kiq
->reg_val_offs
* 4));
4080 amdgpu_fence_emit_polling(ring
, &seq
);
4081 amdgpu_ring_commit(ring
);
4082 spin_unlock_irqrestore(&kiq
->ring_lock
, flags
);
4084 r
= amdgpu_fence_wait_polling(ring
, seq
, MAX_KIQ_REG_WAIT
);
4086 /* don't wait anymore for gpu reset case because this way may
4087 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
4088 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
4089 * never return if we keep waiting in virt_kiq_rreg, which cause
4090 * gpu_recover() hang there.
4092 * also don't wait anymore for IRQ context
4094 if (r
< 1 && (adev
->in_gpu_reset
|| in_interrupt()))
4095 goto failed_kiq_read
;
4098 while (r
< 1 && cnt
++ < MAX_KIQ_REG_TRY
) {
4099 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL
);
4100 r
= amdgpu_fence_wait_polling(ring
, seq
, MAX_KIQ_REG_WAIT
);
4103 if (cnt
> MAX_KIQ_REG_TRY
)
4104 goto failed_kiq_read
;
4106 return (uint64_t)adev
->wb
.wb
[kiq
->reg_val_offs
] |
4107 (uint64_t)adev
->wb
.wb
[kiq
->reg_val_offs
+ 1 ] << 32ULL;
4110 pr_err("failed to read gpu clock\n");
4114 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device
*adev
)
4118 amdgpu_gfx_off_ctrl(adev
, false);
4119 mutex_lock(&adev
->gfx
.gpu_clock_mutex
);
4120 if (adev
->asic_type
== CHIP_VEGA10
&& amdgpu_sriov_runtime(adev
)) {
4121 clock
= gfx_v9_0_kiq_read_clock(adev
);
4123 WREG32_SOC15(GC
, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT
, 1);
4124 clock
= (uint64_t)RREG32_SOC15(GC
, 0, mmRLC_GPU_CLOCK_COUNT_LSB
) |
4125 ((uint64_t)RREG32_SOC15(GC
, 0, mmRLC_GPU_CLOCK_COUNT_MSB
) << 32ULL);
4127 mutex_unlock(&adev
->gfx
.gpu_clock_mutex
);
4128 amdgpu_gfx_off_ctrl(adev
, true);
4132 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring
*ring
,
4134 uint32_t gds_base
, uint32_t gds_size
,
4135 uint32_t gws_base
, uint32_t gws_size
,
4136 uint32_t oa_base
, uint32_t oa_size
)
4138 struct amdgpu_device
*adev
= ring
->adev
;
4141 gfx_v9_0_write_data_to_reg(ring
, 0, false,
4142 SOC15_REG_OFFSET(GC
, 0, mmGDS_VMID0_BASE
) + 2 * vmid
,
4146 gfx_v9_0_write_data_to_reg(ring
, 0, false,
4147 SOC15_REG_OFFSET(GC
, 0, mmGDS_VMID0_SIZE
) + 2 * vmid
,
4151 gfx_v9_0_write_data_to_reg(ring
, 0, false,
4152 SOC15_REG_OFFSET(GC
, 0, mmGDS_GWS_VMID0
) + vmid
,
4153 gws_size
<< GDS_GWS_VMID0__SIZE__SHIFT
| gws_base
);
4156 gfx_v9_0_write_data_to_reg(ring
, 0, false,
4157 SOC15_REG_OFFSET(GC
, 0, mmGDS_OA_VMID0
) + vmid
,
4158 (1 << (oa_size
+ oa_base
)) - (1 << oa_base
));
4161 static const u32 vgpr_init_compute_shader
[] =
4163 0xb07c0000, 0xbe8000ff,
4164 0x000000f8, 0xbf110800,
4165 0x7e000280, 0x7e020280,
4166 0x7e040280, 0x7e060280,
4167 0x7e080280, 0x7e0a0280,
4168 0x7e0c0280, 0x7e0e0280,
4169 0x80808800, 0xbe803200,
4170 0xbf84fff5, 0xbf9c0000,
4171 0xd28c0001, 0x0001007f,
4172 0xd28d0001, 0x0002027e,
4173 0x10020288, 0xb8810904,
4174 0xb7814000, 0xd1196a01,
4175 0x00000301, 0xbe800087,
4176 0xbefc00c1, 0xd89c4000,
4177 0x00020201, 0xd89cc080,
4178 0x00040401, 0x320202ff,
4179 0x00000800, 0x80808100,
4180 0xbf84fff8, 0x7e020280,
4181 0xbf810000, 0x00000000,
4184 static const u32 sgpr_init_compute_shader
[] =
4186 0xb07c0000, 0xbe8000ff,
4187 0x0000005f, 0xbee50080,
4188 0xbe812c65, 0xbe822c65,
4189 0xbe832c65, 0xbe842c65,
4190 0xbe852c65, 0xb77c0005,
4191 0x80808500, 0xbf84fff8,
4192 0xbe800080, 0xbf810000,
4195 static const u32 vgpr_init_compute_shader_arcturus
[] = {
4196 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080,
4197 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080,
4198 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080,
4199 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080,
4200 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080,
4201 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080,
4202 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080,
4203 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080,
4204 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080,
4205 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080,
4206 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080,
4207 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080,
4208 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080,
4209 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080,
4210 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080,
4211 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080,
4212 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080,
4213 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080,
4214 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080,
4215 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080,
4216 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080,
4217 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080,
4218 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080,
4219 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080,
4220 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080,
4221 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080,
4222 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080,
4223 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080,
4224 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080,
4225 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080,
4226 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080,
4227 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080,
4228 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080,
4229 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080,
4230 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080,
4231 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080,
4232 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080,
4233 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080,
4234 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080,
4235 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080,
4236 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080,
4237 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080,
4238 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080,
4239 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080,
4240 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080,
4241 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080,
4242 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080,
4243 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080,
4244 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080,
4245 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080,
4246 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080,
4247 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080,
4248 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080,
4249 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080,
4250 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080,
4251 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080,
4252 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080,
4253 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080,
4254 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080,
4255 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080,
4256 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080,
4257 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080,
4258 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080,
4259 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080,
4260 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080,
4261 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080,
4262 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080,
4263 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080,
4264 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080,
4265 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080,
4266 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080,
4267 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080,
4268 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080,
4269 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080,
4270 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080,
4271 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080,
4272 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080,
4273 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080,
4274 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080,
4275 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080,
4276 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080,
4277 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080,
4278 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080,
4279 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080,
4280 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080,
4281 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a,
4282 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280,
4283 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000,
4284 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904,
4285 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000,
4286 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a,
4287 0xbf84fff8, 0xbf810000,
4290 /* When below register arrays changed, please update gpr_reg_size,
4291 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds,
4292 to cover all gfx9 ASICs */
4293 static const struct soc15_reg_entry vgpr_init_regs
[] = {
4294 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_RESOURCE_LIMITS
), 0x0000000 },
4295 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_X
), 0x40 },
4296 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_Y
), 4 },
4297 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_Z
), 1 },
4298 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_PGM_RSRC1
), 0x3f },
4299 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_PGM_RSRC2
), 0x400000 }, /* 64KB LDS */
4300 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0
), 0xffffffff },
4301 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1
), 0xffffffff },
4302 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2
), 0xffffffff },
4303 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3
), 0xffffffff },
4304 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4
), 0xffffffff },
4305 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5
), 0xffffffff },
4306 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6
), 0xffffffff },
4307 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7
), 0xffffffff },
4310 static const struct soc15_reg_entry vgpr_init_regs_arcturus
[] = {
4311 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_RESOURCE_LIMITS
), 0x0000000 },
4312 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_X
), 0x40 },
4313 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_Y
), 4 },
4314 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_Z
), 1 },
4315 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_PGM_RSRC1
), 0xbf },
4316 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_PGM_RSRC2
), 0x400000 }, /* 64KB LDS */
4317 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0
), 0xffffffff },
4318 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1
), 0xffffffff },
4319 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2
), 0xffffffff },
4320 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3
), 0xffffffff },
4321 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4
), 0xffffffff },
4322 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5
), 0xffffffff },
4323 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6
), 0xffffffff },
4324 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7
), 0xffffffff },
4327 static const struct soc15_reg_entry sgpr1_init_regs
[] = {
4328 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_RESOURCE_LIMITS
), 0x0000000 },
4329 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_X
), 0x40 },
4330 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_Y
), 8 },
4331 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_Z
), 1 },
4332 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_PGM_RSRC1
), 0x240 }, /* (80 GPRS) */
4333 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_PGM_RSRC2
), 0x0 },
4334 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0
), 0x000000ff },
4335 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1
), 0x000000ff },
4336 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2
), 0x000000ff },
4337 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3
), 0x000000ff },
4338 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4
), 0x000000ff },
4339 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5
), 0x000000ff },
4340 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6
), 0x000000ff },
4341 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7
), 0x000000ff },
4344 static const struct soc15_reg_entry sgpr2_init_regs
[] = {
4345 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_RESOURCE_LIMITS
), 0x0000000 },
4346 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_X
), 0x40 },
4347 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_Y
), 8 },
4348 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_NUM_THREAD_Z
), 1 },
4349 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_PGM_RSRC1
), 0x240 }, /* (80 GPRS) */
4350 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_PGM_RSRC2
), 0x0 },
4351 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0
), 0x0000ff00 },
4352 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1
), 0x0000ff00 },
4353 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2
), 0x0000ff00 },
4354 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3
), 0x0000ff00 },
4355 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4
), 0x0000ff00 },
4356 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5
), 0x0000ff00 },
4357 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6
), 0x0000ff00 },
4358 { SOC15_REG_ENTRY(GC
, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7
), 0x0000ff00 },
4361 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs
[] = {
4362 { SOC15_REG_ENTRY(GC
, 0, mmCPC_EDC_SCRATCH_CNT
), 0, 1, 1},
4363 { SOC15_REG_ENTRY(GC
, 0, mmCPC_EDC_UCODE_CNT
), 0, 1, 1},
4364 { SOC15_REG_ENTRY(GC
, 0, mmCPF_EDC_ROQ_CNT
), 0, 1, 1},
4365 { SOC15_REG_ENTRY(GC
, 0, mmCPF_EDC_TAG_CNT
), 0, 1, 1},
4366 { SOC15_REG_ENTRY(GC
, 0, mmCPG_EDC_DMA_CNT
), 0, 1, 1},
4367 { SOC15_REG_ENTRY(GC
, 0, mmCPG_EDC_TAG_CNT
), 0, 1, 1},
4368 { SOC15_REG_ENTRY(GC
, 0, mmDC_EDC_CSINVOC_CNT
), 0, 1, 1},
4369 { SOC15_REG_ENTRY(GC
, 0, mmDC_EDC_RESTORE_CNT
), 0, 1, 1},
4370 { SOC15_REG_ENTRY(GC
, 0, mmDC_EDC_STATE_CNT
), 0, 1, 1},
4371 { SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_CNT
), 0, 1, 1},
4372 { SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_GRBM_CNT
), 0, 1, 1},
4373 { SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_DED
), 0, 1, 1},
4374 { SOC15_REG_ENTRY(GC
, 0, mmSPI_EDC_CNT
), 0, 4, 1},
4375 { SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT
), 0, 4, 6},
4376 { SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_DED_CNT
), 0, 4, 16},
4377 { SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_INFO
), 0, 4, 16},
4378 { SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_SEC_CNT
), 0, 4, 16},
4379 { SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
), 0, 1, 16},
4380 { SOC15_REG_ENTRY(GC
, 0, mmTCP_ATC_EDC_GATCL1_CNT
), 0, 4, 16},
4381 { SOC15_REG_ENTRY(GC
, 0, mmTCP_EDC_CNT
), 0, 4, 16},
4382 { SOC15_REG_ENTRY(GC
, 0, mmTCP_EDC_CNT_NEW
), 0, 4, 16},
4383 { SOC15_REG_ENTRY(GC
, 0, mmTD_EDC_CNT
), 0, 4, 16},
4384 { SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
), 0, 4, 6},
4385 { SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_CNT
), 0, 4, 16},
4386 { SOC15_REG_ENTRY(GC
, 0, mmTA_EDC_CNT
), 0, 4, 16},
4387 { SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_PHY_CNT
), 0, 1, 1},
4388 { SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_PIPE_CNT
), 0, 1, 1},
4389 { SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
), 0, 1, 32},
4390 { SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
), 0, 1, 32},
4391 { SOC15_REG_ENTRY(GC
, 0, mmTCI_EDC_CNT
), 0, 1, 72},
4392 { SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT2
), 0, 1, 16},
4393 { SOC15_REG_ENTRY(GC
, 0, mmTCA_EDC_CNT
), 0, 1, 2},
4394 { SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
), 0, 4, 6},
4397 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device
*adev
)
4399 struct amdgpu_ring
*ring
= &adev
->gfx
.compute_ring
[0];
4402 /* only support when RAS is enabled */
4403 if (!amdgpu_ras_is_supported(adev
, AMDGPU_RAS_BLOCK__GFX
))
4406 r
= amdgpu_ring_alloc(ring
, 7);
4408 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
4413 WREG32_SOC15(GC
, 0, mmGDS_VMID0_BASE
, 0x00000000);
4414 WREG32_SOC15(GC
, 0, mmGDS_VMID0_SIZE
, adev
->gds
.gds_size
);
4416 amdgpu_ring_write(ring
, PACKET3(PACKET3_DMA_DATA
, 5));
4417 amdgpu_ring_write(ring
, (PACKET3_DMA_DATA_CP_SYNC
|
4418 PACKET3_DMA_DATA_DST_SEL(1) |
4419 PACKET3_DMA_DATA_SRC_SEL(2) |
4420 PACKET3_DMA_DATA_ENGINE(0)));
4421 amdgpu_ring_write(ring
, 0);
4422 amdgpu_ring_write(ring
, 0);
4423 amdgpu_ring_write(ring
, 0);
4424 amdgpu_ring_write(ring
, 0);
4425 amdgpu_ring_write(ring
, PACKET3_DMA_DATA_CMD_RAW_WAIT
|
4426 adev
->gds
.gds_size
);
4428 amdgpu_ring_commit(ring
);
4430 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4431 if (ring
->wptr
== gfx_v9_0_ring_get_rptr_compute(ring
))
4436 if (i
>= adev
->usec_timeout
)
4439 WREG32_SOC15(GC
, 0, mmGDS_VMID0_SIZE
, 0x00000000);
4444 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device
*adev
)
4446 struct amdgpu_ring
*ring
= &adev
->gfx
.compute_ring
[0];
4447 struct amdgpu_ib ib
;
4448 struct dma_fence
*f
= NULL
;
4450 unsigned total_size
, vgpr_offset
, sgpr_offset
;
4453 int compute_dim_x
= adev
->gfx
.config
.max_shader_engines
*
4454 adev
->gfx
.config
.max_cu_per_sh
*
4455 adev
->gfx
.config
.max_sh_per_se
;
4456 int sgpr_work_group_size
= 5;
4457 int gpr_reg_size
= adev
->gfx
.config
.max_shader_engines
+ 6;
4458 int vgpr_init_shader_size
;
4459 const u32
*vgpr_init_shader_ptr
;
4460 const struct soc15_reg_entry
*vgpr_init_regs_ptr
;
4462 /* only support when RAS is enabled */
4463 if (!amdgpu_ras_is_supported(adev
, AMDGPU_RAS_BLOCK__GFX
))
4466 /* bail if the compute ring is not ready */
4467 if (!ring
->sched
.ready
)
4470 if (adev
->asic_type
== CHIP_ARCTURUS
) {
4471 vgpr_init_shader_ptr
= vgpr_init_compute_shader_arcturus
;
4472 vgpr_init_shader_size
= sizeof(vgpr_init_compute_shader_arcturus
);
4473 vgpr_init_regs_ptr
= vgpr_init_regs_arcturus
;
4475 vgpr_init_shader_ptr
= vgpr_init_compute_shader
;
4476 vgpr_init_shader_size
= sizeof(vgpr_init_compute_shader
);
4477 vgpr_init_regs_ptr
= vgpr_init_regs
;
4481 (gpr_reg_size
* 3 + 4 + 5 + 2) * 4; /* VGPRS */
4483 (gpr_reg_size
* 3 + 4 + 5 + 2) * 4; /* SGPRS1 */
4485 (gpr_reg_size
* 3 + 4 + 5 + 2) * 4; /* SGPRS2 */
4486 total_size
= ALIGN(total_size
, 256);
4487 vgpr_offset
= total_size
;
4488 total_size
+= ALIGN(vgpr_init_shader_size
, 256);
4489 sgpr_offset
= total_size
;
4490 total_size
+= sizeof(sgpr_init_compute_shader
);
4492 /* allocate an indirect buffer to put the commands in */
4493 memset(&ib
, 0, sizeof(ib
));
4494 r
= amdgpu_ib_get(adev
, NULL
, total_size
, &ib
);
4496 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r
);
4500 /* load the compute shaders */
4501 for (i
= 0; i
< vgpr_init_shader_size
/sizeof(u32
); i
++)
4502 ib
.ptr
[i
+ (vgpr_offset
/ 4)] = vgpr_init_shader_ptr
[i
];
4504 for (i
= 0; i
< ARRAY_SIZE(sgpr_init_compute_shader
); i
++)
4505 ib
.ptr
[i
+ (sgpr_offset
/ 4)] = sgpr_init_compute_shader
[i
];
4507 /* init the ib length to 0 */
4511 /* write the register state for the compute dispatch */
4512 for (i
= 0; i
< gpr_reg_size
; i
++) {
4513 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_SET_SH_REG
, 1);
4514 ib
.ptr
[ib
.length_dw
++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr
[i
])
4515 - PACKET3_SET_SH_REG_START
;
4516 ib
.ptr
[ib
.length_dw
++] = vgpr_init_regs_ptr
[i
].reg_value
;
4518 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4519 gpu_addr
= (ib
.gpu_addr
+ (u64
)vgpr_offset
) >> 8;
4520 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_SET_SH_REG
, 2);
4521 ib
.ptr
[ib
.length_dw
++] = SOC15_REG_OFFSET(GC
, 0, mmCOMPUTE_PGM_LO
)
4522 - PACKET3_SET_SH_REG_START
;
4523 ib
.ptr
[ib
.length_dw
++] = lower_32_bits(gpu_addr
);
4524 ib
.ptr
[ib
.length_dw
++] = upper_32_bits(gpu_addr
);
4526 /* write dispatch packet */
4527 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_DISPATCH_DIRECT
, 3);
4528 ib
.ptr
[ib
.length_dw
++] = compute_dim_x
* 2; /* x */
4529 ib
.ptr
[ib
.length_dw
++] = 1; /* y */
4530 ib
.ptr
[ib
.length_dw
++] = 1; /* z */
4531 ib
.ptr
[ib
.length_dw
++] =
4532 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR
, COMPUTE_SHADER_EN
, 1);
4534 /* write CS partial flush packet */
4535 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_EVENT_WRITE
, 0);
4536 ib
.ptr
[ib
.length_dw
++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4539 /* write the register state for the compute dispatch */
4540 for (i
= 0; i
< gpr_reg_size
; i
++) {
4541 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_SET_SH_REG
, 1);
4542 ib
.ptr
[ib
.length_dw
++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs
[i
])
4543 - PACKET3_SET_SH_REG_START
;
4544 ib
.ptr
[ib
.length_dw
++] = sgpr1_init_regs
[i
].reg_value
;
4546 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4547 gpu_addr
= (ib
.gpu_addr
+ (u64
)sgpr_offset
) >> 8;
4548 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_SET_SH_REG
, 2);
4549 ib
.ptr
[ib
.length_dw
++] = SOC15_REG_OFFSET(GC
, 0, mmCOMPUTE_PGM_LO
)
4550 - PACKET3_SET_SH_REG_START
;
4551 ib
.ptr
[ib
.length_dw
++] = lower_32_bits(gpu_addr
);
4552 ib
.ptr
[ib
.length_dw
++] = upper_32_bits(gpu_addr
);
4554 /* write dispatch packet */
4555 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_DISPATCH_DIRECT
, 3);
4556 ib
.ptr
[ib
.length_dw
++] = compute_dim_x
/ 2 * sgpr_work_group_size
; /* x */
4557 ib
.ptr
[ib
.length_dw
++] = 1; /* y */
4558 ib
.ptr
[ib
.length_dw
++] = 1; /* z */
4559 ib
.ptr
[ib
.length_dw
++] =
4560 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR
, COMPUTE_SHADER_EN
, 1);
4562 /* write CS partial flush packet */
4563 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_EVENT_WRITE
, 0);
4564 ib
.ptr
[ib
.length_dw
++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4567 /* write the register state for the compute dispatch */
4568 for (i
= 0; i
< gpr_reg_size
; i
++) {
4569 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_SET_SH_REG
, 1);
4570 ib
.ptr
[ib
.length_dw
++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs
[i
])
4571 - PACKET3_SET_SH_REG_START
;
4572 ib
.ptr
[ib
.length_dw
++] = sgpr2_init_regs
[i
].reg_value
;
4574 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4575 gpu_addr
= (ib
.gpu_addr
+ (u64
)sgpr_offset
) >> 8;
4576 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_SET_SH_REG
, 2);
4577 ib
.ptr
[ib
.length_dw
++] = SOC15_REG_OFFSET(GC
, 0, mmCOMPUTE_PGM_LO
)
4578 - PACKET3_SET_SH_REG_START
;
4579 ib
.ptr
[ib
.length_dw
++] = lower_32_bits(gpu_addr
);
4580 ib
.ptr
[ib
.length_dw
++] = upper_32_bits(gpu_addr
);
4582 /* write dispatch packet */
4583 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_DISPATCH_DIRECT
, 3);
4584 ib
.ptr
[ib
.length_dw
++] = compute_dim_x
/ 2 * sgpr_work_group_size
; /* x */
4585 ib
.ptr
[ib
.length_dw
++] = 1; /* y */
4586 ib
.ptr
[ib
.length_dw
++] = 1; /* z */
4587 ib
.ptr
[ib
.length_dw
++] =
4588 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR
, COMPUTE_SHADER_EN
, 1);
4590 /* write CS partial flush packet */
4591 ib
.ptr
[ib
.length_dw
++] = PACKET3(PACKET3_EVENT_WRITE
, 0);
4592 ib
.ptr
[ib
.length_dw
++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4594 /* shedule the ib on the ring */
4595 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, &f
);
4597 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r
);
4601 /* wait for the GPU to finish processing the IB */
4602 r
= dma_fence_wait(f
, false);
4604 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
4609 amdgpu_ib_free(adev
, &ib
, NULL
);
4615 static int gfx_v9_0_early_init(void *handle
)
4617 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4619 if (adev
->asic_type
== CHIP_ARCTURUS
)
4620 adev
->gfx
.num_gfx_rings
= 0;
4622 adev
->gfx
.num_gfx_rings
= GFX9_NUM_GFX_RINGS
;
4623 adev
->gfx
.num_compute_rings
= AMDGPU_MAX_COMPUTE_RINGS
;
4624 gfx_v9_0_set_kiq_pm4_funcs(adev
);
4625 gfx_v9_0_set_ring_funcs(adev
);
4626 gfx_v9_0_set_irq_funcs(adev
);
4627 gfx_v9_0_set_gds_init(adev
);
4628 gfx_v9_0_set_rlc_funcs(adev
);
4633 static int gfx_v9_0_ecc_late_init(void *handle
)
4635 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4639 * Temp workaround to fix the issue that CP firmware fails to
4640 * update read pointer when CPDMA is writing clearing operation
4641 * to GDS in suspend/resume sequence on several cards. So just
4642 * limit this operation in cold boot sequence.
4644 if (!adev
->in_suspend
) {
4645 r
= gfx_v9_0_do_edc_gds_workarounds(adev
);
4650 /* requires IBs so do in late init after IB pool is initialized */
4651 r
= gfx_v9_0_do_edc_gpr_workarounds(adev
);
4655 if (adev
->gfx
.funcs
&&
4656 adev
->gfx
.funcs
->reset_ras_error_count
)
4657 adev
->gfx
.funcs
->reset_ras_error_count(adev
);
4659 r
= amdgpu_gfx_ras_late_init(adev
);
4666 static int gfx_v9_0_late_init(void *handle
)
4668 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
4671 r
= amdgpu_irq_get(adev
, &adev
->gfx
.priv_reg_irq
, 0);
4675 r
= amdgpu_irq_get(adev
, &adev
->gfx
.priv_inst_irq
, 0);
4679 r
= gfx_v9_0_ecc_late_init(handle
);
4686 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device
*adev
)
4688 uint32_t rlc_setting
;
4690 /* if RLC is not enabled, do nothing */
4691 rlc_setting
= RREG32_SOC15(GC
, 0, mmRLC_CNTL
);
4692 if (!(rlc_setting
& RLC_CNTL__RLC_ENABLE_F32_MASK
))
4698 static void gfx_v9_0_set_safe_mode(struct amdgpu_device
*adev
)
4703 data
= RLC_SAFE_MODE__CMD_MASK
;
4704 data
|= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT
);
4705 WREG32_SOC15(GC
, 0, mmRLC_SAFE_MODE
, data
);
4707 /* wait for RLC_SAFE_MODE */
4708 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
4709 if (!REG_GET_FIELD(RREG32_SOC15(GC
, 0, mmRLC_SAFE_MODE
), RLC_SAFE_MODE
, CMD
))
4715 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device
*adev
)
4719 data
= RLC_SAFE_MODE__CMD_MASK
;
4720 WREG32_SOC15(GC
, 0, mmRLC_SAFE_MODE
, data
);
4723 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device
*adev
,
4726 amdgpu_gfx_rlc_enter_safe_mode(adev
);
4728 if ((adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PG
) && enable
) {
4729 gfx_v9_0_enable_gfx_cg_power_gating(adev
, true);
4730 if (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PIPELINE
)
4731 gfx_v9_0_enable_gfx_pipeline_powergating(adev
, true);
4733 gfx_v9_0_enable_gfx_cg_power_gating(adev
, false);
4734 if (adev
->pg_flags
& AMD_PG_SUPPORT_GFX_PIPELINE
)
4735 gfx_v9_0_enable_gfx_pipeline_powergating(adev
, false);
4738 amdgpu_gfx_rlc_exit_safe_mode(adev
);
4741 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device
*adev
,
4744 /* TODO: double check if we need to perform under safe mode */
4745 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
4747 if ((adev
->pg_flags
& AMD_PG_SUPPORT_GFX_SMG
) && enable
)
4748 gfx_v9_0_enable_gfx_static_mg_power_gating(adev
, true);
4750 gfx_v9_0_enable_gfx_static_mg_power_gating(adev
, false);
4752 if ((adev
->pg_flags
& AMD_PG_SUPPORT_GFX_DMG
) && enable
)
4753 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev
, true);
4755 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev
, false);
4757 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
4760 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device
*adev
,
4765 amdgpu_gfx_rlc_enter_safe_mode(adev
);
4767 /* It is disabled by HW by default */
4768 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_MGCG
)) {
4769 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4770 def
= data
= RREG32_SOC15(GC
, 0, mmRLC_CGTT_MGCG_OVERRIDE
);
4772 if (adev
->asic_type
!= CHIP_VEGA12
)
4773 data
&= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK
;
4775 data
&= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK
|
4776 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK
|
4777 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK
);
4779 /* only for Vega10 & Raven1 */
4780 data
|= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK
;
4783 WREG32_SOC15(GC
, 0, mmRLC_CGTT_MGCG_OVERRIDE
, data
);
4785 /* MGLS is a global flag to control all MGLS in GFX */
4786 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_MGLS
) {
4787 /* 2 - RLC memory Light sleep */
4788 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_RLC_LS
) {
4789 def
= data
= RREG32_SOC15(GC
, 0, mmRLC_MEM_SLP_CNTL
);
4790 data
|= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
;
4792 WREG32_SOC15(GC
, 0, mmRLC_MEM_SLP_CNTL
, data
);
4794 /* 3 - CP memory Light sleep */
4795 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CP_LS
) {
4796 def
= data
= RREG32_SOC15(GC
, 0, mmCP_MEM_SLP_CNTL
);
4797 data
|= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
;
4799 WREG32_SOC15(GC
, 0, mmCP_MEM_SLP_CNTL
, data
);
4803 /* 1 - MGCG_OVERRIDE */
4804 def
= data
= RREG32_SOC15(GC
, 0, mmRLC_CGTT_MGCG_OVERRIDE
);
4806 if (adev
->asic_type
!= CHIP_VEGA12
)
4807 data
|= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK
;
4809 data
|= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK
|
4810 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK
|
4811 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK
|
4812 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK
);
4815 WREG32_SOC15(GC
, 0, mmRLC_CGTT_MGCG_OVERRIDE
, data
);
4817 /* 2 - disable MGLS in RLC */
4818 data
= RREG32_SOC15(GC
, 0, mmRLC_MEM_SLP_CNTL
);
4819 if (data
& RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
) {
4820 data
&= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
;
4821 WREG32_SOC15(GC
, 0, mmRLC_MEM_SLP_CNTL
, data
);
4824 /* 3 - disable MGLS in CP */
4825 data
= RREG32_SOC15(GC
, 0, mmCP_MEM_SLP_CNTL
);
4826 if (data
& CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
) {
4827 data
&= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
;
4828 WREG32_SOC15(GC
, 0, mmCP_MEM_SLP_CNTL
, data
);
4832 amdgpu_gfx_rlc_exit_safe_mode(adev
);
4835 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device
*adev
,
4840 if (adev
->asic_type
== CHIP_ARCTURUS
)
4843 amdgpu_gfx_rlc_enter_safe_mode(adev
);
4845 /* Enable 3D CGCG/CGLS */
4846 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_3D_CGCG
)) {
4847 /* write cmd to clear cgcg/cgls ov */
4848 def
= data
= RREG32_SOC15(GC
, 0, mmRLC_CGTT_MGCG_OVERRIDE
);
4849 /* unset CGCG override */
4850 data
&= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK
;
4851 /* update CGCG and CGLS override bits */
4853 WREG32_SOC15(GC
, 0, mmRLC_CGTT_MGCG_OVERRIDE
, data
);
4855 /* enable 3Dcgcg FSM(0x0000363f) */
4856 def
= RREG32_SOC15(GC
, 0, mmRLC_CGCG_CGLS_CTRL_3D
);
4858 data
= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT
) |
4859 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK
;
4860 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_3D_CGLS
)
4861 data
|= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT
) |
4862 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK
;
4864 WREG32_SOC15(GC
, 0, mmRLC_CGCG_CGLS_CTRL_3D
, data
);
4866 /* set IDLE_POLL_COUNT(0x00900100) */
4867 def
= RREG32_SOC15(GC
, 0, mmCP_RB_WPTR_POLL_CNTL
);
4868 data
= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT
) |
4869 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
);
4871 WREG32_SOC15(GC
, 0, mmCP_RB_WPTR_POLL_CNTL
, data
);
4873 /* Disable CGCG/CGLS */
4874 def
= data
= RREG32_SOC15(GC
, 0, mmRLC_CGCG_CGLS_CTRL_3D
);
4875 /* disable cgcg, cgls should be disabled */
4876 data
&= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK
|
4877 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK
);
4878 /* disable cgcg and cgls in FSM */
4880 WREG32_SOC15(GC
, 0, mmRLC_CGCG_CGLS_CTRL_3D
, data
);
4883 amdgpu_gfx_rlc_exit_safe_mode(adev
);
4886 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device
*adev
,
4891 amdgpu_gfx_rlc_enter_safe_mode(adev
);
4893 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CGCG
)) {
4894 def
= data
= RREG32_SOC15(GC
, 0, mmRLC_CGTT_MGCG_OVERRIDE
);
4895 /* unset CGCG override */
4896 data
&= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK
;
4897 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CGLS
)
4898 data
&= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK
;
4900 data
|= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK
;
4901 /* update CGCG and CGLS override bits */
4903 WREG32_SOC15(GC
, 0, mmRLC_CGTT_MGCG_OVERRIDE
, data
);
4905 /* enable cgcg FSM(0x0000363F) */
4906 def
= RREG32_SOC15(GC
, 0, mmRLC_CGCG_CGLS_CTRL
);
4908 if (adev
->asic_type
== CHIP_ARCTURUS
)
4909 data
= (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT
) |
4910 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
;
4912 data
= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT
) |
4913 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
;
4914 if (adev
->cg_flags
& AMD_CG_SUPPORT_GFX_CGLS
)
4915 data
|= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT
) |
4916 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
;
4918 WREG32_SOC15(GC
, 0, mmRLC_CGCG_CGLS_CTRL
, data
);
4920 /* set IDLE_POLL_COUNT(0x00900100) */
4921 def
= RREG32_SOC15(GC
, 0, mmCP_RB_WPTR_POLL_CNTL
);
4922 data
= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT
) |
4923 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
);
4925 WREG32_SOC15(GC
, 0, mmCP_RB_WPTR_POLL_CNTL
, data
);
4927 def
= data
= RREG32_SOC15(GC
, 0, mmRLC_CGCG_CGLS_CTRL
);
4928 /* reset CGCG/CGLS bits */
4929 data
&= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
| RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
);
4930 /* disable cgcg and cgls in FSM */
4932 WREG32_SOC15(GC
, 0, mmRLC_CGCG_CGLS_CTRL
, data
);
4935 amdgpu_gfx_rlc_exit_safe_mode(adev
);
4938 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device
*adev
,
4942 /* CGCG/CGLS should be enabled after MGCG/MGLS
4943 * === MGCG + MGLS ===
4945 gfx_v9_0_update_medium_grain_clock_gating(adev
, enable
);
4946 /* === CGCG /CGLS for GFX 3D Only === */
4947 gfx_v9_0_update_3d_clock_gating(adev
, enable
);
4948 /* === CGCG + CGLS === */
4949 gfx_v9_0_update_coarse_grain_clock_gating(adev
, enable
);
4951 /* CGCG/CGLS should be disabled before MGCG/MGLS
4952 * === CGCG + CGLS ===
4954 gfx_v9_0_update_coarse_grain_clock_gating(adev
, enable
);
4955 /* === CGCG /CGLS for GFX 3D Only === */
4956 gfx_v9_0_update_3d_clock_gating(adev
, enable
);
4957 /* === MGCG + MGLS === */
4958 gfx_v9_0_update_medium_grain_clock_gating(adev
, enable
);
4963 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device
*adev
, unsigned vmid
)
4967 data
= RREG32_SOC15(GC
, 0, mmRLC_SPM_MC_CNTL
);
4969 data
&= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK
;
4970 data
|= (vmid
& RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK
) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT
;
4972 WREG32_SOC15(GC
, 0, mmRLC_SPM_MC_CNTL
, data
);
4975 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device
*adev
,
4977 struct soc15_reg_rlcg
*entries
, int arr_size
)
4985 for (i
= 0; i
< arr_size
; i
++) {
4986 const struct soc15_reg_rlcg
*entry
;
4988 entry
= &entries
[i
];
4989 reg
= adev
->reg_offset
[entry
->hwip
][entry
->instance
][entry
->segment
] + entry
->reg
;
4997 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device
*adev
, u32 offset
)
4999 return gfx_v9_0_check_rlcg_range(adev
, offset
,
5000 (void *)rlcg_access_gc_9_0
,
5001 ARRAY_SIZE(rlcg_access_gc_9_0
));
5004 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs
= {
5005 .is_rlc_enabled
= gfx_v9_0_is_rlc_enabled
,
5006 .set_safe_mode
= gfx_v9_0_set_safe_mode
,
5007 .unset_safe_mode
= gfx_v9_0_unset_safe_mode
,
5008 .init
= gfx_v9_0_rlc_init
,
5009 .get_csb_size
= gfx_v9_0_get_csb_size
,
5010 .get_csb_buffer
= gfx_v9_0_get_csb_buffer
,
5011 .get_cp_table_num
= gfx_v9_0_cp_jump_table_num
,
5012 .resume
= gfx_v9_0_rlc_resume
,
5013 .stop
= gfx_v9_0_rlc_stop
,
5014 .reset
= gfx_v9_0_rlc_reset
,
5015 .start
= gfx_v9_0_rlc_start
,
5016 .update_spm_vmid
= gfx_v9_0_update_spm_vmid
,
5017 .rlcg_wreg
= gfx_v9_0_rlcg_wreg
,
5018 .is_rlcg_access_range
= gfx_v9_0_is_rlcg_access_range
,
5021 static int gfx_v9_0_set_powergating_state(void *handle
,
5022 enum amd_powergating_state state
)
5024 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
5025 bool enable
= (state
== AMD_PG_STATE_GATE
);
5027 switch (adev
->asic_type
) {
5031 amdgpu_gfx_off_ctrl(adev
, false);
5033 if (adev
->pg_flags
& AMD_PG_SUPPORT_RLC_SMU_HS
) {
5034 gfx_v9_0_enable_sck_slow_down_on_power_up(adev
, true);
5035 gfx_v9_0_enable_sck_slow_down_on_power_down(adev
, true);
5037 gfx_v9_0_enable_sck_slow_down_on_power_up(adev
, false);
5038 gfx_v9_0_enable_sck_slow_down_on_power_down(adev
, false);
5041 if (adev
->pg_flags
& AMD_PG_SUPPORT_CP
)
5042 gfx_v9_0_enable_cp_power_gating(adev
, true);
5044 gfx_v9_0_enable_cp_power_gating(adev
, false);
5046 /* update gfx cgpg state */
5047 gfx_v9_0_update_gfx_cg_power_gating(adev
, enable
);
5049 /* update mgcg state */
5050 gfx_v9_0_update_gfx_mg_power_gating(adev
, enable
);
5053 amdgpu_gfx_off_ctrl(adev
, true);
5056 amdgpu_gfx_off_ctrl(adev
, enable
);
5065 static int gfx_v9_0_set_clockgating_state(void *handle
,
5066 enum amd_clockgating_state state
)
5068 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
5070 if (amdgpu_sriov_vf(adev
))
5073 switch (adev
->asic_type
) {
5080 gfx_v9_0_update_gfx_clock_gating(adev
,
5081 state
== AMD_CG_STATE_GATE
);
5089 static void gfx_v9_0_get_clockgating_state(void *handle
, u32
*flags
)
5091 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
5094 if (amdgpu_sriov_vf(adev
))
5097 /* AMD_CG_SUPPORT_GFX_MGCG */
5098 data
= RREG32_KIQ(SOC15_REG_OFFSET(GC
, 0, mmRLC_CGTT_MGCG_OVERRIDE
));
5099 if (!(data
& RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK
))
5100 *flags
|= AMD_CG_SUPPORT_GFX_MGCG
;
5102 /* AMD_CG_SUPPORT_GFX_CGCG */
5103 data
= RREG32_KIQ(SOC15_REG_OFFSET(GC
, 0, mmRLC_CGCG_CGLS_CTRL
));
5104 if (data
& RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
)
5105 *flags
|= AMD_CG_SUPPORT_GFX_CGCG
;
5107 /* AMD_CG_SUPPORT_GFX_CGLS */
5108 if (data
& RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
)
5109 *flags
|= AMD_CG_SUPPORT_GFX_CGLS
;
5111 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5112 data
= RREG32_KIQ(SOC15_REG_OFFSET(GC
, 0, mmRLC_MEM_SLP_CNTL
));
5113 if (data
& RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
)
5114 *flags
|= AMD_CG_SUPPORT_GFX_RLC_LS
| AMD_CG_SUPPORT_GFX_MGLS
;
5116 /* AMD_CG_SUPPORT_GFX_CP_LS */
5117 data
= RREG32_KIQ(SOC15_REG_OFFSET(GC
, 0, mmCP_MEM_SLP_CNTL
));
5118 if (data
& CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK
)
5119 *flags
|= AMD_CG_SUPPORT_GFX_CP_LS
| AMD_CG_SUPPORT_GFX_MGLS
;
5121 if (adev
->asic_type
!= CHIP_ARCTURUS
) {
5122 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5123 data
= RREG32_KIQ(SOC15_REG_OFFSET(GC
, 0, mmRLC_CGCG_CGLS_CTRL_3D
));
5124 if (data
& RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK
)
5125 *flags
|= AMD_CG_SUPPORT_GFX_3D_CGCG
;
5127 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
5128 if (data
& RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK
)
5129 *flags
|= AMD_CG_SUPPORT_GFX_3D_CGLS
;
5133 static u64
gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring
*ring
)
5135 return ring
->adev
->wb
.wb
[ring
->rptr_offs
]; /* gfx9 is 32bit rptr*/
5138 static u64
gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring
*ring
)
5140 struct amdgpu_device
*adev
= ring
->adev
;
5143 /* XXX check if swapping is necessary on BE */
5144 if (ring
->use_doorbell
) {
5145 wptr
= atomic64_read((atomic64_t
*)&adev
->wb
.wb
[ring
->wptr_offs
]);
5147 wptr
= RREG32_SOC15(GC
, 0, mmCP_RB0_WPTR
);
5148 wptr
+= (u64
)RREG32_SOC15(GC
, 0, mmCP_RB0_WPTR_HI
) << 32;
5154 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring
*ring
)
5156 struct amdgpu_device
*adev
= ring
->adev
;
5158 if (ring
->use_doorbell
) {
5159 /* XXX check if swapping is necessary on BE */
5160 atomic64_set((atomic64_t
*)&adev
->wb
.wb
[ring
->wptr_offs
], ring
->wptr
);
5161 WDOORBELL64(ring
->doorbell_index
, ring
->wptr
);
5163 WREG32_SOC15(GC
, 0, mmCP_RB0_WPTR
, lower_32_bits(ring
->wptr
));
5164 WREG32_SOC15(GC
, 0, mmCP_RB0_WPTR_HI
, upper_32_bits(ring
->wptr
));
5168 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
5170 struct amdgpu_device
*adev
= ring
->adev
;
5171 u32 ref_and_mask
, reg_mem_engine
;
5172 const struct nbio_hdp_flush_reg
*nbio_hf_reg
= adev
->nbio
.hdp_flush_reg
;
5174 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_COMPUTE
) {
5177 ref_and_mask
= nbio_hf_reg
->ref_and_mask_cp2
<< ring
->pipe
;
5180 ref_and_mask
= nbio_hf_reg
->ref_and_mask_cp6
<< ring
->pipe
;
5187 ref_and_mask
= nbio_hf_reg
->ref_and_mask_cp0
;
5188 reg_mem_engine
= 1; /* pfp */
5191 gfx_v9_0_wait_reg_mem(ring
, reg_mem_engine
, 0, 1,
5192 adev
->nbio
.funcs
->get_hdp_flush_req_offset(adev
),
5193 adev
->nbio
.funcs
->get_hdp_flush_done_offset(adev
),
5194 ref_and_mask
, ref_and_mask
, 0x20);
5197 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring
*ring
,
5198 struct amdgpu_job
*job
,
5199 struct amdgpu_ib
*ib
,
5202 unsigned vmid
= AMDGPU_JOB_GET_VMID(job
);
5203 u32 header
, control
= 0;
5205 if (ib
->flags
& AMDGPU_IB_FLAG_CE
)
5206 header
= PACKET3(PACKET3_INDIRECT_BUFFER_CONST
, 2);
5208 header
= PACKET3(PACKET3_INDIRECT_BUFFER
, 2);
5210 control
|= ib
->length_dw
| (vmid
<< 24);
5212 if (amdgpu_sriov_vf(ring
->adev
) && (ib
->flags
& AMDGPU_IB_FLAG_PREEMPT
)) {
5213 control
|= INDIRECT_BUFFER_PRE_ENB(1);
5215 if (!(ib
->flags
& AMDGPU_IB_FLAG_CE
) && vmid
)
5216 gfx_v9_0_ring_emit_de_meta(ring
);
5219 amdgpu_ring_write(ring
, header
);
5220 BUG_ON(ib
->gpu_addr
& 0x3); /* Dword align */
5221 amdgpu_ring_write(ring
,
5225 lower_32_bits(ib
->gpu_addr
));
5226 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
5227 amdgpu_ring_write(ring
, control
);
5230 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring
*ring
,
5231 struct amdgpu_job
*job
,
5232 struct amdgpu_ib
*ib
,
5235 unsigned vmid
= AMDGPU_JOB_GET_VMID(job
);
5236 u32 control
= INDIRECT_BUFFER_VALID
| ib
->length_dw
| (vmid
<< 24);
5238 /* Currently, there is a high possibility to get wave ID mismatch
5239 * between ME and GDS, leading to a hw deadlock, because ME generates
5240 * different wave IDs than the GDS expects. This situation happens
5241 * randomly when at least 5 compute pipes use GDS ordered append.
5242 * The wave IDs generated by ME are also wrong after suspend/resume.
5243 * Those are probably bugs somewhere else in the kernel driver.
5245 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5246 * GDS to 0 for this ring (me/pipe).
5248 if (ib
->flags
& AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
) {
5249 amdgpu_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
5250 amdgpu_ring_write(ring
, mmGDS_COMPUTE_MAX_WAVE_ID
);
5251 amdgpu_ring_write(ring
, ring
->adev
->gds
.gds_compute_max_wave_id
);
5254 amdgpu_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
5255 BUG_ON(ib
->gpu_addr
& 0x3); /* Dword align */
5256 amdgpu_ring_write(ring
,
5260 lower_32_bits(ib
->gpu_addr
));
5261 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
5262 amdgpu_ring_write(ring
, control
);
5265 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
,
5266 u64 seq
, unsigned flags
)
5268 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
5269 bool int_sel
= flags
& AMDGPU_FENCE_FLAG_INT
;
5270 bool writeback
= flags
& AMDGPU_FENCE_FLAG_TC_WB_ONLY
;
5272 /* RELEASE_MEM - flush caches, send int */
5273 amdgpu_ring_write(ring
, PACKET3(PACKET3_RELEASE_MEM
, 6));
5274 amdgpu_ring_write(ring
, ((writeback
? (EOP_TC_WB_ACTION_EN
|
5275 EOP_TC_NC_ACTION_EN
) :
5276 (EOP_TCL1_ACTION_EN
|
5278 EOP_TC_WB_ACTION_EN
|
5279 EOP_TC_MD_ACTION_EN
)) |
5280 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT
) |
5282 amdgpu_ring_write(ring
, DATA_SEL(write64bit
? 2 : 1) | INT_SEL(int_sel
? 2 : 0));
5285 * the address should be Qword aligned if 64bit write, Dword
5286 * aligned if only send 32bit data low (discard data high)
5292 amdgpu_ring_write(ring
, lower_32_bits(addr
));
5293 amdgpu_ring_write(ring
, upper_32_bits(addr
));
5294 amdgpu_ring_write(ring
, lower_32_bits(seq
));
5295 amdgpu_ring_write(ring
, upper_32_bits(seq
));
5296 amdgpu_ring_write(ring
, 0);
5299 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
5301 int usepfp
= (ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
);
5302 uint32_t seq
= ring
->fence_drv
.sync_seq
;
5303 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
5305 gfx_v9_0_wait_reg_mem(ring
, usepfp
, 1, 0,
5306 lower_32_bits(addr
), upper_32_bits(addr
),
5307 seq
, 0xffffffff, 4);
5310 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
5311 unsigned vmid
, uint64_t pd_addr
)
5313 amdgpu_gmc_emit_flush_gpu_tlb(ring
, vmid
, pd_addr
);
5315 /* compute doesn't have PFP */
5316 if (ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
) {
5317 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5318 amdgpu_ring_write(ring
, PACKET3(PACKET3_PFP_SYNC_ME
, 0));
5319 amdgpu_ring_write(ring
, 0x0);
5323 static u64
gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring
*ring
)
5325 return ring
->adev
->wb
.wb
[ring
->rptr_offs
]; /* gfx9 hardware is 32bit rptr */
5328 static u64
gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring
*ring
)
5332 /* XXX check if swapping is necessary on BE */
5333 if (ring
->use_doorbell
)
5334 wptr
= atomic64_read((atomic64_t
*)&ring
->adev
->wb
.wb
[ring
->wptr_offs
]);
5340 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring
*ring
)
5342 struct amdgpu_device
*adev
= ring
->adev
;
5344 /* XXX check if swapping is necessary on BE */
5345 if (ring
->use_doorbell
) {
5346 atomic64_set((atomic64_t
*)&adev
->wb
.wb
[ring
->wptr_offs
], ring
->wptr
);
5347 WDOORBELL64(ring
->doorbell_index
, ring
->wptr
);
5349 BUG(); /* only DOORBELL method supported on gfx9 now */
5353 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring
*ring
, u64 addr
,
5354 u64 seq
, unsigned int flags
)
5356 struct amdgpu_device
*adev
= ring
->adev
;
5358 /* we only allocate 32bit for each seq wb address */
5359 BUG_ON(flags
& AMDGPU_FENCE_FLAG_64BIT
);
5361 /* write fence seq to the "addr" */
5362 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
5363 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
5364 WRITE_DATA_DST_SEL(5) | WR_CONFIRM
));
5365 amdgpu_ring_write(ring
, lower_32_bits(addr
));
5366 amdgpu_ring_write(ring
, upper_32_bits(addr
));
5367 amdgpu_ring_write(ring
, lower_32_bits(seq
));
5369 if (flags
& AMDGPU_FENCE_FLAG_INT
) {
5370 /* set register to trigger INT */
5371 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
5372 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
5373 WRITE_DATA_DST_SEL(0) | WR_CONFIRM
));
5374 amdgpu_ring_write(ring
, SOC15_REG_OFFSET(GC
, 0, mmCPC_INT_STATUS
));
5375 amdgpu_ring_write(ring
, 0);
5376 amdgpu_ring_write(ring
, 0x20000000); /* src_id is 178 */
5380 static void gfx_v9_ring_emit_sb(struct amdgpu_ring
*ring
)
5382 amdgpu_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
5383 amdgpu_ring_write(ring
, 0);
5386 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring
*ring
)
5388 struct v9_ce_ib_state ce_payload
= {0};
5392 cnt
= (sizeof(ce_payload
) >> 2) + 4 - 2;
5393 csa_addr
= amdgpu_csa_vaddr(ring
->adev
);
5395 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, cnt
));
5396 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(2) |
5397 WRITE_DATA_DST_SEL(8) |
5399 WRITE_DATA_CACHE_POLICY(0));
5400 amdgpu_ring_write(ring
, lower_32_bits(csa_addr
+ offsetof(struct v9_gfx_meta_data
, ce_payload
)));
5401 amdgpu_ring_write(ring
, upper_32_bits(csa_addr
+ offsetof(struct v9_gfx_meta_data
, ce_payload
)));
5402 amdgpu_ring_write_multiple(ring
, (void *)&ce_payload
, sizeof(ce_payload
) >> 2);
5405 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring
*ring
)
5407 struct v9_de_ib_state de_payload
= {0};
5408 uint64_t csa_addr
, gds_addr
;
5411 csa_addr
= amdgpu_csa_vaddr(ring
->adev
);
5412 gds_addr
= csa_addr
+ 4096;
5413 de_payload
.gds_backup_addrlo
= lower_32_bits(gds_addr
);
5414 de_payload
.gds_backup_addrhi
= upper_32_bits(gds_addr
);
5416 cnt
= (sizeof(de_payload
) >> 2) + 4 - 2;
5417 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, cnt
));
5418 amdgpu_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(1) |
5419 WRITE_DATA_DST_SEL(8) |
5421 WRITE_DATA_CACHE_POLICY(0));
5422 amdgpu_ring_write(ring
, lower_32_bits(csa_addr
+ offsetof(struct v9_gfx_meta_data
, de_payload
)));
5423 amdgpu_ring_write(ring
, upper_32_bits(csa_addr
+ offsetof(struct v9_gfx_meta_data
, de_payload
)));
5424 amdgpu_ring_write_multiple(ring
, (void *)&de_payload
, sizeof(de_payload
) >> 2);
5427 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring
*ring
, bool start
)
5429 amdgpu_ring_write(ring
, PACKET3(PACKET3_FRAME_CONTROL
, 0));
5430 amdgpu_ring_write(ring
, FRAME_CMD(start
? 0 : 1)); /* frame_end */
5433 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring
*ring
, uint32_t flags
)
5437 if (amdgpu_sriov_vf(ring
->adev
))
5438 gfx_v9_0_ring_emit_ce_meta(ring
);
5440 gfx_v9_0_ring_emit_tmz(ring
, true);
5442 dw2
|= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5443 if (flags
& AMDGPU_HAVE_CTX_SWITCH
) {
5444 /* set load_global_config & load_global_uconfig */
5446 /* set load_cs_sh_regs */
5448 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5451 /* set load_ce_ram if preamble presented */
5452 if (AMDGPU_PREAMBLE_IB_PRESENT
& flags
)
5455 /* still load_ce_ram if this is the first time preamble presented
5456 * although there is no context switch happens.
5458 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST
& flags
)
5462 amdgpu_ring_write(ring
, PACKET3(PACKET3_CONTEXT_CONTROL
, 1));
5463 amdgpu_ring_write(ring
, dw2
);
5464 amdgpu_ring_write(ring
, 0);
5467 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring
*ring
)
5470 amdgpu_ring_write(ring
, PACKET3(PACKET3_COND_EXEC
, 3));
5471 amdgpu_ring_write(ring
, lower_32_bits(ring
->cond_exe_gpu_addr
));
5472 amdgpu_ring_write(ring
, upper_32_bits(ring
->cond_exe_gpu_addr
));
5473 amdgpu_ring_write(ring
, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5474 ret
= ring
->wptr
& ring
->buf_mask
;
5475 amdgpu_ring_write(ring
, 0x55aa55aa); /* patch dummy value later */
5479 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring
*ring
, unsigned offset
)
5482 BUG_ON(offset
> ring
->buf_mask
);
5483 BUG_ON(ring
->ring
[offset
] != 0x55aa55aa);
5485 cur
= (ring
->wptr
& ring
->buf_mask
) - 1;
5486 if (likely(cur
> offset
))
5487 ring
->ring
[offset
] = cur
- offset
;
5489 ring
->ring
[offset
] = (ring
->ring_size
>>2) - offset
+ cur
;
5492 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring
*ring
, uint32_t reg
)
5494 struct amdgpu_device
*adev
= ring
->adev
;
5495 struct amdgpu_kiq
*kiq
= &adev
->gfx
.kiq
;
5497 amdgpu_ring_write(ring
, PACKET3(PACKET3_COPY_DATA
, 4));
5498 amdgpu_ring_write(ring
, 0 | /* src: register*/
5499 (5 << 8) | /* dst: memory */
5500 (1 << 20)); /* write confirm */
5501 amdgpu_ring_write(ring
, reg
);
5502 amdgpu_ring_write(ring
, 0);
5503 amdgpu_ring_write(ring
, lower_32_bits(adev
->wb
.gpu_addr
+
5504 kiq
->reg_val_offs
* 4));
5505 amdgpu_ring_write(ring
, upper_32_bits(adev
->wb
.gpu_addr
+
5506 kiq
->reg_val_offs
* 4));
5509 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring
*ring
, uint32_t reg
,
5514 switch (ring
->funcs
->type
) {
5515 case AMDGPU_RING_TYPE_GFX
:
5516 cmd
= WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM
;
5518 case AMDGPU_RING_TYPE_KIQ
:
5519 cmd
= (1 << 16); /* no inc addr */
5525 amdgpu_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
5526 amdgpu_ring_write(ring
, cmd
);
5527 amdgpu_ring_write(ring
, reg
);
5528 amdgpu_ring_write(ring
, 0);
5529 amdgpu_ring_write(ring
, val
);
5532 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring
*ring
, uint32_t reg
,
5533 uint32_t val
, uint32_t mask
)
5535 gfx_v9_0_wait_reg_mem(ring
, 0, 0, 0, reg
, 0, val
, mask
, 0x20);
5538 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring
*ring
,
5539 uint32_t reg0
, uint32_t reg1
,
5540 uint32_t ref
, uint32_t mask
)
5542 int usepfp
= (ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
);
5543 struct amdgpu_device
*adev
= ring
->adev
;
5544 bool fw_version_ok
= (ring
->funcs
->type
== AMDGPU_RING_TYPE_GFX
) ?
5545 adev
->gfx
.me_fw_write_wait
: adev
->gfx
.mec_fw_write_wait
;
5548 gfx_v9_0_wait_reg_mem(ring
, usepfp
, 0, 1, reg0
, reg1
,
5551 amdgpu_ring_emit_reg_write_reg_wait_helper(ring
, reg0
, reg1
,
5555 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring
*ring
, unsigned vmid
)
5557 struct amdgpu_device
*adev
= ring
->adev
;
5560 value
= REG_SET_FIELD(value
, SQ_CMD
, CMD
, 0x03);
5561 value
= REG_SET_FIELD(value
, SQ_CMD
, MODE
, 0x01);
5562 value
= REG_SET_FIELD(value
, SQ_CMD
, CHECK_VMID
, 1);
5563 value
= REG_SET_FIELD(value
, SQ_CMD
, VM_ID
, vmid
);
5564 WREG32_SOC15(GC
, 0, mmSQ_CMD
, value
);
5567 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device
*adev
,
5568 enum amdgpu_interrupt_state state
)
5571 case AMDGPU_IRQ_STATE_DISABLE
:
5572 case AMDGPU_IRQ_STATE_ENABLE
:
5573 WREG32_FIELD15(GC
, 0, CP_INT_CNTL_RING0
,
5574 TIME_STAMP_INT_ENABLE
,
5575 state
== AMDGPU_IRQ_STATE_ENABLE
? 1 : 0);
5582 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device
*adev
,
5584 enum amdgpu_interrupt_state state
)
5586 u32 mec_int_cntl
, mec_int_cntl_reg
;
5589 * amdgpu controls only the first MEC. That's why this function only
5590 * handles the setting of interrupts for this specific MEC. All other
5591 * pipes' interrupts are set by amdkfd.
5597 mec_int_cntl_reg
= SOC15_REG_OFFSET(GC
, 0, mmCP_ME1_PIPE0_INT_CNTL
);
5600 mec_int_cntl_reg
= SOC15_REG_OFFSET(GC
, 0, mmCP_ME1_PIPE1_INT_CNTL
);
5603 mec_int_cntl_reg
= SOC15_REG_OFFSET(GC
, 0, mmCP_ME1_PIPE2_INT_CNTL
);
5606 mec_int_cntl_reg
= SOC15_REG_OFFSET(GC
, 0, mmCP_ME1_PIPE3_INT_CNTL
);
5609 DRM_DEBUG("invalid pipe %d\n", pipe
);
5613 DRM_DEBUG("invalid me %d\n", me
);
5618 case AMDGPU_IRQ_STATE_DISABLE
:
5619 mec_int_cntl
= RREG32(mec_int_cntl_reg
);
5620 mec_int_cntl
= REG_SET_FIELD(mec_int_cntl
, CP_ME1_PIPE0_INT_CNTL
,
5621 TIME_STAMP_INT_ENABLE
, 0);
5622 WREG32(mec_int_cntl_reg
, mec_int_cntl
);
5624 case AMDGPU_IRQ_STATE_ENABLE
:
5625 mec_int_cntl
= RREG32(mec_int_cntl_reg
);
5626 mec_int_cntl
= REG_SET_FIELD(mec_int_cntl
, CP_ME1_PIPE0_INT_CNTL
,
5627 TIME_STAMP_INT_ENABLE
, 1);
5628 WREG32(mec_int_cntl_reg
, mec_int_cntl
);
5635 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device
*adev
,
5636 struct amdgpu_irq_src
*source
,
5638 enum amdgpu_interrupt_state state
)
5641 case AMDGPU_IRQ_STATE_DISABLE
:
5642 case AMDGPU_IRQ_STATE_ENABLE
:
5643 WREG32_FIELD15(GC
, 0, CP_INT_CNTL_RING0
,
5644 PRIV_REG_INT_ENABLE
,
5645 state
== AMDGPU_IRQ_STATE_ENABLE
? 1 : 0);
5654 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device
*adev
,
5655 struct amdgpu_irq_src
*source
,
5657 enum amdgpu_interrupt_state state
)
5660 case AMDGPU_IRQ_STATE_DISABLE
:
5661 case AMDGPU_IRQ_STATE_ENABLE
:
5662 WREG32_FIELD15(GC
, 0, CP_INT_CNTL_RING0
,
5663 PRIV_INSTR_INT_ENABLE
,
5664 state
== AMDGPU_IRQ_STATE_ENABLE
? 1 : 0);
5672 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \
5673 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5674 CP_ECC_ERROR_INT_ENABLE, 1)
5676 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \
5677 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5678 CP_ECC_ERROR_INT_ENABLE, 0)
5680 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device
*adev
,
5681 struct amdgpu_irq_src
*source
,
5683 enum amdgpu_interrupt_state state
)
5686 case AMDGPU_IRQ_STATE_DISABLE
:
5687 WREG32_FIELD15(GC
, 0, CP_INT_CNTL_RING0
,
5688 CP_ECC_ERROR_INT_ENABLE
, 0);
5689 DISABLE_ECC_ON_ME_PIPE(1, 0);
5690 DISABLE_ECC_ON_ME_PIPE(1, 1);
5691 DISABLE_ECC_ON_ME_PIPE(1, 2);
5692 DISABLE_ECC_ON_ME_PIPE(1, 3);
5695 case AMDGPU_IRQ_STATE_ENABLE
:
5696 WREG32_FIELD15(GC
, 0, CP_INT_CNTL_RING0
,
5697 CP_ECC_ERROR_INT_ENABLE
, 1);
5698 ENABLE_ECC_ON_ME_PIPE(1, 0);
5699 ENABLE_ECC_ON_ME_PIPE(1, 1);
5700 ENABLE_ECC_ON_ME_PIPE(1, 2);
5701 ENABLE_ECC_ON_ME_PIPE(1, 3);
5711 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device
*adev
,
5712 struct amdgpu_irq_src
*src
,
5714 enum amdgpu_interrupt_state state
)
5717 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP
:
5718 gfx_v9_0_set_gfx_eop_interrupt_state(adev
, state
);
5720 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
:
5721 gfx_v9_0_set_compute_eop_interrupt_state(adev
, 1, 0, state
);
5723 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
:
5724 gfx_v9_0_set_compute_eop_interrupt_state(adev
, 1, 1, state
);
5726 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
:
5727 gfx_v9_0_set_compute_eop_interrupt_state(adev
, 1, 2, state
);
5729 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
:
5730 gfx_v9_0_set_compute_eop_interrupt_state(adev
, 1, 3, state
);
5732 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
:
5733 gfx_v9_0_set_compute_eop_interrupt_state(adev
, 2, 0, state
);
5735 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
:
5736 gfx_v9_0_set_compute_eop_interrupt_state(adev
, 2, 1, state
);
5738 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
:
5739 gfx_v9_0_set_compute_eop_interrupt_state(adev
, 2, 2, state
);
5741 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
:
5742 gfx_v9_0_set_compute_eop_interrupt_state(adev
, 2, 3, state
);
5750 static int gfx_v9_0_eop_irq(struct amdgpu_device
*adev
,
5751 struct amdgpu_irq_src
*source
,
5752 struct amdgpu_iv_entry
*entry
)
5755 u8 me_id
, pipe_id
, queue_id
;
5756 struct amdgpu_ring
*ring
;
5758 DRM_DEBUG("IH: CP EOP\n");
5759 me_id
= (entry
->ring_id
& 0x0c) >> 2;
5760 pipe_id
= (entry
->ring_id
& 0x03) >> 0;
5761 queue_id
= (entry
->ring_id
& 0x70) >> 4;
5765 amdgpu_fence_process(&adev
->gfx
.gfx_ring
[0]);
5769 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
5770 ring
= &adev
->gfx
.compute_ring
[i
];
5771 /* Per-queue interrupt is supported for MEC starting from VI.
5772 * The interrupt can only be enabled/disabled per pipe instead of per queue.
5774 if ((ring
->me
== me_id
) && (ring
->pipe
== pipe_id
) && (ring
->queue
== queue_id
))
5775 amdgpu_fence_process(ring
);
5782 static void gfx_v9_0_fault(struct amdgpu_device
*adev
,
5783 struct amdgpu_iv_entry
*entry
)
5785 u8 me_id
, pipe_id
, queue_id
;
5786 struct amdgpu_ring
*ring
;
5789 me_id
= (entry
->ring_id
& 0x0c) >> 2;
5790 pipe_id
= (entry
->ring_id
& 0x03) >> 0;
5791 queue_id
= (entry
->ring_id
& 0x70) >> 4;
5795 drm_sched_fault(&adev
->gfx
.gfx_ring
[0].sched
);
5799 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++) {
5800 ring
= &adev
->gfx
.compute_ring
[i
];
5801 if (ring
->me
== me_id
&& ring
->pipe
== pipe_id
&&
5802 ring
->queue
== queue_id
)
5803 drm_sched_fault(&ring
->sched
);
5809 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device
*adev
,
5810 struct amdgpu_irq_src
*source
,
5811 struct amdgpu_iv_entry
*entry
)
5813 DRM_ERROR("Illegal register access in command stream\n");
5814 gfx_v9_0_fault(adev
, entry
);
5818 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device
*adev
,
5819 struct amdgpu_irq_src
*source
,
5820 struct amdgpu_iv_entry
*entry
)
5822 DRM_ERROR("Illegal instruction in command stream\n");
5823 gfx_v9_0_fault(adev
, entry
);
5828 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields
[] = {
5829 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC
, 0, mmCPC_EDC_SCRATCH_CNT
),
5830 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT
, SEC_COUNT
),
5831 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT
, DED_COUNT
)
5833 { "CPC_UCODE", SOC15_REG_ENTRY(GC
, 0, mmCPC_EDC_UCODE_CNT
),
5834 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT
, SEC_COUNT
),
5835 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT
, DED_COUNT
)
5837 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC
, 0, mmCPF_EDC_ROQ_CNT
),
5838 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT
, COUNT_ME1
),
5841 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC
, 0, mmCPF_EDC_ROQ_CNT
),
5842 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT
, COUNT_ME2
),
5845 { "CPF_TAG", SOC15_REG_ENTRY(GC
, 0, mmCPF_EDC_TAG_CNT
),
5846 SOC15_REG_FIELD(CPF_EDC_TAG_CNT
, SEC_COUNT
),
5847 SOC15_REG_FIELD(CPF_EDC_TAG_CNT
, DED_COUNT
)
5849 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC
, 0, mmCPG_EDC_DMA_CNT
),
5850 SOC15_REG_FIELD(CPG_EDC_DMA_CNT
, ROQ_COUNT
),
5853 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC
, 0, mmCPG_EDC_DMA_CNT
),
5854 SOC15_REG_FIELD(CPG_EDC_DMA_CNT
, TAG_SEC_COUNT
),
5855 SOC15_REG_FIELD(CPG_EDC_DMA_CNT
, TAG_DED_COUNT
)
5857 { "CPG_TAG", SOC15_REG_ENTRY(GC
, 0, mmCPG_EDC_TAG_CNT
),
5858 SOC15_REG_FIELD(CPG_EDC_TAG_CNT
, SEC_COUNT
),
5859 SOC15_REG_FIELD(CPG_EDC_TAG_CNT
, DED_COUNT
)
5861 { "DC_CSINVOC", SOC15_REG_ENTRY(GC
, 0, mmDC_EDC_CSINVOC_CNT
),
5862 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT
, COUNT_ME1
),
5865 { "DC_RESTORE", SOC15_REG_ENTRY(GC
, 0, mmDC_EDC_RESTORE_CNT
),
5866 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT
, COUNT_ME1
),
5869 { "DC_STATE", SOC15_REG_ENTRY(GC
, 0, mmDC_EDC_STATE_CNT
),
5870 SOC15_REG_FIELD(DC_EDC_STATE_CNT
, COUNT_ME1
),
5873 { "GDS_MEM", SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_CNT
),
5874 SOC15_REG_FIELD(GDS_EDC_CNT
, GDS_MEM_SEC
),
5875 SOC15_REG_FIELD(GDS_EDC_CNT
, GDS_MEM_DED
)
5877 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_CNT
),
5878 SOC15_REG_FIELD(GDS_EDC_CNT
, GDS_INPUT_QUEUE_SED
),
5881 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_PHY_CNT
),
5882 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT
, ME0_CS_PIPE_MEM_SEC
),
5883 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT
, ME0_CS_PIPE_MEM_DED
)
5885 { "GDS_OA_PHY_PHY_CMD_RAM_MEM",
5886 SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_PHY_CNT
),
5887 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT
, PHY_CMD_RAM_MEM_SEC
),
5888 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT
, PHY_CMD_RAM_MEM_DED
)
5890 { "GDS_OA_PHY_PHY_DATA_RAM_MEM",
5891 SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_PHY_CNT
),
5892 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT
, PHY_DATA_RAM_MEM_SED
),
5895 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
5896 SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_PIPE_CNT
),
5897 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT
, ME1_PIPE0_PIPE_MEM_SEC
),
5898 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT
, ME1_PIPE0_PIPE_MEM_DED
)
5900 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
5901 SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_PIPE_CNT
),
5902 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT
, ME1_PIPE1_PIPE_MEM_SEC
),
5903 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT
, ME1_PIPE1_PIPE_MEM_DED
)
5905 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
5906 SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_PIPE_CNT
),
5907 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT
, ME1_PIPE2_PIPE_MEM_SEC
),
5908 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT
, ME1_PIPE2_PIPE_MEM_DED
)
5910 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
5911 SOC15_REG_ENTRY(GC
, 0, mmGDS_EDC_OA_PIPE_CNT
),
5912 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT
, ME1_PIPE3_PIPE_MEM_SEC
),
5913 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT
, ME1_PIPE3_PIPE_MEM_DED
)
5915 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC
, 0, mmSPI_EDC_CNT
),
5916 SOC15_REG_FIELD(SPI_EDC_CNT
, SPI_SR_MEM_SED_COUNT
),
5919 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC
, 0, mmTA_EDC_CNT
),
5920 SOC15_REG_FIELD(TA_EDC_CNT
, TA_FS_DFIFO_SEC_COUNT
),
5921 SOC15_REG_FIELD(TA_EDC_CNT
, TA_FS_DFIFO_DED_COUNT
)
5923 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC
, 0, mmTA_EDC_CNT
),
5924 SOC15_REG_FIELD(TA_EDC_CNT
, TA_FS_AFIFO_SED_COUNT
),
5927 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC
, 0, mmTA_EDC_CNT
),
5928 SOC15_REG_FIELD(TA_EDC_CNT
, TA_FL_LFIFO_SED_COUNT
),
5931 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC
, 0, mmTA_EDC_CNT
),
5932 SOC15_REG_FIELD(TA_EDC_CNT
, TA_FX_LFIFO_SED_COUNT
),
5935 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC
, 0, mmTA_EDC_CNT
),
5936 SOC15_REG_FIELD(TA_EDC_CNT
, TA_FS_CFIFO_SED_COUNT
),
5939 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC
, 0, mmTCA_EDC_CNT
),
5940 SOC15_REG_FIELD(TCA_EDC_CNT
, HOLE_FIFO_SED_COUNT
),
5943 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC
, 0, mmTCA_EDC_CNT
),
5944 SOC15_REG_FIELD(TCA_EDC_CNT
, REQ_FIFO_SED_COUNT
),
5947 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5948 SOC15_REG_FIELD(TCC_EDC_CNT
, CACHE_DATA_SEC_COUNT
),
5949 SOC15_REG_FIELD(TCC_EDC_CNT
, CACHE_DATA_DED_COUNT
)
5951 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5952 SOC15_REG_FIELD(TCC_EDC_CNT
, CACHE_DIRTY_SEC_COUNT
),
5953 SOC15_REG_FIELD(TCC_EDC_CNT
, CACHE_DIRTY_DED_COUNT
)
5955 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5956 SOC15_REG_FIELD(TCC_EDC_CNT
, HIGH_RATE_TAG_SEC_COUNT
),
5957 SOC15_REG_FIELD(TCC_EDC_CNT
, HIGH_RATE_TAG_DED_COUNT
)
5959 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5960 SOC15_REG_FIELD(TCC_EDC_CNT
, LOW_RATE_TAG_SEC_COUNT
),
5961 SOC15_REG_FIELD(TCC_EDC_CNT
, LOW_RATE_TAG_DED_COUNT
)
5963 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5964 SOC15_REG_FIELD(TCC_EDC_CNT
, SRC_FIFO_SEC_COUNT
),
5965 SOC15_REG_FIELD(TCC_EDC_CNT
, SRC_FIFO_DED_COUNT
)
5967 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5968 SOC15_REG_FIELD(TCC_EDC_CNT
, IN_USE_DEC_SED_COUNT
),
5971 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5972 SOC15_REG_FIELD(TCC_EDC_CNT
, IN_USE_TRANSFER_SED_COUNT
),
5975 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5976 SOC15_REG_FIELD(TCC_EDC_CNT
, LATENCY_FIFO_SED_COUNT
),
5979 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5980 SOC15_REG_FIELD(TCC_EDC_CNT
, RETURN_DATA_SED_COUNT
),
5983 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5984 SOC15_REG_FIELD(TCC_EDC_CNT
, RETURN_CONTROL_SED_COUNT
),
5987 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT
),
5988 SOC15_REG_FIELD(TCC_EDC_CNT
, UC_ATOMIC_FIFO_SED_COUNT
),
5991 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT2
),
5992 SOC15_REG_FIELD(TCC_EDC_CNT2
, WRITE_RETURN_SED_COUNT
),
5995 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT2
),
5996 SOC15_REG_FIELD(TCC_EDC_CNT2
, WRITE_CACHE_READ_SED_COUNT
),
5999 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT2
),
6000 SOC15_REG_FIELD(TCC_EDC_CNT2
, SRC_FIFO_NEXT_RAM_SED_COUNT
),
6003 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT2
),
6004 SOC15_REG_FIELD(TCC_EDC_CNT2
, LATENCY_FIFO_NEXT_RAM_SED_COUNT
),
6007 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT2
),
6008 SOC15_REG_FIELD(TCC_EDC_CNT2
, CACHE_TAG_PROBE_FIFO_SED_COUNT
),
6011 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT2
),
6012 SOC15_REG_FIELD(TCC_EDC_CNT2
, WRRET_TAG_WRITE_RETURN_SED_COUNT
),
6015 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC
, 0, mmTCC_EDC_CNT2
),
6016 SOC15_REG_FIELD(TCC_EDC_CNT2
, ATOMIC_RETURN_BUFFER_SED_COUNT
),
6019 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC
, 0, mmTCI_EDC_CNT
),
6020 SOC15_REG_FIELD(TCI_EDC_CNT
, WRITE_RAM_SED_COUNT
),
6023 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC
, 0, mmTCP_EDC_CNT_NEW
),
6024 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, CACHE_RAM_SEC_COUNT
),
6025 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, CACHE_RAM_DED_COUNT
)
6027 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC
, 0, mmTCP_EDC_CNT_NEW
),
6028 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, LFIFO_RAM_SEC_COUNT
),
6029 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, LFIFO_RAM_DED_COUNT
)
6031 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC
, 0, mmTCP_EDC_CNT_NEW
),
6032 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, CMD_FIFO_SED_COUNT
),
6035 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC
, 0, mmTCP_EDC_CNT_NEW
),
6036 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, VM_FIFO_SEC_COUNT
),
6039 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC
, 0, mmTCP_EDC_CNT_NEW
),
6040 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, DB_RAM_SED_COUNT
),
6043 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC
, 0, mmTCP_EDC_CNT_NEW
),
6044 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, UTCL1_LFIFO0_SEC_COUNT
),
6045 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, UTCL1_LFIFO0_DED_COUNT
)
6047 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC
, 0, mmTCP_EDC_CNT_NEW
),
6048 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, UTCL1_LFIFO1_SEC_COUNT
),
6049 SOC15_REG_FIELD(TCP_EDC_CNT_NEW
, UTCL1_LFIFO1_DED_COUNT
)
6051 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC
, 0, mmTD_EDC_CNT
),
6052 SOC15_REG_FIELD(TD_EDC_CNT
, SS_FIFO_LO_SEC_COUNT
),
6053 SOC15_REG_FIELD(TD_EDC_CNT
, SS_FIFO_LO_DED_COUNT
)
6055 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC
, 0, mmTD_EDC_CNT
),
6056 SOC15_REG_FIELD(TD_EDC_CNT
, SS_FIFO_HI_SEC_COUNT
),
6057 SOC15_REG_FIELD(TD_EDC_CNT
, SS_FIFO_HI_DED_COUNT
)
6059 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC
, 0, mmTD_EDC_CNT
),
6060 SOC15_REG_FIELD(TD_EDC_CNT
, CS_FIFO_SED_COUNT
),
6063 { "SQ_LDS_D", SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_CNT
),
6064 SOC15_REG_FIELD(SQ_EDC_CNT
, LDS_D_SEC_COUNT
),
6065 SOC15_REG_FIELD(SQ_EDC_CNT
, LDS_D_DED_COUNT
)
6067 { "SQ_LDS_I", SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_CNT
),
6068 SOC15_REG_FIELD(SQ_EDC_CNT
, LDS_I_SEC_COUNT
),
6069 SOC15_REG_FIELD(SQ_EDC_CNT
, LDS_I_DED_COUNT
)
6071 { "SQ_SGPR", SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_CNT
),
6072 SOC15_REG_FIELD(SQ_EDC_CNT
, SGPR_SEC_COUNT
),
6073 SOC15_REG_FIELD(SQ_EDC_CNT
, SGPR_DED_COUNT
)
6075 { "SQ_VGPR0", SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_CNT
),
6076 SOC15_REG_FIELD(SQ_EDC_CNT
, VGPR0_SEC_COUNT
),
6077 SOC15_REG_FIELD(SQ_EDC_CNT
, VGPR0_DED_COUNT
)
6079 { "SQ_VGPR1", SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_CNT
),
6080 SOC15_REG_FIELD(SQ_EDC_CNT
, VGPR1_SEC_COUNT
),
6081 SOC15_REG_FIELD(SQ_EDC_CNT
, VGPR1_DED_COUNT
)
6083 { "SQ_VGPR2", SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_CNT
),
6084 SOC15_REG_FIELD(SQ_EDC_CNT
, VGPR2_SEC_COUNT
),
6085 SOC15_REG_FIELD(SQ_EDC_CNT
, VGPR2_DED_COUNT
)
6087 { "SQ_VGPR3", SOC15_REG_ENTRY(GC
, 0, mmSQ_EDC_CNT
),
6088 SOC15_REG_FIELD(SQ_EDC_CNT
, VGPR3_SEC_COUNT
),
6089 SOC15_REG_FIELD(SQ_EDC_CNT
, VGPR3_DED_COUNT
)
6091 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT
),
6092 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT
),
6093 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU0_WRITE_DATA_BUF_DED_COUNT
)
6095 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT
),
6096 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU0_UTCL1_LFIFO_SEC_COUNT
),
6097 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU0_UTCL1_LFIFO_DED_COUNT
)
6099 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT
),
6100 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT
),
6101 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU1_WRITE_DATA_BUF_DED_COUNT
)
6103 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT
),
6104 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU1_UTCL1_LFIFO_SEC_COUNT
),
6105 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU1_UTCL1_LFIFO_DED_COUNT
)
6107 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT
),
6108 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT
),
6109 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU2_WRITE_DATA_BUF_DED_COUNT
)
6111 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT
),
6112 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU2_UTCL1_LFIFO_SEC_COUNT
),
6113 SOC15_REG_FIELD(SQC_EDC_CNT
, DATA_CU2_UTCL1_LFIFO_DED_COUNT
)
6115 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6116 SOC15_REG_FIELD(SQC_EDC_CNT2
, INST_BANKA_TAG_RAM_SEC_COUNT
),
6117 SOC15_REG_FIELD(SQC_EDC_CNT2
, INST_BANKA_TAG_RAM_DED_COUNT
)
6119 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6120 SOC15_REG_FIELD(SQC_EDC_CNT2
, INST_BANKA_BANK_RAM_SEC_COUNT
),
6121 SOC15_REG_FIELD(SQC_EDC_CNT2
, INST_BANKA_BANK_RAM_DED_COUNT
)
6123 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6124 SOC15_REG_FIELD(SQC_EDC_CNT2
, DATA_BANKA_TAG_RAM_SEC_COUNT
),
6125 SOC15_REG_FIELD(SQC_EDC_CNT2
, DATA_BANKA_TAG_RAM_DED_COUNT
)
6127 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6128 SOC15_REG_FIELD(SQC_EDC_CNT2
, DATA_BANKA_BANK_RAM_SEC_COUNT
),
6129 SOC15_REG_FIELD(SQC_EDC_CNT2
, DATA_BANKA_BANK_RAM_DED_COUNT
)
6131 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6132 SOC15_REG_FIELD(SQC_EDC_CNT2
, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT
),
6135 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6136 SOC15_REG_FIELD(SQC_EDC_CNT2
, INST_BANKA_MISS_FIFO_SED_COUNT
),
6139 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6140 SOC15_REG_FIELD(SQC_EDC_CNT2
, DATA_BANKA_HIT_FIFO_SED_COUNT
),
6143 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6144 SOC15_REG_FIELD(SQC_EDC_CNT2
, DATA_BANKA_MISS_FIFO_SED_COUNT
),
6147 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6148 SOC15_REG_FIELD(SQC_EDC_CNT2
, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT
),
6151 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT2
),
6152 SOC15_REG_FIELD(SQC_EDC_CNT2
, INST_UTCL1_LFIFO_SEC_COUNT
),
6153 SOC15_REG_FIELD(SQC_EDC_CNT2
, INST_UTCL1_LFIFO_DED_COUNT
)
6155 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
),
6156 SOC15_REG_FIELD(SQC_EDC_CNT3
, INST_BANKB_TAG_RAM_SEC_COUNT
),
6157 SOC15_REG_FIELD(SQC_EDC_CNT3
, INST_BANKB_TAG_RAM_DED_COUNT
)
6159 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
),
6160 SOC15_REG_FIELD(SQC_EDC_CNT3
, INST_BANKB_BANK_RAM_SEC_COUNT
),
6161 SOC15_REG_FIELD(SQC_EDC_CNT3
, INST_BANKB_BANK_RAM_DED_COUNT
)
6163 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
),
6164 SOC15_REG_FIELD(SQC_EDC_CNT3
, DATA_BANKB_TAG_RAM_SEC_COUNT
),
6165 SOC15_REG_FIELD(SQC_EDC_CNT3
, DATA_BANKB_TAG_RAM_DED_COUNT
)
6167 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
),
6168 SOC15_REG_FIELD(SQC_EDC_CNT3
, DATA_BANKB_BANK_RAM_SEC_COUNT
),
6169 SOC15_REG_FIELD(SQC_EDC_CNT3
, DATA_BANKB_BANK_RAM_DED_COUNT
)
6171 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
),
6172 SOC15_REG_FIELD(SQC_EDC_CNT3
, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT
),
6175 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
),
6176 SOC15_REG_FIELD(SQC_EDC_CNT3
, INST_BANKB_MISS_FIFO_SED_COUNT
),
6179 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
),
6180 SOC15_REG_FIELD(SQC_EDC_CNT3
, DATA_BANKB_HIT_FIFO_SED_COUNT
),
6183 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
),
6184 SOC15_REG_FIELD(SQC_EDC_CNT3
, DATA_BANKB_MISS_FIFO_SED_COUNT
),
6187 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC
, 0, mmSQC_EDC_CNT3
),
6188 SOC15_REG_FIELD(SQC_EDC_CNT3
, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT
),
6191 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6192 SOC15_REG_FIELD(GCEA_EDC_CNT
, DRAMRD_CMDMEM_SEC_COUNT
),
6193 SOC15_REG_FIELD(GCEA_EDC_CNT
, DRAMRD_CMDMEM_DED_COUNT
)
6195 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6196 SOC15_REG_FIELD(GCEA_EDC_CNT
, DRAMWR_CMDMEM_SEC_COUNT
),
6197 SOC15_REG_FIELD(GCEA_EDC_CNT
, DRAMWR_CMDMEM_DED_COUNT
)
6199 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6200 SOC15_REG_FIELD(GCEA_EDC_CNT
, DRAMWR_DATAMEM_SEC_COUNT
),
6201 SOC15_REG_FIELD(GCEA_EDC_CNT
, DRAMWR_DATAMEM_DED_COUNT
)
6203 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6204 SOC15_REG_FIELD(GCEA_EDC_CNT
, RRET_TAGMEM_SEC_COUNT
),
6205 SOC15_REG_FIELD(GCEA_EDC_CNT
, RRET_TAGMEM_DED_COUNT
)
6207 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6208 SOC15_REG_FIELD(GCEA_EDC_CNT
, WRET_TAGMEM_SEC_COUNT
),
6209 SOC15_REG_FIELD(GCEA_EDC_CNT
, WRET_TAGMEM_DED_COUNT
)
6211 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6212 SOC15_REG_FIELD(GCEA_EDC_CNT
, DRAMRD_PAGEMEM_SED_COUNT
),
6215 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6216 SOC15_REG_FIELD(GCEA_EDC_CNT
, DRAMWR_PAGEMEM_SED_COUNT
),
6219 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6220 SOC15_REG_FIELD(GCEA_EDC_CNT
, IORD_CMDMEM_SED_COUNT
),
6223 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6224 SOC15_REG_FIELD(GCEA_EDC_CNT
, IOWR_CMDMEM_SED_COUNT
),
6227 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT
),
6228 SOC15_REG_FIELD(GCEA_EDC_CNT
, IOWR_DATAMEM_SED_COUNT
),
6231 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
),
6232 SOC15_REG_FIELD(GCEA_EDC_CNT2
, GMIRD_CMDMEM_SEC_COUNT
),
6233 SOC15_REG_FIELD(GCEA_EDC_CNT2
, GMIRD_CMDMEM_DED_COUNT
)
6235 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
),
6236 SOC15_REG_FIELD(GCEA_EDC_CNT2
, GMIWR_CMDMEM_SEC_COUNT
),
6237 SOC15_REG_FIELD(GCEA_EDC_CNT2
, GMIWR_CMDMEM_DED_COUNT
)
6239 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
),
6240 SOC15_REG_FIELD(GCEA_EDC_CNT2
, GMIWR_DATAMEM_SEC_COUNT
),
6241 SOC15_REG_FIELD(GCEA_EDC_CNT2
, GMIWR_DATAMEM_DED_COUNT
)
6243 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
),
6244 SOC15_REG_FIELD(GCEA_EDC_CNT2
, GMIRD_PAGEMEM_SED_COUNT
),
6247 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
),
6248 SOC15_REG_FIELD(GCEA_EDC_CNT2
, GMIWR_PAGEMEM_SED_COUNT
),
6251 { "MAM_D0MEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
),
6252 SOC15_REG_FIELD(GCEA_EDC_CNT2
, MAM_D0MEM_SED_COUNT
),
6255 { "MAM_D1MEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
),
6256 SOC15_REG_FIELD(GCEA_EDC_CNT2
, MAM_D1MEM_SED_COUNT
),
6259 { "MAM_D2MEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
),
6260 SOC15_REG_FIELD(GCEA_EDC_CNT2
, MAM_D2MEM_SED_COUNT
),
6263 { "MAM_D3MEM", SOC15_REG_ENTRY(GC
, 0, mmGCEA_EDC_CNT2
),
6264 SOC15_REG_FIELD(GCEA_EDC_CNT2
, MAM_D3MEM_SED_COUNT
),
6269 static int gfx_v9_0_ras_error_inject(struct amdgpu_device
*adev
,
6272 struct ras_inject_if
*info
= (struct ras_inject_if
*)inject_if
;
6274 struct ta_ras_trigger_error_input block_info
= { 0 };
6276 if (!amdgpu_ras_is_supported(adev
, AMDGPU_RAS_BLOCK__GFX
))
6279 if (info
->head
.sub_block_index
>= ARRAY_SIZE(ras_gfx_subblocks
))
6282 if (!ras_gfx_subblocks
[info
->head
.sub_block_index
].name
)
6285 if (!(ras_gfx_subblocks
[info
->head
.sub_block_index
].hw_supported_error_type
&
6287 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n",
6288 ras_gfx_subblocks
[info
->head
.sub_block_index
].name
,
6293 if (!(ras_gfx_subblocks
[info
->head
.sub_block_index
].sw_supported_error_type
&
6295 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n",
6296 ras_gfx_subblocks
[info
->head
.sub_block_index
].name
,
6301 block_info
.block_id
= amdgpu_ras_block_to_ta(info
->head
.block
);
6302 block_info
.sub_block_index
=
6303 ras_gfx_subblocks
[info
->head
.sub_block_index
].ta_subblock
;
6304 block_info
.inject_error_type
= amdgpu_ras_error_to_ta(info
->head
.type
);
6305 block_info
.address
= info
->address
;
6306 block_info
.value
= info
->value
;
6308 mutex_lock(&adev
->grbm_idx_mutex
);
6309 ret
= psp_ras_trigger_error(&adev
->psp
, &block_info
);
6310 mutex_unlock(&adev
->grbm_idx_mutex
);
6315 static const char *vml2_mems
[] = {
6316 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
6317 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
6318 "UTC_VML2_BANK_CACHE_0_4K_MEM0",
6319 "UTC_VML2_BANK_CACHE_0_4K_MEM1",
6320 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
6321 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
6322 "UTC_VML2_BANK_CACHE_1_4K_MEM0",
6323 "UTC_VML2_BANK_CACHE_1_4K_MEM1",
6324 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
6325 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
6326 "UTC_VML2_BANK_CACHE_2_4K_MEM0",
6327 "UTC_VML2_BANK_CACHE_2_4K_MEM1",
6328 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
6329 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
6330 "UTC_VML2_BANK_CACHE_3_4K_MEM0",
6331 "UTC_VML2_BANK_CACHE_3_4K_MEM1",
6334 static const char *vml2_walker_mems
[] = {
6335 "UTC_VML2_CACHE_PDE0_MEM0",
6336 "UTC_VML2_CACHE_PDE0_MEM1",
6337 "UTC_VML2_CACHE_PDE1_MEM0",
6338 "UTC_VML2_CACHE_PDE1_MEM1",
6339 "UTC_VML2_CACHE_PDE2_MEM0",
6340 "UTC_VML2_CACHE_PDE2_MEM1",
6341 "UTC_VML2_RDIF_LOG_FIFO",
6344 static const char *atc_l2_cache_2m_mems
[] = {
6345 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
6346 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
6347 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
6348 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
6351 static const char *atc_l2_cache_4k_mems
[] = {
6352 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
6353 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
6354 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
6355 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
6356 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
6357 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
6358 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
6359 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
6360 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
6361 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
6362 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
6363 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
6364 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
6365 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
6366 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
6367 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
6368 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
6369 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
6370 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
6371 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
6372 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
6373 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
6374 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
6375 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
6376 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
6377 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
6378 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
6379 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
6380 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
6381 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
6382 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
6383 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
6386 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device
*adev
,
6387 struct ras_err_data
*err_data
)
6390 uint32_t sec_count
, ded_count
;
6392 WREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_INDEX
, 255);
6393 WREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_CNT
, 0);
6394 WREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_INDEX
, 255);
6395 WREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_CNT
, 0);
6396 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_INDEX
, 255);
6397 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_CNT
, 0);
6398 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_INDEX
, 255);
6399 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_CNT
, 0);
6401 for (i
= 0; i
< ARRAY_SIZE(vml2_mems
); i
++) {
6402 WREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_INDEX
, i
);
6403 data
= RREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_CNT
);
6405 sec_count
= REG_GET_FIELD(data
, VM_L2_MEM_ECC_CNT
, SEC_COUNT
);
6407 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i
,
6408 vml2_mems
[i
], sec_count
);
6409 err_data
->ce_count
+= sec_count
;
6412 ded_count
= REG_GET_FIELD(data
, VM_L2_MEM_ECC_CNT
, DED_COUNT
);
6414 DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i
,
6415 vml2_mems
[i
], ded_count
);
6416 err_data
->ue_count
+= ded_count
;
6420 for (i
= 0; i
< ARRAY_SIZE(vml2_walker_mems
); i
++) {
6421 WREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_INDEX
, i
);
6422 data
= RREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_CNT
);
6424 sec_count
= REG_GET_FIELD(data
, VM_L2_WALKER_MEM_ECC_CNT
,
6427 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i
,
6428 vml2_walker_mems
[i
], sec_count
);
6429 err_data
->ce_count
+= sec_count
;
6432 ded_count
= REG_GET_FIELD(data
, VM_L2_WALKER_MEM_ECC_CNT
,
6435 DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i
,
6436 vml2_walker_mems
[i
], ded_count
);
6437 err_data
->ue_count
+= ded_count
;
6441 for (i
= 0; i
< ARRAY_SIZE(atc_l2_cache_2m_mems
); i
++) {
6442 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_INDEX
, i
);
6443 data
= RREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_CNT
);
6445 sec_count
= (data
& 0x00006000L
) >> 0xd;
6447 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i
,
6448 atc_l2_cache_2m_mems
[i
], sec_count
);
6449 err_data
->ce_count
+= sec_count
;
6453 for (i
= 0; i
< ARRAY_SIZE(atc_l2_cache_4k_mems
); i
++) {
6454 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_INDEX
, i
);
6455 data
= RREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_CNT
);
6457 sec_count
= (data
& 0x00006000L
) >> 0xd;
6459 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i
,
6460 atc_l2_cache_4k_mems
[i
], sec_count
);
6461 err_data
->ce_count
+= sec_count
;
6464 ded_count
= (data
& 0x00018000L
) >> 0xf;
6466 DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i
,
6467 atc_l2_cache_4k_mems
[i
], ded_count
);
6468 err_data
->ue_count
+= ded_count
;
6472 WREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_INDEX
, 255);
6473 WREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_INDEX
, 255);
6474 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_INDEX
, 255);
6475 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_INDEX
, 255);
6480 static int gfx_v9_0_ras_error_count(const struct soc15_reg_entry
*reg
,
6481 uint32_t se_id
, uint32_t inst_id
, uint32_t value
,
6482 uint32_t *sec_count
, uint32_t *ded_count
)
6485 uint32_t sec_cnt
, ded_cnt
;
6487 for (i
= 0; i
< ARRAY_SIZE(gfx_v9_0_ras_fields
); i
++) {
6488 if(gfx_v9_0_ras_fields
[i
].reg_offset
!= reg
->reg_offset
||
6489 gfx_v9_0_ras_fields
[i
].seg
!= reg
->seg
||
6490 gfx_v9_0_ras_fields
[i
].inst
!= reg
->inst
)
6494 gfx_v9_0_ras_fields
[i
].sec_count_mask
) >>
6495 gfx_v9_0_ras_fields
[i
].sec_count_shift
;
6497 DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
6498 gfx_v9_0_ras_fields
[i
].name
,
6501 *sec_count
+= sec_cnt
;
6505 gfx_v9_0_ras_fields
[i
].ded_count_mask
) >>
6506 gfx_v9_0_ras_fields
[i
].ded_count_shift
;
6508 DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
6509 gfx_v9_0_ras_fields
[i
].name
,
6512 *ded_count
+= ded_cnt
;
6519 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device
*adev
)
6523 if (!amdgpu_ras_is_supported(adev
, AMDGPU_RAS_BLOCK__GFX
))
6526 /* read back registers to clear the counters */
6527 mutex_lock(&adev
->grbm_idx_mutex
);
6528 for (i
= 0; i
< ARRAY_SIZE(gfx_v9_0_edc_counter_regs
); i
++) {
6529 for (j
= 0; j
< gfx_v9_0_edc_counter_regs
[i
].se_num
; j
++) {
6530 for (k
= 0; k
< gfx_v9_0_edc_counter_regs
[i
].instance
; k
++) {
6531 gfx_v9_0_select_se_sh(adev
, j
, 0x0, k
);
6532 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs
[i
]));
6536 WREG32_SOC15(GC
, 0, mmGRBM_GFX_INDEX
, 0xe0000000);
6537 mutex_unlock(&adev
->grbm_idx_mutex
);
6539 WREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_INDEX
, 255);
6540 WREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_CNT
, 0);
6541 WREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_INDEX
, 255);
6542 WREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_CNT
, 0);
6543 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_INDEX
, 255);
6544 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_CNT
, 0);
6545 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_INDEX
, 255);
6546 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_CNT
, 0);
6548 for (i
= 0; i
< ARRAY_SIZE(vml2_mems
); i
++) {
6549 WREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_INDEX
, i
);
6550 RREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_CNT
);
6553 for (i
= 0; i
< ARRAY_SIZE(vml2_walker_mems
); i
++) {
6554 WREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_INDEX
, i
);
6555 RREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_CNT
);
6558 for (i
= 0; i
< ARRAY_SIZE(atc_l2_cache_2m_mems
); i
++) {
6559 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_INDEX
, i
);
6560 RREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_CNT
);
6563 for (i
= 0; i
< ARRAY_SIZE(atc_l2_cache_4k_mems
); i
++) {
6564 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_INDEX
, i
);
6565 RREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_CNT
);
6568 WREG32_SOC15(GC
, 0, mmVM_L2_MEM_ECC_INDEX
, 255);
6569 WREG32_SOC15(GC
, 0, mmVM_L2_WALKER_MEM_ECC_INDEX
, 255);
6570 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_2M_EDC_INDEX
, 255);
6571 WREG32_SOC15(GC
, 0, mmATC_L2_CACHE_4K_EDC_INDEX
, 255);
6574 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device
*adev
,
6575 void *ras_error_status
)
6577 struct ras_err_data
*err_data
= (struct ras_err_data
*)ras_error_status
;
6578 uint32_t sec_count
= 0, ded_count
= 0;
6582 if (!amdgpu_ras_is_supported(adev
, AMDGPU_RAS_BLOCK__GFX
))
6585 err_data
->ue_count
= 0;
6586 err_data
->ce_count
= 0;
6588 mutex_lock(&adev
->grbm_idx_mutex
);
6590 for (i
= 0; i
< ARRAY_SIZE(gfx_v9_0_edc_counter_regs
); i
++) {
6591 for (j
= 0; j
< gfx_v9_0_edc_counter_regs
[i
].se_num
; j
++) {
6592 for (k
= 0; k
< gfx_v9_0_edc_counter_regs
[i
].instance
; k
++) {
6593 gfx_v9_0_select_se_sh(adev
, j
, 0, k
);
6595 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs
[i
]));
6597 gfx_v9_0_ras_error_count(&gfx_v9_0_edc_counter_regs
[i
],
6599 &sec_count
, &ded_count
);
6604 err_data
->ce_count
+= sec_count
;
6605 err_data
->ue_count
+= ded_count
;
6607 gfx_v9_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
6608 mutex_unlock(&adev
->grbm_idx_mutex
);
6610 gfx_v9_0_query_utc_edc_status(adev
, err_data
);
6615 static const struct amd_ip_funcs gfx_v9_0_ip_funcs
= {
6617 .early_init
= gfx_v9_0_early_init
,
6618 .late_init
= gfx_v9_0_late_init
,
6619 .sw_init
= gfx_v9_0_sw_init
,
6620 .sw_fini
= gfx_v9_0_sw_fini
,
6621 .hw_init
= gfx_v9_0_hw_init
,
6622 .hw_fini
= gfx_v9_0_hw_fini
,
6623 .suspend
= gfx_v9_0_suspend
,
6624 .resume
= gfx_v9_0_resume
,
6625 .is_idle
= gfx_v9_0_is_idle
,
6626 .wait_for_idle
= gfx_v9_0_wait_for_idle
,
6627 .soft_reset
= gfx_v9_0_soft_reset
,
6628 .set_clockgating_state
= gfx_v9_0_set_clockgating_state
,
6629 .set_powergating_state
= gfx_v9_0_set_powergating_state
,
6630 .get_clockgating_state
= gfx_v9_0_get_clockgating_state
,
6633 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx
= {
6634 .type
= AMDGPU_RING_TYPE_GFX
,
6636 .nop
= PACKET3(PACKET3_NOP
, 0x3FFF),
6637 .support_64bit_ptrs
= true,
6638 .vmhub
= AMDGPU_GFXHUB_0
,
6639 .get_rptr
= gfx_v9_0_ring_get_rptr_gfx
,
6640 .get_wptr
= gfx_v9_0_ring_get_wptr_gfx
,
6641 .set_wptr
= gfx_v9_0_ring_set_wptr_gfx
,
6642 .emit_frame_size
= /* totally 242 maximum if 16 IBs */
6644 7 + /* PIPELINE_SYNC */
6645 SOC15_FLUSH_GPU_TLB_NUM_WREG
* 5 +
6646 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT
* 7 +
6648 8 + /* FENCE for VM_FLUSH */
6649 20 + /* GDS switch */
6650 4 + /* double SWITCH_BUFFER,
6651 the first COND_EXEC jump to the place just
6652 prior to this double SWITCH_BUFFER */
6660 8 + 8 + /* FENCE x2 */
6661 2, /* SWITCH_BUFFER */
6662 .emit_ib_size
= 4, /* gfx_v9_0_ring_emit_ib_gfx */
6663 .emit_ib
= gfx_v9_0_ring_emit_ib_gfx
,
6664 .emit_fence
= gfx_v9_0_ring_emit_fence
,
6665 .emit_pipeline_sync
= gfx_v9_0_ring_emit_pipeline_sync
,
6666 .emit_vm_flush
= gfx_v9_0_ring_emit_vm_flush
,
6667 .emit_gds_switch
= gfx_v9_0_ring_emit_gds_switch
,
6668 .emit_hdp_flush
= gfx_v9_0_ring_emit_hdp_flush
,
6669 .test_ring
= gfx_v9_0_ring_test_ring
,
6670 .test_ib
= gfx_v9_0_ring_test_ib
,
6671 .insert_nop
= amdgpu_ring_insert_nop
,
6672 .pad_ib
= amdgpu_ring_generic_pad_ib
,
6673 .emit_switch_buffer
= gfx_v9_ring_emit_sb
,
6674 .emit_cntxcntl
= gfx_v9_ring_emit_cntxcntl
,
6675 .init_cond_exec
= gfx_v9_0_ring_emit_init_cond_exec
,
6676 .patch_cond_exec
= gfx_v9_0_ring_emit_patch_cond_exec
,
6677 .emit_tmz
= gfx_v9_0_ring_emit_tmz
,
6678 .emit_wreg
= gfx_v9_0_ring_emit_wreg
,
6679 .emit_reg_wait
= gfx_v9_0_ring_emit_reg_wait
,
6680 .emit_reg_write_reg_wait
= gfx_v9_0_ring_emit_reg_write_reg_wait
,
6681 .soft_recovery
= gfx_v9_0_ring_soft_recovery
,
6684 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute
= {
6685 .type
= AMDGPU_RING_TYPE_COMPUTE
,
6687 .nop
= PACKET3(PACKET3_NOP
, 0x3FFF),
6688 .support_64bit_ptrs
= true,
6689 .vmhub
= AMDGPU_GFXHUB_0
,
6690 .get_rptr
= gfx_v9_0_ring_get_rptr_compute
,
6691 .get_wptr
= gfx_v9_0_ring_get_wptr_compute
,
6692 .set_wptr
= gfx_v9_0_ring_set_wptr_compute
,
6694 20 + /* gfx_v9_0_ring_emit_gds_switch */
6695 7 + /* gfx_v9_0_ring_emit_hdp_flush */
6696 5 + /* hdp invalidate */
6697 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
6698 SOC15_FLUSH_GPU_TLB_NUM_WREG
* 5 +
6699 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT
* 7 +
6700 2 + /* gfx_v9_0_ring_emit_vm_flush */
6701 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
6702 .emit_ib_size
= 7, /* gfx_v9_0_ring_emit_ib_compute */
6703 .emit_ib
= gfx_v9_0_ring_emit_ib_compute
,
6704 .emit_fence
= gfx_v9_0_ring_emit_fence
,
6705 .emit_pipeline_sync
= gfx_v9_0_ring_emit_pipeline_sync
,
6706 .emit_vm_flush
= gfx_v9_0_ring_emit_vm_flush
,
6707 .emit_gds_switch
= gfx_v9_0_ring_emit_gds_switch
,
6708 .emit_hdp_flush
= gfx_v9_0_ring_emit_hdp_flush
,
6709 .test_ring
= gfx_v9_0_ring_test_ring
,
6710 .test_ib
= gfx_v9_0_ring_test_ib
,
6711 .insert_nop
= amdgpu_ring_insert_nop
,
6712 .pad_ib
= amdgpu_ring_generic_pad_ib
,
6713 .emit_wreg
= gfx_v9_0_ring_emit_wreg
,
6714 .emit_reg_wait
= gfx_v9_0_ring_emit_reg_wait
,
6715 .emit_reg_write_reg_wait
= gfx_v9_0_ring_emit_reg_write_reg_wait
,
6718 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq
= {
6719 .type
= AMDGPU_RING_TYPE_KIQ
,
6721 .nop
= PACKET3(PACKET3_NOP
, 0x3FFF),
6722 .support_64bit_ptrs
= true,
6723 .vmhub
= AMDGPU_GFXHUB_0
,
6724 .get_rptr
= gfx_v9_0_ring_get_rptr_compute
,
6725 .get_wptr
= gfx_v9_0_ring_get_wptr_compute
,
6726 .set_wptr
= gfx_v9_0_ring_set_wptr_compute
,
6728 20 + /* gfx_v9_0_ring_emit_gds_switch */
6729 7 + /* gfx_v9_0_ring_emit_hdp_flush */
6730 5 + /* hdp invalidate */
6731 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
6732 SOC15_FLUSH_GPU_TLB_NUM_WREG
* 5 +
6733 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT
* 7 +
6734 2 + /* gfx_v9_0_ring_emit_vm_flush */
6735 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6736 .emit_ib_size
= 7, /* gfx_v9_0_ring_emit_ib_compute */
6737 .emit_fence
= gfx_v9_0_ring_emit_fence_kiq
,
6738 .test_ring
= gfx_v9_0_ring_test_ring
,
6739 .insert_nop
= amdgpu_ring_insert_nop
,
6740 .pad_ib
= amdgpu_ring_generic_pad_ib
,
6741 .emit_rreg
= gfx_v9_0_ring_emit_rreg
,
6742 .emit_wreg
= gfx_v9_0_ring_emit_wreg
,
6743 .emit_reg_wait
= gfx_v9_0_ring_emit_reg_wait
,
6744 .emit_reg_write_reg_wait
= gfx_v9_0_ring_emit_reg_write_reg_wait
,
6747 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device
*adev
)
6751 adev
->gfx
.kiq
.ring
.funcs
= &gfx_v9_0_ring_funcs_kiq
;
6753 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
6754 adev
->gfx
.gfx_ring
[i
].funcs
= &gfx_v9_0_ring_funcs_gfx
;
6756 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
6757 adev
->gfx
.compute_ring
[i
].funcs
= &gfx_v9_0_ring_funcs_compute
;
6760 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs
= {
6761 .set
= gfx_v9_0_set_eop_interrupt_state
,
6762 .process
= gfx_v9_0_eop_irq
,
6765 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs
= {
6766 .set
= gfx_v9_0_set_priv_reg_fault_state
,
6767 .process
= gfx_v9_0_priv_reg_irq
,
6770 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs
= {
6771 .set
= gfx_v9_0_set_priv_inst_fault_state
,
6772 .process
= gfx_v9_0_priv_inst_irq
,
6775 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs
= {
6776 .set
= gfx_v9_0_set_cp_ecc_error_state
,
6777 .process
= amdgpu_gfx_cp_ecc_error_irq
,
6781 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device
*adev
)
6783 adev
->gfx
.eop_irq
.num_types
= AMDGPU_CP_IRQ_LAST
;
6784 adev
->gfx
.eop_irq
.funcs
= &gfx_v9_0_eop_irq_funcs
;
6786 adev
->gfx
.priv_reg_irq
.num_types
= 1;
6787 adev
->gfx
.priv_reg_irq
.funcs
= &gfx_v9_0_priv_reg_irq_funcs
;
6789 adev
->gfx
.priv_inst_irq
.num_types
= 1;
6790 adev
->gfx
.priv_inst_irq
.funcs
= &gfx_v9_0_priv_inst_irq_funcs
;
6792 adev
->gfx
.cp_ecc_error_irq
.num_types
= 2; /*C5 ECC error and C9 FUE error*/
6793 adev
->gfx
.cp_ecc_error_irq
.funcs
= &gfx_v9_0_cp_ecc_error_irq_funcs
;
6796 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device
*adev
)
6798 switch (adev
->asic_type
) {
6805 adev
->gfx
.rlc
.funcs
= &gfx_v9_0_rlc_funcs
;
6812 static void gfx_v9_0_set_gds_init(struct amdgpu_device
*adev
)
6814 /* init asci gds info */
6815 switch (adev
->asic_type
) {
6819 adev
->gds
.gds_size
= 0x10000;
6823 adev
->gds
.gds_size
= 0x1000;
6826 adev
->gds
.gds_size
= 0x10000;
6830 switch (adev
->asic_type
) {
6833 adev
->gds
.gds_compute_max_wave_id
= 0x7ff;
6836 adev
->gds
.gds_compute_max_wave_id
= 0x27f;
6839 if (adev
->rev_id
>= 0x8)
6840 adev
->gds
.gds_compute_max_wave_id
= 0x77; /* raven2 */
6842 adev
->gds
.gds_compute_max_wave_id
= 0x15f; /* raven1 */
6845 adev
->gds
.gds_compute_max_wave_id
= 0xfff;
6848 /* this really depends on the chip */
6849 adev
->gds
.gds_compute_max_wave_id
= 0x7ff;
6853 adev
->gds
.gws_size
= 64;
6854 adev
->gds
.oa_size
= 16;
6857 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device
*adev
,
6865 data
= bitmap
<< GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT
;
6866 data
&= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK
;
6868 WREG32_SOC15(GC
, 0, mmGC_USER_SHADER_ARRAY_CONFIG
, data
);
6871 static u32
gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device
*adev
)
6875 data
= RREG32_SOC15(GC
, 0, mmCC_GC_SHADER_ARRAY_CONFIG
);
6876 data
|= RREG32_SOC15(GC
, 0, mmGC_USER_SHADER_ARRAY_CONFIG
);
6878 data
&= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK
;
6879 data
>>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT
;
6881 mask
= amdgpu_gfx_create_bitmask(adev
->gfx
.config
.max_cu_per_sh
);
6883 return (~data
) & mask
;
6886 static int gfx_v9_0_get_cu_info(struct amdgpu_device
*adev
,
6887 struct amdgpu_cu_info
*cu_info
)
6889 int i
, j
, k
, counter
, active_cu_number
= 0;
6890 u32 mask
, bitmap
, ao_bitmap
, ao_cu_mask
= 0;
6891 unsigned disable_masks
[4 * 4];
6893 if (!adev
|| !cu_info
)
6897 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
6899 if (adev
->gfx
.config
.max_shader_engines
*
6900 adev
->gfx
.config
.max_sh_per_se
> 16)
6903 amdgpu_gfx_parse_disable_cu(disable_masks
,
6904 adev
->gfx
.config
.max_shader_engines
,
6905 adev
->gfx
.config
.max_sh_per_se
);
6907 mutex_lock(&adev
->grbm_idx_mutex
);
6908 for (i
= 0; i
< adev
->gfx
.config
.max_shader_engines
; i
++) {
6909 for (j
= 0; j
< adev
->gfx
.config
.max_sh_per_se
; j
++) {
6913 gfx_v9_0_select_se_sh(adev
, i
, j
, 0xffffffff);
6914 gfx_v9_0_set_user_cu_inactive_bitmap(
6915 adev
, disable_masks
[i
* adev
->gfx
.config
.max_sh_per_se
+ j
]);
6916 bitmap
= gfx_v9_0_get_cu_active_bitmap(adev
);
6919 * The bitmap(and ao_cu_bitmap) in cu_info structure is
6920 * 4x4 size array, and it's usually suitable for Vega
6921 * ASICs which has 4*2 SE/SH layout.
6922 * But for Arcturus, SE/SH layout is changed to 8*1.
6923 * To mostly reduce the impact, we make it compatible
6924 * with current bitmap array as below:
6925 * SE4,SH0 --> bitmap[0][1]
6926 * SE5,SH0 --> bitmap[1][1]
6927 * SE6,SH0 --> bitmap[2][1]
6928 * SE7,SH0 --> bitmap[3][1]
6930 cu_info
->bitmap
[i
% 4][j
+ i
/ 4] = bitmap
;
6932 for (k
= 0; k
< adev
->gfx
.config
.max_cu_per_sh
; k
++) {
6933 if (bitmap
& mask
) {
6934 if (counter
< adev
->gfx
.config
.max_cu_per_sh
)
6940 active_cu_number
+= counter
;
6942 ao_cu_mask
|= (ao_bitmap
<< (i
* 16 + j
* 8));
6943 cu_info
->ao_cu_bitmap
[i
% 4][j
+ i
/ 4] = ao_bitmap
;
6946 gfx_v9_0_select_se_sh(adev
, 0xffffffff, 0xffffffff, 0xffffffff);
6947 mutex_unlock(&adev
->grbm_idx_mutex
);
6949 cu_info
->number
= active_cu_number
;
6950 cu_info
->ao_cu_mask
= ao_cu_mask
;
6951 cu_info
->simd_per_cu
= NUM_SIMD_PER_CU
;
6956 const struct amdgpu_ip_block_version gfx_v9_0_ip_block
=
6958 .type
= AMD_IP_BLOCK_TYPE_GFX
,
6962 .funcs
= &gfx_v9_0_ip_funcs
,