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Merge tag 'drm-next-5.6-2019-12-11' of git://people.freedesktop.org/~agd5f/linux...
[people/ms/linux.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/pci.h>
26
27 #include <drm/drm_cache.h>
28
29 #include "amdgpu.h"
30 #include "gmc_v9_0.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_gem.h"
33
34 #include "hdp/hdp_4_0_offset.h"
35 #include "hdp/hdp_4_0_sh_mask.h"
36 #include "gc/gc_9_0_sh_mask.h"
37 #include "dce/dce_12_0_offset.h"
38 #include "dce/dce_12_0_sh_mask.h"
39 #include "vega10_enum.h"
40 #include "mmhub/mmhub_1_0_offset.h"
41 #include "athub/athub_1_0_offset.h"
42 #include "oss/osssys_4_0_offset.h"
43
44 #include "soc15.h"
45 #include "soc15_common.h"
46 #include "umc/umc_6_0_sh_mask.h"
47
48 #include "gfxhub_v1_0.h"
49 #include "mmhub_v1_0.h"
50 #include "athub_v1_0.h"
51 #include "gfxhub_v1_1.h"
52 #include "mmhub_v9_4.h"
53 #include "umc_v6_1.h"
54 #include "umc_v6_0.h"
55
56 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
57
58 #include "amdgpu_ras.h"
59 #include "amdgpu_xgmi.h"
60
61 /* add these here since we already include dce12 headers and these are for DCN */
62 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
63 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
68
69 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
70 #define AMDGPU_NUM_OF_VMIDS 8
71
72 static const u32 golden_settings_vega10_hdp[] =
73 {
74 0xf64, 0x0fffffff, 0x00000000,
75 0xf65, 0x0fffffff, 0x00000000,
76 0xf66, 0x0fffffff, 0x00000000,
77 0xf67, 0x0fffffff, 0x00000000,
78 0xf68, 0x0fffffff, 0x00000000,
79 0xf6a, 0x0fffffff, 0x00000000,
80 0xf6b, 0x0fffffff, 0x00000000,
81 0xf6c, 0x0fffffff, 0x00000000,
82 0xf6d, 0x0fffffff, 0x00000000,
83 0xf6e, 0x0fffffff, 0x00000000,
84 };
85
86 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
87 {
88 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
89 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
90 };
91
92 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
93 {
94 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
95 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
96 };
97
98 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
99 (0x000143c0 + 0x00000000),
100 (0x000143c0 + 0x00000800),
101 (0x000143c0 + 0x00001000),
102 (0x000143c0 + 0x00001800),
103 (0x000543c0 + 0x00000000),
104 (0x000543c0 + 0x00000800),
105 (0x000543c0 + 0x00001000),
106 (0x000543c0 + 0x00001800),
107 (0x000943c0 + 0x00000000),
108 (0x000943c0 + 0x00000800),
109 (0x000943c0 + 0x00001000),
110 (0x000943c0 + 0x00001800),
111 (0x000d43c0 + 0x00000000),
112 (0x000d43c0 + 0x00000800),
113 (0x000d43c0 + 0x00001000),
114 (0x000d43c0 + 0x00001800),
115 (0x001143c0 + 0x00000000),
116 (0x001143c0 + 0x00000800),
117 (0x001143c0 + 0x00001000),
118 (0x001143c0 + 0x00001800),
119 (0x001543c0 + 0x00000000),
120 (0x001543c0 + 0x00000800),
121 (0x001543c0 + 0x00001000),
122 (0x001543c0 + 0x00001800),
123 (0x001943c0 + 0x00000000),
124 (0x001943c0 + 0x00000800),
125 (0x001943c0 + 0x00001000),
126 (0x001943c0 + 0x00001800),
127 (0x001d43c0 + 0x00000000),
128 (0x001d43c0 + 0x00000800),
129 (0x001d43c0 + 0x00001000),
130 (0x001d43c0 + 0x00001800),
131 };
132
133 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
134 (0x000143e0 + 0x00000000),
135 (0x000143e0 + 0x00000800),
136 (0x000143e0 + 0x00001000),
137 (0x000143e0 + 0x00001800),
138 (0x000543e0 + 0x00000000),
139 (0x000543e0 + 0x00000800),
140 (0x000543e0 + 0x00001000),
141 (0x000543e0 + 0x00001800),
142 (0x000943e0 + 0x00000000),
143 (0x000943e0 + 0x00000800),
144 (0x000943e0 + 0x00001000),
145 (0x000943e0 + 0x00001800),
146 (0x000d43e0 + 0x00000000),
147 (0x000d43e0 + 0x00000800),
148 (0x000d43e0 + 0x00001000),
149 (0x000d43e0 + 0x00001800),
150 (0x001143e0 + 0x00000000),
151 (0x001143e0 + 0x00000800),
152 (0x001143e0 + 0x00001000),
153 (0x001143e0 + 0x00001800),
154 (0x001543e0 + 0x00000000),
155 (0x001543e0 + 0x00000800),
156 (0x001543e0 + 0x00001000),
157 (0x001543e0 + 0x00001800),
158 (0x001943e0 + 0x00000000),
159 (0x001943e0 + 0x00000800),
160 (0x001943e0 + 0x00001000),
161 (0x001943e0 + 0x00001800),
162 (0x001d43e0 + 0x00000000),
163 (0x001d43e0 + 0x00000800),
164 (0x001d43e0 + 0x00001000),
165 (0x001d43e0 + 0x00001800),
166 };
167
168 static const uint32_t ecc_umc_mcumc_status_addrs[] = {
169 (0x000143c2 + 0x00000000),
170 (0x000143c2 + 0x00000800),
171 (0x000143c2 + 0x00001000),
172 (0x000143c2 + 0x00001800),
173 (0x000543c2 + 0x00000000),
174 (0x000543c2 + 0x00000800),
175 (0x000543c2 + 0x00001000),
176 (0x000543c2 + 0x00001800),
177 (0x000943c2 + 0x00000000),
178 (0x000943c2 + 0x00000800),
179 (0x000943c2 + 0x00001000),
180 (0x000943c2 + 0x00001800),
181 (0x000d43c2 + 0x00000000),
182 (0x000d43c2 + 0x00000800),
183 (0x000d43c2 + 0x00001000),
184 (0x000d43c2 + 0x00001800),
185 (0x001143c2 + 0x00000000),
186 (0x001143c2 + 0x00000800),
187 (0x001143c2 + 0x00001000),
188 (0x001143c2 + 0x00001800),
189 (0x001543c2 + 0x00000000),
190 (0x001543c2 + 0x00000800),
191 (0x001543c2 + 0x00001000),
192 (0x001543c2 + 0x00001800),
193 (0x001943c2 + 0x00000000),
194 (0x001943c2 + 0x00000800),
195 (0x001943c2 + 0x00001000),
196 (0x001943c2 + 0x00001800),
197 (0x001d43c2 + 0x00000000),
198 (0x001d43c2 + 0x00000800),
199 (0x001d43c2 + 0x00001000),
200 (0x001d43c2 + 0x00001800),
201 };
202
203 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
204 struct amdgpu_irq_src *src,
205 unsigned type,
206 enum amdgpu_interrupt_state state)
207 {
208 u32 bits, i, tmp, reg;
209
210 bits = 0x7f;
211
212 switch (state) {
213 case AMDGPU_IRQ_STATE_DISABLE:
214 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
215 reg = ecc_umc_mcumc_ctrl_addrs[i];
216 tmp = RREG32(reg);
217 tmp &= ~bits;
218 WREG32(reg, tmp);
219 }
220 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
221 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
222 tmp = RREG32(reg);
223 tmp &= ~bits;
224 WREG32(reg, tmp);
225 }
226 break;
227 case AMDGPU_IRQ_STATE_ENABLE:
228 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
229 reg = ecc_umc_mcumc_ctrl_addrs[i];
230 tmp = RREG32(reg);
231 tmp |= bits;
232 WREG32(reg, tmp);
233 }
234 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
235 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
236 tmp = RREG32(reg);
237 tmp |= bits;
238 WREG32(reg, tmp);
239 }
240 break;
241 default:
242 break;
243 }
244
245 return 0;
246 }
247
248 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
249 struct amdgpu_irq_src *src,
250 unsigned type,
251 enum amdgpu_interrupt_state state)
252 {
253 struct amdgpu_vmhub *hub;
254 u32 tmp, reg, bits, i, j;
255
256 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
257 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
258 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
259 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
260 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
261 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
262 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
263
264 switch (state) {
265 case AMDGPU_IRQ_STATE_DISABLE:
266 for (j = 0; j < adev->num_vmhubs; j++) {
267 hub = &adev->vmhub[j];
268 for (i = 0; i < 16; i++) {
269 reg = hub->vm_context0_cntl + i;
270 tmp = RREG32(reg);
271 tmp &= ~bits;
272 WREG32(reg, tmp);
273 }
274 }
275 break;
276 case AMDGPU_IRQ_STATE_ENABLE:
277 for (j = 0; j < adev->num_vmhubs; j++) {
278 hub = &adev->vmhub[j];
279 for (i = 0; i < 16; i++) {
280 reg = hub->vm_context0_cntl + i;
281 tmp = RREG32(reg);
282 tmp |= bits;
283 WREG32(reg, tmp);
284 }
285 }
286 default:
287 break;
288 }
289
290 return 0;
291 }
292
293 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
294 struct amdgpu_irq_src *source,
295 struct amdgpu_iv_entry *entry)
296 {
297 struct amdgpu_vmhub *hub;
298 bool retry_fault = !!(entry->src_data[1] & 0x80);
299 uint32_t status = 0;
300 u64 addr;
301 char hub_name[10];
302
303 addr = (u64)entry->src_data[0] << 12;
304 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
305
306 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
307 entry->timestamp))
308 return 1; /* This also prevents sending it to KFD */
309
310 if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
311 snprintf(hub_name, sizeof(hub_name), "mmhub0");
312 hub = &adev->vmhub[AMDGPU_MMHUB_0];
313 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
314 snprintf(hub_name, sizeof(hub_name), "mmhub1");
315 hub = &adev->vmhub[AMDGPU_MMHUB_1];
316 } else {
317 snprintf(hub_name, sizeof(hub_name), "gfxhub0");
318 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
319 }
320
321 /* If it's the first fault for this address, process it normally */
322 if (retry_fault && !in_interrupt() &&
323 amdgpu_vm_handle_fault(adev, entry->pasid, addr))
324 return 1; /* This also prevents sending it to KFD */
325
326 if (!amdgpu_sriov_vf(adev)) {
327 /*
328 * Issue a dummy read to wait for the status register to
329 * be updated to avoid reading an incorrect value due to
330 * the new fast GRBM interface.
331 */
332 if (entry->vmid_src == AMDGPU_GFXHUB_0)
333 RREG32(hub->vm_l2_pro_fault_status);
334
335 status = RREG32(hub->vm_l2_pro_fault_status);
336 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
337 }
338
339 if (printk_ratelimit()) {
340 struct amdgpu_task_info task_info;
341
342 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
343 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
344
345 dev_err(adev->dev,
346 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
347 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
348 hub_name, retry_fault ? "retry" : "no-retry",
349 entry->src_id, entry->ring_id, entry->vmid,
350 entry->pasid, task_info.process_name, task_info.tgid,
351 task_info.task_name, task_info.pid);
352 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
353 addr, entry->client_id);
354 if (!amdgpu_sriov_vf(adev)) {
355 dev_err(adev->dev,
356 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
357 status);
358 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
359 REG_GET_FIELD(status,
360 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
361 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
362 REG_GET_FIELD(status,
363 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
364 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
365 REG_GET_FIELD(status,
366 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
367 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
368 REG_GET_FIELD(status,
369 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
370 dev_err(adev->dev, "\t RW: 0x%lx\n",
371 REG_GET_FIELD(status,
372 VM_L2_PROTECTION_FAULT_STATUS, RW));
373
374 }
375 }
376
377 return 0;
378 }
379
380 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
381 .set = gmc_v9_0_vm_fault_interrupt_state,
382 .process = gmc_v9_0_process_interrupt,
383 };
384
385
386 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
387 .set = gmc_v9_0_ecc_interrupt_state,
388 .process = amdgpu_umc_process_ecc_irq,
389 };
390
391 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
392 {
393 adev->gmc.vm_fault.num_types = 1;
394 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
395
396 adev->gmc.ecc_irq.num_types = 1;
397 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
398 }
399
400 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
401 uint32_t flush_type)
402 {
403 u32 req = 0;
404
405 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
406 PER_VMID_INVALIDATE_REQ, 1 << vmid);
407 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
408 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
409 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
410 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
411 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
412 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
413 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
414 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
415
416 return req;
417 }
418
419 /**
420 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
421 *
422 * @adev: amdgpu_device pointer
423 * @vmhub: vmhub type
424 *
425 */
426 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
427 uint32_t vmhub)
428 {
429 return ((vmhub == AMDGPU_MMHUB_0 ||
430 vmhub == AMDGPU_MMHUB_1) &&
431 (!amdgpu_sriov_vf(adev)) &&
432 (!(adev->asic_type == CHIP_RAVEN &&
433 adev->rev_id < 0x8 &&
434 adev->pdev->device == 0x15d8)));
435 }
436
437 /*
438 * GART
439 * VMID 0 is the physical GPU addresses as used by the kernel.
440 * VMIDs 1-15 are used for userspace clients and are handled
441 * by the amdgpu vm/hsa code.
442 */
443
444 /**
445 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
446 *
447 * @adev: amdgpu_device pointer
448 * @vmid: vm instance to flush
449 * @flush_type: the flush type
450 *
451 * Flush the TLB for the requested page table using certain type.
452 */
453 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
454 uint32_t vmhub, uint32_t flush_type)
455 {
456 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
457 const unsigned eng = 17;
458 u32 j, tmp;
459 struct amdgpu_vmhub *hub;
460
461 BUG_ON(vmhub >= adev->num_vmhubs);
462
463 hub = &adev->vmhub[vmhub];
464 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
465
466 /* This is necessary for a HW workaround under SRIOV as well
467 * as GFXOFF under bare metal
468 */
469 if (adev->gfx.kiq.ring.sched.ready &&
470 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
471 !adev->in_gpu_reset) {
472 uint32_t req = hub->vm_inv_eng0_req + eng;
473 uint32_t ack = hub->vm_inv_eng0_ack + eng;
474
475 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
476 1 << vmid);
477 return;
478 }
479
480 spin_lock(&adev->gmc.invalidate_lock);
481
482 /*
483 * It may lose gpuvm invalidate acknowldege state across power-gating
484 * off cycle, add semaphore acquire before invalidation and semaphore
485 * release after invalidation to avoid entering power gated state
486 * to WA the Issue
487 */
488
489 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
490 if (use_semaphore) {
491 for (j = 0; j < adev->usec_timeout; j++) {
492 /* a read return value of 1 means semaphore acuqire */
493 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
494 if (tmp & 0x1)
495 break;
496 udelay(1);
497 }
498
499 if (j >= adev->usec_timeout)
500 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
501 }
502
503 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
504
505 /*
506 * Issue a dummy read to wait for the ACK register to be cleared
507 * to avoid a false ACK due to the new fast GRBM interface.
508 */
509 if (vmhub == AMDGPU_GFXHUB_0)
510 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
511
512 for (j = 0; j < adev->usec_timeout; j++) {
513 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
514 if (tmp & (1 << vmid))
515 break;
516 udelay(1);
517 }
518
519 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
520 if (use_semaphore)
521 /*
522 * add semaphore release after invalidation,
523 * write with 0 means semaphore release
524 */
525 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
526
527 spin_unlock(&adev->gmc.invalidate_lock);
528
529 if (j < adev->usec_timeout)
530 return;
531
532 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
533 }
534
535 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
536 unsigned vmid, uint64_t pd_addr)
537 {
538 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
539 struct amdgpu_device *adev = ring->adev;
540 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
541 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
542 unsigned eng = ring->vm_inv_eng;
543
544 /*
545 * It may lose gpuvm invalidate acknowldege state across power-gating
546 * off cycle, add semaphore acquire before invalidation and semaphore
547 * release after invalidation to avoid entering power gated state
548 * to WA the Issue
549 */
550
551 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
552 if (use_semaphore)
553 /* a read return value of 1 means semaphore acuqire */
554 amdgpu_ring_emit_reg_wait(ring,
555 hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
556
557 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
558 lower_32_bits(pd_addr));
559
560 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
561 upper_32_bits(pd_addr));
562
563 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
564 hub->vm_inv_eng0_ack + eng,
565 req, 1 << vmid);
566
567 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
568 if (use_semaphore)
569 /*
570 * add semaphore release after invalidation,
571 * write with 0 means semaphore release
572 */
573 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
574
575 return pd_addr;
576 }
577
578 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
579 unsigned pasid)
580 {
581 struct amdgpu_device *adev = ring->adev;
582 uint32_t reg;
583
584 /* Do nothing because there's no lut register for mmhub1. */
585 if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
586 return;
587
588 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
589 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
590 else
591 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
592
593 amdgpu_ring_emit_wreg(ring, reg, pasid);
594 }
595
596 /*
597 * PTE format on VEGA 10:
598 * 63:59 reserved
599 * 58:57 mtype
600 * 56 F
601 * 55 L
602 * 54 P
603 * 53 SW
604 * 52 T
605 * 50:48 reserved
606 * 47:12 4k physical page base address
607 * 11:7 fragment
608 * 6 write
609 * 5 read
610 * 4 exe
611 * 3 Z
612 * 2 snooped
613 * 1 system
614 * 0 valid
615 *
616 * PDE format on VEGA 10:
617 * 63:59 block fragment size
618 * 58:55 reserved
619 * 54 P
620 * 53:48 reserved
621 * 47:6 physical base address of PD or PTE
622 * 5:3 reserved
623 * 2 C
624 * 1 system
625 * 0 valid
626 */
627
628 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
629
630 {
631 switch (flags) {
632 case AMDGPU_VM_MTYPE_DEFAULT:
633 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
634 case AMDGPU_VM_MTYPE_NC:
635 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
636 case AMDGPU_VM_MTYPE_WC:
637 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
638 case AMDGPU_VM_MTYPE_RW:
639 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
640 case AMDGPU_VM_MTYPE_CC:
641 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
642 case AMDGPU_VM_MTYPE_UC:
643 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
644 default:
645 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
646 }
647 }
648
649 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
650 uint64_t *addr, uint64_t *flags)
651 {
652 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
653 *addr = adev->vm_manager.vram_base_offset + *addr -
654 adev->gmc.vram_start;
655 BUG_ON(*addr & 0xFFFF00000000003FULL);
656
657 if (!adev->gmc.translate_further)
658 return;
659
660 if (level == AMDGPU_VM_PDB1) {
661 /* Set the block fragment size */
662 if (!(*flags & AMDGPU_PDE_PTE))
663 *flags |= AMDGPU_PDE_BFS(0x9);
664
665 } else if (level == AMDGPU_VM_PDB0) {
666 if (*flags & AMDGPU_PDE_PTE)
667 *flags &= ~AMDGPU_PDE_PTE;
668 else
669 *flags |= AMDGPU_PTE_TF;
670 }
671 }
672
673 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
674 struct amdgpu_bo_va_mapping *mapping,
675 uint64_t *flags)
676 {
677 *flags &= ~AMDGPU_PTE_EXECUTABLE;
678 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
679
680 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
681 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
682
683 if (mapping->flags & AMDGPU_PTE_PRT) {
684 *flags |= AMDGPU_PTE_PRT;
685 *flags &= ~AMDGPU_PTE_VALID;
686 }
687
688 if (adev->asic_type == CHIP_ARCTURUS &&
689 !(*flags & AMDGPU_PTE_SYSTEM) &&
690 mapping->bo_va->is_xgmi)
691 *flags |= AMDGPU_PTE_SNOOPED;
692 }
693
694 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
695 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
696 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
697 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
698 .map_mtype = gmc_v9_0_map_mtype,
699 .get_vm_pde = gmc_v9_0_get_vm_pde,
700 .get_vm_pte = gmc_v9_0_get_vm_pte
701 };
702
703 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
704 {
705 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
706 }
707
708 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
709 {
710 switch (adev->asic_type) {
711 case CHIP_VEGA10:
712 adev->umc.funcs = &umc_v6_0_funcs;
713 break;
714 case CHIP_VEGA20:
715 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
716 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
717 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
718 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
719 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
720 adev->umc.funcs = &umc_v6_1_funcs;
721 break;
722 case CHIP_ARCTURUS:
723 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
724 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
725 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
726 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
727 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
728 adev->umc.funcs = &umc_v6_1_funcs;
729 break;
730 default:
731 break;
732 }
733 }
734
735 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
736 {
737 switch (adev->asic_type) {
738 case CHIP_VEGA20:
739 adev->mmhub.funcs = &mmhub_v1_0_funcs;
740 break;
741 case CHIP_ARCTURUS:
742 adev->mmhub.funcs = &mmhub_v9_4_funcs;
743 break;
744 default:
745 break;
746 }
747 }
748
749 static int gmc_v9_0_early_init(void *handle)
750 {
751 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
752
753 gmc_v9_0_set_gmc_funcs(adev);
754 gmc_v9_0_set_irq_funcs(adev);
755 gmc_v9_0_set_umc_funcs(adev);
756 gmc_v9_0_set_mmhub_funcs(adev);
757
758 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
759 adev->gmc.shared_aperture_end =
760 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
761 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
762 adev->gmc.private_aperture_end =
763 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
764
765 return 0;
766 }
767
768 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
769 {
770
771 /*
772 * TODO:
773 * Currently there is a bug where some memory client outside
774 * of the driver writes to first 8M of VRAM on S3 resume,
775 * this overrides GART which by default gets placed in first 8M and
776 * causes VM_FAULTS once GTT is accessed.
777 * Keep the stolen memory reservation until the while this is not solved.
778 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
779 */
780 switch (adev->asic_type) {
781 case CHIP_VEGA10:
782 case CHIP_RAVEN:
783 case CHIP_ARCTURUS:
784 case CHIP_RENOIR:
785 return true;
786 case CHIP_VEGA12:
787 case CHIP_VEGA20:
788 default:
789 return false;
790 }
791 }
792
793 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
794 {
795 struct amdgpu_ring *ring;
796 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
797 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
798 GFXHUB_FREE_VM_INV_ENGS_BITMAP};
799 unsigned i;
800 unsigned vmhub, inv_eng;
801
802 for (i = 0; i < adev->num_rings; ++i) {
803 ring = adev->rings[i];
804 vmhub = ring->funcs->vmhub;
805
806 inv_eng = ffs(vm_inv_engs[vmhub]);
807 if (!inv_eng) {
808 dev_err(adev->dev, "no VM inv eng for ring %s\n",
809 ring->name);
810 return -EINVAL;
811 }
812
813 ring->vm_inv_eng = inv_eng - 1;
814 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
815
816 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
817 ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
818 }
819
820 return 0;
821 }
822
823 static int gmc_v9_0_late_init(void *handle)
824 {
825 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
826 int r;
827
828 if (!gmc_v9_0_keep_stolen_memory(adev))
829 amdgpu_bo_late_init(adev);
830
831 r = gmc_v9_0_allocate_vm_inv_eng(adev);
832 if (r)
833 return r;
834 /* Check if ecc is available */
835 if (!amdgpu_sriov_vf(adev)) {
836 switch (adev->asic_type) {
837 case CHIP_VEGA10:
838 case CHIP_VEGA20:
839 case CHIP_ARCTURUS:
840 r = amdgpu_atomfirmware_mem_ecc_supported(adev);
841 if (!r) {
842 DRM_INFO("ECC is not present.\n");
843 if (adev->df_funcs->enable_ecc_force_par_wr_rmw)
844 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
845 } else {
846 DRM_INFO("ECC is active.\n");
847 }
848
849 r = amdgpu_atomfirmware_sram_ecc_supported(adev);
850 if (!r) {
851 DRM_INFO("SRAM ECC is not present.\n");
852 } else {
853 DRM_INFO("SRAM ECC is active.\n");
854 }
855 break;
856 default:
857 break;
858 }
859 }
860
861 r = amdgpu_gmc_ras_late_init(adev);
862 if (r)
863 return r;
864
865 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
866 }
867
868 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
869 struct amdgpu_gmc *mc)
870 {
871 u64 base = 0;
872
873 if (adev->asic_type == CHIP_ARCTURUS)
874 base = mmhub_v9_4_get_fb_location(adev);
875 else if (!amdgpu_sriov_vf(adev))
876 base = mmhub_v1_0_get_fb_location(adev);
877
878 /* add the xgmi offset of the physical node */
879 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
880 amdgpu_gmc_vram_location(adev, mc, base);
881 amdgpu_gmc_gart_location(adev, mc);
882 amdgpu_gmc_agp_location(adev, mc);
883 /* base offset of vram pages */
884 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
885
886 /* XXX: add the xgmi offset of the physical node? */
887 adev->vm_manager.vram_base_offset +=
888 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
889 }
890
891 /**
892 * gmc_v9_0_mc_init - initialize the memory controller driver params
893 *
894 * @adev: amdgpu_device pointer
895 *
896 * Look up the amount of vram, vram width, and decide how to place
897 * vram and gart within the GPU's physical address space.
898 * Returns 0 for success.
899 */
900 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
901 {
902 int r;
903
904 /* size in MB on si */
905 adev->gmc.mc_vram_size =
906 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
907 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
908
909 if (!(adev->flags & AMD_IS_APU)) {
910 r = amdgpu_device_resize_fb_bar(adev);
911 if (r)
912 return r;
913 }
914 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
915 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
916
917 #ifdef CONFIG_X86_64
918 if (adev->flags & AMD_IS_APU) {
919 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
920 adev->gmc.aper_size = adev->gmc.real_vram_size;
921 }
922 #endif
923 /* In case the PCI BAR is larger than the actual amount of vram */
924 adev->gmc.visible_vram_size = adev->gmc.aper_size;
925 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
926 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
927
928 /* set the gart size */
929 if (amdgpu_gart_size == -1) {
930 switch (adev->asic_type) {
931 case CHIP_VEGA10: /* all engines support GPUVM */
932 case CHIP_VEGA12: /* all engines support GPUVM */
933 case CHIP_VEGA20:
934 case CHIP_ARCTURUS:
935 default:
936 adev->gmc.gart_size = 512ULL << 20;
937 break;
938 case CHIP_RAVEN: /* DCE SG support */
939 case CHIP_RENOIR:
940 adev->gmc.gart_size = 1024ULL << 20;
941 break;
942 }
943 } else {
944 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
945 }
946
947 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
948
949 return 0;
950 }
951
952 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
953 {
954 int r;
955
956 if (adev->gart.bo) {
957 WARN(1, "VEGA10 PCIE GART already initialized\n");
958 return 0;
959 }
960 /* Initialize common gart structure */
961 r = amdgpu_gart_init(adev);
962 if (r)
963 return r;
964 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
965 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
966 AMDGPU_PTE_EXECUTABLE;
967 return amdgpu_gart_table_vram_alloc(adev);
968 }
969
970 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
971 {
972 u32 d1vga_control;
973 unsigned size;
974
975 /*
976 * TODO Remove once GART corruption is resolved
977 * Check related code in gmc_v9_0_sw_fini
978 * */
979 if (gmc_v9_0_keep_stolen_memory(adev))
980 return 9 * 1024 * 1024;
981
982 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
983 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
984 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
985 } else {
986 u32 viewport;
987
988 switch (adev->asic_type) {
989 case CHIP_RAVEN:
990 case CHIP_RENOIR:
991 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
992 size = (REG_GET_FIELD(viewport,
993 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
994 REG_GET_FIELD(viewport,
995 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
996 4);
997 break;
998 case CHIP_VEGA10:
999 case CHIP_VEGA12:
1000 case CHIP_VEGA20:
1001 default:
1002 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1003 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1004 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1005 4);
1006 break;
1007 }
1008 }
1009 /* return 0 if the pre-OS buffer uses up most of vram */
1010 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1011 return 0;
1012
1013 return size;
1014 }
1015
1016 static int gmc_v9_0_sw_init(void *handle)
1017 {
1018 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1019 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1020
1021 gfxhub_v1_0_init(adev);
1022 if (adev->asic_type == CHIP_ARCTURUS)
1023 mmhub_v9_4_init(adev);
1024 else
1025 mmhub_v1_0_init(adev);
1026
1027 spin_lock_init(&adev->gmc.invalidate_lock);
1028
1029 r = amdgpu_atomfirmware_get_vram_info(adev,
1030 &vram_width, &vram_type, &vram_vendor);
1031 if (amdgpu_sriov_vf(adev))
1032 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1033 * and DF related registers is not readable, seems hardcord is the
1034 * only way to set the correct vram_width
1035 */
1036 adev->gmc.vram_width = 2048;
1037 else if (amdgpu_emu_mode != 1)
1038 adev->gmc.vram_width = vram_width;
1039
1040 if (!adev->gmc.vram_width) {
1041 int chansize, numchan;
1042
1043 /* hbm memory channel size */
1044 if (adev->flags & AMD_IS_APU)
1045 chansize = 64;
1046 else
1047 chansize = 128;
1048
1049 numchan = adev->df_funcs->get_hbm_channel_number(adev);
1050 adev->gmc.vram_width = numchan * chansize;
1051 }
1052
1053 adev->gmc.vram_type = vram_type;
1054 adev->gmc.vram_vendor = vram_vendor;
1055 switch (adev->asic_type) {
1056 case CHIP_RAVEN:
1057 adev->num_vmhubs = 2;
1058
1059 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1060 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1061 } else {
1062 /* vm_size is 128TB + 512GB for legacy 3-level page support */
1063 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1064 adev->gmc.translate_further =
1065 adev->vm_manager.num_level > 1;
1066 }
1067 break;
1068 case CHIP_VEGA10:
1069 case CHIP_VEGA12:
1070 case CHIP_VEGA20:
1071 case CHIP_RENOIR:
1072 adev->num_vmhubs = 2;
1073
1074
1075 /*
1076 * To fulfill 4-level page support,
1077 * vm size is 256TB (48bit), maximum size of Vega10,
1078 * block size 512 (9bit)
1079 */
1080 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1081 if (amdgpu_sriov_vf(adev))
1082 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1083 else
1084 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1085 break;
1086 case CHIP_ARCTURUS:
1087 adev->num_vmhubs = 3;
1088
1089 /* Keep the vm size same with Vega20 */
1090 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1091 break;
1092 default:
1093 break;
1094 }
1095
1096 /* This interrupt is VMC page fault.*/
1097 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1098 &adev->gmc.vm_fault);
1099 if (r)
1100 return r;
1101
1102 if (adev->asic_type == CHIP_ARCTURUS) {
1103 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1104 &adev->gmc.vm_fault);
1105 if (r)
1106 return r;
1107 }
1108
1109 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1110 &adev->gmc.vm_fault);
1111
1112 if (r)
1113 return r;
1114
1115 /* interrupt sent to DF. */
1116 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1117 &adev->gmc.ecc_irq);
1118 if (r)
1119 return r;
1120
1121 /* Set the internal MC address mask
1122 * This is the max address of the GPU's
1123 * internal address space.
1124 */
1125 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1126
1127 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1128 if (r) {
1129 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1130 return r;
1131 }
1132 adev->need_swiotlb = drm_need_swiotlb(44);
1133
1134 if (adev->gmc.xgmi.supported) {
1135 r = gfxhub_v1_1_get_xgmi_info(adev);
1136 if (r)
1137 return r;
1138 }
1139
1140 r = gmc_v9_0_mc_init(adev);
1141 if (r)
1142 return r;
1143
1144 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1145
1146 /* Memory manager */
1147 r = amdgpu_bo_init(adev);
1148 if (r)
1149 return r;
1150
1151 r = gmc_v9_0_gart_init(adev);
1152 if (r)
1153 return r;
1154
1155 /*
1156 * number of VMs
1157 * VMID 0 is reserved for System
1158 * amdgpu graphics/compute will use VMIDs 1-7
1159 * amdkfd will use VMIDs 8-15
1160 */
1161 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1162 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1163 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
1164
1165 amdgpu_vm_manager_init(adev);
1166
1167 return 0;
1168 }
1169
1170 static int gmc_v9_0_sw_fini(void *handle)
1171 {
1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1173 void *stolen_vga_buf;
1174
1175 amdgpu_gmc_ras_fini(adev);
1176 amdgpu_gem_force_release(adev);
1177 amdgpu_vm_manager_fini(adev);
1178
1179 if (gmc_v9_0_keep_stolen_memory(adev))
1180 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1181
1182 amdgpu_gart_table_vram_free(adev);
1183 amdgpu_bo_fini(adev);
1184 amdgpu_gart_fini(adev);
1185
1186 return 0;
1187 }
1188
1189 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1190 {
1191
1192 switch (adev->asic_type) {
1193 case CHIP_VEGA10:
1194 if (amdgpu_sriov_vf(adev))
1195 break;
1196 /* fall through */
1197 case CHIP_VEGA20:
1198 soc15_program_register_sequence(adev,
1199 golden_settings_mmhub_1_0_0,
1200 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1201 soc15_program_register_sequence(adev,
1202 golden_settings_athub_1_0_0,
1203 ARRAY_SIZE(golden_settings_athub_1_0_0));
1204 break;
1205 case CHIP_VEGA12:
1206 break;
1207 case CHIP_RAVEN:
1208 /* TODO for renoir */
1209 soc15_program_register_sequence(adev,
1210 golden_settings_athub_1_0_0,
1211 ARRAY_SIZE(golden_settings_athub_1_0_0));
1212 break;
1213 default:
1214 break;
1215 }
1216 }
1217
1218 /**
1219 * gmc_v9_0_gart_enable - gart enable
1220 *
1221 * @adev: amdgpu_device pointer
1222 */
1223 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1224 {
1225 int r;
1226
1227 if (adev->gart.bo == NULL) {
1228 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1229 return -EINVAL;
1230 }
1231 r = amdgpu_gart_table_vram_pin(adev);
1232 if (r)
1233 return r;
1234
1235 r = gfxhub_v1_0_gart_enable(adev);
1236 if (r)
1237 return r;
1238
1239 if (adev->asic_type == CHIP_ARCTURUS)
1240 r = mmhub_v9_4_gart_enable(adev);
1241 else
1242 r = mmhub_v1_0_gart_enable(adev);
1243 if (r)
1244 return r;
1245
1246 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1247 (unsigned)(adev->gmc.gart_size >> 20),
1248 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1249 adev->gart.ready = true;
1250 return 0;
1251 }
1252
1253 static int gmc_v9_0_hw_init(void *handle)
1254 {
1255 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1256 bool value;
1257 int r, i;
1258 u32 tmp;
1259
1260 /* The sequence of these two function calls matters.*/
1261 gmc_v9_0_init_golden_registers(adev);
1262
1263 if (adev->mode_info.num_crtc) {
1264 if (adev->asic_type != CHIP_ARCTURUS) {
1265 /* Lockout access through VGA aperture*/
1266 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1267
1268 /* disable VGA render */
1269 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1270 }
1271 }
1272
1273 amdgpu_device_program_register_sequence(adev,
1274 golden_settings_vega10_hdp,
1275 ARRAY_SIZE(golden_settings_vega10_hdp));
1276
1277 switch (adev->asic_type) {
1278 case CHIP_RAVEN:
1279 /* TODO for renoir */
1280 mmhub_v1_0_update_power_gating(adev, true);
1281 break;
1282 case CHIP_ARCTURUS:
1283 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
1284 break;
1285 default:
1286 break;
1287 }
1288
1289 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1290
1291 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1292 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1293
1294 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1295 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1296
1297 /* After HDP is initialized, flush HDP.*/
1298 adev->nbio.funcs->hdp_flush(adev, NULL);
1299
1300 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1301 value = false;
1302 else
1303 value = true;
1304
1305 gfxhub_v1_0_set_fault_enable_default(adev, value);
1306 if (adev->asic_type == CHIP_ARCTURUS)
1307 mmhub_v9_4_set_fault_enable_default(adev, value);
1308 else
1309 mmhub_v1_0_set_fault_enable_default(adev, value);
1310
1311 for (i = 0; i < adev->num_vmhubs; ++i)
1312 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1313
1314 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1315 adev->umc.funcs->init_registers(adev);
1316
1317 r = gmc_v9_0_gart_enable(adev);
1318
1319 return r;
1320 }
1321
1322 /**
1323 * gmc_v9_0_gart_disable - gart disable
1324 *
1325 * @adev: amdgpu_device pointer
1326 *
1327 * This disables all VM page table.
1328 */
1329 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1330 {
1331 gfxhub_v1_0_gart_disable(adev);
1332 if (adev->asic_type == CHIP_ARCTURUS)
1333 mmhub_v9_4_gart_disable(adev);
1334 else
1335 mmhub_v1_0_gart_disable(adev);
1336 amdgpu_gart_table_vram_unpin(adev);
1337 }
1338
1339 static int gmc_v9_0_hw_fini(void *handle)
1340 {
1341 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1342
1343 if (amdgpu_sriov_vf(adev)) {
1344 /* full access mode, so don't touch any GMC register */
1345 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1346 return 0;
1347 }
1348
1349 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1350 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1351 gmc_v9_0_gart_disable(adev);
1352
1353 return 0;
1354 }
1355
1356 static int gmc_v9_0_suspend(void *handle)
1357 {
1358 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1359
1360 return gmc_v9_0_hw_fini(adev);
1361 }
1362
1363 static int gmc_v9_0_resume(void *handle)
1364 {
1365 int r;
1366 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1367
1368 r = gmc_v9_0_hw_init(adev);
1369 if (r)
1370 return r;
1371
1372 amdgpu_vmid_reset_all(adev);
1373
1374 return 0;
1375 }
1376
1377 static bool gmc_v9_0_is_idle(void *handle)
1378 {
1379 /* MC is always ready in GMC v9.*/
1380 return true;
1381 }
1382
1383 static int gmc_v9_0_wait_for_idle(void *handle)
1384 {
1385 /* There is no need to wait for MC idle in GMC v9.*/
1386 return 0;
1387 }
1388
1389 static int gmc_v9_0_soft_reset(void *handle)
1390 {
1391 /* XXX for emulation.*/
1392 return 0;
1393 }
1394
1395 static int gmc_v9_0_set_clockgating_state(void *handle,
1396 enum amd_clockgating_state state)
1397 {
1398 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1399
1400 if (adev->asic_type == CHIP_ARCTURUS)
1401 mmhub_v9_4_set_clockgating(adev, state);
1402 else
1403 mmhub_v1_0_set_clockgating(adev, state);
1404
1405 athub_v1_0_set_clockgating(adev, state);
1406
1407 return 0;
1408 }
1409
1410 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1411 {
1412 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1413
1414 if (adev->asic_type == CHIP_ARCTURUS)
1415 mmhub_v9_4_get_clockgating(adev, flags);
1416 else
1417 mmhub_v1_0_get_clockgating(adev, flags);
1418
1419 athub_v1_0_get_clockgating(adev, flags);
1420 }
1421
1422 static int gmc_v9_0_set_powergating_state(void *handle,
1423 enum amd_powergating_state state)
1424 {
1425 return 0;
1426 }
1427
1428 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1429 .name = "gmc_v9_0",
1430 .early_init = gmc_v9_0_early_init,
1431 .late_init = gmc_v9_0_late_init,
1432 .sw_init = gmc_v9_0_sw_init,
1433 .sw_fini = gmc_v9_0_sw_fini,
1434 .hw_init = gmc_v9_0_hw_init,
1435 .hw_fini = gmc_v9_0_hw_fini,
1436 .suspend = gmc_v9_0_suspend,
1437 .resume = gmc_v9_0_resume,
1438 .is_idle = gmc_v9_0_is_idle,
1439 .wait_for_idle = gmc_v9_0_wait_for_idle,
1440 .soft_reset = gmc_v9_0_soft_reset,
1441 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1442 .set_powergating_state = gmc_v9_0_set_powergating_state,
1443 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1444 };
1445
1446 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1447 {
1448 .type = AMD_IP_BLOCK_TYPE_GMC,
1449 .major = 9,
1450 .minor = 0,
1451 .rev = 0,
1452 .funcs = &gmc_v9_0_ip_funcs,
1453 };
Michael's Linux tree.