2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "amdgpu_atombios.h"
26 #include "amdgpu_ras.h"
28 #include "hdp/hdp_4_0_offset.h"
29 #include "hdp/hdp_4_0_sh_mask.h"
30 #include <uapi/linux/kfd_ioctl.h>
32 /* for Vega20 register name change */
33 #define mmHDP_MEM_POWER_CTRL 0x00d4
34 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
35 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
36 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
37 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
38 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
40 static void hdp_v4_0_flush_hdp(struct amdgpu_device
*adev
,
41 struct amdgpu_ring
*ring
)
43 if (!ring
|| !ring
->funcs
->emit_wreg
)
44 WREG32_NO_KIQ((adev
->rmmio_remap
.reg_offset
+ KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL
) >> 2, 0);
46 amdgpu_ring_emit_wreg(ring
, (adev
->rmmio_remap
.reg_offset
+ KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL
) >> 2, 0);
49 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device
*adev
,
50 struct amdgpu_ring
*ring
)
52 if (amdgpu_ip_version(adev
, HDP_HWIP
, 0) == IP_VERSION(4, 4, 0) ||
53 amdgpu_ip_version(adev
, HDP_HWIP
, 0) == IP_VERSION(4, 4, 2))
56 if (!ring
|| !ring
->funcs
->emit_wreg
)
57 WREG32_SOC15_NO_KIQ(HDP
, 0, mmHDP_READ_CACHE_INVALIDATE
, 1);
59 amdgpu_ring_emit_wreg(ring
, SOC15_REG_OFFSET(
60 HDP
, 0, mmHDP_READ_CACHE_INVALIDATE
), 1);
63 static void hdp_v4_0_query_ras_error_count(struct amdgpu_device
*adev
,
64 void *ras_error_status
)
66 struct ras_err_data
*err_data
= (struct ras_err_data
*)ras_error_status
;
68 err_data
->ue_count
= 0;
69 err_data
->ce_count
= 0;
71 if (!amdgpu_ras_is_supported(adev
, AMDGPU_RAS_BLOCK__HDP
))
74 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
75 err_data
->ue_count
+= RREG32_SOC15(HDP
, 0, mmHDP_EDC_CNT
);
78 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device
*adev
)
80 if (!amdgpu_ras_is_supported(adev
, AMDGPU_RAS_BLOCK__HDP
))
83 if (amdgpu_ip_version(adev
, HDP_HWIP
, 0) >= IP_VERSION(4, 4, 0))
84 WREG32_SOC15(HDP
, 0, mmHDP_EDC_CNT
, 0);
86 /*read back hdp ras counter to reset it to 0 */
87 RREG32_SOC15(HDP
, 0, mmHDP_EDC_CNT
);
90 static void hdp_v4_0_update_clock_gating(struct amdgpu_device
*adev
,
95 if (amdgpu_ip_version(adev
, HDP_HWIP
, 0) == IP_VERSION(4, 0, 0) ||
96 amdgpu_ip_version(adev
, HDP_HWIP
, 0) == IP_VERSION(4, 0, 1) ||
97 amdgpu_ip_version(adev
, HDP_HWIP
, 0) == IP_VERSION(4, 1, 1) ||
98 amdgpu_ip_version(adev
, HDP_HWIP
, 0) == IP_VERSION(4, 1, 0)) {
99 def
= data
= RREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_LS
));
101 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_LS
))
102 data
|= HDP_MEM_POWER_LS__LS_ENABLE_MASK
;
104 data
&= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK
;
107 WREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_LS
), data
);
109 def
= data
= RREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_CTRL
));
111 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_LS
))
112 data
|= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK
|
113 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
|
114 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK
|
115 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK
;
117 data
&= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK
|
118 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
|
119 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK
|
120 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK
);
123 WREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_CTRL
), data
);
127 static void hdp_v4_0_get_clockgating_state(struct amdgpu_device
*adev
,
132 if (amdgpu_ip_version(adev
, HDP_HWIP
, 0) == IP_VERSION(4, 4, 2)) {
133 /* Default enabled */
134 *flags
|= AMD_CG_SUPPORT_HDP_MGCG
;
137 /* AMD_CG_SUPPORT_HDP_LS */
138 data
= RREG32(SOC15_REG_OFFSET(HDP
, 0, mmHDP_MEM_POWER_LS
));
139 if (data
& HDP_MEM_POWER_LS__LS_ENABLE_MASK
)
140 *flags
|= AMD_CG_SUPPORT_HDP_LS
;
143 static void hdp_v4_0_init_registers(struct amdgpu_device
*adev
)
145 switch (amdgpu_ip_version(adev
, HDP_HWIP
, 0)) {
146 case IP_VERSION(4, 2, 1):
147 WREG32_FIELD15(HDP
, 0, HDP_MMHUB_CNTL
, HDP_MMHUB_GCC
, 1);
153 /* Do not program registers if VF */
154 if (amdgpu_sriov_vf(adev
))
157 WREG32_FIELD15(HDP
, 0, HDP_MISC_CNTL
, FLUSH_INVALIDATE_CACHE
, 1);
159 if (amdgpu_ip_version(adev
, HDP_HWIP
, 0) == IP_VERSION(4, 4, 0))
160 WREG32_FIELD15(HDP
, 0, HDP_MISC_CNTL
, READ_BUFFER_WATERMARK
, 2);
162 WREG32_SOC15(HDP
, 0, mmHDP_NONSURFACE_BASE
, (adev
->gmc
.vram_start
>> 8));
163 WREG32_SOC15(HDP
, 0, mmHDP_NONSURFACE_BASE_HI
, (adev
->gmc
.vram_start
>> 40));
166 struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops
= {
167 .query_ras_error_count
= hdp_v4_0_query_ras_error_count
,
168 .reset_ras_error_count
= hdp_v4_0_reset_ras_error_count
,
171 struct amdgpu_hdp_ras hdp_v4_0_ras
= {
173 .hw_ops
= &hdp_v4_0_ras_hw_ops
,
177 const struct amdgpu_hdp_funcs hdp_v4_0_funcs
= {
178 .flush_hdp
= hdp_v4_0_flush_hdp
,
179 .invalidate_hdp
= hdp_v4_0_invalidate_hdp
,
180 .update_clock_gating
= hdp_v4_0_update_clock_gating
,
181 .get_clock_gating_state
= hdp_v4_0_get_clockgating_state
,
182 .init_registers
= hdp_v4_0_init_registers
,