]> git.ipfire.org Git - thirdparty/linux.git/blob - drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
projects / thirdparty / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/amdgpu/sdma: simplify sdma instance setup
[thirdparty/linux.git] / drivers / gpu / drm / amd / amdgpu / sdma_v4_0.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
29
30 #include "sdma0/sdma0_4_0_offset.h"
31 #include "sdma0/sdma0_4_0_sh_mask.h"
32 #include "sdma1/sdma1_4_0_offset.h"
33 #include "sdma1/sdma1_4_0_sh_mask.h"
34 #include "hdp/hdp_4_0_offset.h"
35 #include "sdma0/sdma0_4_1_default.h"
36
37 #include "soc15_common.h"
38 #include "soc15.h"
39 #include "vega10_sdma_pkt_open.h"
40
41 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
42 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
43 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
44 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
45 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
46 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
47 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
48
49 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
50 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
51
52 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
53 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
54 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
55 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
56
57 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
58 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
59 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
60 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
61 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
62 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
63 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
64 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
65 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
66 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
67 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
68 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
69 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
70 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
71 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
72 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
73 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
75 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
77 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
78 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
80 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)
82 };
83
84 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
85 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
86 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
87 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
88 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
89 };
90
91 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
94 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
95 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
96 };
97
98 static const struct soc15_reg_golden golden_settings_sdma_4_1[] =
99 {
100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
103 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
105 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
106 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
108 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0)
110 };
111
112 static const struct soc15_reg_golden golden_settings_sdma_4_2[] =
113 {
114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
121 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
122 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
125 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
126 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
127 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
128 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
129 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
130 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)
132 };
133
134 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
135 {
136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
138 };
139
140 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
141 u32 instance, u32 offset)
142 {
143 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
144 (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
145 }
146
147 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
148 {
149 switch (adev->asic_type) {
150 case CHIP_VEGA10:
151 soc15_program_register_sequence(adev,
152 golden_settings_sdma_4,
153 ARRAY_SIZE(golden_settings_sdma_4));
154 soc15_program_register_sequence(adev,
155 golden_settings_sdma_vg10,
156 ARRAY_SIZE(golden_settings_sdma_vg10));
157 break;
158 case CHIP_VEGA12:
159 soc15_program_register_sequence(adev,
160 golden_settings_sdma_4,
161 ARRAY_SIZE(golden_settings_sdma_4));
162 soc15_program_register_sequence(adev,
163 golden_settings_sdma_vg12,
164 ARRAY_SIZE(golden_settings_sdma_vg12));
165 break;
166 case CHIP_VEGA20:
167 soc15_program_register_sequence(adev,
168 golden_settings_sdma_4_2,
169 ARRAY_SIZE(golden_settings_sdma_4_2));
170 break;
171 case CHIP_RAVEN:
172 soc15_program_register_sequence(adev,
173 golden_settings_sdma_4_1,
174 ARRAY_SIZE(golden_settings_sdma_4_1));
175 soc15_program_register_sequence(adev,
176 golden_settings_sdma_rv1,
177 ARRAY_SIZE(golden_settings_sdma_rv1));
178 break;
179 default:
180 break;
181 }
182 }
183
184 /**
185 * sdma_v4_0_init_microcode - load ucode images from disk
186 *
187 * @adev: amdgpu_device pointer
188 *
189 * Use the firmware interface to load the ucode images into
190 * the driver (not loaded into hw).
191 * Returns 0 on success, error on failure.
192 */
193
194 // emulation only, won't work on real chip
195 // vega10 real chip need to use PSP to load firmware
196 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
197 {
198 const char *chip_name;
199 char fw_name[30];
200 int err = 0, i;
201 struct amdgpu_firmware_info *info = NULL;
202 const struct common_firmware_header *header = NULL;
203 const struct sdma_firmware_header_v1_0 *hdr;
204
205 DRM_DEBUG("\n");
206
207 switch (adev->asic_type) {
208 case CHIP_VEGA10:
209 chip_name = "vega10";
210 break;
211 case CHIP_VEGA12:
212 chip_name = "vega12";
213 break;
214 case CHIP_VEGA20:
215 chip_name = "vega20";
216 break;
217 case CHIP_RAVEN:
218 chip_name = "raven";
219 break;
220 default:
221 BUG();
222 }
223
224 for (i = 0; i < adev->sdma.num_instances; i++) {
225 if (i == 0)
226 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
227 else
228 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
229 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
230 if (err)
231 goto out;
232 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
233 if (err)
234 goto out;
235 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
236 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
237 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
238 if (adev->sdma.instance[i].feature_version >= 20)
239 adev->sdma.instance[i].burst_nop = true;
240 DRM_DEBUG("psp_load == '%s'\n",
241 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
242
243 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
244 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
245 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
246 info->fw = adev->sdma.instance[i].fw;
247 header = (const struct common_firmware_header *)info->fw->data;
248 adev->firmware.fw_size +=
249 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
250 }
251 }
252 out:
253 if (err) {
254 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
255 for (i = 0; i < adev->sdma.num_instances; i++) {
256 release_firmware(adev->sdma.instance[i].fw);
257 adev->sdma.instance[i].fw = NULL;
258 }
259 }
260 return err;
261 }
262
263 /**
264 * sdma_v4_0_ring_get_rptr - get the current read pointer
265 *
266 * @ring: amdgpu ring pointer
267 *
268 * Get the current rptr from the hardware (VEGA10+).
269 */
270 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
271 {
272 u64 *rptr;
273
274 /* XXX check if swapping is necessary on BE */
275 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
276
277 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
278 return ((*rptr) >> 2);
279 }
280
281 /**
282 * sdma_v4_0_ring_get_wptr - get the current write pointer
283 *
284 * @ring: amdgpu ring pointer
285 *
286 * Get the current wptr from the hardware (VEGA10+).
287 */
288 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
289 {
290 struct amdgpu_device *adev = ring->adev;
291 u64 wptr;
292
293 if (ring->use_doorbell) {
294 /* XXX check if swapping is necessary on BE */
295 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
296 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
297 } else {
298 u32 lowbit, highbit;
299
300 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
301 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
302
303 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
304 ring->me, highbit, lowbit);
305 wptr = highbit;
306 wptr = wptr << 32;
307 wptr |= lowbit;
308 }
309
310 return wptr >> 2;
311 }
312
313 /**
314 * sdma_v4_0_ring_set_wptr - commit the write pointer
315 *
316 * @ring: amdgpu ring pointer
317 *
318 * Write the wptr back to the hardware (VEGA10+).
319 */
320 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
321 {
322 struct amdgpu_device *adev = ring->adev;
323
324 DRM_DEBUG("Setting write pointer\n");
325 if (ring->use_doorbell) {
326 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
327
328 DRM_DEBUG("Using doorbell -- "
329 "wptr_offs == 0x%08x "
330 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
331 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
332 ring->wptr_offs,
333 lower_32_bits(ring->wptr << 2),
334 upper_32_bits(ring->wptr << 2));
335 /* XXX check if swapping is necessary on BE */
336 WRITE_ONCE(*wb, (ring->wptr << 2));
337 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
338 ring->doorbell_index, ring->wptr << 2);
339 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
340 } else {
341 DRM_DEBUG("Not using doorbell -- "
342 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
343 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
344 ring->me,
345 lower_32_bits(ring->wptr << 2),
346 ring->me,
347 upper_32_bits(ring->wptr << 2));
348 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
349 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
350 }
351 }
352
353 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
354 {
355 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
356 int i;
357
358 for (i = 0; i < count; i++)
359 if (sdma && sdma->burst_nop && (i == 0))
360 amdgpu_ring_write(ring, ring->funcs->nop |
361 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
362 else
363 amdgpu_ring_write(ring, ring->funcs->nop);
364 }
365
366 /**
367 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
368 *
369 * @ring: amdgpu ring pointer
370 * @ib: IB object to schedule
371 *
372 * Schedule an IB in the DMA ring (VEGA10).
373 */
374 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
375 struct amdgpu_ib *ib,
376 unsigned vmid, bool ctx_switch)
377 {
378 /* IB packet must end on a 8 DW boundary */
379 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
380
381 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
382 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
383 /* base must be 32 byte aligned */
384 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
385 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
386 amdgpu_ring_write(ring, ib->length_dw);
387 amdgpu_ring_write(ring, 0);
388 amdgpu_ring_write(ring, 0);
389
390 }
391
392 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
393 int mem_space, int hdp,
394 uint32_t addr0, uint32_t addr1,
395 uint32_t ref, uint32_t mask,
396 uint32_t inv)
397 {
398 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
399 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
400 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
401 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
402 if (mem_space) {
403 /* memory */
404 amdgpu_ring_write(ring, addr0);
405 amdgpu_ring_write(ring, addr1);
406 } else {
407 /* registers */
408 amdgpu_ring_write(ring, addr0 << 2);
409 amdgpu_ring_write(ring, addr1 << 2);
410 }
411 amdgpu_ring_write(ring, ref); /* reference */
412 amdgpu_ring_write(ring, mask); /* mask */
413 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
414 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
415 }
416
417 /**
418 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
419 *
420 * @ring: amdgpu ring pointer
421 *
422 * Emit an hdp flush packet on the requested DMA ring.
423 */
424 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
425 {
426 struct amdgpu_device *adev = ring->adev;
427 u32 ref_and_mask = 0;
428 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
429
430 if (ring->me == 0)
431 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
432 else
433 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
434
435 sdma_v4_0_wait_reg_mem(ring, 0, 1,
436 adev->nbio_funcs->get_hdp_flush_done_offset(adev),
437 adev->nbio_funcs->get_hdp_flush_req_offset(adev),
438 ref_and_mask, ref_and_mask, 10);
439 }
440
441 /**
442 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
443 *
444 * @ring: amdgpu ring pointer
445 * @fence: amdgpu fence object
446 *
447 * Add a DMA fence packet to the ring to write
448 * the fence seq number and DMA trap packet to generate
449 * an interrupt if needed (VEGA10).
450 */
451 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
452 unsigned flags)
453 {
454 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
455 /* write the fence */
456 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
457 /* zero in first two bits */
458 BUG_ON(addr & 0x3);
459 amdgpu_ring_write(ring, lower_32_bits(addr));
460 amdgpu_ring_write(ring, upper_32_bits(addr));
461 amdgpu_ring_write(ring, lower_32_bits(seq));
462
463 /* optionally write high bits as well */
464 if (write64bit) {
465 addr += 4;
466 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
467 /* zero in first two bits */
468 BUG_ON(addr & 0x3);
469 amdgpu_ring_write(ring, lower_32_bits(addr));
470 amdgpu_ring_write(ring, upper_32_bits(addr));
471 amdgpu_ring_write(ring, upper_32_bits(seq));
472 }
473
474 /* generate an interrupt */
475 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
476 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
477 }
478
479
480 /**
481 * sdma_v4_0_gfx_stop - stop the gfx async dma engines
482 *
483 * @adev: amdgpu_device pointer
484 *
485 * Stop the gfx async dma ring buffers (VEGA10).
486 */
487 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
488 {
489 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
490 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
491 u32 rb_cntl, ib_cntl;
492 int i;
493
494 if ((adev->mman.buffer_funcs_ring == sdma0) ||
495 (adev->mman.buffer_funcs_ring == sdma1))
496 amdgpu_ttm_set_buffer_funcs_status(adev, false);
497
498 for (i = 0; i < adev->sdma.num_instances; i++) {
499 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
501 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
502 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
503 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
504 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
505 }
506
507 sdma0->ready = false;
508 sdma1->ready = false;
509 }
510
511 /**
512 * sdma_v4_0_rlc_stop - stop the compute async dma engines
513 *
514 * @adev: amdgpu_device pointer
515 *
516 * Stop the compute async dma queues (VEGA10).
517 */
518 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
519 {
520 /* XXX todo */
521 }
522
523 /**
524 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
525 *
526 * @adev: amdgpu_device pointer
527 * @enable: enable/disable the DMA MEs context switch.
528 *
529 * Halt or unhalt the async dma engines context switch (VEGA10).
530 */
531 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
532 {
533 u32 f32_cntl, phase_quantum = 0;
534 int i;
535
536 if (amdgpu_sdma_phase_quantum) {
537 unsigned value = amdgpu_sdma_phase_quantum;
538 unsigned unit = 0;
539
540 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
541 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
542 value = (value + 1) >> 1;
543 unit++;
544 }
545 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
546 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
547 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
548 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
549 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
550 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
551 WARN_ONCE(1,
552 "clamping sdma_phase_quantum to %uK clock cycles\n",
553 value << unit);
554 }
555 phase_quantum =
556 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
557 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
558 }
559
560 for (i = 0; i < adev->sdma.num_instances; i++) {
561 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
562 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
563 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
564 if (enable && amdgpu_sdma_phase_quantum) {
565 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
566 phase_quantum);
567 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
568 phase_quantum);
569 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
570 phase_quantum);
571 }
572 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
573 }
574
575 }
576
577 /**
578 * sdma_v4_0_enable - stop the async dma engines
579 *
580 * @adev: amdgpu_device pointer
581 * @enable: enable/disable the DMA MEs.
582 *
583 * Halt or unhalt the async dma engines (VEGA10).
584 */
585 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
586 {
587 u32 f32_cntl;
588 int i;
589
590 if (enable == false) {
591 sdma_v4_0_gfx_stop(adev);
592 sdma_v4_0_rlc_stop(adev);
593 }
594
595 for (i = 0; i < adev->sdma.num_instances; i++) {
596 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
597 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
598 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
599 }
600 }
601
602 /**
603 * sdma_v4_0_gfx_resume - setup and start the async dma engines
604 *
605 * @adev: amdgpu_device pointer
606 *
607 * Set up the gfx DMA ring buffers and enable them (VEGA10).
608 * Returns 0 for success, error for failure.
609 */
610 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
611 {
612 struct amdgpu_ring *ring;
613 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
614 u32 rb_bufsz;
615 u32 wb_offset;
616 u32 doorbell;
617 u32 doorbell_offset;
618 u32 temp;
619 u64 wptr_gpu_addr;
620 int i, r;
621
622 for (i = 0; i < adev->sdma.num_instances; i++) {
623 ring = &adev->sdma.instance[i].ring;
624 wb_offset = (ring->rptr_offs * 4);
625
626 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
627
628 /* Set ring buffer size in dwords */
629 rb_bufsz = order_base_2(ring->ring_size / 4);
630 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
631 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
632 #ifdef __BIG_ENDIAN
633 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
634 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
635 RPTR_WRITEBACK_SWAP_ENABLE, 1);
636 #endif
637 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
638
639 /* Initialize the ring buffer's read and write pointers */
640 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
641 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
642 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
643 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
644
645 /* set the wb address whether it's enabled or not */
646 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
647 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
648 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
649 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
650
651 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
652
653 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
654 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
655
656 ring->wptr = 0;
657
658 /* before programing wptr to a less value, need set minor_ptr_update first */
659 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
660
661 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
662 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
663 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
664 }
665
666 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
667 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
668
669 if (ring->use_doorbell) {
670 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
671 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
672 OFFSET, ring->doorbell_index);
673 } else {
674 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
675 }
676 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
677 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
678 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
679 ring->doorbell_index);
680
681 if (amdgpu_sriov_vf(adev))
682 sdma_v4_0_ring_set_wptr(ring);
683
684 /* set minor_ptr_update to 0 after wptr programed */
685 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
686
687 /* set utc l1 enable flag always to 1 */
688 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
689 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
690 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
691
692 if (!amdgpu_sriov_vf(adev)) {
693 /* unhalt engine */
694 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
695 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
696 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
697 }
698
699 /* setup the wptr shadow polling */
700 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
701 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
702 lower_32_bits(wptr_gpu_addr));
703 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
704 upper_32_bits(wptr_gpu_addr));
705 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
706 if (amdgpu_sriov_vf(adev))
707 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
708 else
709 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
710 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
711
712 /* enable DMA RB */
713 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
714 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
715
716 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
717 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
718 #ifdef __BIG_ENDIAN
719 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
720 #endif
721 /* enable DMA IBs */
722 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
723
724 ring->ready = true;
725
726 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
727 sdma_v4_0_ctx_switch_enable(adev, true);
728 sdma_v4_0_enable(adev, true);
729 }
730
731 r = amdgpu_ring_test_ring(ring);
732 if (r) {
733 ring->ready = false;
734 return r;
735 }
736
737 if (adev->mman.buffer_funcs_ring == ring)
738 amdgpu_ttm_set_buffer_funcs_status(adev, true);
739
740 }
741
742 return 0;
743 }
744
745 static void
746 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
747 {
748 uint32_t def, data;
749
750 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
751 /* disable idle interrupt */
752 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
753 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
754
755 if (data != def)
756 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
757 } else {
758 /* disable idle interrupt */
759 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
760 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
761 if (data != def)
762 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
763 }
764 }
765
766 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
767 {
768 uint32_t def, data;
769
770 /* Enable HW based PG. */
771 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
772 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
773 if (data != def)
774 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
775
776 /* enable interrupt */
777 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
778 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
779 if (data != def)
780 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
781
782 /* Configure hold time to filter in-valid power on/off request. Use default right now */
783 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
784 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
785 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
786 /* Configure switch time for hysteresis purpose. Use default right now */
787 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
788 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
789 if(data != def)
790 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
791 }
792
793 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
794 {
795 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
796 return;
797
798 switch (adev->asic_type) {
799 case CHIP_RAVEN:
800 sdma_v4_1_init_power_gating(adev);
801 sdma_v4_1_update_power_gating(adev, true);
802 break;
803 default:
804 break;
805 }
806 }
807
808 /**
809 * sdma_v4_0_rlc_resume - setup and start the async dma engines
810 *
811 * @adev: amdgpu_device pointer
812 *
813 * Set up the compute DMA queues and enable them (VEGA10).
814 * Returns 0 for success, error for failure.
815 */
816 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
817 {
818 sdma_v4_0_init_pg(adev);
819
820 return 0;
821 }
822
823 /**
824 * sdma_v4_0_load_microcode - load the sDMA ME ucode
825 *
826 * @adev: amdgpu_device pointer
827 *
828 * Loads the sDMA0/1 ucode.
829 * Returns 0 for success, -EINVAL if the ucode is not available.
830 */
831 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
832 {
833 const struct sdma_firmware_header_v1_0 *hdr;
834 const __le32 *fw_data;
835 u32 fw_size;
836 int i, j;
837
838 /* halt the MEs */
839 sdma_v4_0_enable(adev, false);
840
841 for (i = 0; i < adev->sdma.num_instances; i++) {
842 if (!adev->sdma.instance[i].fw)
843 return -EINVAL;
844
845 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
846 amdgpu_ucode_print_sdma_hdr(&hdr->header);
847 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
848
849 fw_data = (const __le32 *)
850 (adev->sdma.instance[i].fw->data +
851 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
852
853 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
854
855 for (j = 0; j < fw_size; j++)
856 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
857
858 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
859 }
860
861 return 0;
862 }
863
864 /**
865 * sdma_v4_0_start - setup and start the async dma engines
866 *
867 * @adev: amdgpu_device pointer
868 *
869 * Set up the DMA engines and enable them (VEGA10).
870 * Returns 0 for success, error for failure.
871 */
872 static int sdma_v4_0_start(struct amdgpu_device *adev)
873 {
874 int r = 0;
875
876 if (amdgpu_sriov_vf(adev)) {
877 sdma_v4_0_ctx_switch_enable(adev, false);
878 sdma_v4_0_enable(adev, false);
879
880 /* set RB registers */
881 r = sdma_v4_0_gfx_resume(adev);
882 return r;
883 }
884
885 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
886 r = sdma_v4_0_load_microcode(adev);
887 if (r)
888 return r;
889 }
890
891 /* unhalt the MEs */
892 sdma_v4_0_enable(adev, true);
893 /* enable sdma ring preemption */
894 sdma_v4_0_ctx_switch_enable(adev, true);
895
896 /* start the gfx rings and rlc compute queues */
897 r = sdma_v4_0_gfx_resume(adev);
898 if (r)
899 return r;
900 r = sdma_v4_0_rlc_resume(adev);
901
902 return r;
903 }
904
905 /**
906 * sdma_v4_0_ring_test_ring - simple async dma engine test
907 *
908 * @ring: amdgpu_ring structure holding ring information
909 *
910 * Test the DMA engine by writing using it to write an
911 * value to memory. (VEGA10).
912 * Returns 0 for success, error for failure.
913 */
914 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
915 {
916 struct amdgpu_device *adev = ring->adev;
917 unsigned i;
918 unsigned index;
919 int r;
920 u32 tmp;
921 u64 gpu_addr;
922
923 r = amdgpu_device_wb_get(adev, &index);
924 if (r) {
925 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
926 return r;
927 }
928
929 gpu_addr = adev->wb.gpu_addr + (index * 4);
930 tmp = 0xCAFEDEAD;
931 adev->wb.wb[index] = cpu_to_le32(tmp);
932
933 r = amdgpu_ring_alloc(ring, 5);
934 if (r) {
935 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
936 amdgpu_device_wb_free(adev, index);
937 return r;
938 }
939
940 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
941 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
942 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
943 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
944 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
945 amdgpu_ring_write(ring, 0xDEADBEEF);
946 amdgpu_ring_commit(ring);
947
948 for (i = 0; i < adev->usec_timeout; i++) {
949 tmp = le32_to_cpu(adev->wb.wb[index]);
950 if (tmp == 0xDEADBEEF)
951 break;
952 DRM_UDELAY(1);
953 }
954
955 if (i < adev->usec_timeout) {
956 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
957 } else {
958 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
959 ring->idx, tmp);
960 r = -EINVAL;
961 }
962 amdgpu_device_wb_free(adev, index);
963
964 return r;
965 }
966
967 /**
968 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
969 *
970 * @ring: amdgpu_ring structure holding ring information
971 *
972 * Test a simple IB in the DMA ring (VEGA10).
973 * Returns 0 on success, error on failure.
974 */
975 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
976 {
977 struct amdgpu_device *adev = ring->adev;
978 struct amdgpu_ib ib;
979 struct dma_fence *f = NULL;
980 unsigned index;
981 long r;
982 u32 tmp = 0;
983 u64 gpu_addr;
984
985 r = amdgpu_device_wb_get(adev, &index);
986 if (r) {
987 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
988 return r;
989 }
990
991 gpu_addr = adev->wb.gpu_addr + (index * 4);
992 tmp = 0xCAFEDEAD;
993 adev->wb.wb[index] = cpu_to_le32(tmp);
994 memset(&ib, 0, sizeof(ib));
995 r = amdgpu_ib_get(adev, NULL, 256, &ib);
996 if (r) {
997 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
998 goto err0;
999 }
1000
1001 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1002 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1003 ib.ptr[1] = lower_32_bits(gpu_addr);
1004 ib.ptr[2] = upper_32_bits(gpu_addr);
1005 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1006 ib.ptr[4] = 0xDEADBEEF;
1007 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1008 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1009 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1010 ib.length_dw = 8;
1011
1012 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1013 if (r)
1014 goto err1;
1015
1016 r = dma_fence_wait_timeout(f, false, timeout);
1017 if (r == 0) {
1018 DRM_ERROR("amdgpu: IB test timed out\n");
1019 r = -ETIMEDOUT;
1020 goto err1;
1021 } else if (r < 0) {
1022 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1023 goto err1;
1024 }
1025 tmp = le32_to_cpu(adev->wb.wb[index]);
1026 if (tmp == 0xDEADBEEF) {
1027 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1028 r = 0;
1029 } else {
1030 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
1031 r = -EINVAL;
1032 }
1033 err1:
1034 amdgpu_ib_free(adev, &ib, NULL);
1035 dma_fence_put(f);
1036 err0:
1037 amdgpu_device_wb_free(adev, index);
1038 return r;
1039 }
1040
1041
1042 /**
1043 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1044 *
1045 * @ib: indirect buffer to fill with commands
1046 * @pe: addr of the page entry
1047 * @src: src addr to copy from
1048 * @count: number of page entries to update
1049 *
1050 * Update PTEs by copying them from the GART using sDMA (VEGA10).
1051 */
1052 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1053 uint64_t pe, uint64_t src,
1054 unsigned count)
1055 {
1056 unsigned bytes = count * 8;
1057
1058 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1059 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1060 ib->ptr[ib->length_dw++] = bytes - 1;
1061 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1062 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1063 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1064 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1065 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1066
1067 }
1068
1069 /**
1070 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1071 *
1072 * @ib: indirect buffer to fill with commands
1073 * @pe: addr of the page entry
1074 * @addr: dst addr to write into pe
1075 * @count: number of page entries to update
1076 * @incr: increase next addr by incr bytes
1077 * @flags: access flags
1078 *
1079 * Update PTEs by writing them manually using sDMA (VEGA10).
1080 */
1081 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1082 uint64_t value, unsigned count,
1083 uint32_t incr)
1084 {
1085 unsigned ndw = count * 2;
1086
1087 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1088 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1089 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1090 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1091 ib->ptr[ib->length_dw++] = ndw - 1;
1092 for (; ndw > 0; ndw -= 2) {
1093 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1094 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1095 value += incr;
1096 }
1097 }
1098
1099 /**
1100 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1101 *
1102 * @ib: indirect buffer to fill with commands
1103 * @pe: addr of the page entry
1104 * @addr: dst addr to write into pe
1105 * @count: number of page entries to update
1106 * @incr: increase next addr by incr bytes
1107 * @flags: access flags
1108 *
1109 * Update the page tables using sDMA (VEGA10).
1110 */
1111 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1112 uint64_t pe,
1113 uint64_t addr, unsigned count,
1114 uint32_t incr, uint64_t flags)
1115 {
1116 /* for physically contiguous pages (vram) */
1117 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1118 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1119 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1120 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1121 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1122 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1123 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1124 ib->ptr[ib->length_dw++] = incr; /* increment size */
1125 ib->ptr[ib->length_dw++] = 0;
1126 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1127 }
1128
1129 /**
1130 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1131 *
1132 * @ib: indirect buffer to fill with padding
1133 *
1134 */
1135 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1136 {
1137 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1138 u32 pad_count;
1139 int i;
1140
1141 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1142 for (i = 0; i < pad_count; i++)
1143 if (sdma && sdma->burst_nop && (i == 0))
1144 ib->ptr[ib->length_dw++] =
1145 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1146 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1147 else
1148 ib->ptr[ib->length_dw++] =
1149 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1150 }
1151
1152
1153 /**
1154 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1155 *
1156 * @ring: amdgpu_ring pointer
1157 *
1158 * Make sure all previous operations are completed (CIK).
1159 */
1160 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1161 {
1162 uint32_t seq = ring->fence_drv.sync_seq;
1163 uint64_t addr = ring->fence_drv.gpu_addr;
1164
1165 /* wait for idle */
1166 sdma_v4_0_wait_reg_mem(ring, 1, 0,
1167 addr & 0xfffffffc,
1168 upper_32_bits(addr) & 0xffffffff,
1169 seq, 0xffffffff, 4);
1170 }
1171
1172
1173 /**
1174 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1175 *
1176 * @ring: amdgpu_ring pointer
1177 * @vm: amdgpu_vm pointer
1178 *
1179 * Update the page table base and flush the VM TLB
1180 * using sDMA (VEGA10).
1181 */
1182 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1183 unsigned vmid, uint64_t pd_addr)
1184 {
1185 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1186 }
1187
1188 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1189 uint32_t reg, uint32_t val)
1190 {
1191 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1192 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1193 amdgpu_ring_write(ring, reg);
1194 amdgpu_ring_write(ring, val);
1195 }
1196
1197 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1198 uint32_t val, uint32_t mask)
1199 {
1200 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1201 }
1202
1203 static int sdma_v4_0_early_init(void *handle)
1204 {
1205 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206
1207 if (adev->asic_type == CHIP_RAVEN)
1208 adev->sdma.num_instances = 1;
1209 else
1210 adev->sdma.num_instances = 2;
1211
1212 sdma_v4_0_set_ring_funcs(adev);
1213 sdma_v4_0_set_buffer_funcs(adev);
1214 sdma_v4_0_set_vm_pte_funcs(adev);
1215 sdma_v4_0_set_irq_funcs(adev);
1216
1217 return 0;
1218 }
1219
1220
1221 static int sdma_v4_0_sw_init(void *handle)
1222 {
1223 struct amdgpu_ring *ring;
1224 int r, i;
1225 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1226
1227 /* SDMA trap event */
1228 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224,
1229 &adev->sdma.trap_irq);
1230 if (r)
1231 return r;
1232
1233 /* SDMA trap event */
1234 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224,
1235 &adev->sdma.trap_irq);
1236 if (r)
1237 return r;
1238
1239 r = sdma_v4_0_init_microcode(adev);
1240 if (r) {
1241 DRM_ERROR("Failed to load sdma firmware!\n");
1242 return r;
1243 }
1244
1245 for (i = 0; i < adev->sdma.num_instances; i++) {
1246 ring = &adev->sdma.instance[i].ring;
1247 ring->ring_obj = NULL;
1248 ring->use_doorbell = true;
1249
1250 DRM_INFO("use_doorbell being set to: [%s]\n",
1251 ring->use_doorbell?"true":"false");
1252
1253 ring->doorbell_index = (i == 0) ?
1254 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1255 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1256
1257 sprintf(ring->name, "sdma%d", i);
1258 r = amdgpu_ring_init(adev, ring, 1024,
1259 &adev->sdma.trap_irq,
1260 (i == 0) ?
1261 AMDGPU_SDMA_IRQ_TRAP0 :
1262 AMDGPU_SDMA_IRQ_TRAP1);
1263 if (r)
1264 return r;
1265 }
1266
1267 return r;
1268 }
1269
1270 static int sdma_v4_0_sw_fini(void *handle)
1271 {
1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1273 int i;
1274
1275 for (i = 0; i < adev->sdma.num_instances; i++)
1276 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1277
1278 for (i = 0; i < adev->sdma.num_instances; i++) {
1279 release_firmware(adev->sdma.instance[i].fw);
1280 adev->sdma.instance[i].fw = NULL;
1281 }
1282
1283 return 0;
1284 }
1285
1286 static int sdma_v4_0_hw_init(void *handle)
1287 {
1288 int r;
1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290
1291 sdma_v4_0_init_golden_registers(adev);
1292
1293 r = sdma_v4_0_start(adev);
1294
1295 return r;
1296 }
1297
1298 static int sdma_v4_0_hw_fini(void *handle)
1299 {
1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1301
1302 if (amdgpu_sriov_vf(adev))
1303 return 0;
1304
1305 sdma_v4_0_ctx_switch_enable(adev, false);
1306 sdma_v4_0_enable(adev, false);
1307
1308 return 0;
1309 }
1310
1311 static int sdma_v4_0_suspend(void *handle)
1312 {
1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314
1315 return sdma_v4_0_hw_fini(adev);
1316 }
1317
1318 static int sdma_v4_0_resume(void *handle)
1319 {
1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
1322 return sdma_v4_0_hw_init(adev);
1323 }
1324
1325 static bool sdma_v4_0_is_idle(void *handle)
1326 {
1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328 u32 i;
1329
1330 for (i = 0; i < adev->sdma.num_instances; i++) {
1331 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1332
1333 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1334 return false;
1335 }
1336
1337 return true;
1338 }
1339
1340 static int sdma_v4_0_wait_for_idle(void *handle)
1341 {
1342 unsigned i;
1343 u32 sdma0, sdma1;
1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1345
1346 for (i = 0; i < adev->usec_timeout; i++) {
1347 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1348 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1349
1350 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1351 return 0;
1352 udelay(1);
1353 }
1354 return -ETIMEDOUT;
1355 }
1356
1357 static int sdma_v4_0_soft_reset(void *handle)
1358 {
1359 /* todo */
1360
1361 return 0;
1362 }
1363
1364 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1365 struct amdgpu_irq_src *source,
1366 unsigned type,
1367 enum amdgpu_interrupt_state state)
1368 {
1369 u32 sdma_cntl;
1370
1371 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
1372 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1373 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1374
1375 sdma_cntl = RREG32(reg_offset);
1376 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1377 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1378 WREG32(reg_offset, sdma_cntl);
1379
1380 return 0;
1381 }
1382
1383 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1384 struct amdgpu_irq_src *source,
1385 struct amdgpu_iv_entry *entry)
1386 {
1387 DRM_DEBUG("IH: SDMA trap\n");
1388 switch (entry->client_id) {
1389 case SOC15_IH_CLIENTID_SDMA0:
1390 switch (entry->ring_id) {
1391 case 0:
1392 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1393 break;
1394 case 1:
1395 /* XXX compute */
1396 break;
1397 case 2:
1398 /* XXX compute */
1399 break;
1400 case 3:
1401 /* XXX page queue*/
1402 break;
1403 }
1404 break;
1405 case SOC15_IH_CLIENTID_SDMA1:
1406 switch (entry->ring_id) {
1407 case 0:
1408 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1409 break;
1410 case 1:
1411 /* XXX compute */
1412 break;
1413 case 2:
1414 /* XXX compute */
1415 break;
1416 case 3:
1417 /* XXX page queue*/
1418 break;
1419 }
1420 break;
1421 }
1422 return 0;
1423 }
1424
1425 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1426 struct amdgpu_irq_src *source,
1427 struct amdgpu_iv_entry *entry)
1428 {
1429 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1430 schedule_work(&adev->reset_work);
1431 return 0;
1432 }
1433
1434
1435 static void sdma_v4_0_update_medium_grain_clock_gating(
1436 struct amdgpu_device *adev,
1437 bool enable)
1438 {
1439 uint32_t data, def;
1440
1441 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1442 /* enable sdma0 clock gating */
1443 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1444 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1445 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1446 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1447 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1448 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1449 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1450 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1451 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1452 if (def != data)
1453 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1454
1455 if (adev->sdma.num_instances > 1) {
1456 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1457 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1458 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1459 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1460 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1461 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1462 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1463 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1464 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1465 if (def != data)
1466 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1467 }
1468 } else {
1469 /* disable sdma0 clock gating */
1470 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1471 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1477 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1478 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1479
1480 if (def != data)
1481 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1482
1483 if (adev->sdma.num_instances > 1) {
1484 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1485 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1486 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1487 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1488 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1489 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1490 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1491 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1492 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1493 if (def != data)
1494 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1495 }
1496 }
1497 }
1498
1499
1500 static void sdma_v4_0_update_medium_grain_light_sleep(
1501 struct amdgpu_device *adev,
1502 bool enable)
1503 {
1504 uint32_t data, def;
1505
1506 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1507 /* 1-not override: enable sdma0 mem light sleep */
1508 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1509 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1510 if (def != data)
1511 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1512
1513 /* 1-not override: enable sdma1 mem light sleep */
1514 if (adev->sdma.num_instances > 1) {
1515 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1516 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1517 if (def != data)
1518 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1519 }
1520 } else {
1521 /* 0-override:disable sdma0 mem light sleep */
1522 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1523 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1524 if (def != data)
1525 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1526
1527 /* 0-override:disable sdma1 mem light sleep */
1528 if (adev->sdma.num_instances > 1) {
1529 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1530 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1531 if (def != data)
1532 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1533 }
1534 }
1535 }
1536
1537 static int sdma_v4_0_set_clockgating_state(void *handle,
1538 enum amd_clockgating_state state)
1539 {
1540 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1541
1542 if (amdgpu_sriov_vf(adev))
1543 return 0;
1544
1545 switch (adev->asic_type) {
1546 case CHIP_VEGA10:
1547 case CHIP_VEGA12:
1548 case CHIP_VEGA20:
1549 case CHIP_RAVEN:
1550 sdma_v4_0_update_medium_grain_clock_gating(adev,
1551 state == AMD_CG_STATE_GATE ? true : false);
1552 sdma_v4_0_update_medium_grain_light_sleep(adev,
1553 state == AMD_CG_STATE_GATE ? true : false);
1554 break;
1555 default:
1556 break;
1557 }
1558 return 0;
1559 }
1560
1561 static int sdma_v4_0_set_powergating_state(void *handle,
1562 enum amd_powergating_state state)
1563 {
1564 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1565
1566 switch (adev->asic_type) {
1567 case CHIP_RAVEN:
1568 sdma_v4_1_update_power_gating(adev,
1569 state == AMD_PG_STATE_GATE ? true : false);
1570 break;
1571 default:
1572 break;
1573 }
1574
1575 return 0;
1576 }
1577
1578 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1579 {
1580 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1581 int data;
1582
1583 if (amdgpu_sriov_vf(adev))
1584 *flags = 0;
1585
1586 /* AMD_CG_SUPPORT_SDMA_MGCG */
1587 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1588 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1589 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1590
1591 /* AMD_CG_SUPPORT_SDMA_LS */
1592 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1593 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1594 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1595 }
1596
1597 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1598 .name = "sdma_v4_0",
1599 .early_init = sdma_v4_0_early_init,
1600 .late_init = NULL,
1601 .sw_init = sdma_v4_0_sw_init,
1602 .sw_fini = sdma_v4_0_sw_fini,
1603 .hw_init = sdma_v4_0_hw_init,
1604 .hw_fini = sdma_v4_0_hw_fini,
1605 .suspend = sdma_v4_0_suspend,
1606 .resume = sdma_v4_0_resume,
1607 .is_idle = sdma_v4_0_is_idle,
1608 .wait_for_idle = sdma_v4_0_wait_for_idle,
1609 .soft_reset = sdma_v4_0_soft_reset,
1610 .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1611 .set_powergating_state = sdma_v4_0_set_powergating_state,
1612 .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1613 };
1614
1615 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1616 .type = AMDGPU_RING_TYPE_SDMA,
1617 .align_mask = 0xf,
1618 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1619 .support_64bit_ptrs = true,
1620 .vmhub = AMDGPU_MMHUB,
1621 .get_rptr = sdma_v4_0_ring_get_rptr,
1622 .get_wptr = sdma_v4_0_ring_get_wptr,
1623 .set_wptr = sdma_v4_0_ring_set_wptr,
1624 .emit_frame_size =
1625 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1626 3 + /* hdp invalidate */
1627 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1628 /* sdma_v4_0_ring_emit_vm_flush */
1629 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1630 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1631 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1632 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1633 .emit_ib = sdma_v4_0_ring_emit_ib,
1634 .emit_fence = sdma_v4_0_ring_emit_fence,
1635 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1636 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1637 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1638 .test_ring = sdma_v4_0_ring_test_ring,
1639 .test_ib = sdma_v4_0_ring_test_ib,
1640 .insert_nop = sdma_v4_0_ring_insert_nop,
1641 .pad_ib = sdma_v4_0_ring_pad_ib,
1642 .emit_wreg = sdma_v4_0_ring_emit_wreg,
1643 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
1644 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1645 };
1646
1647 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1648 {
1649 int i;
1650
1651 for (i = 0; i < adev->sdma.num_instances; i++) {
1652 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1653 adev->sdma.instance[i].ring.me = i;
1654 }
1655 }
1656
1657 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
1658 .set = sdma_v4_0_set_trap_irq_state,
1659 .process = sdma_v4_0_process_trap_irq,
1660 };
1661
1662 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
1663 .process = sdma_v4_0_process_illegal_inst_irq,
1664 };
1665
1666 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1667 {
1668 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1669 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
1670 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
1671 }
1672
1673 /**
1674 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
1675 *
1676 * @ring: amdgpu_ring structure holding ring information
1677 * @src_offset: src GPU address
1678 * @dst_offset: dst GPU address
1679 * @byte_count: number of bytes to xfer
1680 *
1681 * Copy GPU buffers using the DMA engine (VEGA10/12).
1682 * Used by the amdgpu ttm implementation to move pages if
1683 * registered as the asic copy callback.
1684 */
1685 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
1686 uint64_t src_offset,
1687 uint64_t dst_offset,
1688 uint32_t byte_count)
1689 {
1690 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1691 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1692 ib->ptr[ib->length_dw++] = byte_count - 1;
1693 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1694 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1695 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1696 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1697 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1698 }
1699
1700 /**
1701 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
1702 *
1703 * @ring: amdgpu_ring structure holding ring information
1704 * @src_data: value to write to buffer
1705 * @dst_offset: dst GPU address
1706 * @byte_count: number of bytes to xfer
1707 *
1708 * Fill GPU buffers using the DMA engine (VEGA10/12).
1709 */
1710 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
1711 uint32_t src_data,
1712 uint64_t dst_offset,
1713 uint32_t byte_count)
1714 {
1715 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1716 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1717 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1718 ib->ptr[ib->length_dw++] = src_data;
1719 ib->ptr[ib->length_dw++] = byte_count - 1;
1720 }
1721
1722 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
1723 .copy_max_bytes = 0x400000,
1724 .copy_num_dw = 7,
1725 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
1726
1727 .fill_max_bytes = 0x400000,
1728 .fill_num_dw = 5,
1729 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
1730 };
1731
1732 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1733 {
1734 if (adev->mman.buffer_funcs == NULL) {
1735 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
1736 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1737 }
1738 }
1739
1740 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1741 .copy_pte_num_dw = 7,
1742 .copy_pte = sdma_v4_0_vm_copy_pte,
1743
1744 .write_pte = sdma_v4_0_vm_write_pte,
1745 .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1746 };
1747
1748 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1749 {
1750 unsigned i;
1751
1752 if (adev->vm_manager.vm_pte_funcs == NULL) {
1753 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
1754 for (i = 0; i < adev->sdma.num_instances; i++)
1755 adev->vm_manager.vm_pte_rings[i] =
1756 &adev->sdma.instance[i].ring;
1757
1758 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1759 }
1760 }
1761
1762 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
1763 .type = AMD_IP_BLOCK_TYPE_SDMA,
1764 .major = 4,
1765 .minor = 0,
1766 .rev = 0,
1767 .funcs = &sdma_v4_0_ip_funcs,
1768 };
A mirror of Linus' kernel repository