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Merge v5.0-rc7 into drm-next
[thirdparty/linux.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <drm/drmP.h>
27 #include "amdgpu.h"
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
34 #include "atom.h"
35 #include "amd_pcie.h"
36
37 #include "uvd/uvd_7_0_offset.h"
38 #include "gc/gc_9_0_offset.h"
39 #include "gc/gc_9_0_sh_mask.h"
40 #include "sdma0/sdma0_4_0_offset.h"
41 #include "sdma1/sdma1_4_0_offset.h"
42 #include "hdp/hdp_4_0_offset.h"
43 #include "hdp/hdp_4_0_sh_mask.h"
44 #include "smuio/smuio_9_0_offset.h"
45 #include "smuio/smuio_9_0_sh_mask.h"
46 #include "nbio/nbio_7_0_default.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
49 #include "mp/mp_9_0_offset.h"
50
51 #include "soc15.h"
52 #include "soc15_common.h"
53 #include "gfx_v9_0.h"
54 #include "gmc_v9_0.h"
55 #include "gfxhub_v1_0.h"
56 #include "mmhub_v1_0.h"
57 #include "df_v1_7.h"
58 #include "df_v3_6.h"
59 #include "vega10_ih.h"
60 #include "sdma_v4_0.h"
61 #include "uvd_v7_0.h"
62 #include "vce_v4_0.h"
63 #include "vcn_v1_0.h"
64 #include "dce_virtual.h"
65 #include "mxgpu_ai.h"
66
67 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
68 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
69 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
70 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
71
72 /* for Vega20 register name change */
73 #define mmHDP_MEM_POWER_CTRL 0x00d4
74 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
75 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
76 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
77 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
78 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
79 /*
80 * Indirect registers accessor
81 */
82 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
83 {
84 unsigned long flags, address, data;
85 u32 r;
86 address = adev->nbio_funcs->get_pcie_index_offset(adev);
87 data = adev->nbio_funcs->get_pcie_data_offset(adev);
88
89 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
90 WREG32(address, reg);
91 (void)RREG32(address);
92 r = RREG32(data);
93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
94 return r;
95 }
96
97 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
98 {
99 unsigned long flags, address, data;
100
101 address = adev->nbio_funcs->get_pcie_index_offset(adev);
102 data = adev->nbio_funcs->get_pcie_data_offset(adev);
103
104 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
105 WREG32(address, reg);
106 (void)RREG32(address);
107 WREG32(data, v);
108 (void)RREG32(data);
109 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
110 }
111
112 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
113 {
114 unsigned long flags, address, data;
115 u32 r;
116
117 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
118 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
119
120 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
121 WREG32(address, ((reg) & 0x1ff));
122 r = RREG32(data);
123 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
124 return r;
125 }
126
127 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
128 {
129 unsigned long flags, address, data;
130
131 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
132 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
133
134 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
135 WREG32(address, ((reg) & 0x1ff));
136 WREG32(data, (v));
137 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
138 }
139
140 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
141 {
142 unsigned long flags, address, data;
143 u32 r;
144
145 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
146 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
147
148 spin_lock_irqsave(&adev->didt_idx_lock, flags);
149 WREG32(address, (reg));
150 r = RREG32(data);
151 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
152 return r;
153 }
154
155 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
156 {
157 unsigned long flags, address, data;
158
159 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
160 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
161
162 spin_lock_irqsave(&adev->didt_idx_lock, flags);
163 WREG32(address, (reg));
164 WREG32(data, (v));
165 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
166 }
167
168 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
169 {
170 unsigned long flags;
171 u32 r;
172
173 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
174 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
175 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
176 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
177 return r;
178 }
179
180 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
181 {
182 unsigned long flags;
183
184 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
185 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
186 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
187 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
188 }
189
190 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
191 {
192 unsigned long flags;
193 u32 r;
194
195 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
196 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
197 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
198 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
199 return r;
200 }
201
202 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
203 {
204 unsigned long flags;
205
206 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
207 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
208 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
209 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
210 }
211
212 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
213 {
214 return adev->nbio_funcs->get_memsize(adev);
215 }
216
217 static u32 soc15_get_xclk(struct amdgpu_device *adev)
218 {
219 return adev->clock.spll.reference_freq;
220 }
221
222
223 void soc15_grbm_select(struct amdgpu_device *adev,
224 u32 me, u32 pipe, u32 queue, u32 vmid)
225 {
226 u32 grbm_gfx_cntl = 0;
227 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
228 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
229 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
230 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
231
232 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
233 }
234
235 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
236 {
237 /* todo */
238 }
239
240 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
241 {
242 /* todo */
243 return false;
244 }
245
246 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
247 u8 *bios, u32 length_bytes)
248 {
249 u32 *dw_ptr;
250 u32 i, length_dw;
251
252 if (bios == NULL)
253 return false;
254 if (length_bytes == 0)
255 return false;
256 /* APU vbios image is part of sbios image */
257 if (adev->flags & AMD_IS_APU)
258 return false;
259
260 dw_ptr = (u32 *)bios;
261 length_dw = ALIGN(length_bytes, 4) / 4;
262
263 /* set rom index to 0 */
264 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
265 /* read out the rom data */
266 for (i = 0; i < length_dw; i++)
267 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
268
269 return true;
270 }
271
272 struct soc15_allowed_register_entry {
273 uint32_t hwip;
274 uint32_t inst;
275 uint32_t seg;
276 uint32_t reg_offset;
277 bool grbm_indexed;
278 };
279
280
281 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
282 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
283 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
284 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
285 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
286 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
287 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
288 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
289 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
290 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
291 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
292 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
293 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
294 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
295 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
296 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
297 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
298 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
299 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
300 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
301 };
302
303 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
304 u32 sh_num, u32 reg_offset)
305 {
306 uint32_t val;
307
308 mutex_lock(&adev->grbm_idx_mutex);
309 if (se_num != 0xffffffff || sh_num != 0xffffffff)
310 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
311
312 val = RREG32(reg_offset);
313
314 if (se_num != 0xffffffff || sh_num != 0xffffffff)
315 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
316 mutex_unlock(&adev->grbm_idx_mutex);
317 return val;
318 }
319
320 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
321 bool indexed, u32 se_num,
322 u32 sh_num, u32 reg_offset)
323 {
324 if (indexed) {
325 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
326 } else {
327 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
328 return adev->gfx.config.gb_addr_config;
329 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
330 return adev->gfx.config.db_debug2;
331 return RREG32(reg_offset);
332 }
333 }
334
335 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
336 u32 sh_num, u32 reg_offset, u32 *value)
337 {
338 uint32_t i;
339 struct soc15_allowed_register_entry *en;
340
341 *value = 0;
342 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
343 en = &soc15_allowed_read_registers[i];
344 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
345 + en->reg_offset))
346 continue;
347
348 *value = soc15_get_register_value(adev,
349 soc15_allowed_read_registers[i].grbm_indexed,
350 se_num, sh_num, reg_offset);
351 return 0;
352 }
353 return -EINVAL;
354 }
355
356
357 /**
358 * soc15_program_register_sequence - program an array of registers.
359 *
360 * @adev: amdgpu_device pointer
361 * @regs: pointer to the register array
362 * @array_size: size of the register array
363 *
364 * Programs an array or registers with and and or masks.
365 * This is a helper for setting golden registers.
366 */
367
368 void soc15_program_register_sequence(struct amdgpu_device *adev,
369 const struct soc15_reg_golden *regs,
370 const u32 array_size)
371 {
372 const struct soc15_reg_golden *entry;
373 u32 tmp, reg;
374 int i;
375
376 for (i = 0; i < array_size; ++i) {
377 entry = &regs[i];
378 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
379
380 if (entry->and_mask == 0xffffffff) {
381 tmp = entry->or_mask;
382 } else {
383 tmp = RREG32(reg);
384 tmp &= ~(entry->and_mask);
385 tmp |= entry->or_mask;
386 }
387 WREG32(reg, tmp);
388 }
389
390 }
391
392 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
393 {
394 u32 i;
395
396 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
397
398 dev_info(adev->dev, "GPU mode1 reset\n");
399
400 /* disable BM */
401 pci_clear_master(adev->pdev);
402
403 pci_save_state(adev->pdev);
404
405 psp_gpu_reset(adev);
406
407 pci_restore_state(adev->pdev);
408
409 /* wait for asic to come out of reset */
410 for (i = 0; i < adev->usec_timeout; i++) {
411 u32 memsize = adev->nbio_funcs->get_memsize(adev);
412
413 if (memsize != 0xffffffff)
414 break;
415 udelay(1);
416 }
417
418 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
419
420 return 0;
421 }
422
423 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
424 {
425 void *pp_handle = adev->powerplay.pp_handle;
426 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
427
428 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
429 *cap = false;
430 return -ENOENT;
431 }
432
433 return pp_funcs->get_asic_baco_capability(pp_handle, cap);
434 }
435
436 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
437 {
438 void *pp_handle = adev->powerplay.pp_handle;
439 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
440
441 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
442 return -ENOENT;
443
444 /* enter BACO state */
445 if (pp_funcs->set_asic_baco_state(pp_handle, 1))
446 return -EIO;
447
448 /* exit BACO state */
449 if (pp_funcs->set_asic_baco_state(pp_handle, 0))
450 return -EIO;
451
452 dev_info(adev->dev, "GPU BACO reset\n");
453
454 return 0;
455 }
456
457 static int soc15_asic_reset(struct amdgpu_device *adev)
458 {
459 int ret;
460 bool baco_reset;
461
462 switch (adev->asic_type) {
463 case CHIP_VEGA10:
464 case CHIP_VEGA20:
465 soc15_asic_get_baco_capability(adev, &baco_reset);
466 break;
467 default:
468 baco_reset = false;
469 break;
470 }
471
472 if (baco_reset)
473 ret = soc15_asic_baco_reset(adev);
474 else
475 ret = soc15_asic_mode1_reset(adev);
476
477 return ret;
478 }
479
480 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
481 u32 cntl_reg, u32 status_reg)
482 {
483 return 0;
484 }*/
485
486 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
487 {
488 /*int r;
489
490 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
491 if (r)
492 return r;
493
494 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
495 */
496 return 0;
497 }
498
499 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
500 {
501 /* todo */
502
503 return 0;
504 }
505
506 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
507 {
508 if (pci_is_root_bus(adev->pdev->bus))
509 return;
510
511 if (amdgpu_pcie_gen2 == 0)
512 return;
513
514 if (adev->flags & AMD_IS_APU)
515 return;
516
517 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
518 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
519 return;
520
521 /* todo */
522 }
523
524 static void soc15_program_aspm(struct amdgpu_device *adev)
525 {
526
527 if (amdgpu_aspm == 0)
528 return;
529
530 /* todo */
531 }
532
533 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
534 bool enable)
535 {
536 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
537 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
538 }
539
540 static const struct amdgpu_ip_block_version vega10_common_ip_block =
541 {
542 .type = AMD_IP_BLOCK_TYPE_COMMON,
543 .major = 2,
544 .minor = 0,
545 .rev = 0,
546 .funcs = &soc15_common_ip_funcs,
547 };
548
549 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
550 {
551 return adev->nbio_funcs->get_rev_id(adev);
552 }
553
554 int soc15_set_ip_blocks(struct amdgpu_device *adev)
555 {
556 /* Set IP register base before any HW register access */
557 switch (adev->asic_type) {
558 case CHIP_VEGA10:
559 case CHIP_VEGA12:
560 case CHIP_RAVEN:
561 vega10_reg_base_init(adev);
562 break;
563 case CHIP_VEGA20:
564 vega20_reg_base_init(adev);
565 break;
566 default:
567 return -EINVAL;
568 }
569
570 if (adev->asic_type == CHIP_VEGA20)
571 adev->gmc.xgmi.supported = true;
572
573 if (adev->flags & AMD_IS_APU)
574 adev->nbio_funcs = &nbio_v7_0_funcs;
575 else if (adev->asic_type == CHIP_VEGA20)
576 adev->nbio_funcs = &nbio_v7_4_funcs;
577 else
578 adev->nbio_funcs = &nbio_v6_1_funcs;
579
580 if (adev->asic_type == CHIP_VEGA20)
581 adev->df_funcs = &df_v3_6_funcs;
582 else
583 adev->df_funcs = &df_v1_7_funcs;
584
585 adev->rev_id = soc15_get_rev_id(adev);
586 adev->nbio_funcs->detect_hw_virt(adev);
587
588 if (amdgpu_sriov_vf(adev))
589 adev->virt.ops = &xgpu_ai_virt_ops;
590
591 switch (adev->asic_type) {
592 case CHIP_VEGA10:
593 case CHIP_VEGA12:
594 case CHIP_VEGA20:
595 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
596 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
597 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
598 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
599 if (adev->asic_type == CHIP_VEGA20)
600 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
601 else
602 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
603 }
604 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
605 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
606 if (!amdgpu_sriov_vf(adev))
607 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
608 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
609 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
610 #if defined(CONFIG_DRM_AMD_DC)
611 else if (amdgpu_device_has_dc_support(adev))
612 amdgpu_device_ip_block_add(adev, &dm_ip_block);
613 #else
614 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
615 #endif
616 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
617 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
618 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
619 }
620 break;
621 case CHIP_RAVEN:
622 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
623 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
624 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
625 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
626 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
627 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
628 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
629 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
630 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
631 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
632 #if defined(CONFIG_DRM_AMD_DC)
633 else if (amdgpu_device_has_dc_support(adev))
634 amdgpu_device_ip_block_add(adev, &dm_ip_block);
635 #else
636 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
637 #endif
638 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
639 break;
640 default:
641 return -EINVAL;
642 }
643
644 return 0;
645 }
646
647 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
648 {
649 adev->nbio_funcs->hdp_flush(adev, ring);
650 }
651
652 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
653 struct amdgpu_ring *ring)
654 {
655 if (!ring || !ring->funcs->emit_wreg)
656 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
657 else
658 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
659 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
660 }
661
662 static bool soc15_need_full_reset(struct amdgpu_device *adev)
663 {
664 /* change this when we implement soft reset */
665 return true;
666 }
667 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
668 uint64_t *count1)
669 {
670 uint32_t perfctr = 0;
671 uint64_t cnt0_of, cnt1_of;
672 int tmp;
673
674 /* This reports 0 on APUs, so return to avoid writing/reading registers
675 * that may or may not be different from their GPU counterparts
676 */
677 if (adev->flags & AMD_IS_APU)
678 return;
679
680 /* Set the 2 events that we wish to watch, defined above */
681 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
682 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
683 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
684
685 /* Write to enable desired perf counters */
686 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
687 /* Zero out and enable the perf counters
688 * Write 0x5:
689 * Bit 0 = Start all counters(1)
690 * Bit 2 = Global counter reset enable(1)
691 */
692 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
693
694 msleep(1000);
695
696 /* Load the shadow and disable the perf counters
697 * Write 0x2:
698 * Bit 0 = Stop counters(0)
699 * Bit 1 = Load the shadow counters(1)
700 */
701 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
702
703 /* Read register values to get any >32bit overflow */
704 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
705 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
706 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
707
708 /* Get the values and add the overflow */
709 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
710 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
711 }
712
713 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
714 {
715 u32 sol_reg;
716
717 if (adev->flags & AMD_IS_APU)
718 return false;
719
720 /* Check sOS sign of life register to confirm sys driver and sOS
721 * are already been loaded.
722 */
723 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
724 if (sol_reg)
725 return true;
726
727 return false;
728 }
729
730 static const struct amdgpu_asic_funcs soc15_asic_funcs =
731 {
732 .read_disabled_bios = &soc15_read_disabled_bios,
733 .read_bios_from_rom = &soc15_read_bios_from_rom,
734 .read_register = &soc15_read_register,
735 .reset = &soc15_asic_reset,
736 .set_vga_state = &soc15_vga_set_state,
737 .get_xclk = &soc15_get_xclk,
738 .set_uvd_clocks = &soc15_set_uvd_clocks,
739 .set_vce_clocks = &soc15_set_vce_clocks,
740 .get_config_memsize = &soc15_get_config_memsize,
741 .flush_hdp = &soc15_flush_hdp,
742 .invalidate_hdp = &soc15_invalidate_hdp,
743 .need_full_reset = &soc15_need_full_reset,
744 .init_doorbell_index = &vega10_doorbell_index_init,
745 .get_pcie_usage = &soc15_get_pcie_usage,
746 .need_reset_on_init = &soc15_need_reset_on_init,
747 };
748
749 static const struct amdgpu_asic_funcs vega20_asic_funcs =
750 {
751 .read_disabled_bios = &soc15_read_disabled_bios,
752 .read_bios_from_rom = &soc15_read_bios_from_rom,
753 .read_register = &soc15_read_register,
754 .reset = &soc15_asic_reset,
755 .set_vga_state = &soc15_vga_set_state,
756 .get_xclk = &soc15_get_xclk,
757 .set_uvd_clocks = &soc15_set_uvd_clocks,
758 .set_vce_clocks = &soc15_set_vce_clocks,
759 .get_config_memsize = &soc15_get_config_memsize,
760 .flush_hdp = &soc15_flush_hdp,
761 .invalidate_hdp = &soc15_invalidate_hdp,
762 .need_full_reset = &soc15_need_full_reset,
763 .init_doorbell_index = &vega20_doorbell_index_init,
764 .get_pcie_usage = &soc15_get_pcie_usage,
765 .need_reset_on_init = &soc15_need_reset_on_init,
766 };
767
768 static int soc15_common_early_init(void *handle)
769 {
770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771
772 adev->smc_rreg = NULL;
773 adev->smc_wreg = NULL;
774 adev->pcie_rreg = &soc15_pcie_rreg;
775 adev->pcie_wreg = &soc15_pcie_wreg;
776 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
777 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
778 adev->didt_rreg = &soc15_didt_rreg;
779 adev->didt_wreg = &soc15_didt_wreg;
780 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
781 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
782 adev->se_cac_rreg = &soc15_se_cac_rreg;
783 adev->se_cac_wreg = &soc15_se_cac_wreg;
784
785
786 adev->external_rev_id = 0xFF;
787 switch (adev->asic_type) {
788 case CHIP_VEGA10:
789 adev->asic_funcs = &soc15_asic_funcs;
790 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
791 AMD_CG_SUPPORT_GFX_MGLS |
792 AMD_CG_SUPPORT_GFX_RLC_LS |
793 AMD_CG_SUPPORT_GFX_CP_LS |
794 AMD_CG_SUPPORT_GFX_3D_CGCG |
795 AMD_CG_SUPPORT_GFX_3D_CGLS |
796 AMD_CG_SUPPORT_GFX_CGCG |
797 AMD_CG_SUPPORT_GFX_CGLS |
798 AMD_CG_SUPPORT_BIF_MGCG |
799 AMD_CG_SUPPORT_BIF_LS |
800 AMD_CG_SUPPORT_HDP_LS |
801 AMD_CG_SUPPORT_DRM_MGCG |
802 AMD_CG_SUPPORT_DRM_LS |
803 AMD_CG_SUPPORT_ROM_MGCG |
804 AMD_CG_SUPPORT_DF_MGCG |
805 AMD_CG_SUPPORT_SDMA_MGCG |
806 AMD_CG_SUPPORT_SDMA_LS |
807 AMD_CG_SUPPORT_MC_MGCG |
808 AMD_CG_SUPPORT_MC_LS;
809 adev->pg_flags = 0;
810 adev->external_rev_id = 0x1;
811 break;
812 case CHIP_VEGA12:
813 adev->asic_funcs = &soc15_asic_funcs;
814 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
815 AMD_CG_SUPPORT_GFX_MGLS |
816 AMD_CG_SUPPORT_GFX_CGCG |
817 AMD_CG_SUPPORT_GFX_CGLS |
818 AMD_CG_SUPPORT_GFX_3D_CGCG |
819 AMD_CG_SUPPORT_GFX_3D_CGLS |
820 AMD_CG_SUPPORT_GFX_CP_LS |
821 AMD_CG_SUPPORT_MC_LS |
822 AMD_CG_SUPPORT_MC_MGCG |
823 AMD_CG_SUPPORT_SDMA_MGCG |
824 AMD_CG_SUPPORT_SDMA_LS |
825 AMD_CG_SUPPORT_BIF_MGCG |
826 AMD_CG_SUPPORT_BIF_LS |
827 AMD_CG_SUPPORT_HDP_MGCG |
828 AMD_CG_SUPPORT_HDP_LS |
829 AMD_CG_SUPPORT_ROM_MGCG |
830 AMD_CG_SUPPORT_VCE_MGCG |
831 AMD_CG_SUPPORT_UVD_MGCG;
832 adev->pg_flags = 0;
833 adev->external_rev_id = adev->rev_id + 0x14;
834 break;
835 case CHIP_VEGA20:
836 adev->asic_funcs = &vega20_asic_funcs;
837 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
838 AMD_CG_SUPPORT_GFX_MGLS |
839 AMD_CG_SUPPORT_GFX_CGCG |
840 AMD_CG_SUPPORT_GFX_CGLS |
841 AMD_CG_SUPPORT_GFX_3D_CGCG |
842 AMD_CG_SUPPORT_GFX_3D_CGLS |
843 AMD_CG_SUPPORT_GFX_CP_LS |
844 AMD_CG_SUPPORT_MC_LS |
845 AMD_CG_SUPPORT_MC_MGCG |
846 AMD_CG_SUPPORT_SDMA_MGCG |
847 AMD_CG_SUPPORT_SDMA_LS |
848 AMD_CG_SUPPORT_BIF_MGCG |
849 AMD_CG_SUPPORT_BIF_LS |
850 AMD_CG_SUPPORT_HDP_MGCG |
851 AMD_CG_SUPPORT_HDP_LS |
852 AMD_CG_SUPPORT_ROM_MGCG |
853 AMD_CG_SUPPORT_VCE_MGCG |
854 AMD_CG_SUPPORT_UVD_MGCG;
855 adev->pg_flags = 0;
856 adev->external_rev_id = adev->rev_id + 0x28;
857 break;
858 case CHIP_RAVEN:
859 adev->asic_funcs = &soc15_asic_funcs;
860 if (adev->rev_id >= 0x8)
861 adev->external_rev_id = adev->rev_id + 0x79;
862 else if (adev->pdev->device == 0x15d8)
863 adev->external_rev_id = adev->rev_id + 0x41;
864 else if (adev->rev_id == 1)
865 adev->external_rev_id = adev->rev_id + 0x20;
866 else
867 adev->external_rev_id = adev->rev_id + 0x01;
868
869 if (adev->rev_id >= 0x8) {
870 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
871 AMD_CG_SUPPORT_GFX_MGLS |
872 AMD_CG_SUPPORT_GFX_CP_LS |
873 AMD_CG_SUPPORT_GFX_3D_CGCG |
874 AMD_CG_SUPPORT_GFX_3D_CGLS |
875 AMD_CG_SUPPORT_GFX_CGCG |
876 AMD_CG_SUPPORT_GFX_CGLS |
877 AMD_CG_SUPPORT_BIF_LS |
878 AMD_CG_SUPPORT_HDP_LS |
879 AMD_CG_SUPPORT_ROM_MGCG |
880 AMD_CG_SUPPORT_MC_MGCG |
881 AMD_CG_SUPPORT_MC_LS |
882 AMD_CG_SUPPORT_SDMA_MGCG |
883 AMD_CG_SUPPORT_SDMA_LS |
884 AMD_CG_SUPPORT_VCN_MGCG;
885
886 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
887 } else if (adev->pdev->device == 0x15d8) {
888 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
889 AMD_CG_SUPPORT_GFX_CP_LS |
890 AMD_CG_SUPPORT_GFX_3D_CGCG |
891 AMD_CG_SUPPORT_GFX_3D_CGLS |
892 AMD_CG_SUPPORT_GFX_CGCG |
893 AMD_CG_SUPPORT_GFX_CGLS |
894 AMD_CG_SUPPORT_BIF_LS |
895 AMD_CG_SUPPORT_HDP_LS |
896 AMD_CG_SUPPORT_ROM_MGCG |
897 AMD_CG_SUPPORT_MC_MGCG |
898 AMD_CG_SUPPORT_MC_LS |
899 AMD_CG_SUPPORT_SDMA_MGCG |
900 AMD_CG_SUPPORT_SDMA_LS;
901
902 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
903 AMD_PG_SUPPORT_MMHUB |
904 AMD_PG_SUPPORT_VCN |
905 AMD_PG_SUPPORT_VCN_DPG;
906 } else {
907 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
908 AMD_CG_SUPPORT_GFX_MGLS |
909 AMD_CG_SUPPORT_GFX_RLC_LS |
910 AMD_CG_SUPPORT_GFX_CP_LS |
911 AMD_CG_SUPPORT_GFX_3D_CGCG |
912 AMD_CG_SUPPORT_GFX_3D_CGLS |
913 AMD_CG_SUPPORT_GFX_CGCG |
914 AMD_CG_SUPPORT_GFX_CGLS |
915 AMD_CG_SUPPORT_BIF_MGCG |
916 AMD_CG_SUPPORT_BIF_LS |
917 AMD_CG_SUPPORT_HDP_MGCG |
918 AMD_CG_SUPPORT_HDP_LS |
919 AMD_CG_SUPPORT_DRM_MGCG |
920 AMD_CG_SUPPORT_DRM_LS |
921 AMD_CG_SUPPORT_ROM_MGCG |
922 AMD_CG_SUPPORT_MC_MGCG |
923 AMD_CG_SUPPORT_MC_LS |
924 AMD_CG_SUPPORT_SDMA_MGCG |
925 AMD_CG_SUPPORT_SDMA_LS |
926 AMD_CG_SUPPORT_VCN_MGCG;
927
928 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
929 }
930
931 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
932 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
933 AMD_PG_SUPPORT_CP |
934 AMD_PG_SUPPORT_RLC_SMU_HS;
935 break;
936 default:
937 /* FIXME: not supported yet */
938 return -EINVAL;
939 }
940
941 if (amdgpu_sriov_vf(adev)) {
942 amdgpu_virt_init_setting(adev);
943 xgpu_ai_mailbox_set_irq_funcs(adev);
944 }
945
946 return 0;
947 }
948
949 static int soc15_common_late_init(void *handle)
950 {
951 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
952
953 if (amdgpu_sriov_vf(adev))
954 xgpu_ai_mailbox_get_irq(adev);
955
956 return 0;
957 }
958
959 static int soc15_common_sw_init(void *handle)
960 {
961 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
962
963 if (amdgpu_sriov_vf(adev))
964 xgpu_ai_mailbox_add_irq_id(adev);
965
966 return 0;
967 }
968
969 static int soc15_common_sw_fini(void *handle)
970 {
971 return 0;
972 }
973
974 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
975 {
976 int i;
977 struct amdgpu_ring *ring;
978
979 for (i = 0; i < adev->sdma.num_instances; i++) {
980 ring = &adev->sdma.instance[i].ring;
981 adev->nbio_funcs->sdma_doorbell_range(adev, i,
982 ring->use_doorbell, ring->doorbell_index,
983 adev->doorbell_index.sdma_doorbell_range);
984 }
985
986 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
987 adev->irq.ih.doorbell_index);
988 }
989
990 static int soc15_common_hw_init(void *handle)
991 {
992 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
993
994 /* enable pcie gen2/3 link */
995 soc15_pcie_gen3_enable(adev);
996 /* enable aspm */
997 soc15_program_aspm(adev);
998 /* setup nbio registers */
999 adev->nbio_funcs->init_registers(adev);
1000 /* enable the doorbell aperture */
1001 soc15_enable_doorbell_aperture(adev, true);
1002 /* HW doorbell routing policy: doorbell writing not
1003 * in SDMA/IH/MM/ACV range will be routed to CP. So
1004 * we need to init SDMA/IH/MM/ACV doorbell range prior
1005 * to CP ip block init and ring test.
1006 */
1007 soc15_doorbell_range_init(adev);
1008
1009 return 0;
1010 }
1011
1012 static int soc15_common_hw_fini(void *handle)
1013 {
1014 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1015
1016 /* disable the doorbell aperture */
1017 soc15_enable_doorbell_aperture(adev, false);
1018 if (amdgpu_sriov_vf(adev))
1019 xgpu_ai_mailbox_put_irq(adev);
1020
1021 return 0;
1022 }
1023
1024 static int soc15_common_suspend(void *handle)
1025 {
1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027
1028 return soc15_common_hw_fini(adev);
1029 }
1030
1031 static int soc15_common_resume(void *handle)
1032 {
1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035 return soc15_common_hw_init(adev);
1036 }
1037
1038 static bool soc15_common_is_idle(void *handle)
1039 {
1040 return true;
1041 }
1042
1043 static int soc15_common_wait_for_idle(void *handle)
1044 {
1045 return 0;
1046 }
1047
1048 static int soc15_common_soft_reset(void *handle)
1049 {
1050 return 0;
1051 }
1052
1053 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1054 {
1055 uint32_t def, data;
1056
1057 if (adev->asic_type == CHIP_VEGA20) {
1058 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1059
1060 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1061 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1062 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1063 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1064 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1065 else
1066 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1067 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1068 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1069 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1070
1071 if (def != data)
1072 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1073 } else {
1074 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1075
1076 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1077 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1078 else
1079 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1080
1081 if (def != data)
1082 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1083 }
1084 }
1085
1086 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1087 {
1088 uint32_t def, data;
1089
1090 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1091
1092 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1093 data &= ~(0x01000000 |
1094 0x02000000 |
1095 0x04000000 |
1096 0x08000000 |
1097 0x10000000 |
1098 0x20000000 |
1099 0x40000000 |
1100 0x80000000);
1101 else
1102 data |= (0x01000000 |
1103 0x02000000 |
1104 0x04000000 |
1105 0x08000000 |
1106 0x10000000 |
1107 0x20000000 |
1108 0x40000000 |
1109 0x80000000);
1110
1111 if (def != data)
1112 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1113 }
1114
1115 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1116 {
1117 uint32_t def, data;
1118
1119 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1120
1121 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1122 data |= 1;
1123 else
1124 data &= ~1;
1125
1126 if (def != data)
1127 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1128 }
1129
1130 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1131 bool enable)
1132 {
1133 uint32_t def, data;
1134
1135 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1136
1137 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1138 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1139 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1140 else
1141 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1142 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1143
1144 if (def != data)
1145 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1146 }
1147
1148 static int soc15_common_set_clockgating_state(void *handle,
1149 enum amd_clockgating_state state)
1150 {
1151 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1152
1153 if (amdgpu_sriov_vf(adev))
1154 return 0;
1155
1156 switch (adev->asic_type) {
1157 case CHIP_VEGA10:
1158 case CHIP_VEGA12:
1159 case CHIP_VEGA20:
1160 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1161 state == AMD_CG_STATE_GATE ? true : false);
1162 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1163 state == AMD_CG_STATE_GATE ? true : false);
1164 soc15_update_hdp_light_sleep(adev,
1165 state == AMD_CG_STATE_GATE ? true : false);
1166 soc15_update_drm_clock_gating(adev,
1167 state == AMD_CG_STATE_GATE ? true : false);
1168 soc15_update_drm_light_sleep(adev,
1169 state == AMD_CG_STATE_GATE ? true : false);
1170 soc15_update_rom_medium_grain_clock_gating(adev,
1171 state == AMD_CG_STATE_GATE ? true : false);
1172 adev->df_funcs->update_medium_grain_clock_gating(adev,
1173 state == AMD_CG_STATE_GATE ? true : false);
1174 break;
1175 case CHIP_RAVEN:
1176 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1177 state == AMD_CG_STATE_GATE ? true : false);
1178 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1179 state == AMD_CG_STATE_GATE ? true : false);
1180 soc15_update_hdp_light_sleep(adev,
1181 state == AMD_CG_STATE_GATE ? true : false);
1182 soc15_update_drm_clock_gating(adev,
1183 state == AMD_CG_STATE_GATE ? true : false);
1184 soc15_update_drm_light_sleep(adev,
1185 state == AMD_CG_STATE_GATE ? true : false);
1186 soc15_update_rom_medium_grain_clock_gating(adev,
1187 state == AMD_CG_STATE_GATE ? true : false);
1188 break;
1189 default:
1190 break;
1191 }
1192 return 0;
1193 }
1194
1195 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1196 {
1197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1198 int data;
1199
1200 if (amdgpu_sriov_vf(adev))
1201 *flags = 0;
1202
1203 adev->nbio_funcs->get_clockgating_state(adev, flags);
1204
1205 /* AMD_CG_SUPPORT_HDP_LS */
1206 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1207 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1208 *flags |= AMD_CG_SUPPORT_HDP_LS;
1209
1210 /* AMD_CG_SUPPORT_DRM_MGCG */
1211 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1212 if (!(data & 0x01000000))
1213 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1214
1215 /* AMD_CG_SUPPORT_DRM_LS */
1216 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1217 if (data & 0x1)
1218 *flags |= AMD_CG_SUPPORT_DRM_LS;
1219
1220 /* AMD_CG_SUPPORT_ROM_MGCG */
1221 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1222 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1223 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1224
1225 adev->df_funcs->get_clockgating_state(adev, flags);
1226 }
1227
1228 static int soc15_common_set_powergating_state(void *handle,
1229 enum amd_powergating_state state)
1230 {
1231 /* todo */
1232 return 0;
1233 }
1234
1235 const struct amd_ip_funcs soc15_common_ip_funcs = {
1236 .name = "soc15_common",
1237 .early_init = soc15_common_early_init,
1238 .late_init = soc15_common_late_init,
1239 .sw_init = soc15_common_sw_init,
1240 .sw_fini = soc15_common_sw_fini,
1241 .hw_init = soc15_common_hw_init,
1242 .hw_fini = soc15_common_hw_fini,
1243 .suspend = soc15_common_suspend,
1244 .resume = soc15_common_resume,
1245 .is_idle = soc15_common_is_idle,
1246 .wait_for_idle = soc15_common_wait_for_idle,
1247 .soft_reset = soc15_common_soft_reset,
1248 .set_clockgating_state = soc15_common_set_clockgating_state,
1249 .set_powergating_state = soc15_common_set_powergating_state,
1250 .get_clockgating_state= soc15_common_get_clockgating_state,
1251 };
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