drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/version.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_dp_mst_helper.h>
  29 #include "dm_services.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_mst_types.h"
  33
  34 #include "dc.h"
  35 #include "dm_helpers.h"
  36
  37 #include "dc_link_ddc.h"
  38
  39 #include "i2caux_interface.h"
  40 #if defined(CONFIG_DEBUG_FS)
  41 #include "amdgpu_dm_debugfs.h"
  42 #endif
  43
  44
  45 #if defined(CONFIG_DRM_AMD_DC_DCN)
  46 #include "dc/dcn20/dcn20_resource.h"
  47 #endif
  48
  49 /* #define TRACE_DPCD */
  50
  51 #ifdef TRACE_DPCD
  52 #define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
  53
  54 static inline char *side_band_msg_type_to_str(uint32_t address)
  55 {
  56         static char str[10] = {0};
  57
  58         if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
  59                 strcpy(str, "DOWN_REQ");
  60         else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
  61                 strcpy(str, "UP_REP");
  62         else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
  63                 strcpy(str, "DOWN_REP");
  64         else
  65                 strcpy(str, "UP_REQ");
  66
  67         return str;
  68 }
  69
  70 static void log_dpcd(uint8_t type,
  71                      uint32_t address,
  72                      uint8_t *data,
  73                      uint32_t size,
  74                      bool res)
  75 {
  76         DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
  77                         (type == DP_AUX_NATIVE_READ) ||
  78                         (type == DP_AUX_I2C_READ) ?
  79                                         "Read" : "Write",
  80                         address,
  81                         SIDE_BAND_MSG(address) ?
  82                                         side_band_msg_type_to_str(address) : "Nop",
  83                         res ? "OK" : "Fail");
  84
  85         if (res) {
  86                 print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
  87         }
  88 }
  89 #endif
  90
  91 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  92                                   struct drm_dp_aux_msg *msg)
  93 {
  94         ssize_t result = 0;
  95         struct aux_payload payload;
  96         enum aux_channel_operation_result operation_result;
  97
  98         if (WARN_ON(msg->size > 16))
  99                 return -E2BIG;
 100
 101         payload.address = msg->address;
 102         payload.data = msg->buffer;
 103         payload.length = msg->size;
 104         payload.reply = &msg->reply;
 105         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
 106         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
 107         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
 108         payload.defer_delay = 0;
 109
 110         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
 111                                       &operation_result);
 112
 113         if (payload.write)
 114                 result = msg->size;
 115
 116         if (result < 0)
 117                 switch (operation_result) {
 118                 case AUX_CHANNEL_OPERATION_SUCCEEDED:
 119                         break;
 120                 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
 121                 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
 122                         result = -EIO;
 123                         break;
 124                 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
 125                 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
 126                         result = -EBUSY;
 127                         break;
 128                 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
 129                         result = -ETIMEDOUT;
 130                         break;
 131                 }
 132
 133         return result;
 134 }
 135
 136 static void
 137 dm_dp_mst_connector_destroy(struct drm_connector *connector)
 138 {
 139         struct amdgpu_dm_connector *aconnector =
 140                 to_amdgpu_dm_connector(connector);
 141         struct amdgpu_encoder *amdgpu_encoder = aconnector->mst_encoder;
 142
 143         if (aconnector->dc_sink) {
 144                 dc_link_remove_remote_sink(aconnector->dc_link,
 145                                            aconnector->dc_sink);
 146                 dc_sink_release(aconnector->dc_sink);
 147         }
 148
 149         kfree(aconnector->edid);
 150
 151         drm_encoder_cleanup(&amdgpu_encoder->base);
 152         kfree(amdgpu_encoder);
 153         drm_connector_cleanup(connector);
 154         drm_dp_mst_put_port_malloc(aconnector->port);
 155         kfree(aconnector);
 156 }
 157
 158 static int
 159 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 160 {
 161         struct amdgpu_dm_connector *amdgpu_dm_connector =
 162                 to_amdgpu_dm_connector(connector);
 163         int r;
 164
 165         amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
 166         r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
 167         if (r)
 168                 return r;
 169
 170 #if defined(CONFIG_DEBUG_FS)
 171         connector_debugfs_init(amdgpu_dm_connector);
 172 #endif
 173
 174         return r;
 175 }
 176
 177 static void
 178 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 179 {
 180         struct amdgpu_dm_connector *amdgpu_dm_connector =
 181                 to_amdgpu_dm_connector(connector);
 182         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 183
 184         drm_dp_mst_connector_early_unregister(connector, port);
 185 }
 186
 187 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 188         .fill_modes = drm_helper_probe_single_connector_modes,
 189         .destroy = dm_dp_mst_connector_destroy,
 190         .reset = amdgpu_dm_connector_funcs_reset,
 191         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 192         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 193         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 194         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 195         .late_register = amdgpu_dm_mst_connector_late_register,
 196         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 197 };
 198
 199 #if defined(CONFIG_DRM_AMD_DC_DCN)
 200 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 201 {
 202         struct dc_sink *dc_sink = aconnector->dc_sink;
 203         struct drm_dp_mst_port *port = aconnector->port;
 204         u8 dsc_caps[16] = { 0 };
 205
 206         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 207
 208         if (!aconnector->dsc_aux)
 209                 return false;
 210
 211         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 212                 return false;
 213
 214         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 215                                    dsc_caps, NULL,
 216                                    &dc_sink->dsc_caps.dsc_dec_caps))
 217                 return false;
 218
 219         return true;
 220 }
 221 #endif
 222
 223 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 224 {
 225         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 226         int ret = 0;
 227
 228         if (!aconnector)
 229                 return drm_add_edid_modes(connector, NULL);
 230
 231         if (!aconnector->edid) {
 232                 struct edid *edid;
 233                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 234
 235                 if (!edid) {
 236                         drm_connector_update_edid_property(
 237                                 &aconnector->base,
 238                                 NULL);
 239                         return ret;
 240                 }
 241
 242                 aconnector->edid = edid;
 243         }
 244
 245         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 246                 dc_sink_release(aconnector->dc_sink);
 247                 aconnector->dc_sink = NULL;
 248         }
 249
 250         if (!aconnector->dc_sink) {
 251                 struct dc_sink *dc_sink;
 252                 struct dc_sink_init_data init_params = {
 253                                 .link = aconnector->dc_link,
 254                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 255                 dc_sink = dc_link_add_remote_sink(
 256                         aconnector->dc_link,
 257                         (uint8_t *)aconnector->edid,
 258                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 259                         &init_params);
 260
 261                 dc_sink->priv = aconnector;
 262                 /* dc_link_add_remote_sink returns a new reference */
 263                 aconnector->dc_sink = dc_sink;
 264
 265                 if (aconnector->dc_sink) {
 266                         amdgpu_dm_update_freesync_caps(
 267                                         connector, aconnector->edid);
 268
 269 #if defined(CONFIG_DRM_AMD_DC_DCN)
 270                         if (!validate_dsc_caps_on_connector(aconnector))
 271                                 memset(&aconnector->dc_sink->dsc_caps,
 272                                        0, sizeof(aconnector->dc_sink->dsc_caps));
 273 #endif
 274                 }
 275         }
 276
 277         drm_connector_update_edid_property(
 278                                         &aconnector->base, aconnector->edid);
 279
 280         ret = drm_add_edid_modes(connector, aconnector->edid);
 281
 282         return ret;
 283 }
 284
 285 static struct drm_encoder *
 286 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 287                            struct drm_connector_state *connector_state)
 288 {
 289         return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
 290 }
 291
 292 static int
 293 dm_dp_mst_detect(struct drm_connector *connector,
 294                  struct drm_modeset_acquire_ctx *ctx, bool force)
 295 {
 296         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 297         struct amdgpu_dm_connector *master = aconnector->mst_port;
 298
 299         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 300                                       aconnector->port);
 301 }
 302
 303 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 304                                 struct drm_atomic_state *state)
 305 {
 306         struct drm_connector_state *new_conn_state =
 307                         drm_atomic_get_new_connector_state(state, connector);
 308         struct drm_connector_state *old_conn_state =
 309                         drm_atomic_get_old_connector_state(state, connector);
 310         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 311         struct drm_crtc_state *new_crtc_state;
 312         struct drm_dp_mst_topology_mgr *mst_mgr;
 313         struct drm_dp_mst_port *mst_port;
 314
 315         mst_port = aconnector->port;
 316         mst_mgr = &aconnector->mst_port->mst_mgr;
 317
 318         if (!old_conn_state->crtc)
 319                 return 0;
 320
 321         if (new_conn_state->crtc) {
 322                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 323                 if (!new_crtc_state ||
 324                     !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
 325                     new_crtc_state->enable)
 326                         return 0;
 327                 }
 328
 329         return drm_dp_atomic_release_vcpi_slots(state,
 330                                                 mst_mgr,
 331                                                 mst_port);
 332 }
 333
 334 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 335         .get_modes = dm_dp_mst_get_modes,
 336         .mode_valid = amdgpu_dm_connector_mode_valid,
 337         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 338         .detect_ctx = dm_dp_mst_detect,
 339         .atomic_check = dm_dp_mst_atomic_check,
 340 };
 341
 342 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 343 {
 344         drm_encoder_cleanup(encoder);
 345         kfree(encoder);
 346 }
 347
 348 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 349         .destroy = amdgpu_dm_encoder_destroy,
 350 };
 351
 352 static struct amdgpu_encoder *
 353 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
 354 {
 355         struct drm_device *dev = connector->base.dev;
 356         struct amdgpu_device *adev = dev->dev_private;
 357         struct amdgpu_encoder *amdgpu_encoder;
 358         struct drm_encoder *encoder;
 359
 360         amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
 361         if (!amdgpu_encoder)
 362                 return NULL;
 363
 364         encoder = &amdgpu_encoder->base;
 365         encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 366
 367         drm_encoder_init(
 368                 dev,
 369                 &amdgpu_encoder->base,
 370                 &amdgpu_dm_encoder_funcs,
 371                 DRM_MODE_ENCODER_DPMST,
 372                 NULL);
 373
 374         drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 375
 376         return amdgpu_encoder;
 377 }
 378
 379 static struct drm_connector *
 380 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 381                         struct drm_dp_mst_port *port,
 382                         const char *pathprop)
 383 {
 384         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 385         struct drm_device *dev = master->base.dev;
 386         struct amdgpu_device *adev = dev->dev_private;
 387         struct amdgpu_dm_connector *aconnector;
 388         struct drm_connector *connector;
 389
 390         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 391         if (!aconnector)
 392                 return NULL;
 393
 394         connector = &aconnector->base;
 395         aconnector->port = port;
 396         aconnector->mst_port = master;
 397
 398         if (drm_connector_init(
 399                 dev,
 400                 connector,
 401                 &dm_dp_mst_connector_funcs,
 402                 DRM_MODE_CONNECTOR_DisplayPort)) {
 403                 kfree(aconnector);
 404                 return NULL;
 405         }
 406         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 407
 408         amdgpu_dm_connector_init_helper(
 409                 &adev->dm,
 410                 aconnector,
 411                 DRM_MODE_CONNECTOR_DisplayPort,
 412                 master->dc_link,
 413                 master->connector_id);
 414
 415         aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
 416         drm_connector_attach_encoder(&aconnector->base,
 417                                      &aconnector->mst_encoder->base);
 418
 419         connector->max_bpc_property = master->base.max_bpc_property;
 420         if (connector->max_bpc_property)
 421                 drm_connector_attach_max_bpc_property(connector, 8, 16);
 422
 423         connector->vrr_capable_property = master->base.vrr_capable_property;
 424         if (connector->vrr_capable_property)
 425                 drm_connector_attach_vrr_capable_property(connector);
 426
 427         drm_object_attach_property(
 428                 &connector->base,
 429                 dev->mode_config.path_property,
 430                 0);
 431         drm_object_attach_property(
 432                 &connector->base,
 433                 dev->mode_config.tile_property,
 434                 0);
 435
 436         drm_connector_set_path_property(connector, pathprop);
 437
 438         /*
 439          * Initialize connector state before adding the connectror to drm and
 440          * framebuffer lists
 441          */
 442         amdgpu_dm_connector_funcs_reset(connector);
 443
 444         drm_dp_mst_get_port_malloc(port);
 445
 446         return connector;
 447 }
 448
 449 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 450         .add_connector = dm_dp_add_mst_connector,
 451 };
 452
 453 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 454                                        struct amdgpu_dm_connector *aconnector)
 455 {
 456         aconnector->dm_dp_aux.aux.name = "dmdc";
 457         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 458         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 459
 460         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 461         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 462                                       &aconnector->base);
 463
 464         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 465                 return;
 466
 467         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 468         drm_dp_mst_topology_mgr_init(
 469                 &aconnector->mst_mgr,
 470                 dm->adev->ddev,
 471                 &aconnector->dm_dp_aux.aux,
 472                 16,
 473                 4,
 474                 aconnector->connector_id);
 475 }
 476
 477 int dm_mst_get_pbn_divider(struct dc_link *link)
 478 {
 479         if (!link)
 480                 return 0;
 481
 482         return dc_link_bandwidth_kbps(link,
 483                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 484 }
 485
 486 #if defined(CONFIG_DRM_AMD_DC_DCN)
 487
 488 struct dsc_mst_fairness_params {
 489         struct dc_crtc_timing *timing;
 490         struct dc_sink *sink;
 491         struct dc_dsc_bw_range bw_range;
 492         bool compression_possible;
 493         struct drm_dp_mst_port *port;
 494 };
 495
 496 struct dsc_mst_fairness_vars {
 497         int pbn;
 498         bool dsc_enabled;
 499         int bpp_x16;
 500 };
 501
 502 static int kbps_to_peak_pbn(int kbps)
 503 {
 504         u64 peak_kbps = kbps;
 505
 506         peak_kbps *= 1006;
 507         peak_kbps = div_u64(peak_kbps, 1000);
 508         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 509 }
 510
 511 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 512                 struct dsc_mst_fairness_vars *vars,
 513                 int count)
 514 {
 515         int i;
 516
 517         for (i = 0; i < count; i++) {
 518                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 519                 if (vars[i].dsc_enabled && dc_dsc_compute_config(
 520                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 521                                         &params[i].sink->dsc_caps.dsc_dec_caps,
 522                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 523                                         0,
 524                                         params[i].timing,
 525                                         &params[i].timing->dsc_cfg)) {
 526                         params[i].timing->flags.DSC = 1;
 527                         params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 528                 } else {
 529                         params[i].timing->flags.DSC = 0;
 530                 }
 531         }
 532 }
 533
 534 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 535 {
 536         struct dc_dsc_config dsc_config;
 537         u64 kbps;
 538
 539         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 540         dc_dsc_compute_config(
 541                         param.sink->ctx->dc->res_pool->dscs[0],
 542                         &param.sink->dsc_caps.dsc_dec_caps,
 543                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 544                         (int) kbps, param.timing, &dsc_config);
 545
 546         return dsc_config.bits_per_pixel;
 547 }
 548
 549 static void increase_dsc_bpp(struct drm_atomic_state *state,
 550                              struct dc_link *dc_link,
 551                              struct dsc_mst_fairness_params *params,
 552                              struct dsc_mst_fairness_vars *vars,
 553                              int count)
 554 {
 555         int i;
 556         bool bpp_increased[MAX_PIPES];
 557         int initial_slack[MAX_PIPES];
 558         int min_initial_slack;
 559         int next_index;
 560         int remaining_to_increase = 0;
 561         int pbn_per_timeslot;
 562         int link_timeslots_used;
 563         int fair_pbn_alloc;
 564
 565         for (i = 0; i < count; i++) {
 566                 if (vars[i].dsc_enabled) {
 567                         initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
 568                         bpp_increased[i] = false;
 569                         remaining_to_increase += 1;
 570                 } else {
 571                         initial_slack[i] = 0;
 572                         bpp_increased[i] = true;
 573                 }
 574         }
 575
 576         pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
 577                         dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
 578
 579         while (remaining_to_increase) {
 580                 next_index = -1;
 581                 min_initial_slack = -1;
 582                 for (i = 0; i < count; i++) {
 583                         if (!bpp_increased[i]) {
 584                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 585                                         min_initial_slack = initial_slack[i];
 586                                         next_index = i;
 587                                 }
 588                         }
 589                 }
 590
 591                 if (next_index == -1)
 592                         break;
 593
 594                 link_timeslots_used = 0;
 595
 596                 for (i = 0; i < count; i++)
 597                         link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
 598
 599                 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
 600
 601                 if (initial_slack[next_index] > fair_pbn_alloc) {
 602                         vars[next_index].pbn += fair_pbn_alloc;
 603                         if (drm_dp_atomic_find_vcpi_slots(state,
 604                                                           params[next_index].port->mgr,
 605                                                           params[next_index].port,
 606                                                           vars[next_index].pbn,
 607                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 608                                 return;
 609                         if (!drm_dp_mst_atomic_check(state)) {
 610                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 611                         } else {
 612                                 vars[next_index].pbn -= fair_pbn_alloc;
 613                                 if (drm_dp_atomic_find_vcpi_slots(state,
 614                                                                   params[next_index].port->mgr,
 615                                                                   params[next_index].port,
 616                                                                   vars[next_index].pbn,
 617                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 618                                         return;
 619                         }
 620                 } else {
 621                         vars[next_index].pbn += initial_slack[next_index];
 622                         if (drm_dp_atomic_find_vcpi_slots(state,
 623                                                           params[next_index].port->mgr,
 624                                                           params[next_index].port,
 625                                                           vars[next_index].pbn,
 626                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 627                                 return;
 628                         if (!drm_dp_mst_atomic_check(state)) {
 629                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 630                         } else {
 631                                 vars[next_index].pbn -= initial_slack[next_index];
 632                                 if (drm_dp_atomic_find_vcpi_slots(state,
 633                                                                   params[next_index].port->mgr,
 634                                                                   params[next_index].port,
 635                                                                   vars[next_index].pbn,
 636                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 637                                         return;
 638                         }
 639                 }
 640
 641                 bpp_increased[next_index] = true;
 642                 remaining_to_increase--;
 643         }
 644 }
 645
 646 static void try_disable_dsc(struct drm_atomic_state *state,
 647                             struct dc_link *dc_link,
 648                             struct dsc_mst_fairness_params *params,
 649                             struct dsc_mst_fairness_vars *vars,
 650                             int count)
 651 {
 652         int i;
 653         bool tried[MAX_PIPES];
 654         int kbps_increase[MAX_PIPES];
 655         int max_kbps_increase;
 656         int next_index;
 657         int remaining_to_try = 0;
 658
 659         for (i = 0; i < count; i++) {
 660                 if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
 661                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 662                         tried[i] = false;
 663                         remaining_to_try += 1;
 664                 } else {
 665                         kbps_increase[i] = 0;
 666                         tried[i] = true;
 667                 }
 668         }
 669
 670         while (remaining_to_try) {
 671                 next_index = -1;
 672                 max_kbps_increase = -1;
 673                 for (i = 0; i < count; i++) {
 674                         if (!tried[i]) {
 675                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 676                                         max_kbps_increase = kbps_increase[i];
 677                                         next_index = i;
 678                                 }
 679                         }
 680                 }
 681
 682                 if (next_index == -1)
 683                         break;
 684
 685                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 686                 if (drm_dp_atomic_find_vcpi_slots(state,
 687                                                   params[next_index].port->mgr,
 688                                                   params[next_index].port,
 689                                                   vars[next_index].pbn,
 690                                                   0) < 0)
 691                         return;
 692
 693                 if (!drm_dp_mst_atomic_check(state)) {
 694                         vars[next_index].dsc_enabled = false;
 695                         vars[next_index].bpp_x16 = 0;
 696                 } else {
 697                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 698                         if (drm_dp_atomic_find_vcpi_slots(state,
 699                                                           params[next_index].port->mgr,
 700                                                           params[next_index].port,
 701                                                           vars[next_index].pbn,
 702                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 703                                 return;
 704                 }
 705
 706                 tried[next_index] = true;
 707                 remaining_to_try--;
 708         }
 709 }
 710
 711 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 712                                              struct dc_state *dc_state,
 713                                              struct dc_link *dc_link)
 714 {
 715         int i;
 716         struct dc_stream_state *stream;
 717         struct dsc_mst_fairness_params params[MAX_PIPES];
 718         struct dsc_mst_fairness_vars vars[MAX_PIPES];
 719         struct amdgpu_dm_connector *aconnector;
 720         int count = 0;
 721
 722         memset(params, 0, sizeof(params));
 723
 724         /* Set up params */
 725         for (i = 0; i < dc_state->stream_count; i++) {
 726                 struct dc_dsc_policy dsc_policy = {0};
 727
 728                 stream = dc_state->streams[i];
 729
 730                 if (stream->link != dc_link)
 731                         continue;
 732
 733                 stream->timing.flags.DSC = 0;
 734
 735                 params[count].timing = &stream->timing;
 736                 params[count].sink = stream->sink;
 737                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 738                 params[count].port = aconnector->port;
 739                 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
 740                 dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
 741                 if (!dc_dsc_compute_bandwidth_range(
 742                                 stream->sink->ctx->dc->res_pool->dscs[0],
 743                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 744                                 dsc_policy.min_target_bpp,
 745                                 dsc_policy.max_target_bpp,
 746                                 &stream->sink->dsc_caps.dsc_dec_caps,
 747                                 &stream->timing, &params[count].bw_range))
 748                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 749
 750                 count++;
 751         }
 752         /* Try no compression */
 753         for (i = 0; i < count; i++) {
 754                 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 755                 vars[i].dsc_enabled = false;
 756                 vars[i].bpp_x16 = 0;
 757                 if (drm_dp_atomic_find_vcpi_slots(state,
 758                                                  params[i].port->mgr,
 759                                                  params[i].port,
 760                                                  vars[i].pbn,
 761                                                  0) < 0)
 762                         return false;
 763         }
 764         if (!drm_dp_mst_atomic_check(state)) {
 765                 set_dsc_configs_from_fairness_vars(params, vars, count);
 766                 return true;
 767         }
 768
 769         /* Try max compression */
 770         for (i = 0; i < count; i++) {
 771                 if (params[i].compression_possible) {
 772                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 773                         vars[i].dsc_enabled = true;
 774                         vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 775                         if (drm_dp_atomic_find_vcpi_slots(state,
 776                                                           params[i].port->mgr,
 777                                                           params[i].port,
 778                                                           vars[i].pbn,
 779                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 780                                 return false;
 781                 } else {
 782                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 783                         vars[i].dsc_enabled = false;
 784                         vars[i].bpp_x16 = 0;
 785                         if (drm_dp_atomic_find_vcpi_slots(state,
 786                                                           params[i].port->mgr,
 787                                                           params[i].port,
 788                                                           vars[i].pbn,
 789                                                           0) < 0)
 790                                 return false;
 791                 }
 792         }
 793         if (drm_dp_mst_atomic_check(state))
 794                 return false;
 795
 796         /* Optimize degree of compression */
 797         increase_dsc_bpp(state, dc_link, params, vars, count);
 798
 799         try_disable_dsc(state, dc_link, params, vars, count);
 800
 801         set_dsc_configs_from_fairness_vars(params, vars, count);
 802
 803         return true;
 804 }
 805
 806 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 807                                        struct dc_state *dc_state)
 808 {
 809         int i, j;
 810         struct dc_stream_state *stream;
 811         bool computed_streams[MAX_PIPES];
 812         struct amdgpu_dm_connector *aconnector;
 813
 814         for (i = 0; i < dc_state->stream_count; i++)
 815                 computed_streams[i] = false;
 816
 817         for (i = 0; i < dc_state->stream_count; i++) {
 818                 stream = dc_state->streams[i];
 819
 820                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
 821                         continue;
 822
 823                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 824
 825                 if (!aconnector || !aconnector->dc_sink)
 826                         continue;
 827
 828                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
 829                         continue;
 830
 831                 if (computed_streams[i])
 832                         continue;
 833
 834                 mutex_lock(&aconnector->mst_mgr.lock);
 835                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
 836                         mutex_unlock(&aconnector->mst_mgr.lock);
 837                         return false;
 838                 }
 839                 mutex_unlock(&aconnector->mst_mgr.lock);
 840
 841                 for (j = 0; j < dc_state->stream_count; j++) {
 842                         if (dc_state->streams[j]->link == stream->link)
 843                                 computed_streams[j] = true;
 844                 }
 845         }
 846
 847         for (i = 0; i < dc_state->stream_count; i++) {
 848                 stream = dc_state->streams[i];
 849
 850                 if (stream->timing.flags.DSC == 1)
 851                         dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);
 852         }
 853
 854         return true;
 855 }
 856
 857 #endif