1 // SPDX-License-Identifier: MIT
3 * Copyright 2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
29 #include "dcn314_clk_mgr.h"
32 #include "clk_mgr_internal.h"
34 // For dce12_get_dp_ref_freq_khz
35 #include "dce100/dce_clk_mgr.h"
37 // For dcn20_update_clocks_update_dpp_dto
38 #include "dcn20/dcn20_clk_mgr.h"
42 #include "reg_helper.h"
43 #include "core_types.h"
44 #include "dm_helpers.h"
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48 #include "dcn31/dcn31_clk_mgr.h"
50 #include "dc_dmub_srv.h"
51 #include "dc_link_dp.h"
52 #include "dcn314_smu.h"
54 #define MAX_INSTANCE 7
57 struct IP_BASE_INSTANCE
{
58 unsigned int segment
[MAX_SEGMENT
];
62 struct IP_BASE_INSTANCE instance
[MAX_INSTANCE
];
65 static const struct IP_BASE CLK_BASE
= { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } },
66 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } },
67 { { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } },
68 { { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } },
69 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } },
70 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } },
71 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0, 0, 0 } } } };
73 #define regCLK1_CLK_PLL_REQ 0x0237
74 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
76 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
77 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
78 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
79 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
80 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
81 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
83 #define REG(reg_name) \
84 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
86 #define TO_CLK_MGR_DCN314(clk_mgr)\
87 container_of(clk_mgr, struct clk_mgr_dcn314, base)
89 static int dcn314_get_active_display_cnt_wa(
91 struct dc_state
*context
)
94 bool tmds_present
= false;
97 for (i
= 0; i
< context
->stream_count
; i
++) {
98 const struct dc_stream_state
*stream
= context
->streams
[i
];
100 if (stream
->signal
== SIGNAL_TYPE_HDMI_TYPE_A
||
101 stream
->signal
== SIGNAL_TYPE_DVI_SINGLE_LINK
||
102 stream
->signal
== SIGNAL_TYPE_DVI_DUAL_LINK
)
106 for (i
= 0; i
< dc
->link_count
; i
++) {
107 const struct dc_link
*link
= dc
->links
[i
];
109 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
110 if (link
->link_enc
&& link
->link_enc
->funcs
->is_dig_enabled
&&
111 link
->link_enc
->funcs
->is_dig_enabled(link
->link_enc
))
115 /* WA for hang on HDMI after display off back on*/
116 if (display_count
== 0 && tmds_present
)
119 return display_count
;
122 static void dcn314_disable_otg_wa(struct clk_mgr
*clk_mgr_base
, bool disable
)
124 struct dc
*dc
= clk_mgr_base
->ctx
->dc
;
127 for (i
= 0; i
< dc
->res_pool
->pipe_count
; ++i
) {
128 struct pipe_ctx
*pipe
= &dc
->current_state
->res_ctx
.pipe_ctx
[i
];
130 if (pipe
->top_pipe
|| pipe
->prev_odm_pipe
)
132 if (pipe
->stream
&& (pipe
->stream
->dpms_off
|| pipe
->plane_state
== NULL
||
133 dc_is_virtual_signal(pipe
->stream
->signal
))) {
135 pipe
->stream_res
.tg
->funcs
->immediate_disable_crtc(pipe
->stream_res
.tg
);
137 pipe
->stream_res
.tg
->funcs
->enable_crtc(pipe
->stream_res
.tg
);
142 void dcn314_update_clocks(struct clk_mgr
*clk_mgr_base
,
143 struct dc_state
*context
,
146 union dmub_rb_cmd cmd
;
147 struct clk_mgr_internal
*clk_mgr
= TO_CLK_MGR_INTERNAL(clk_mgr_base
);
148 struct dc_clocks
*new_clocks
= &context
->bw_ctx
.bw
.dcn
.clk
;
149 struct dc
*dc
= clk_mgr_base
->ctx
->dc
;
151 bool update_dppclk
= false;
152 bool update_dispclk
= false;
153 bool dpp_clock_lowered
= false;
155 if (dc
->work_arounds
.skip_clock_update
)
159 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
160 * also if safe to lower is false, we just go in the higher state
163 if (new_clocks
->zstate_support
!= DCN_ZSTATE_SUPPORT_DISALLOW
&&
164 new_clocks
->zstate_support
!= clk_mgr_base
->clks
.zstate_support
) {
165 dcn314_smu_set_zstate_support(clk_mgr
, new_clocks
->zstate_support
);
166 dm_helpers_enable_periodic_detection(clk_mgr_base
->ctx
, true);
167 clk_mgr_base
->clks
.zstate_support
= new_clocks
->zstate_support
;
170 if (clk_mgr_base
->clks
.dtbclk_en
&& !new_clocks
->dtbclk_en
) {
171 dcn314_smu_set_dtbclk(clk_mgr
, false);
172 clk_mgr_base
->clks
.dtbclk_en
= new_clocks
->dtbclk_en
;
174 /* check that we're not already in lower */
175 if (clk_mgr_base
->clks
.pwr_state
!= DCN_PWR_STATE_LOW_POWER
) {
176 display_count
= dcn314_get_active_display_cnt_wa(dc
, context
);
177 /* if we can go lower, go lower */
178 if (display_count
== 0) {
179 union display_idle_optimization_u idle_info
= { 0 };
180 idle_info
.idle_info
.df_request_disabled
= 1;
181 idle_info
.idle_info
.phy_ref_clk_off
= 1;
182 idle_info
.idle_info
.s0i2_rdy
= 1;
183 dcn314_smu_set_display_idle_optimization(clk_mgr
, idle_info
.data
);
184 /* update power state */
185 clk_mgr_base
->clks
.pwr_state
= DCN_PWR_STATE_LOW_POWER
;
189 if (new_clocks
->zstate_support
== DCN_ZSTATE_SUPPORT_DISALLOW
&&
190 new_clocks
->zstate_support
!= clk_mgr_base
->clks
.zstate_support
) {
191 dcn314_smu_set_zstate_support(clk_mgr
, DCN_ZSTATE_SUPPORT_DISALLOW
);
192 dm_helpers_enable_periodic_detection(clk_mgr_base
->ctx
, false);
193 clk_mgr_base
->clks
.zstate_support
= new_clocks
->zstate_support
;
196 if (!clk_mgr_base
->clks
.dtbclk_en
&& new_clocks
->dtbclk_en
) {
197 dcn314_smu_set_dtbclk(clk_mgr
, true);
198 clk_mgr_base
->clks
.dtbclk_en
= new_clocks
->dtbclk_en
;
201 /* check that we're not already in D0 */
202 if (clk_mgr_base
->clks
.pwr_state
!= DCN_PWR_STATE_MISSION_MODE
) {
203 union display_idle_optimization_u idle_info
= { 0 };
205 dcn314_smu_set_display_idle_optimization(clk_mgr
, idle_info
.data
);
206 /* update power state */
207 clk_mgr_base
->clks
.pwr_state
= DCN_PWR_STATE_MISSION_MODE
;
211 if (should_set_clock(safe_to_lower
, new_clocks
->dcfclk_khz
, clk_mgr_base
->clks
.dcfclk_khz
)) {
212 clk_mgr_base
->clks
.dcfclk_khz
= new_clocks
->dcfclk_khz
;
213 dcn314_smu_set_hard_min_dcfclk(clk_mgr
, clk_mgr_base
->clks
.dcfclk_khz
);
216 if (should_set_clock(safe_to_lower
,
217 new_clocks
->dcfclk_deep_sleep_khz
, clk_mgr_base
->clks
.dcfclk_deep_sleep_khz
)) {
218 clk_mgr_base
->clks
.dcfclk_deep_sleep_khz
= new_clocks
->dcfclk_deep_sleep_khz
;
219 dcn314_smu_set_min_deep_sleep_dcfclk(clk_mgr
, clk_mgr_base
->clks
.dcfclk_deep_sleep_khz
);
222 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
223 if (!IS_DIAG_DC(dc
->ctx
->dce_environment
)) {
224 if (new_clocks
->dppclk_khz
< 100000)
225 new_clocks
->dppclk_khz
= 100000;
228 if (should_set_clock(safe_to_lower
, new_clocks
->dppclk_khz
, clk_mgr
->base
.clks
.dppclk_khz
)) {
229 if (clk_mgr
->base
.clks
.dppclk_khz
> new_clocks
->dppclk_khz
)
230 dpp_clock_lowered
= true;
231 clk_mgr_base
->clks
.dppclk_khz
= new_clocks
->dppclk_khz
;
232 update_dppclk
= true;
235 if (should_set_clock(safe_to_lower
, new_clocks
->dispclk_khz
, clk_mgr_base
->clks
.dispclk_khz
)) {
236 dcn314_disable_otg_wa(clk_mgr_base
, true);
238 clk_mgr_base
->clks
.dispclk_khz
= new_clocks
->dispclk_khz
;
239 dcn314_smu_set_dispclk(clk_mgr
, clk_mgr_base
->clks
.dispclk_khz
);
240 dcn314_disable_otg_wa(clk_mgr_base
, false);
242 update_dispclk
= true;
245 if (dpp_clock_lowered
) {
246 // increase per DPP DTO before lowering global dppclk
247 dcn20_update_clocks_update_dpp_dto(clk_mgr
, context
, safe_to_lower
);
248 dcn314_smu_set_dppclk(clk_mgr
, clk_mgr_base
->clks
.dppclk_khz
);
250 // increase global DPPCLK before lowering per DPP DTO
251 if (update_dppclk
|| update_dispclk
)
252 dcn314_smu_set_dppclk(clk_mgr
, clk_mgr_base
->clks
.dppclk_khz
);
253 // always update dtos unless clock is lowered and not safe to lower
254 if (new_clocks
->dppclk_khz
>= dc
->current_state
->bw_ctx
.bw
.dcn
.clk
.dppclk_khz
)
255 dcn20_update_clocks_update_dpp_dto(clk_mgr
, context
, safe_to_lower
);
258 // notify DMCUB of latest clocks
259 memset(&cmd
, 0, sizeof(cmd
));
260 cmd
.notify_clocks
.header
.type
= DMUB_CMD__CLK_MGR
;
261 cmd
.notify_clocks
.header
.sub_type
= DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS
;
262 cmd
.notify_clocks
.clocks
.dcfclk_khz
= clk_mgr_base
->clks
.dcfclk_khz
;
263 cmd
.notify_clocks
.clocks
.dcfclk_deep_sleep_khz
=
264 clk_mgr_base
->clks
.dcfclk_deep_sleep_khz
;
265 cmd
.notify_clocks
.clocks
.dispclk_khz
= clk_mgr_base
->clks
.dispclk_khz
;
266 cmd
.notify_clocks
.clocks
.dppclk_khz
= clk_mgr_base
->clks
.dppclk_khz
;
268 dc_dmub_srv_cmd_queue(dc
->ctx
->dmub_srv
, &cmd
);
269 dc_dmub_srv_cmd_execute(dc
->ctx
->dmub_srv
);
270 dc_dmub_srv_wait_idle(dc
->ctx
->dmub_srv
);
273 static int get_vco_frequency_from_reg(struct clk_mgr_internal
*clk_mgr
)
275 /* get FbMult value */
276 struct fixed31_32 pll_req
;
277 unsigned int fbmult_frac_val
= 0;
278 unsigned int fbmult_int_val
= 0;
281 * Register value of fbmult is in 8.16 format, we are converting to 314.32
282 * to leverage the fix point operations available in driver
285 REG_GET(CLK1_CLK_PLL_REQ
, FbMult_frac
, &fbmult_frac_val
); /* 16 bit fractional part*/
286 REG_GET(CLK1_CLK_PLL_REQ
, FbMult_int
, &fbmult_int_val
); /* 8 bit integer part */
288 pll_req
= dc_fixpt_from_int(fbmult_int_val
);
291 * since fractional part is only 16 bit in register definition but is 32 bit
292 * in our fix point definiton, need to shift left by 16 to obtain correct value
294 pll_req
.value
|= fbmult_frac_val
<< 16;
296 /* multiply by REFCLK period */
297 pll_req
= dc_fixpt_mul_int(pll_req
, clk_mgr
->dfs_ref_freq_khz
);
299 /* integer part is now VCO frequency in kHz */
300 return dc_fixpt_floor(pll_req
);
303 static void dcn314_enable_pme_wa(struct clk_mgr
*clk_mgr_base
)
305 struct clk_mgr_internal
*clk_mgr
= TO_CLK_MGR_INTERNAL(clk_mgr_base
);
307 dcn314_smu_enable_pme_wa(clk_mgr
);
310 void dcn314_init_clocks(struct clk_mgr
*clk_mgr
)
312 memset(&(clk_mgr
->clks
), 0, sizeof(struct dc_clocks
));
313 // Assumption is that boot state always supports pstate
314 clk_mgr
->clks
.p_state_change_support
= true;
315 clk_mgr
->clks
.prev_p_state_change_support
= true;
316 clk_mgr
->clks
.pwr_state
= DCN_PWR_STATE_UNKNOWN
;
317 clk_mgr
->clks
.zstate_support
= DCN_ZSTATE_SUPPORT_UNKNOWN
;
320 bool dcn314_are_clock_states_equal(struct dc_clocks
*a
,
323 if (a
->dispclk_khz
!= b
->dispclk_khz
)
325 else if (a
->dppclk_khz
!= b
->dppclk_khz
)
327 else if (a
->dcfclk_khz
!= b
->dcfclk_khz
)
329 else if (a
->dcfclk_deep_sleep_khz
!= b
->dcfclk_deep_sleep_khz
)
331 else if (a
->zstate_support
!= b
->zstate_support
)
333 else if (a
->dtbclk_en
!= b
->dtbclk_en
)
339 static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass
*regs_and_bypass
,
340 struct clk_mgr
*clk_mgr_base
, struct clk_log_info
*log_info
)
345 static struct clk_bw_params dcn314_bw_params
= {
346 .vram_type
= Ddr4MemType
,
354 static struct wm_table ddr5_wm_table
= {
358 .wm_type
= WM_TYPE_PSTATE_CHG
,
359 .pstate_latency_us
= 11.72,
360 .sr_exit_time_us
= 9,
361 .sr_enter_plus_exit_time_us
= 11,
366 .wm_type
= WM_TYPE_PSTATE_CHG
,
367 .pstate_latency_us
= 11.72,
368 .sr_exit_time_us
= 9,
369 .sr_enter_plus_exit_time_us
= 11,
374 .wm_type
= WM_TYPE_PSTATE_CHG
,
375 .pstate_latency_us
= 11.72,
376 .sr_exit_time_us
= 9,
377 .sr_enter_plus_exit_time_us
= 11,
382 .wm_type
= WM_TYPE_PSTATE_CHG
,
383 .pstate_latency_us
= 11.72,
384 .sr_exit_time_us
= 9,
385 .sr_enter_plus_exit_time_us
= 11,
391 static struct wm_table lpddr5_wm_table
= {
395 .wm_type
= WM_TYPE_PSTATE_CHG
,
396 .pstate_latency_us
= 11.65333,
397 .sr_exit_time_us
= 11.5,
398 .sr_enter_plus_exit_time_us
= 14.5,
403 .wm_type
= WM_TYPE_PSTATE_CHG
,
404 .pstate_latency_us
= 11.65333,
405 .sr_exit_time_us
= 11.5,
406 .sr_enter_plus_exit_time_us
= 14.5,
411 .wm_type
= WM_TYPE_PSTATE_CHG
,
412 .pstate_latency_us
= 11.65333,
413 .sr_exit_time_us
= 11.5,
414 .sr_enter_plus_exit_time_us
= 14.5,
419 .wm_type
= WM_TYPE_PSTATE_CHG
,
420 .pstate_latency_us
= 11.65333,
421 .sr_exit_time_us
= 11.5,
422 .sr_enter_plus_exit_time_us
= 14.5,
428 static DpmClocks_t dummy_clocks
;
430 static struct dcn314_watermarks dummy_wms
= { 0 };
432 static void dcn314_build_watermark_ranges(struct clk_bw_params
*bw_params
, struct dcn314_watermarks
*table
)
434 int i
, num_valid_sets
;
438 for (i
= 0; i
< WM_SET_COUNT
; i
++) {
439 /* skip empty entries, the smu array has no holes*/
440 if (!bw_params
->wm_table
.entries
[i
].valid
)
443 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].WmSetting
= bw_params
->wm_table
.entries
[i
].wm_inst
;
444 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].WmType
= bw_params
->wm_table
.entries
[i
].wm_type
;
445 /* We will not select WM based on fclk, so leave it as unconstrained */
446 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].MinClock
= 0;
447 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].MaxClock
= 0xFFFF;
449 if (table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].WmType
== WM_TYPE_PSTATE_CHG
) {
451 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].MinMclk
= 0;
453 /* add 1 to make it non-overlapping with next lvl */
454 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].MinMclk
=
455 bw_params
->clk_table
.entries
[i
- 1].dcfclk_mhz
+ 1;
457 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].MaxMclk
=
458 bw_params
->clk_table
.entries
[i
].dcfclk_mhz
;
461 /* unconstrained for memory retraining */
462 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].MinClock
= 0;
463 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
].MaxClock
= 0xFFFF;
465 /* Modify previous watermark range to cover up to max */
466 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
- 1].MaxClock
= 0xFFFF;
471 ASSERT(num_valid_sets
!= 0); /* Must have at least one set of valid watermarks */
473 /* modify the min and max to make sure we cover the whole range*/
474 table
->WatermarkRow
[WM_DCFCLK
][0].MinMclk
= 0;
475 table
->WatermarkRow
[WM_DCFCLK
][0].MinClock
= 0;
476 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
- 1].MaxMclk
= 0xFFFF;
477 table
->WatermarkRow
[WM_DCFCLK
][num_valid_sets
- 1].MaxClock
= 0xFFFF;
479 /* This is for writeback only, does not matter currently as no writeback support*/
480 table
->WatermarkRow
[WM_SOCCLK
][0].WmSetting
= WM_A
;
481 table
->WatermarkRow
[WM_SOCCLK
][0].MinClock
= 0;
482 table
->WatermarkRow
[WM_SOCCLK
][0].MaxClock
= 0xFFFF;
483 table
->WatermarkRow
[WM_SOCCLK
][0].MinMclk
= 0;
484 table
->WatermarkRow
[WM_SOCCLK
][0].MaxMclk
= 0xFFFF;
487 static void dcn314_notify_wm_ranges(struct clk_mgr
*clk_mgr_base
)
489 struct clk_mgr_internal
*clk_mgr
= TO_CLK_MGR_INTERNAL(clk_mgr_base
);
490 struct clk_mgr_dcn314
*clk_mgr_dcn314
= TO_CLK_MGR_DCN314(clk_mgr
);
491 struct dcn314_watermarks
*table
= clk_mgr_dcn314
->smu_wm_set
.wm_set
;
493 if (!clk_mgr
->smu_ver
)
496 if (!table
|| clk_mgr_dcn314
->smu_wm_set
.mc_address
.quad_part
== 0)
499 memset(table
, 0, sizeof(*table
));
501 dcn314_build_watermark_ranges(clk_mgr_base
->bw_params
, table
);
503 dcn314_smu_set_dram_addr_high(clk_mgr
,
504 clk_mgr_dcn314
->smu_wm_set
.mc_address
.high_part
);
505 dcn314_smu_set_dram_addr_low(clk_mgr
,
506 clk_mgr_dcn314
->smu_wm_set
.mc_address
.low_part
);
507 dcn314_smu_transfer_wm_table_dram_2_smu(clk_mgr
);
510 static void dcn314_get_dpm_table_from_smu(struct clk_mgr_internal
*clk_mgr
,
511 struct dcn314_smu_dpm_clks
*smu_dpm_clks
)
513 DpmClocks_t
*table
= smu_dpm_clks
->dpm_clks
;
515 if (!clk_mgr
->smu_ver
)
518 if (!table
|| smu_dpm_clks
->mc_address
.quad_part
== 0)
521 memset(table
, 0, sizeof(*table
));
523 dcn314_smu_set_dram_addr_high(clk_mgr
,
524 smu_dpm_clks
->mc_address
.high_part
);
525 dcn314_smu_set_dram_addr_low(clk_mgr
,
526 smu_dpm_clks
->mc_address
.low_part
);
527 dcn314_smu_transfer_dpm_table_smu_2_dram(clk_mgr
);
530 static uint32_t find_max_clk_value(const uint32_t clocks
[], uint32_t num_clocks
)
535 for (i
= 0; i
< num_clocks
; ++i
) {
543 static unsigned int find_clk_for_voltage(
544 const DpmClocks_t
*clock_table
,
545 const uint32_t clocks
[],
546 unsigned int voltage
)
552 for (i
= 0; i
< NUM_SOC_VOLTAGE_LEVELS
; i
++) {
553 if (clock_table
->SocVoltage
[i
] == voltage
) {
555 } else if (clock_table
->SocVoltage
[i
] >= max_voltage
&&
556 clock_table
->SocVoltage
[i
] < voltage
) {
557 max_voltage
= clock_table
->SocVoltage
[i
];
566 static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal
*clk_mgr
,
567 struct integrated_info
*bios_info
,
568 const DpmClocks_t
*clock_table
)
571 struct clk_bw_params
*bw_params
= clk_mgr
->base
.bw_params
;
572 uint32_t max_dispclk
= 0, max_dppclk
= 0;
576 ASSERT(NUM_DF_PSTATE_LEVELS
<= MAX_NUM_DPM_LVL
);
578 /* Find lowest DPM, FCLK is filled in reverse order*/
580 for (i
= NUM_DF_PSTATE_LEVELS
- 1; i
>= 0; i
--) {
581 if (clock_table
->DfPstateTable
[i
].FClk
!= 0) {
588 /* clock table is all 0s, just use our own hardcode */
593 bw_params
->clk_table
.num_entries
= j
+ 1;
595 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
596 if (clock_table
->NumDispClkLevelsEnabled
<= NUM_DISPCLK_DPM_LEVELS
&&
597 clock_table
->NumDispClkLevelsEnabled
<= NUM_DPPCLK_DPM_LEVELS
) {
598 max_dispclk
= find_max_clk_value(clock_table
->DispClocks
, clock_table
->NumDispClkLevelsEnabled
);
599 max_dppclk
= find_max_clk_value(clock_table
->DppClocks
, clock_table
->NumDispClkLevelsEnabled
);
604 for (i
= 0; i
< bw_params
->clk_table
.num_entries
; i
++, j
--) {
605 bw_params
->clk_table
.entries
[i
].fclk_mhz
= clock_table
->DfPstateTable
[j
].FClk
;
606 bw_params
->clk_table
.entries
[i
].memclk_mhz
= clock_table
->DfPstateTable
[j
].MemClk
;
607 bw_params
->clk_table
.entries
[i
].voltage
= clock_table
->DfPstateTable
[j
].Voltage
;
608 switch (clock_table
->DfPstateTable
[j
].WckRatio
) {
610 bw_params
->clk_table
.entries
[i
].wck_ratio
= 2;
613 bw_params
->clk_table
.entries
[i
].wck_ratio
= 4;
616 bw_params
->clk_table
.entries
[i
].wck_ratio
= 1;
618 bw_params
->clk_table
.entries
[i
].dcfclk_mhz
= find_clk_for_voltage(clock_table
, clock_table
->DcfClocks
, clock_table
->DfPstateTable
[j
].Voltage
);
619 bw_params
->clk_table
.entries
[i
].socclk_mhz
= find_clk_for_voltage(clock_table
, clock_table
->SocClocks
, clock_table
->DfPstateTable
[j
].Voltage
);
620 bw_params
->clk_table
.entries
[i
].dispclk_mhz
= max_dispclk
;
621 bw_params
->clk_table
.entries
[i
].dppclk_mhz
= max_dppclk
;
624 bw_params
->vram_type
= bios_info
->memory_type
;
625 bw_params
->num_channels
= bios_info
->ma_channel_number
;
627 for (i
= 0; i
< WM_SET_COUNT
; i
++) {
628 bw_params
->wm_table
.entries
[i
].wm_inst
= i
;
630 if (i
>= bw_params
->clk_table
.num_entries
) {
631 bw_params
->wm_table
.entries
[i
].valid
= false;
635 bw_params
->wm_table
.entries
[i
].wm_type
= WM_TYPE_PSTATE_CHG
;
636 bw_params
->wm_table
.entries
[i
].valid
= true;
640 static struct clk_mgr_funcs dcn314_funcs
= {
641 .get_dp_ref_clk_frequency
= dce12_get_dp_ref_freq_khz
,
642 .get_dtb_ref_clk_frequency
= dcn31_get_dtb_ref_freq_khz
,
643 .update_clocks
= dcn314_update_clocks
,
644 .init_clocks
= dcn314_init_clocks
,
645 .enable_pme_wa
= dcn314_enable_pme_wa
,
646 .are_clock_states_equal
= dcn314_are_clock_states_equal
,
647 .notify_wm_ranges
= dcn314_notify_wm_ranges
649 extern struct clk_mgr_funcs dcn3_fpga_funcs
;
651 void dcn314_clk_mgr_construct(
652 struct dc_context
*ctx
,
653 struct clk_mgr_dcn314
*clk_mgr
,
654 struct pp_smu_funcs
*pp_smu
,
657 struct dcn314_smu_dpm_clks smu_dpm_clks
= { 0 };
659 clk_mgr
->base
.base
.ctx
= ctx
;
660 clk_mgr
->base
.base
.funcs
= &dcn314_funcs
;
662 clk_mgr
->base
.pp_smu
= pp_smu
;
664 clk_mgr
->base
.dccg
= dccg
;
665 clk_mgr
->base
.dfs_bypass_disp_clk
= 0;
667 clk_mgr
->base
.dprefclk_ss_percentage
= 0;
668 clk_mgr
->base
.dprefclk_ss_divider
= 1000;
669 clk_mgr
->base
.ss_on_dprefclk
= false;
670 clk_mgr
->base
.dfs_ref_freq_khz
= 48000;
672 clk_mgr
->smu_wm_set
.wm_set
= (struct dcn314_watermarks
*)dm_helpers_allocate_gpu_mem(
673 clk_mgr
->base
.base
.ctx
,
674 DC_MEM_ALLOC_TYPE_FRAME_BUFFER
,
675 sizeof(struct dcn314_watermarks
),
676 &clk_mgr
->smu_wm_set
.mc_address
.quad_part
);
678 if (!clk_mgr
->smu_wm_set
.wm_set
) {
679 clk_mgr
->smu_wm_set
.wm_set
= &dummy_wms
;
680 clk_mgr
->smu_wm_set
.mc_address
.quad_part
= 0;
682 ASSERT(clk_mgr
->smu_wm_set
.wm_set
);
684 smu_dpm_clks
.dpm_clks
= (DpmClocks_t
*)dm_helpers_allocate_gpu_mem(
685 clk_mgr
->base
.base
.ctx
,
686 DC_MEM_ALLOC_TYPE_FRAME_BUFFER
,
688 &smu_dpm_clks
.mc_address
.quad_part
);
690 if (smu_dpm_clks
.dpm_clks
== NULL
) {
691 smu_dpm_clks
.dpm_clks
= &dummy_clocks
;
692 smu_dpm_clks
.mc_address
.quad_part
= 0;
695 ASSERT(smu_dpm_clks
.dpm_clks
);
697 if (IS_FPGA_MAXIMUS_DC(ctx
->dce_environment
)) {
698 clk_mgr
->base
.base
.funcs
= &dcn3_fpga_funcs
;
700 struct clk_log_info log_info
= {0};
702 clk_mgr
->base
.smu_ver
= dcn314_smu_get_smu_version(&clk_mgr
->base
);
704 if (clk_mgr
->base
.smu_ver
)
705 clk_mgr
->base
.smu_present
= true;
707 /* TODO: Check we get what we expect during bringup */
708 clk_mgr
->base
.base
.dentist_vco_freq_khz
= get_vco_frequency_from_reg(&clk_mgr
->base
);
710 if (ctx
->dc_bios
->integrated_info
->memory_type
== LpDdr5MemType
)
711 dcn314_bw_params
.wm_table
= lpddr5_wm_table
;
713 dcn314_bw_params
.wm_table
= ddr5_wm_table
;
715 /* Saved clocks configured at boot for debug purposes */
716 dcn314_dump_clk_registers(&clk_mgr
->base
.base
.boot_snapshot
,
717 &clk_mgr
->base
.base
, &log_info
);
721 clk_mgr
->base
.base
.dprefclk_khz
= 600000;
722 clk_mgr
->base
.base
.clks
.ref_dtbclk_khz
= 600000;
723 dce_clock_read_ss_info(&clk_mgr
->base
);
724 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/
725 //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);
727 clk_mgr
->base
.base
.bw_params
= &dcn314_bw_params
;
729 if (clk_mgr
->base
.base
.ctx
->dc
->debug
.pstate_enabled
) {
730 dcn314_get_dpm_table_from_smu(&clk_mgr
->base
, &smu_dpm_clks
);
732 if (ctx
->dc_bios
&& ctx
->dc_bios
->integrated_info
) {
733 dcn314_clk_mgr_helper_populate_bw_params(
735 ctx
->dc_bios
->integrated_info
,
736 smu_dpm_clks
.dpm_clks
);
740 if (smu_dpm_clks
.dpm_clks
&& smu_dpm_clks
.mc_address
.quad_part
!= 0)
741 dm_helpers_free_gpu_mem(clk_mgr
->base
.base
.ctx
, DC_MEM_ALLOC_TYPE_FRAME_BUFFER
,
742 smu_dpm_clks
.dpm_clks
);
745 void dcn314_clk_mgr_destroy(struct clk_mgr_internal
*clk_mgr_int
)
747 struct clk_mgr_dcn314
*clk_mgr
= TO_CLK_MGR_DCN314(clk_mgr_int
);
749 if (clk_mgr
->smu_wm_set
.wm_set
&& clk_mgr
->smu_wm_set
.mc_address
.quad_part
!= 0)
750 dm_helpers_free_gpu_mem(clk_mgr_int
->base
.ctx
, DC_MEM_ALLOC_TYPE_FRAME_BUFFER
,
751 clk_mgr
->smu_wm_set
.wm_set
);