drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27
  28 #include "dccg.h"
  29 #include "clk_mgr_internal.h"
  30
  31 // For dce12_get_dp_ref_freq_khz
  32 #include "dce100/dce_clk_mgr.h"
  33 // For dcn20_update_clocks_update_dpp_dto
  34 #include "dcn20/dcn20_clk_mgr.h"
  35 #include "dcn31/dcn31_clk_mgr.h"
  36 #include "dcn315_clk_mgr.h"
  37
  38 #include "core_types.h"
  39 #include "dcn315_smu.h"
  40 #include "dm_helpers.h"
  41
  42 #include "dc_dmub_srv.h"
  43
  44 #include "logger_types.h"
  45 #undef DC_LOGGER
  46 #define DC_LOGGER \
  47         clk_mgr->base.base.ctx->logger
  48
  49 #include "link.h"
  50
  51 #define TO_CLK_MGR_DCN315(clk_mgr)\
  52         container_of(clk_mgr, struct clk_mgr_dcn315, base)
  53
  54 #define UNSUPPORTED_DCFCLK 10000000
  55 #define MIN_DPP_DISP_CLK     100000
  56
  57 static int dcn315_get_active_display_cnt_wa(
  58                 struct dc *dc,
  59                 struct dc_state *context)
  60 {
  61         int i, display_count;
  62         bool tmds_present = false;
  63
  64         display_count = 0;
  65         for (i = 0; i < context->stream_count; i++) {
  66                 const struct dc_stream_state *stream = context->streams[i];
  67
  68                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  69                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  70                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  71                         tmds_present = true;
  72         }
  73
  74         for (i = 0; i < dc->link_count; i++) {
  75                 const struct dc_link *link = dc->links[i];
  76
  77                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
  78                 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
  79                                 link->link_enc->funcs->is_dig_enabled(link->link_enc))
  80                         display_count++;
  81         }
  82
  83         /* WA for hang on HDMI after display off back back on*/
  84         if (display_count == 0 && tmds_present)
  85                 display_count = 1;
  86
  87         return display_count;
  88 }
  89
  90 static bool should_disable_otg(struct pipe_ctx *pipe)
  91 {
  92         bool ret = true;
  93
  94         if (pipe->stream->link->link_enc && pipe->stream->link->link_enc->funcs->is_dig_enabled &&
  95                         pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc))
  96                 ret = false;
  97         return ret;
  98 }
  99
 100 static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
 101 {
 102         struct dc *dc = clk_mgr_base->ctx->dc;
 103         int i;
 104
 105         for (i = 0; i < dc->res_pool->pipe_count; ++i) {
 106                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 107
 108                 if (pipe->top_pipe || pipe->prev_odm_pipe)
 109                         continue;
 110                 if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
 111                                         dc_is_virtual_signal(pipe->stream->signal))) {
 112
 113                         /* This w/a should not trigger when we have a dig active */
 114                         if (should_disable_otg(pipe)) {
 115                                 if (disable) {
 116                                         pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
 117                                         reset_sync_context_for_pipe(dc, context, i);
 118                                 } else
 119                                         pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
 120                         }
 121                 }
 122         }
 123 }
 124
 125 static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
 126                         struct dc_state *context,
 127                         bool safe_to_lower)
 128 {
 129         union dmub_rb_cmd cmd;
 130         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 131         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 132         struct dc *dc = clk_mgr_base->ctx->dc;
 133         int display_count;
 134         bool update_dppclk = false;
 135         bool update_dispclk = false;
 136         bool dpp_clock_lowered = false;
 137
 138         if (dc->work_arounds.skip_clock_update)
 139                 return;
 140
 141         clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
 142         /*
 143          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 144          * also if safe to lower is false, we just go in the higher state
 145          */
 146         clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
 147         if (safe_to_lower) {
 148                 /* check that we're not already in lower */
 149                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 150                         display_count = dcn315_get_active_display_cnt_wa(dc, context);
 151                         /* if we can go lower, go lower */
 152                         if (display_count == 0) {
 153                                 union display_idle_optimization_u idle_info = { 0 };
 154                                 idle_info.idle_info.df_request_disabled = 1;
 155                                 idle_info.idle_info.phy_ref_clk_off = 1;
 156                                 idle_info.idle_info.s0i2_rdy = 1;
 157                                 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 158                                 /* update power state */
 159                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 160                         }
 161                 }
 162         } else {
 163                 /* check that we're not already in D0 */
 164                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 165                         union display_idle_optimization_u idle_info = { 0 };
 166                         dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 167                         /* update power state */
 168                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 169                 }
 170         }
 171
 172         /* Lock pstate by requesting unsupported dcfclk if change is unsupported */
 173         if (!new_clocks->p_state_change_support)
 174                 new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK;
 175         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 176                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 177                 dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 178         }
 179
 180         if (should_set_clock(safe_to_lower,
 181                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 182                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 183                 dcn315_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 184         }
 185
 186         // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
 187         if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
 188                 new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
 189         if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK)
 190                 new_clocks->dispclk_khz = MIN_DPP_DISP_CLK;
 191
 192         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
 193                 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
 194                         dpp_clock_lowered = true;
 195                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 196                 update_dppclk = true;
 197         }
 198
 199         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 200                 /* No need to apply the w/a if we haven't taken over from bios yet */
 201                 if (clk_mgr_base->clks.dispclk_khz)
 202                         dcn315_disable_otg_wa(clk_mgr_base, context, true);
 203
 204                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 205                 dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 206                 if (clk_mgr_base->clks.dispclk_khz)
 207                         dcn315_disable_otg_wa(clk_mgr_base, context, false);
 208
 209                 update_dispclk = true;
 210         }
 211
 212         if (dpp_clock_lowered) {
 213                 // increase per DPP DTO before lowering global dppclk
 214                 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 215                 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 216         } else {
 217                 // increase global DPPCLK before lowering per DPP DTO
 218                 if (update_dppclk || update_dispclk)
 219                         dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 220                 // always update dtos unless clock is lowered and not safe to lower
 221                 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
 222                         dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 223         }
 224
 225         // notify DMCUB of latest clocks
 226         memset(&cmd, 0, sizeof(cmd));
 227         cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
 228         cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
 229         cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
 230         cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
 231                 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
 232         cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
 233         cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
 234
 235         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 236 }
 237
 238 static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 239                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 240 {
 241         return;
 242 }
 243
 244 static struct clk_bw_params dcn315_bw_params = {
 245         .vram_type = Ddr4MemType,
 246         .num_channels = 2,
 247         .clk_table = {
 248                 .entries = {
 249                         {
 250                                 .voltage = 0,
 251                                 .dispclk_mhz = 640,
 252                                 .dppclk_mhz = 640,
 253                                 .phyclk_mhz = 810,
 254                                 .phyclk_d18_mhz = 667,
 255                                 .dtbclk_mhz = 600,
 256                         },
 257                         {
 258                                 .voltage = 1,
 259                                 .dispclk_mhz = 739,
 260                                 .dppclk_mhz = 739,
 261                                 .phyclk_mhz = 810,
 262                                 .phyclk_d18_mhz = 667,
 263                                 .dtbclk_mhz = 600,
 264                         },
 265                         {
 266                                 .voltage = 2,
 267                                 .dispclk_mhz = 960,
 268                                 .dppclk_mhz = 960,
 269                                 .phyclk_mhz = 810,
 270                                 .phyclk_d18_mhz = 667,
 271                                 .dtbclk_mhz = 600,
 272                         },
 273                         {
 274                                 .voltage = 3,
 275                                 .dispclk_mhz = 1200,
 276                                 .dppclk_mhz = 1200,
 277                                 .phyclk_mhz = 810,
 278                                 .phyclk_d18_mhz = 667,
 279                                 .dtbclk_mhz = 600,
 280                         },
 281                         {
 282                                 .voltage = 4,
 283                                 .dispclk_mhz = 1372,
 284                                 .dppclk_mhz = 1372,
 285                                 .phyclk_mhz = 810,
 286                                 .phyclk_d18_mhz = 667,
 287                                 .dtbclk_mhz = 600,
 288                         },
 289                 },
 290                 .num_entries = 5,
 291         },
 292
 293 };
 294
 295 static struct wm_table ddr5_wm_table = {
 296         .entries = {
 297                 {
 298                         .wm_inst = WM_A,
 299                         .wm_type = WM_TYPE_PSTATE_CHG,
 300                         .pstate_latency_us = 129.0,
 301                         .sr_exit_time_us = 11.5,
 302                         .sr_enter_plus_exit_time_us = 14.5,
 303                         .valid = true,
 304                 },
 305                 {
 306                         .wm_inst = WM_B,
 307                         .wm_type = WM_TYPE_PSTATE_CHG,
 308                         .pstate_latency_us = 129.0,
 309                         .sr_exit_time_us = 11.5,
 310                         .sr_enter_plus_exit_time_us = 14.5,
 311                         .valid = true,
 312                 },
 313                 {
 314                         .wm_inst = WM_C,
 315                         .wm_type = WM_TYPE_PSTATE_CHG,
 316                         .pstate_latency_us = 129.0,
 317                         .sr_exit_time_us = 11.5,
 318                         .sr_enter_plus_exit_time_us = 14.5,
 319                         .valid = true,
 320                 },
 321                 {
 322                         .wm_inst = WM_D,
 323                         .wm_type = WM_TYPE_PSTATE_CHG,
 324                         .pstate_latency_us = 129.0,
 325                         .sr_exit_time_us = 11.5,
 326                         .sr_enter_plus_exit_time_us = 14.5,
 327                         .valid = true,
 328                 },
 329         }
 330 };
 331
 332 static struct wm_table lpddr5_wm_table = {
 333         .entries = {
 334                 {
 335                         .wm_inst = WM_A,
 336                         .wm_type = WM_TYPE_PSTATE_CHG,
 337                         .pstate_latency_us = 129.0,
 338                         .sr_exit_time_us = 11.5,
 339                         .sr_enter_plus_exit_time_us = 14.5,
 340                         .valid = true,
 341                 },
 342                 {
 343                         .wm_inst = WM_B,
 344                         .wm_type = WM_TYPE_PSTATE_CHG,
 345                         .pstate_latency_us = 129.0,
 346                         .sr_exit_time_us = 11.5,
 347                         .sr_enter_plus_exit_time_us = 14.5,
 348                         .valid = true,
 349                 },
 350                 {
 351                         .wm_inst = WM_C,
 352                         .wm_type = WM_TYPE_PSTATE_CHG,
 353                         .pstate_latency_us = 129.0,
 354                         .sr_exit_time_us = 11.5,
 355                         .sr_enter_plus_exit_time_us = 14.5,
 356                         .valid = true,
 357                 },
 358                 {
 359                         .wm_inst = WM_D,
 360                         .wm_type = WM_TYPE_PSTATE_CHG,
 361                         .pstate_latency_us = 129.0,
 362                         .sr_exit_time_us = 11.5,
 363                         .sr_enter_plus_exit_time_us = 14.5,
 364                         .valid = true,
 365                 },
 366         }
 367 };
 368
 369 /* Temporary Place holder until we can get them from fuse */
 370 static DpmClocks_315_t dummy_clocks = { 0 };
 371 static struct dcn315_watermarks dummy_wms = { 0 };
 372
 373 static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
 374 {
 375         int i, num_valid_sets;
 376
 377         num_valid_sets = 0;
 378
 379         for (i = 0; i < WM_SET_COUNT; i++) {
 380                 /* skip empty entries, the smu array has no holes*/
 381                 if (!bw_params->wm_table.entries[i].valid)
 382                         continue;
 383
 384                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
 385                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
 386                 /* We will not select WM based on fclk, so leave it as unconstrained */
 387                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 388                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 389
 390                 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
 391                         if (i == 0)
 392                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
 393                         else {
 394                                 /* add 1 to make it non-overlapping with next lvl */
 395                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
 396                                                 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
 397                         }
 398                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
 399                                         bw_params->clk_table.entries[i].dcfclk_mhz;
 400
 401                 } else {
 402                         /* unconstrained for memory retraining */
 403                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 404                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 405
 406                         /* Modify previous watermark range to cover up to max */
 407                         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 408                 }
 409                 num_valid_sets++;
 410         }
 411
 412         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 413
 414         /* modify the min and max to make sure we cover the whole range*/
 415         table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
 416         table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
 417         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
 418         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 419
 420         /* This is for writeback only, does not matter currently as no writeback support*/
 421         table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
 422         table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
 423         table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
 424         table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
 425         table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
 426 }
 427
 428 static void dcn315_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 429 {
 430         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 431         struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr);
 432         struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set;
 433
 434         if (!clk_mgr->smu_ver)
 435                 return;
 436
 437         if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0)
 438                 return;
 439
 440         memset(table, 0, sizeof(*table));
 441
 442         dcn315_build_watermark_ranges(clk_mgr_base->bw_params, table);
 443
 444         dcn315_smu_set_dram_addr_high(clk_mgr,
 445                         clk_mgr_dcn315->smu_wm_set.mc_address.high_part);
 446         dcn315_smu_set_dram_addr_low(clk_mgr,
 447                         clk_mgr_dcn315->smu_wm_set.mc_address.low_part);
 448         dcn315_smu_transfer_wm_table_dram_2_smu(clk_mgr);
 449 }
 450
 451 static void dcn315_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
 452                 struct dcn315_smu_dpm_clks *smu_dpm_clks)
 453 {
 454         DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;
 455
 456         if (!clk_mgr->smu_ver)
 457                 return;
 458
 459         if (!table || smu_dpm_clks->mc_address.quad_part == 0)
 460                 return;
 461
 462         memset(table, 0, sizeof(*table));
 463
 464         dcn315_smu_set_dram_addr_high(clk_mgr,
 465                         smu_dpm_clks->mc_address.high_part);
 466         dcn315_smu_set_dram_addr_low(clk_mgr,
 467                         smu_dpm_clks->mc_address.low_part);
 468         dcn315_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
 469 }
 470
 471 static void dcn315_clk_mgr_helper_populate_bw_params(
 472                 struct clk_mgr_internal *clk_mgr,
 473                 struct integrated_info *bios_info,
 474                 const DpmClocks_315_t *clock_table)
 475 {
 476         int i;
 477         struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
 478         uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1;
 479         struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
 480
 481         /* For 315 we want to base clock table on dcfclk, need at least one entry regardless of pmfw table */
 482         for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
 483                 int j;
 484
 485                 /* DF table is sorted with clocks decreasing */
 486                 for (j = clock_table->NumDfPstatesEnabled - 2; j >= 0; j--) {
 487                         if (clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i])
 488                                 max_pstate = j;
 489                 }
 490                 /* Max DCFCLK should match up with max pstate */
 491                 if (i == clock_table->NumDcfClkLevelsEnabled - 1)
 492                         max_pstate = 0;
 493
 494                 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
 495                 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
 496                         if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
 497                                 break;
 498                 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
 499                 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
 500                 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
 501
 502                 /* Now update clocks we do read */
 503                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[max_pstate].FClk;
 504                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
 505                 bw_params->clk_table.entries[i].voltage = clock_table->SocVoltage[i];
 506                 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
 507                 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
 508                 bw_params->clk_table.entries[i].dispclk_mhz = clock_table->DispClocks[i];
 509                 bw_params->clk_table.entries[i].dppclk_mhz = clock_table->DppClocks[i];
 510                 bw_params->clk_table.entries[i].wck_ratio = 1;
 511         }
 512
 513         /* Make sure to include at least one entry */
 514         if (i == 0) {
 515                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[0].FClk;
 516                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[0].MemClk;
 517                 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[0].Voltage;
 518                 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0];
 519                 bw_params->clk_table.entries[i].wck_ratio = 1;
 520                 i++;
 521         } else if (clock_table->NumDcfClkLevelsEnabled != clock_table->NumSocClkLevelsEnabled) {
 522                 bw_params->clk_table.entries[i-1].voltage = clock_table->SocVoltage[clock_table->NumSocClkLevelsEnabled - 1];
 523                 bw_params->clk_table.entries[i-1].socclk_mhz = clock_table->SocClocks[clock_table->NumSocClkLevelsEnabled - 1];
 524                 bw_params->clk_table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1];
 525                 bw_params->clk_table.entries[i-1].dppclk_mhz = clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1];
 526         }
 527         bw_params->clk_table.num_entries = i;
 528
 529         /* Set any 0 clocks to max default setting. Not an issue for
 530          * power since we aren't doing switching in such case anyway
 531          */
 532         for (i = 0; i < bw_params->clk_table.num_entries; i++) {
 533                 if (!bw_params->clk_table.entries[i].fclk_mhz) {
 534                         bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
 535                         bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
 536                         bw_params->clk_table.entries[i].voltage = def_max.voltage;
 537                 }
 538                 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
 539                         bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
 540                 if (!bw_params->clk_table.entries[i].socclk_mhz)
 541                         bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
 542                 if (!bw_params->clk_table.entries[i].dispclk_mhz)
 543                         bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
 544                 if (!bw_params->clk_table.entries[i].dppclk_mhz)
 545                         bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
 546                 if (!bw_params->clk_table.entries[i].phyclk_mhz)
 547                         bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
 548                 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
 549                         bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
 550                 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
 551                         bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
 552         }
 553
 554         /* Make sure all highest default clocks are included*/
 555         ASSERT(bw_params->clk_table.entries[i-1].phyclk_mhz == def_max.phyclk_mhz);
 556         ASSERT(bw_params->clk_table.entries[i-1].phyclk_d18_mhz == def_max.phyclk_d18_mhz);
 557         ASSERT(bw_params->clk_table.entries[i-1].dtbclk_mhz == def_max.dtbclk_mhz);
 558         ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
 559         bw_params->vram_type = bios_info->memory_type;
 560         bw_params->num_channels = bios_info->ma_channel_number;
 561         bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
 562
 563         for (i = 0; i < WM_SET_COUNT; i++) {
 564                 bw_params->wm_table.entries[i].wm_inst = i;
 565
 566                 if (i >= bw_params->clk_table.num_entries) {
 567                         bw_params->wm_table.entries[i].valid = false;
 568                         continue;
 569                 }
 570
 571                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 572                 bw_params->wm_table.entries[i].valid = true;
 573         }
 574 }
 575
 576 static void dcn315_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 577 {
 578         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 579
 580         dcn315_smu_enable_pme_wa(clk_mgr);
 581 }
 582
 583 static struct clk_mgr_funcs dcn315_funcs = {
 584         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 585         .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
 586         .update_clocks = dcn315_update_clocks,
 587         .init_clocks = dcn31_init_clocks,
 588         .enable_pme_wa = dcn315_enable_pme_wa,
 589         .are_clock_states_equal = dcn31_are_clock_states_equal,
 590         .notify_wm_ranges = dcn315_notify_wm_ranges
 591 };
 592 extern struct clk_mgr_funcs dcn3_fpga_funcs;
 593
 594 void dcn315_clk_mgr_construct(
 595                 struct dc_context *ctx,
 596                 struct clk_mgr_dcn315 *clk_mgr,
 597                 struct pp_smu_funcs *pp_smu,
 598                 struct dccg *dccg)
 599 {
 600         struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
 601         struct clk_log_info log_info = {0};
 602
 603         clk_mgr->base.base.ctx = ctx;
 604         clk_mgr->base.base.funcs = &dcn315_funcs;
 605
 606         clk_mgr->base.pp_smu = pp_smu;
 607
 608         clk_mgr->base.dccg = dccg;
 609         clk_mgr->base.dfs_bypass_disp_clk = 0;
 610
 611         clk_mgr->base.dprefclk_ss_percentage = 0;
 612         clk_mgr->base.dprefclk_ss_divider = 1000;
 613         clk_mgr->base.ss_on_dprefclk = false;
 614         clk_mgr->base.dfs_ref_freq_khz = 48000;
 615
 616         clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem(
 617                                 clk_mgr->base.base.ctx,
 618                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 619                                 sizeof(struct dcn315_watermarks),
 620                                 &clk_mgr->smu_wm_set.mc_address.quad_part);
 621
 622         if (!clk_mgr->smu_wm_set.wm_set) {
 623                 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
 624                 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
 625         }
 626         ASSERT(clk_mgr->smu_wm_set.wm_set);
 627
 628         smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(
 629                                 clk_mgr->base.base.ctx,
 630                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 631                                 sizeof(DpmClocks_315_t),
 632                                 &smu_dpm_clks.mc_address.quad_part);
 633
 634         if (smu_dpm_clks.dpm_clks == NULL) {
 635                 smu_dpm_clks.dpm_clks = &dummy_clocks;
 636                 smu_dpm_clks.mc_address.quad_part = 0;
 637         }
 638
 639         ASSERT(smu_dpm_clks.dpm_clks);
 640
 641         clk_mgr->base.smu_ver = dcn315_smu_get_smu_version(&clk_mgr->base);
 642
 643         if (clk_mgr->base.smu_ver > 0)
 644                 clk_mgr->base.smu_present = true;
 645
 646         if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
 647                 dcn315_bw_params.wm_table = lpddr5_wm_table;
 648         } else {
 649                 dcn315_bw_params.wm_table = ddr5_wm_table;
 650         }
 651         /* Saved clocks configured at boot for debug purposes */
 652         dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
 653                                   &clk_mgr->base.base, &log_info);
 654
 655         clk_mgr->base.base.dprefclk_khz = 600000;
 656         clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);
 657         clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
 658         dce_clock_read_ss_info(&clk_mgr->base);
 659         clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
 660
 661         clk_mgr->base.base.bw_params = &dcn315_bw_params;
 662
 663         if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
 664                 int i;
 665
 666                 dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
 667                 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
 668                                    "NumDispClkLevelsEnabled: %d\n"
 669                                    "NumSocClkLevelsEnabled: %d\n"
 670                                    "VcnClkLevelsEnabled: %d\n"
 671                                    "NumDfPst atesEnabled: %d\n"
 672                                    "MinGfxClk: %d\n"
 673                                    "MaxGfxClk: %d\n",
 674                                    smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
 675                                    smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
 676                                    smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
 677                                    smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
 678                                    smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
 679                                    smu_dpm_clks.dpm_clks->MinGfxClk,
 680                                    smu_dpm_clks.dpm_clks->MaxGfxClk);
 681                 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
 682                         DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
 683                                            i,
 684                                            smu_dpm_clks.dpm_clks->DcfClocks[i]);
 685                 }
 686                 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
 687                         DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
 688                                            i, smu_dpm_clks.dpm_clks->DispClocks[i]);
 689                 }
 690                 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
 691                         DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
 692                                            i, smu_dpm_clks.dpm_clks->SocClocks[i]);
 693                 }
 694                 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
 695                         DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
 696                                            i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
 697
 698                 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
 699                         DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
 700                                            "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
 701                                            "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
 702                                            i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
 703                                            i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
 704                                            i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
 705                 }
 706
 707                 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
 708                         dcn315_clk_mgr_helper_populate_bw_params(
 709                                         &clk_mgr->base,
 710                                         ctx->dc_bios->integrated_info,
 711                                         smu_dpm_clks.dpm_clks);
 712                 }
 713         }
 714
 715         if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
 716                 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 717                                 smu_dpm_clks.dpm_clks);
 718 }
 719
 720 void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
 721 {
 722         struct clk_mgr_dcn315 *clk_mgr = TO_CLK_MGR_DCN315(clk_mgr_int);
 723
 724         if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
 725                 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 726                                 clk_mgr->smu_wm_set.wm_set);
 727 }