1 /* Copyright 2015 Advanced Micro Devices, Inc. */
2 #include "dm_services.h"
4 #include "dc_link_dp.h"
5 #include "dm_helpers.h"
10 #include "inc/core_types.h"
11 #include "link_hwss.h"
12 #include "dc_link_ddc.h"
13 #include "core_status.h"
14 #include "dpcd_defs.h"
21 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
23 /* maximum pre emphasis level allowed for each voltage swing level*/
24 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis
[] = {
28 PRE_EMPHASIS_DISABLED
};
31 POST_LT_ADJ_REQ_LIMIT
= 6,
32 POST_LT_ADJ_REQ_TIMEOUT
= 200
36 LINK_TRAINING_MAX_RETRY_COUNT
= 5,
37 /* to avoid infinite loop where-in the receiver
38 * switches between different VS
40 LINK_TRAINING_MAX_CR_RETRY
= 100
43 static bool decide_fallback_link_setting(
44 struct dc_link_settings initial_link_settings
,
45 struct dc_link_settings
*current_link_setting
,
46 enum link_training_result training_result
);
47 static struct dc_link_settings
get_common_supported_link_settings(
48 struct dc_link_settings link_setting_a
,
49 struct dc_link_settings link_setting_b
);
51 static uint32_t get_training_aux_rd_interval(
53 uint32_t default_wait_in_micro_secs
)
55 union training_aux_rd_interval training_rd_interval
;
57 memset(&training_rd_interval
, 0, sizeof(training_rd_interval
));
59 /* overwrite the delay if rev > 1.1*/
60 if (link
->dpcd_caps
.dpcd_rev
.raw
>= DPCD_REV_12
) {
61 /* DP 1.2 or later - retrieve delay through
62 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
65 DP_TRAINING_AUX_RD_INTERVAL
,
66 (uint8_t *)&training_rd_interval
,
67 sizeof(training_rd_interval
));
69 if (training_rd_interval
.bits
.TRAINIG_AUX_RD_INTERVAL
)
70 default_wait_in_micro_secs
= training_rd_interval
.bits
.TRAINIG_AUX_RD_INTERVAL
* 4000;
73 return default_wait_in_micro_secs
;
76 static void wait_for_training_aux_rd_interval(
78 uint32_t wait_in_micro_secs
)
80 udelay(wait_in_micro_secs
);
82 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
87 static void dpcd_set_training_pattern(
89 union dpcd_training_pattern dpcd_pattern
)
93 DP_TRAINING_PATTERN_SET
,
97 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
99 DP_TRAINING_PATTERN_SET
,
100 dpcd_pattern
.v1_4
.TRAINING_PATTERN_SET
);
103 static enum dc_dp_training_pattern
get_supported_tp(struct dc_link
*link
)
105 enum dc_dp_training_pattern highest_tp
= DP_TRAINING_PATTERN_SEQUENCE_2
;
106 struct encoder_feature_support
*features
= &link
->link_enc
->features
;
107 struct dpcd_caps
*dpcd_caps
= &link
->dpcd_caps
;
109 if (features
->flags
.bits
.IS_TPS3_CAPABLE
)
110 highest_tp
= DP_TRAINING_PATTERN_SEQUENCE_3
;
112 if (features
->flags
.bits
.IS_TPS4_CAPABLE
)
113 highest_tp
= DP_TRAINING_PATTERN_SEQUENCE_4
;
115 if (dpcd_caps
->max_down_spread
.bits
.TPS4_SUPPORTED
&&
116 highest_tp
>= DP_TRAINING_PATTERN_SEQUENCE_4
)
117 return DP_TRAINING_PATTERN_SEQUENCE_4
;
119 if (dpcd_caps
->max_ln_count
.bits
.TPS3_SUPPORTED
&&
120 highest_tp
>= DP_TRAINING_PATTERN_SEQUENCE_3
)
121 return DP_TRAINING_PATTERN_SEQUENCE_3
;
123 return DP_TRAINING_PATTERN_SEQUENCE_2
;
126 static void dpcd_set_link_settings(
127 struct dc_link
*link
,
128 const struct link_training_settings
*lt_settings
)
132 union down_spread_ctrl downspread
= { {0} };
133 union lane_count_set lane_count_set
= { {0} };
134 enum dc_dp_training_pattern dp_tr_pattern
;
136 downspread
.raw
= (uint8_t)
137 (lt_settings
->link_settings
.link_spread
);
139 lane_count_set
.bits
.LANE_COUNT_SET
=
140 lt_settings
->link_settings
.lane_count
;
142 lane_count_set
.bits
.ENHANCED_FRAMING
= lt_settings
->enhanced_framing
;
143 lane_count_set
.bits
.POST_LT_ADJ_REQ_GRANTED
= 0;
145 dp_tr_pattern
= get_supported_tp(link
);
147 if (dp_tr_pattern
!= DP_TRAINING_PATTERN_SEQUENCE_4
) {
148 lane_count_set
.bits
.POST_LT_ADJ_REQ_GRANTED
=
149 link
->dpcd_caps
.max_ln_count
.bits
.POST_LT_ADJ_REQ_SUPPORTED
;
152 core_link_write_dpcd(link
, DP_DOWNSPREAD_CTRL
,
153 &downspread
.raw
, sizeof(downspread
));
155 core_link_write_dpcd(link
, DP_LANE_COUNT_SET
,
156 &lane_count_set
.raw
, 1);
158 if (link
->dpcd_caps
.dpcd_rev
.raw
>= DPCD_REV_14
&&
159 lt_settings
->link_settings
.use_link_rate_set
== true) {
161 core_link_write_dpcd(link
, DP_LINK_BW_SET
, &rate
, 1);
162 core_link_write_dpcd(link
, DP_LINK_RATE_SET
,
163 <_settings
->link_settings
.link_rate_set
, 1);
165 rate
= (uint8_t) (lt_settings
->link_settings
.link_rate
);
166 core_link_write_dpcd(link
, DP_LINK_BW_SET
, &rate
, 1);
170 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
173 lt_settings
->link_settings
.link_rate
,
175 lt_settings
->link_settings
.lane_count
,
176 lt_settings
->enhanced_framing
,
178 lt_settings
->link_settings
.link_spread
);
180 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
183 lt_settings
->link_settings
.link_rate_set
,
185 lt_settings
->link_settings
.lane_count
,
186 lt_settings
->enhanced_framing
,
188 lt_settings
->link_settings
.link_spread
);
192 static enum dpcd_training_patterns
193 dc_dp_training_pattern_to_dpcd_training_pattern(
194 struct dc_link
*link
,
195 enum dc_dp_training_pattern pattern
)
197 enum dpcd_training_patterns dpcd_tr_pattern
=
198 DPCD_TRAINING_PATTERN_VIDEOIDLE
;
201 case DP_TRAINING_PATTERN_SEQUENCE_1
:
202 dpcd_tr_pattern
= DPCD_TRAINING_PATTERN_1
;
204 case DP_TRAINING_PATTERN_SEQUENCE_2
:
205 dpcd_tr_pattern
= DPCD_TRAINING_PATTERN_2
;
207 case DP_TRAINING_PATTERN_SEQUENCE_3
:
208 dpcd_tr_pattern
= DPCD_TRAINING_PATTERN_3
;
210 case DP_TRAINING_PATTERN_SEQUENCE_4
:
211 dpcd_tr_pattern
= DPCD_TRAINING_PATTERN_4
;
215 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
220 return dpcd_tr_pattern
;
223 static inline bool is_repeater(struct dc_link
*link
, uint32_t offset
)
225 return (!link
->is_lttpr_mode_transparent
&& offset
!= 0);
228 static void dpcd_set_lt_pattern_and_lane_settings(
229 struct dc_link
*link
,
230 const struct link_training_settings
*lt_settings
,
231 enum dc_dp_training_pattern pattern
,
234 union dpcd_training_lane dpcd_lane
[LANE_COUNT_DP_MAX
] = { { {0} } };
236 uint32_t dpcd_base_lt_offset
;
238 uint8_t dpcd_lt_buffer
[5] = {0};
239 union dpcd_training_pattern dpcd_pattern
= { {0} };
241 uint32_t size_in_bytes
;
242 bool edp_workaround
= false; /* TODO link_prop.INTERNAL */
243 dpcd_base_lt_offset
= DP_TRAINING_PATTERN_SET
;
245 if (is_repeater(link
, offset
))
246 dpcd_base_lt_offset
= DP_TRAINING_PATTERN_SET_PHY_REPEATER1
+
247 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE
) * (offset
- 1));
249 /*****************************************************************
250 * DpcdAddress_TrainingPatternSet
251 *****************************************************************/
252 dpcd_pattern
.v1_4
.TRAINING_PATTERN_SET
=
253 dc_dp_training_pattern_to_dpcd_training_pattern(link
, pattern
);
255 dpcd_lt_buffer
[DP_TRAINING_PATTERN_SET
- DP_TRAINING_PATTERN_SET
]
258 if (is_repeater(link
, offset
)) {
259 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
263 dpcd_pattern
.v1_4
.TRAINING_PATTERN_SET
);
265 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
268 dpcd_pattern
.v1_4
.TRAINING_PATTERN_SET
);
270 /*****************************************************************
271 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
272 *****************************************************************/
273 for (lane
= 0; lane
<
274 (uint32_t)(lt_settings
->link_settings
.lane_count
); lane
++) {
276 dpcd_lane
[lane
].bits
.VOLTAGE_SWING_SET
=
277 (uint8_t)(lt_settings
->lane_settings
[lane
].VOLTAGE_SWING
);
278 dpcd_lane
[lane
].bits
.PRE_EMPHASIS_SET
=
279 (uint8_t)(lt_settings
->lane_settings
[lane
].PRE_EMPHASIS
);
281 dpcd_lane
[lane
].bits
.MAX_SWING_REACHED
=
282 (lt_settings
->lane_settings
[lane
].VOLTAGE_SWING
==
283 VOLTAGE_SWING_MAX_LEVEL
? 1 : 0);
284 dpcd_lane
[lane
].bits
.MAX_PRE_EMPHASIS_REACHED
=
285 (lt_settings
->lane_settings
[lane
].PRE_EMPHASIS
==
286 PRE_EMPHASIS_MAX_LEVEL
? 1 : 0);
289 /* concatenate everything into one buffer*/
291 size_in_bytes
= lt_settings
->link_settings
.lane_count
* sizeof(dpcd_lane
[0]);
295 &dpcd_lt_buffer
[DP_TRAINING_LANE0_SET
- DP_TRAINING_PATTERN_SET
],
299 if (is_repeater(link
, offset
)) {
300 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
301 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
305 dpcd_lane
[0].bits
.VOLTAGE_SWING_SET
,
306 dpcd_lane
[0].bits
.PRE_EMPHASIS_SET
,
307 dpcd_lane
[0].bits
.MAX_SWING_REACHED
,
308 dpcd_lane
[0].bits
.MAX_PRE_EMPHASIS_REACHED
);
310 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
313 dpcd_lane
[0].bits
.VOLTAGE_SWING_SET
,
314 dpcd_lane
[0].bits
.PRE_EMPHASIS_SET
,
315 dpcd_lane
[0].bits
.MAX_SWING_REACHED
,
316 dpcd_lane
[0].bits
.MAX_PRE_EMPHASIS_REACHED
);
318 if (edp_workaround
) {
319 /* for eDP write in 2 parts because the 5-byte burst is
320 * causing issues on some eDP panels (EPR#366724)
322 core_link_write_dpcd(
324 DP_TRAINING_PATTERN_SET
,
326 sizeof(dpcd_pattern
.raw
));
328 core_link_write_dpcd(
330 DP_TRAINING_LANE0_SET
,
331 (uint8_t *)(dpcd_lane
),
335 /* write it all in (1 + number-of-lanes)-byte burst*/
336 core_link_write_dpcd(
340 size_in_bytes
+ sizeof(dpcd_pattern
.raw
));
342 link
->cur_lane_setting
= lt_settings
->lane_settings
[0];
345 static bool is_cr_done(enum dc_lane_count ln_count
,
346 union lane_status
*dpcd_lane_status
)
350 /*LANEx_CR_DONE bits All 1's?*/
351 for (lane
= 0; lane
< (uint32_t)(ln_count
); lane
++) {
352 if (!dpcd_lane_status
[lane
].bits
.CR_DONE_0
)
359 static bool is_ch_eq_done(enum dc_lane_count ln_count
,
360 union lane_status
*dpcd_lane_status
,
361 union lane_align_status_updated
*lane_status_updated
)
365 if (!lane_status_updated
->bits
.INTERLANE_ALIGN_DONE
)
368 for (lane
= 0; lane
< (uint32_t)(ln_count
); lane
++) {
369 if (!dpcd_lane_status
[lane
].bits
.SYMBOL_LOCKED_0
||
370 !dpcd_lane_status
[lane
].bits
.CHANNEL_EQ_DONE_0
)
378 static void update_drive_settings(
379 struct link_training_settings
*dest
,
380 struct link_training_settings src
)
383 for (lane
= 0; lane
< src
.link_settings
.lane_count
; lane
++) {
384 if (dest
->voltage_swing
== NULL
)
385 dest
->lane_settings
[lane
].VOLTAGE_SWING
= src
.lane_settings
[lane
].VOLTAGE_SWING
;
387 dest
->lane_settings
[lane
].VOLTAGE_SWING
= *dest
->voltage_swing
;
389 if (dest
->pre_emphasis
== NULL
)
390 dest
->lane_settings
[lane
].PRE_EMPHASIS
= src
.lane_settings
[lane
].PRE_EMPHASIS
;
392 dest
->lane_settings
[lane
].PRE_EMPHASIS
= *dest
->pre_emphasis
;
394 if (dest
->post_cursor2
== NULL
)
395 dest
->lane_settings
[lane
].POST_CURSOR2
= src
.lane_settings
[lane
].POST_CURSOR2
;
397 dest
->lane_settings
[lane
].POST_CURSOR2
= *dest
->post_cursor2
;
401 static uint8_t get_nibble_at_index(const uint8_t *buf
,
405 nibble
= buf
[index
/ 2];
415 static enum dc_pre_emphasis
get_max_pre_emphasis_for_voltage_swing(
416 enum dc_voltage_swing voltage
)
418 enum dc_pre_emphasis pre_emphasis
;
419 pre_emphasis
= PRE_EMPHASIS_MAX_LEVEL
;
421 if (voltage
<= VOLTAGE_SWING_MAX_LEVEL
)
422 pre_emphasis
= voltage_swing_to_pre_emphasis
[voltage
];
428 static void find_max_drive_settings(
429 const struct link_training_settings
*link_training_setting
,
430 struct link_training_settings
*max_lt_setting
)
433 struct dc_lane_settings max_requested
;
435 max_requested
.VOLTAGE_SWING
=
436 link_training_setting
->
437 lane_settings
[0].VOLTAGE_SWING
;
438 max_requested
.PRE_EMPHASIS
=
439 link_training_setting
->
440 lane_settings
[0].PRE_EMPHASIS
;
441 /*max_requested.postCursor2 =
442 * link_training_setting->laneSettings[0].postCursor2;*/
444 /* Determine what the maximum of the requested settings are*/
445 for (lane
= 1; lane
< link_training_setting
->link_settings
.lane_count
;
447 if (link_training_setting
->lane_settings
[lane
].VOLTAGE_SWING
>
448 max_requested
.VOLTAGE_SWING
)
450 max_requested
.VOLTAGE_SWING
=
451 link_training_setting
->
452 lane_settings
[lane
].VOLTAGE_SWING
;
454 if (link_training_setting
->lane_settings
[lane
].PRE_EMPHASIS
>
455 max_requested
.PRE_EMPHASIS
)
456 max_requested
.PRE_EMPHASIS
=
457 link_training_setting
->
458 lane_settings
[lane
].PRE_EMPHASIS
;
461 if (link_training_setting->laneSettings[lane].postCursor2 >
462 max_requested.postCursor2)
464 max_requested.postCursor2 =
465 link_training_setting->laneSettings[lane].postCursor2;
470 /* make sure the requested settings are
471 * not higher than maximum settings*/
472 if (max_requested
.VOLTAGE_SWING
> VOLTAGE_SWING_MAX_LEVEL
)
473 max_requested
.VOLTAGE_SWING
= VOLTAGE_SWING_MAX_LEVEL
;
475 if (max_requested
.PRE_EMPHASIS
> PRE_EMPHASIS_MAX_LEVEL
)
476 max_requested
.PRE_EMPHASIS
= PRE_EMPHASIS_MAX_LEVEL
;
478 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
479 max_requested.postCursor2 = PostCursor2_MaxLevel;
482 /* make sure the pre-emphasis matches the voltage swing*/
483 if (max_requested
.PRE_EMPHASIS
>
484 get_max_pre_emphasis_for_voltage_swing(
485 max_requested
.VOLTAGE_SWING
))
486 max_requested
.PRE_EMPHASIS
=
487 get_max_pre_emphasis_for_voltage_swing(
488 max_requested
.VOLTAGE_SWING
);
491 * Post Cursor2 levels are completely independent from
492 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
493 * can only be applied to each allowable combination of voltage
494 * swing and pre-emphasis levels */
495 /* if ( max_requested.postCursor2 >
496 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
497 * max_requested.postCursor2 =
498 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
501 max_lt_setting
->link_settings
.link_rate
=
502 link_training_setting
->link_settings
.link_rate
;
503 max_lt_setting
->link_settings
.lane_count
=
504 link_training_setting
->link_settings
.lane_count
;
505 max_lt_setting
->link_settings
.link_spread
=
506 link_training_setting
->link_settings
.link_spread
;
508 for (lane
= 0; lane
<
509 link_training_setting
->link_settings
.lane_count
;
511 max_lt_setting
->lane_settings
[lane
].VOLTAGE_SWING
=
512 max_requested
.VOLTAGE_SWING
;
513 max_lt_setting
->lane_settings
[lane
].PRE_EMPHASIS
=
514 max_requested
.PRE_EMPHASIS
;
515 /*max_lt_setting->laneSettings[lane].postCursor2 =
516 * max_requested.postCursor2;
522 static void get_lane_status_and_drive_settings(
523 struct dc_link
*link
,
524 const struct link_training_settings
*link_training_setting
,
525 union lane_status
*ln_status
,
526 union lane_align_status_updated
*ln_status_updated
,
527 struct link_training_settings
*req_settings
,
530 unsigned int lane01_status_address
= DP_LANE0_1_STATUS
;
531 uint8_t lane_adjust_offset
= 4;
532 unsigned int lane01_adjust_address
;
533 uint8_t dpcd_buf
[6] = {0};
534 union lane_adjust dpcd_lane_adjust
[LANE_COUNT_DP_MAX
] = { { {0} } };
535 struct link_training_settings request_settings
= { {0} };
538 memset(req_settings
, '\0', sizeof(struct link_training_settings
));
540 if (is_repeater(link
, offset
)) {
541 lane01_status_address
=
542 DP_LANE0_1_STATUS_PHY_REPEATER1
+
543 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE
) * (offset
- 1));
544 lane_adjust_offset
= 3;
549 lane01_status_address
,
550 (uint8_t *)(dpcd_buf
),
553 for (lane
= 0; lane
<
554 (uint32_t)(link_training_setting
->link_settings
.lane_count
);
557 ln_status
[lane
].raw
=
558 get_nibble_at_index(&dpcd_buf
[0], lane
);
559 dpcd_lane_adjust
[lane
].raw
=
560 get_nibble_at_index(&dpcd_buf
[lane_adjust_offset
], lane
);
563 ln_status_updated
->raw
= dpcd_buf
[2];
565 if (is_repeater(link
, offset
)) {
566 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
567 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
570 lane01_status_address
, dpcd_buf
[0],
571 lane01_status_address
+ 1, dpcd_buf
[1]);
573 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
575 lane01_status_address
, dpcd_buf
[0],
576 lane01_status_address
+ 1, dpcd_buf
[1]);
578 lane01_adjust_address
= DP_ADJUST_REQUEST_LANE0_1
;
580 if (is_repeater(link
, offset
))
581 lane01_adjust_address
= DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1
+
582 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE
) * (offset
- 1));
584 if (is_repeater(link
, offset
)) {
585 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
586 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
589 lane01_adjust_address
,
590 dpcd_buf
[lane_adjust_offset
],
591 lane01_adjust_address
+ 1,
592 dpcd_buf
[lane_adjust_offset
+ 1]);
594 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
596 lane01_adjust_address
,
597 dpcd_buf
[lane_adjust_offset
],
598 lane01_adjust_address
+ 1,
599 dpcd_buf
[lane_adjust_offset
+ 1]);
602 /*copy to req_settings*/
603 request_settings
.link_settings
.lane_count
=
604 link_training_setting
->link_settings
.lane_count
;
605 request_settings
.link_settings
.link_rate
=
606 link_training_setting
->link_settings
.link_rate
;
607 request_settings
.link_settings
.link_spread
=
608 link_training_setting
->link_settings
.link_spread
;
610 for (lane
= 0; lane
<
611 (uint32_t)(link_training_setting
->link_settings
.lane_count
);
614 request_settings
.lane_settings
[lane
].VOLTAGE_SWING
=
615 (enum dc_voltage_swing
)(dpcd_lane_adjust
[lane
].bits
.
617 request_settings
.lane_settings
[lane
].PRE_EMPHASIS
=
618 (enum dc_pre_emphasis
)(dpcd_lane_adjust
[lane
].bits
.
622 /*Note: for postcursor2, read adjusted
623 * postcursor2 settings from*/
624 /*DpcdAddress_AdjustRequestPostCursor2 =
625 *0x020C (not implemented yet)*/
627 /* we find the maximum of the requested settings across all lanes*/
628 /* and set this maximum for all lanes*/
629 find_max_drive_settings(&request_settings
, req_settings
);
631 /* if post cursor 2 is needed in the future,
632 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
637 static void dpcd_set_lane_settings(
638 struct dc_link
*link
,
639 const struct link_training_settings
*link_training_setting
,
642 union dpcd_training_lane dpcd_lane
[LANE_COUNT_DP_MAX
] = {{{0}}};
644 unsigned int lane0_set_address
;
646 lane0_set_address
= DP_TRAINING_LANE0_SET
;
648 if (is_repeater(link
, offset
))
649 lane0_set_address
= DP_TRAINING_LANE0_SET_PHY_REPEATER1
+
650 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE
) * (offset
- 1));
652 for (lane
= 0; lane
<
653 (uint32_t)(link_training_setting
->
654 link_settings
.lane_count
);
656 dpcd_lane
[lane
].bits
.VOLTAGE_SWING_SET
=
657 (uint8_t)(link_training_setting
->
658 lane_settings
[lane
].VOLTAGE_SWING
);
659 dpcd_lane
[lane
].bits
.PRE_EMPHASIS_SET
=
660 (uint8_t)(link_training_setting
->
661 lane_settings
[lane
].PRE_EMPHASIS
);
662 dpcd_lane
[lane
].bits
.MAX_SWING_REACHED
=
663 (link_training_setting
->
664 lane_settings
[lane
].VOLTAGE_SWING
==
665 VOLTAGE_SWING_MAX_LEVEL
? 1 : 0);
666 dpcd_lane
[lane
].bits
.MAX_PRE_EMPHASIS_REACHED
=
667 (link_training_setting
->
668 lane_settings
[lane
].PRE_EMPHASIS
==
669 PRE_EMPHASIS_MAX_LEVEL
? 1 : 0);
672 core_link_write_dpcd(link
,
674 (uint8_t *)(dpcd_lane
),
675 link_training_setting
->link_settings
.lane_count
);
678 if (LTSettings.link.rate == LinkRate_High2)
680 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
681 for ( uint32_t lane = 0;
682 lane < lane_count_DPMax; lane++)
684 dpcd_lane2[lane].bits.post_cursor2_set =
685 static_cast<unsigned char>(
686 LTSettings.laneSettings[lane].postCursor2);
687 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
689 m_pDpcdAccessSrv->WriteDpcdData(
690 DpcdAddress_Lane0Set2,
691 reinterpret_cast<unsigned char*>(dpcd_lane2),
692 LTSettings.link.lanes);
696 if (is_repeater(link
, offset
)) {
697 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
698 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
702 dpcd_lane
[0].bits
.VOLTAGE_SWING_SET
,
703 dpcd_lane
[0].bits
.PRE_EMPHASIS_SET
,
704 dpcd_lane
[0].bits
.MAX_SWING_REACHED
,
705 dpcd_lane
[0].bits
.MAX_PRE_EMPHASIS_REACHED
);
708 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
711 dpcd_lane
[0].bits
.VOLTAGE_SWING_SET
,
712 dpcd_lane
[0].bits
.PRE_EMPHASIS_SET
,
713 dpcd_lane
[0].bits
.MAX_SWING_REACHED
,
714 dpcd_lane
[0].bits
.MAX_PRE_EMPHASIS_REACHED
);
716 link
->cur_lane_setting
= link_training_setting
->lane_settings
[0];
720 static bool is_max_vs_reached(
721 const struct link_training_settings
*lt_settings
)
724 for (lane
= 0; lane
<
725 (uint32_t)(lt_settings
->link_settings
.lane_count
);
727 if (lt_settings
->lane_settings
[lane
].VOLTAGE_SWING
728 == VOLTAGE_SWING_MAX_LEVEL
)
735 static bool perform_post_lt_adj_req_sequence(
736 struct dc_link
*link
,
737 struct link_training_settings
*lt_settings
)
739 enum dc_lane_count lane_count
=
740 lt_settings
->link_settings
.lane_count
;
742 uint32_t adj_req_count
;
743 uint32_t adj_req_timer
;
744 bool req_drv_setting_changed
;
747 req_drv_setting_changed
= false;
748 for (adj_req_count
= 0; adj_req_count
< POST_LT_ADJ_REQ_LIMIT
;
751 req_drv_setting_changed
= false;
753 for (adj_req_timer
= 0;
754 adj_req_timer
< POST_LT_ADJ_REQ_TIMEOUT
;
757 struct link_training_settings req_settings
;
758 union lane_status dpcd_lane_status
[LANE_COUNT_DP_MAX
];
759 union lane_align_status_updated
760 dpcd_lane_status_updated
;
762 get_lane_status_and_drive_settings(
766 &dpcd_lane_status_updated
,
770 if (dpcd_lane_status_updated
.bits
.
771 POST_LT_ADJ_REQ_IN_PROGRESS
== 0)
774 if (!is_cr_done(lane_count
, dpcd_lane_status
))
780 &dpcd_lane_status_updated
))
783 for (lane
= 0; lane
< (uint32_t)(lane_count
); lane
++) {
786 lane_settings
[lane
].VOLTAGE_SWING
!=
787 req_settings
.lane_settings
[lane
].
789 lt_settings
->lane_settings
[lane
].PRE_EMPHASIS
!=
790 req_settings
.lane_settings
[lane
].PRE_EMPHASIS
) {
792 req_drv_setting_changed
= true;
797 if (req_drv_setting_changed
) {
798 update_drive_settings(
799 lt_settings
, req_settings
);
801 dc_link_dp_set_drive_settings(link
,
809 if (!req_drv_setting_changed
) {
810 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
817 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
825 /* Only used for channel equalization */
826 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval
)
828 unsigned int aux_rd_interval_us
= 400;
830 switch (dpcd_aux_read_interval
) {
832 aux_rd_interval_us
= 400;
835 aux_rd_interval_us
= 4000;
838 aux_rd_interval_us
= 8000;
841 aux_rd_interval_us
= 16000;
847 return aux_rd_interval_us
;
850 static enum link_training_result
get_cr_failure(enum dc_lane_count ln_count
,
851 union lane_status
*dpcd_lane_status
)
853 enum link_training_result result
= LINK_TRAINING_SUCCESS
;
855 if (ln_count
>= LANE_COUNT_ONE
&& !dpcd_lane_status
[0].bits
.CR_DONE_0
)
856 result
= LINK_TRAINING_CR_FAIL_LANE0
;
857 else if (ln_count
>= LANE_COUNT_TWO
&& !dpcd_lane_status
[1].bits
.CR_DONE_0
)
858 result
= LINK_TRAINING_CR_FAIL_LANE1
;
859 else if (ln_count
>= LANE_COUNT_FOUR
&& !dpcd_lane_status
[2].bits
.CR_DONE_0
)
860 result
= LINK_TRAINING_CR_FAIL_LANE23
;
861 else if (ln_count
>= LANE_COUNT_FOUR
&& !dpcd_lane_status
[3].bits
.CR_DONE_0
)
862 result
= LINK_TRAINING_CR_FAIL_LANE23
;
866 static enum link_training_result
perform_channel_equalization_sequence(
867 struct dc_link
*link
,
868 struct link_training_settings
*lt_settings
,
871 struct link_training_settings req_settings
;
872 enum dc_dp_training_pattern tr_pattern
;
873 uint32_t retries_ch_eq
;
874 uint32_t wait_time_microsec
;
875 enum dc_lane_count lane_count
= lt_settings
->link_settings
.lane_count
;
876 union lane_align_status_updated dpcd_lane_status_updated
= { {0} };
877 union lane_status dpcd_lane_status
[LANE_COUNT_DP_MAX
] = { { {0} } };
879 /* Note: also check that TPS4 is a supported feature*/
881 tr_pattern
= lt_settings
->pattern_for_eq
;
883 if (is_repeater(link
, offset
))
884 tr_pattern
= DP_TRAINING_PATTERN_SEQUENCE_4
;
886 dp_set_hw_training_pattern(link
, tr_pattern
, offset
);
888 for (retries_ch_eq
= 0; retries_ch_eq
<= LINK_TRAINING_MAX_RETRY_COUNT
;
891 dp_set_hw_lane_settings(link
, lt_settings
, offset
);
895 /* EPR #361076 - write as a 5-byte burst,
896 * but only for the 1-st iteration
899 dpcd_set_lt_pattern_and_lane_settings(
904 dpcd_set_lane_settings(link
, lt_settings
, offset
);
906 /* 3. wait for receiver to lock-on*/
907 wait_time_microsec
= lt_settings
->eq_pattern_time
;
909 if (is_repeater(link
, offset
))
911 translate_training_aux_read_interval(
912 link
->dpcd_caps
.lttpr_caps
.aux_rd_interval
[offset
- 1]);
914 wait_for_training_aux_rd_interval(
918 /* 4. Read lane status and requested
919 * drive settings as set by the sink*/
921 get_lane_status_and_drive_settings(
925 &dpcd_lane_status_updated
,
929 /* 5. check CR done*/
930 if (!is_cr_done(lane_count
, dpcd_lane_status
))
931 return LINK_TRAINING_EQ_FAIL_CR
;
933 /* 6. check CHEQ done*/
934 if (is_ch_eq_done(lane_count
,
936 &dpcd_lane_status_updated
))
937 return LINK_TRAINING_SUCCESS
;
939 /* 7. update VS/PE/PC2 in lt_settings*/
940 update_drive_settings(lt_settings
, req_settings
);
943 return LINK_TRAINING_EQ_FAIL_EQ
;
946 #define TRAINING_AUX_RD_INTERVAL 100 //us
948 static void start_clock_recovery_pattern_early(struct dc_link
*link
,
949 struct link_training_settings
*lt_settings
,
952 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
954 dp_set_hw_training_pattern(link
, DP_TRAINING_PATTERN_SEQUENCE_1
, offset
);
955 dp_set_hw_lane_settings(link
, lt_settings
, offset
);
959 static enum link_training_result
perform_clock_recovery_sequence(
960 struct dc_link
*link
,
961 struct link_training_settings
*lt_settings
,
965 uint32_t retry_count
;
966 uint32_t wait_time_microsec
;
967 struct link_training_settings req_settings
;
968 enum dc_lane_count lane_count
= lt_settings
->link_settings
.lane_count
;
969 enum dc_dp_training_pattern tr_pattern
= DP_TRAINING_PATTERN_SEQUENCE_1
;
970 union lane_status dpcd_lane_status
[LANE_COUNT_DP_MAX
];
971 union lane_align_status_updated dpcd_lane_status_updated
;
976 if (!link
->ctx
->dc
->work_arounds
.lt_early_cr_pattern
)
977 dp_set_hw_training_pattern(link
, tr_pattern
, offset
);
979 /* najeeb - The synaptics MST hub can put the LT in
980 * infinite loop by switching the VS
982 /* between level 0 and level 1 continuously, here
983 * we try for CR lock for LinkTrainingMaxCRRetry count*/
984 while ((retries_cr
< LINK_TRAINING_MAX_RETRY_COUNT
) &&
985 (retry_count
< LINK_TRAINING_MAX_CR_RETRY
)) {
987 memset(&dpcd_lane_status
, '\0', sizeof(dpcd_lane_status
));
988 memset(&dpcd_lane_status_updated
, '\0',
989 sizeof(dpcd_lane_status_updated
));
991 /* 1. call HWSS to set lane settings*/
992 dp_set_hw_lane_settings(
997 /* 2. update DPCD of the receiver*/
999 /* EPR #361076 - write as a 5-byte burst,
1000 * but only for the 1-st iteration.*/
1001 dpcd_set_lt_pattern_and_lane_settings(
1007 dpcd_set_lane_settings(
1012 /* 3. wait receiver to lock-on*/
1013 wait_time_microsec
= lt_settings
->cr_pattern_time
;
1015 if (!link
->is_lttpr_mode_transparent
)
1016 wait_time_microsec
= TRAINING_AUX_RD_INTERVAL
;
1018 wait_for_training_aux_rd_interval(
1020 wait_time_microsec
);
1022 /* 4. Read lane status and requested drive
1023 * settings as set by the sink
1025 get_lane_status_and_drive_settings(
1029 &dpcd_lane_status_updated
,
1033 /* 5. check CR done*/
1034 if (is_cr_done(lane_count
, dpcd_lane_status
))
1035 return LINK_TRAINING_SUCCESS
;
1037 /* 6. max VS reached*/
1038 if (is_max_vs_reached(lt_settings
))
1041 /* 7. same voltage*/
1042 /* Note: VS same for all lanes,
1043 * so comparing first lane is sufficient*/
1044 if (lt_settings
->lane_settings
[0].VOLTAGE_SWING
==
1045 req_settings
.lane_settings
[0].VOLTAGE_SWING
)
1050 /* 8. update VS/PE/PC2 in lt_settings*/
1051 update_drive_settings(lt_settings
, req_settings
);
1056 if (retry_count
>= LINK_TRAINING_MAX_CR_RETRY
) {
1058 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1060 LINK_TRAINING_MAX_CR_RETRY
);
1064 return get_cr_failure(lane_count
, dpcd_lane_status
);
1067 static inline enum link_training_result
perform_link_training_int(
1068 struct dc_link
*link
,
1069 struct link_training_settings
*lt_settings
,
1070 enum link_training_result status
)
1072 union lane_count_set lane_count_set
= { {0} };
1073 union dpcd_training_pattern dpcd_pattern
= { {0} };
1075 /* 3. set training not in progress*/
1076 dpcd_pattern
.v1_4
.TRAINING_PATTERN_SET
= DPCD_TRAINING_PATTERN_VIDEOIDLE
;
1077 dpcd_set_training_pattern(link
, dpcd_pattern
);
1079 /* 4. mainlink output idle pattern*/
1080 dp_set_hw_test_pattern(link
, DP_TEST_PATTERN_VIDEO_MODE
, NULL
, 0);
1083 * 5. post training adjust if required
1084 * If the upstream DPTX and downstream DPRX both support TPS4,
1085 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1087 if (link
->dpcd_caps
.max_ln_count
.bits
.POST_LT_ADJ_REQ_SUPPORTED
!= 1 ||
1088 get_supported_tp(link
) == DP_TRAINING_PATTERN_SEQUENCE_4
)
1091 if (status
== LINK_TRAINING_SUCCESS
&&
1092 perform_post_lt_adj_req_sequence(link
, lt_settings
) == false)
1093 status
= LINK_TRAINING_LQA_FAIL
;
1095 lane_count_set
.bits
.LANE_COUNT_SET
= lt_settings
->link_settings
.lane_count
;
1096 lane_count_set
.bits
.ENHANCED_FRAMING
= lt_settings
->enhanced_framing
;
1097 lane_count_set
.bits
.POST_LT_ADJ_REQ_GRANTED
= 0;
1099 core_link_write_dpcd(
1102 &lane_count_set
.raw
,
1103 sizeof(lane_count_set
));
1108 static void initialize_training_settings(
1109 struct dc_link
*link
,
1110 const struct dc_link_settings
*link_setting
,
1111 const struct dc_link_training_overrides
*overrides
,
1112 struct link_training_settings
*lt_settings
)
1116 memset(lt_settings
, '\0', sizeof(struct link_training_settings
));
1118 /* Initialize link settings */
1119 lt_settings
->link_settings
.use_link_rate_set
= link_setting
->use_link_rate_set
;
1120 lt_settings
->link_settings
.link_rate_set
= link_setting
->link_rate_set
;
1122 if (link
->preferred_link_setting
.link_rate
!= LINK_RATE_UNKNOWN
)
1123 lt_settings
->link_settings
.link_rate
= link
->preferred_link_setting
.link_rate
;
1125 lt_settings
->link_settings
.link_rate
= link_setting
->link_rate
;
1127 if (link
->preferred_link_setting
.lane_count
!= LANE_COUNT_UNKNOWN
)
1128 lt_settings
->link_settings
.lane_count
= link
->preferred_link_setting
.lane_count
;
1130 lt_settings
->link_settings
.lane_count
= link_setting
->lane_count
;
1132 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1134 /* TODO hard coded to SS for now
1135 * lt_settings.link_settings.link_spread =
1136 * dal_display_path_is_ss_supported(
1137 * path_mode->display_path) ?
1138 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1139 * LINK_SPREAD_DISABLED;
1141 /* Initialize link spread */
1142 if (link
->dp_ss_off
)
1143 lt_settings
->link_settings
.link_spread
= LINK_SPREAD_DISABLED
;
1144 else if (overrides
->downspread
!= NULL
)
1145 lt_settings
->link_settings
.link_spread
1146 = *overrides
->downspread
1147 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1148 : LINK_SPREAD_DISABLED
;
1150 lt_settings
->link_settings
.link_spread
= LINK_SPREAD_05_DOWNSPREAD_30KHZ
;
1152 /* Initialize lane settings overrides */
1153 if (overrides
->voltage_swing
!= NULL
)
1154 lt_settings
->voltage_swing
= overrides
->voltage_swing
;
1156 if (overrides
->pre_emphasis
!= NULL
)
1157 lt_settings
->pre_emphasis
= overrides
->pre_emphasis
;
1159 if (overrides
->post_cursor2
!= NULL
)
1160 lt_settings
->post_cursor2
= overrides
->post_cursor2
;
1162 /* Initialize lane settings (VS/PE/PC2) */
1163 for (lane
= 0; lane
< LANE_COUNT_DP_MAX
; lane
++) {
1164 lt_settings
->lane_settings
[lane
].VOLTAGE_SWING
=
1165 lt_settings
->voltage_swing
!= NULL
?
1166 *lt_settings
->voltage_swing
:
1167 VOLTAGE_SWING_LEVEL0
;
1168 lt_settings
->lane_settings
[lane
].PRE_EMPHASIS
=
1169 lt_settings
->pre_emphasis
!= NULL
?
1170 *lt_settings
->pre_emphasis
1171 : PRE_EMPHASIS_DISABLED
;
1172 lt_settings
->lane_settings
[lane
].POST_CURSOR2
=
1173 lt_settings
->post_cursor2
!= NULL
?
1174 *lt_settings
->post_cursor2
1175 : POST_CURSOR2_DISABLED
;
1178 /* Initialize training timings */
1179 if (overrides
->cr_pattern_time
!= NULL
)
1180 lt_settings
->cr_pattern_time
= *overrides
->cr_pattern_time
;
1182 lt_settings
->cr_pattern_time
= get_training_aux_rd_interval(link
, 100);
1184 if (overrides
->eq_pattern_time
!= NULL
)
1185 lt_settings
->eq_pattern_time
= *overrides
->eq_pattern_time
;
1187 lt_settings
->eq_pattern_time
= get_training_aux_rd_interval(link
, 400);
1189 if (overrides
->pattern_for_eq
!= NULL
)
1190 lt_settings
->pattern_for_eq
= *overrides
->pattern_for_eq
;
1192 lt_settings
->pattern_for_eq
= get_supported_tp(link
);
1194 if (overrides
->enhanced_framing
!= NULL
)
1195 lt_settings
->enhanced_framing
= *overrides
->enhanced_framing
;
1197 lt_settings
->enhanced_framing
= 1;
1200 static uint8_t convert_to_count(uint8_t lttpr_repeater_count
)
1202 switch (lttpr_repeater_count
) {
1203 case 0x80: // 1 lttpr repeater
1205 case 0x40: // 2 lttpr repeaters
1207 case 0x20: // 3 lttpr repeaters
1209 case 0x10: // 4 lttpr repeaters
1211 case 0x08: // 5 lttpr repeaters
1213 case 0x04: // 6 lttpr repeaters
1215 case 0x02: // 7 lttpr repeaters
1217 case 0x01: // 8 lttpr repeaters
1222 return 0; // invalid value
1225 static void configure_lttpr_mode(struct dc_link
*link
)
1227 /* aux timeout is already set to extended */
1228 /* RESET/SET lttpr mode to enable non transparent mode */
1229 uint8_t repeater_cnt
;
1230 uint32_t aux_interval_address
;
1231 uint8_t repeater_id
;
1232 enum dc_status result
= DC_ERROR_UNEXPECTED
;
1233 uint8_t repeater_mode
= DP_PHY_REPEATER_MODE_TRANSPARENT
;
1235 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__
);
1236 result
= core_link_write_dpcd(link
,
1237 DP_PHY_REPEATER_MODE
,
1238 (uint8_t *)&repeater_mode
,
1239 sizeof(repeater_mode
));
1241 if (result
== DC_OK
) {
1242 link
->dpcd_caps
.lttpr_caps
.mode
= repeater_mode
;
1245 if (!link
->is_lttpr_mode_transparent
) {
1247 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__
);
1249 repeater_mode
= DP_PHY_REPEATER_MODE_NON_TRANSPARENT
;
1250 result
= core_link_write_dpcd(link
,
1251 DP_PHY_REPEATER_MODE
,
1252 (uint8_t *)&repeater_mode
,
1253 sizeof(repeater_mode
));
1255 if (result
== DC_OK
) {
1256 link
->dpcd_caps
.lttpr_caps
.mode
= repeater_mode
;
1259 repeater_cnt
= convert_to_count(link
->dpcd_caps
.lttpr_caps
.phy_repeater_cnt
);
1260 for (repeater_id
= repeater_cnt
; repeater_id
> 0; repeater_id
--) {
1261 aux_interval_address
= DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
+
1262 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE
) * (repeater_id
- 1));
1263 core_link_read_dpcd(
1265 aux_interval_address
,
1266 (uint8_t *)&link
->dpcd_caps
.lttpr_caps
.aux_rd_interval
[repeater_id
- 1],
1267 sizeof(link
->dpcd_caps
.lttpr_caps
.aux_rd_interval
[repeater_id
- 1]));
1268 link
->dpcd_caps
.lttpr_caps
.aux_rd_interval
[repeater_id
- 1] &= 0x7F;
1273 static void repeater_training_done(struct dc_link
*link
, uint32_t offset
)
1275 union dpcd_training_pattern dpcd_pattern
= { {0} };
1277 const uint32_t dpcd_base_lt_offset
=
1278 DP_TRAINING_PATTERN_SET_PHY_REPEATER1
+
1279 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE
) * (offset
- 1));
1280 /* Set training not in progress*/
1281 dpcd_pattern
.v1_4
.TRAINING_PATTERN_SET
= DPCD_TRAINING_PATTERN_VIDEOIDLE
;
1283 core_link_write_dpcd(
1285 dpcd_base_lt_offset
,
1289 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1292 dpcd_base_lt_offset
,
1293 dpcd_pattern
.v1_4
.TRAINING_PATTERN_SET
);
1296 static void print_status_message(
1297 struct dc_link
*link
,
1298 const struct link_training_settings
*lt_settings
,
1299 enum link_training_result status
)
1301 char *link_rate
= "Unknown";
1302 char *lt_result
= "Unknown";
1303 char *lt_spread
= "Disabled";
1305 switch (lt_settings
->link_settings
.link_rate
) {
1309 case LINK_RATE_HIGH
:
1312 case LINK_RATE_HIGH2
:
1315 case LINK_RATE_RBR2
:
1318 case LINK_RATE_HIGH3
:
1326 case LINK_TRAINING_SUCCESS
:
1329 case LINK_TRAINING_CR_FAIL_LANE0
:
1330 lt_result
= "CR failed lane0";
1332 case LINK_TRAINING_CR_FAIL_LANE1
:
1333 lt_result
= "CR failed lane1";
1335 case LINK_TRAINING_CR_FAIL_LANE23
:
1336 lt_result
= "CR failed lane23";
1338 case LINK_TRAINING_EQ_FAIL_CR
:
1339 lt_result
= "CR failed in EQ";
1341 case LINK_TRAINING_EQ_FAIL_EQ
:
1342 lt_result
= "EQ failed";
1344 case LINK_TRAINING_LQA_FAIL
:
1345 lt_result
= "LQA failed";
1351 switch (lt_settings
->link_settings
.link_spread
) {
1352 case LINK_SPREAD_DISABLED
:
1353 lt_spread
= "Disabled";
1355 case LINK_SPREAD_05_DOWNSPREAD_30KHZ
:
1356 lt_spread
= "0.5% 30KHz";
1358 case LINK_SPREAD_05_DOWNSPREAD_33KHZ
:
1359 lt_spread
= "0.5% 33KHz";
1365 /* Connectivity log: link training */
1366 CONN_MSG_LT(link
, "%sx%d %s VS=%d, PE=%d, DS=%s",
1368 lt_settings
->link_settings
.lane_count
,
1370 lt_settings
->lane_settings
[0].VOLTAGE_SWING
,
1371 lt_settings
->lane_settings
[0].PRE_EMPHASIS
,
1375 void dc_link_dp_set_drive_settings(
1376 struct dc_link
*link
,
1377 struct link_training_settings
*lt_settings
)
1379 /* program ASIC PHY settings*/
1380 dp_set_hw_lane_settings(link
, lt_settings
, DPRX
);
1382 /* Notify DP sink the PHY settings from source */
1383 dpcd_set_lane_settings(link
, lt_settings
, DPRX
);
1386 bool dc_link_dp_perform_link_training_skip_aux(
1387 struct dc_link
*link
,
1388 const struct dc_link_settings
*link_setting
)
1390 struct link_training_settings lt_settings
;
1391 enum dc_dp_training_pattern pattern_for_cr
= DP_TRAINING_PATTERN_SEQUENCE_1
;
1393 initialize_training_settings(
1396 &link
->preferred_training_settings
,
1399 /* 1. Perform_clock_recovery_sequence. */
1401 /* transmit training pattern for clock recovery */
1402 dp_set_hw_training_pattern(link
, pattern_for_cr
, DPRX
);
1404 /* call HWSS to set lane settings*/
1405 dp_set_hw_lane_settings(link
, <_settings
, DPRX
);
1407 /* wait receiver to lock-on*/
1408 wait_for_training_aux_rd_interval(link
, lt_settings
.cr_pattern_time
);
1410 /* 2. Perform_channel_equalization_sequence. */
1412 /* transmit training pattern for channel equalization. */
1413 dp_set_hw_training_pattern(link
, lt_settings
.pattern_for_eq
, DPRX
);
1415 /* call HWSS to set lane settings*/
1416 dp_set_hw_lane_settings(link
, <_settings
, DPRX
);
1418 /* wait receiver to lock-on. */
1419 wait_for_training_aux_rd_interval(link
, lt_settings
.eq_pattern_time
);
1421 /* 3. Perform_link_training_int. */
1423 /* Mainlink output idle pattern. */
1424 dp_set_hw_test_pattern(link
, DP_TEST_PATTERN_VIDEO_MODE
, NULL
, 0);
1426 print_status_message(link
, <_settings
, LINK_TRAINING_SUCCESS
);
1431 enum link_training_result
dc_link_dp_perform_link_training(
1432 struct dc_link
*link
,
1433 const struct dc_link_settings
*link_setting
,
1434 bool skip_video_pattern
)
1436 enum link_training_result status
= LINK_TRAINING_SUCCESS
;
1437 struct link_training_settings lt_settings
;
1440 uint8_t repeater_cnt
;
1441 uint8_t repeater_id
;
1443 initialize_training_settings(
1446 &link
->preferred_training_settings
,
1449 /* Configure lttpr mode */
1450 if (!link
->is_lttpr_mode_transparent
)
1451 configure_lttpr_mode(link
);
1453 if (link
->ctx
->dc
->work_arounds
.lt_early_cr_pattern
)
1454 start_clock_recovery_pattern_early(link
, <_settings
, DPRX
);
1456 /* 1. set link rate, lane count and spread. */
1457 dpcd_set_link_settings(link
, <_settings
);
1459 if (link
->preferred_training_settings
.fec_enable
!= NULL
)
1460 fec_enable
= *link
->preferred_training_settings
.fec_enable
;
1464 dp_set_fec_ready(link
, fec_enable
);
1466 if (!link
->is_lttpr_mode_transparent
) {
1468 /* 2. perform link training (set link training done
1469 * to false is done as well)
1471 repeater_cnt
= convert_to_count(link
->dpcd_caps
.lttpr_caps
.phy_repeater_cnt
);
1473 for (repeater_id
= repeater_cnt
; (repeater_id
> 0 && status
== LINK_TRAINING_SUCCESS
);
1475 status
= perform_clock_recovery_sequence(link
, <_settings
, repeater_id
);
1477 if (status
!= LINK_TRAINING_SUCCESS
)
1480 status
= perform_channel_equalization_sequence(link
,
1484 if (status
!= LINK_TRAINING_SUCCESS
)
1487 repeater_training_done(link
, repeater_id
);
1491 if (status
== LINK_TRAINING_SUCCESS
) {
1492 status
= perform_clock_recovery_sequence(link
, <_settings
, DPRX
);
1493 if (status
== LINK_TRAINING_SUCCESS
) {
1494 status
= perform_channel_equalization_sequence(link
,
1500 if ((status
== LINK_TRAINING_SUCCESS
) || !skip_video_pattern
) {
1501 status
= perform_link_training_int(link
,
1506 /* 6. print status message*/
1507 print_status_message(link
, <_settings
, status
);
1509 if (status
!= LINK_TRAINING_SUCCESS
)
1510 link
->ctx
->dc
->debug_data
.ltFailCount
++;
1515 bool perform_link_training_with_retries(
1516 const struct dc_link_settings
*link_setting
,
1517 bool skip_video_pattern
,
1519 struct pipe_ctx
*pipe_ctx
,
1520 enum signal_type signal
)
1523 uint8_t delay_between_attempts
= LINK_TRAINING_RETRY_DELAY
;
1524 struct dc_stream_state
*stream
= pipe_ctx
->stream
;
1525 struct dc_link
*link
= stream
->link
;
1526 enum dp_panel_mode panel_mode
= dp_get_panel_mode(link
);
1528 for (j
= 0; j
< attempts
; ++j
) {
1533 pipe_ctx
->clock_source
->id
,
1536 if (stream
->sink_patches
.dppowerup_delay
> 0) {
1537 int delay_dp_power_up_in_ms
= stream
->sink_patches
.dppowerup_delay
;
1539 msleep(delay_dp_power_up_in_ms
);
1542 dp_set_panel_mode(link
, panel_mode
);
1544 /* We need to do this before the link training to ensure the idle pattern in SST
1545 * mode will be sent right after the link training
1547 link
->link_enc
->funcs
->connect_dig_be_to_fe(link
->link_enc
,
1548 pipe_ctx
->stream_res
.stream_enc
->id
, true);
1550 if (link
->aux_access_disabled
) {
1551 dc_link_dp_perform_link_training_skip_aux(link
, link_setting
);
1553 } else if (dc_link_dp_perform_link_training(
1556 skip_video_pattern
) == LINK_TRAINING_SUCCESS
)
1559 /* latest link training still fail, skip delay and keep PHY on
1561 if (j
== (attempts
- 1))
1564 dp_disable_link_phy(link
, signal
);
1566 msleep(delay_between_attempts
);
1568 delay_between_attempts
+= LINK_TRAINING_RETRY_DELAY
;
1574 static enum clock_source_id
get_clock_source_id(struct dc_link
*link
)
1576 enum clock_source_id dp_cs_id
= CLOCK_SOURCE_ID_UNDEFINED
;
1577 struct clock_source
*dp_cs
= link
->dc
->res_pool
->dp_clock_source
;
1579 if (dp_cs
!= NULL
) {
1580 dp_cs_id
= dp_cs
->id
;
1583 * dp clock source is not initialized for some reason.
1584 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1592 static void set_dp_mst_mode(struct dc_link
*link
, bool mst_enable
)
1594 if (mst_enable
== false &&
1595 link
->type
== dc_connection_mst_branch
) {
1596 /* Disable MST on link. Use only local sink. */
1597 dp_disable_link_phy_mst(link
, link
->connector_signal
);
1599 link
->type
= dc_connection_single
;
1600 link
->local_sink
= link
->remote_sinks
[0];
1601 link
->local_sink
->sink_signal
= SIGNAL_TYPE_DISPLAY_PORT
;
1602 } else if (mst_enable
== true &&
1603 link
->type
== dc_connection_single
&&
1604 link
->remote_sinks
[0] != NULL
) {
1605 /* Re-enable MST on link. */
1606 dp_disable_link_phy(link
, link
->connector_signal
);
1607 dp_enable_mst_on_sink(link
, true);
1609 link
->type
= dc_connection_mst_branch
;
1610 link
->local_sink
->sink_signal
= SIGNAL_TYPE_DISPLAY_PORT_MST
;
1614 bool dc_link_dp_sync_lt_begin(struct dc_link
*link
)
1616 /* Begin Sync LT. During this time,
1617 * DPCD:600h must not be powered down.
1619 link
->sync_lt_in_progress
= true;
1621 /*Clear any existing preferred settings.*/
1622 memset(&link
->preferred_training_settings
, 0,
1623 sizeof(struct dc_link_training_overrides
));
1624 memset(&link
->preferred_link_setting
, 0,
1625 sizeof(struct dc_link_settings
));
1630 enum link_training_result
dc_link_dp_sync_lt_attempt(
1631 struct dc_link
*link
,
1632 struct dc_link_settings
*link_settings
,
1633 struct dc_link_training_overrides
*lt_overrides
)
1635 struct link_training_settings lt_settings
;
1636 enum link_training_result lt_status
= LINK_TRAINING_SUCCESS
;
1637 enum dp_panel_mode panel_mode
= DP_PANEL_MODE_DEFAULT
;
1638 enum clock_source_id dp_cs_id
= CLOCK_SOURCE_ID_EXTERNAL
;
1639 bool fec_enable
= false;
1641 initialize_training_settings(
1647 /* Setup MST Mode */
1648 if (lt_overrides
->mst_enable
)
1649 set_dp_mst_mode(link
, *lt_overrides
->mst_enable
);
1652 dp_disable_link_phy(link
, link
->connector_signal
);
1655 dp_cs_id
= get_clock_source_id(link
);
1656 dp_enable_link_phy(link
, link
->connector_signal
,
1657 dp_cs_id
, link_settings
);
1659 /* Set FEC enable */
1660 fec_enable
= lt_overrides
->fec_enable
&& *lt_overrides
->fec_enable
;
1661 dp_set_fec_ready(link
, fec_enable
);
1663 if (lt_overrides
->alternate_scrambler_reset
) {
1664 if (*lt_overrides
->alternate_scrambler_reset
)
1665 panel_mode
= DP_PANEL_MODE_EDP
;
1667 panel_mode
= DP_PANEL_MODE_DEFAULT
;
1669 panel_mode
= dp_get_panel_mode(link
);
1671 dp_set_panel_mode(link
, panel_mode
);
1673 /* Attempt to train with given link training settings */
1674 if (link
->ctx
->dc
->work_arounds
.lt_early_cr_pattern
)
1675 start_clock_recovery_pattern_early(link
, <_settings
, DPRX
);
1677 /* Set link rate, lane count and spread. */
1678 dpcd_set_link_settings(link
, <_settings
);
1680 /* 2. perform link training (set link training done
1681 * to false is done as well)
1683 lt_status
= perform_clock_recovery_sequence(link
, <_settings
, DPRX
);
1684 if (lt_status
== LINK_TRAINING_SUCCESS
) {
1685 lt_status
= perform_channel_equalization_sequence(link
,
1690 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1691 /* 4. print status message*/
1692 print_status_message(link
, <_settings
, lt_status
);
1697 bool dc_link_dp_sync_lt_end(struct dc_link
*link
, bool link_down
)
1699 /* If input parameter is set, shut down phy.
1700 * Still shouldn't turn off dp_receiver (DPCD:600h)
1702 if (link_down
== true) {
1703 dp_disable_link_phy(link
, link
->connector_signal
);
1704 dp_set_fec_ready(link
, false);
1707 link
->sync_lt_in_progress
= false;
1711 static struct dc_link_settings
get_max_link_cap(struct dc_link
*link
)
1713 /* Set Default link settings */
1714 struct dc_link_settings max_link_cap
= {LANE_COUNT_FOUR
, LINK_RATE_HIGH
,
1715 LINK_SPREAD_05_DOWNSPREAD_30KHZ
, false, 0};
1717 /* Higher link settings based on feature supported */
1718 if (link
->link_enc
->features
.flags
.bits
.IS_HBR2_CAPABLE
)
1719 max_link_cap
.link_rate
= LINK_RATE_HIGH2
;
1721 if (link
->link_enc
->features
.flags
.bits
.IS_HBR3_CAPABLE
)
1722 max_link_cap
.link_rate
= LINK_RATE_HIGH3
;
1724 if (link
->link_enc
->funcs
->get_max_link_cap
)
1725 link
->link_enc
->funcs
->get_max_link_cap(link
->link_enc
, &max_link_cap
);
1727 /* Lower link settings based on sink's link cap */
1728 if (link
->reported_link_cap
.lane_count
< max_link_cap
.lane_count
)
1729 max_link_cap
.lane_count
=
1730 link
->reported_link_cap
.lane_count
;
1731 if (link
->reported_link_cap
.link_rate
< max_link_cap
.link_rate
)
1732 max_link_cap
.link_rate
=
1733 link
->reported_link_cap
.link_rate
;
1734 if (link
->reported_link_cap
.link_spread
<
1735 max_link_cap
.link_spread
)
1736 max_link_cap
.link_spread
=
1737 link
->reported_link_cap
.link_spread
;
1739 * account for lttpr repeaters cap
1740 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1742 if (!link
->is_lttpr_mode_transparent
) {
1743 if (link
->dpcd_caps
.lttpr_caps
.max_lane_count
< max_link_cap
.lane_count
)
1744 max_link_cap
.lane_count
= link
->dpcd_caps
.lttpr_caps
.max_lane_count
;
1746 if (link
->dpcd_caps
.lttpr_caps
.max_link_rate
< max_link_cap
.link_rate
)
1747 max_link_cap
.link_rate
= link
->dpcd_caps
.lttpr_caps
.max_link_rate
;
1749 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
1751 max_link_cap
.lane_count
,
1752 max_link_cap
.link_rate
);
1754 return max_link_cap
;
1757 static enum dc_status
read_hpd_rx_irq_data(
1758 struct dc_link
*link
,
1759 union hpd_irq_data
*irq_data
)
1761 static enum dc_status retval
;
1763 /* The HW reads 16 bytes from 200h on HPD,
1764 * but if we get an AUX_DEFER, the HW cannot retry
1765 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1766 * fail, so we now explicitly read 6 bytes which is
1767 * the req from the above mentioned test cases.
1769 * For DP 1.4 we need to read those from 2002h range.
1771 if (link
->dpcd_caps
.dpcd_rev
.raw
< DPCD_REV_14
)
1772 retval
= core_link_read_dpcd(
1776 sizeof(union hpd_irq_data
));
1778 /* Read 14 bytes in a single read and then copy only the required fields.
1779 * This is more efficient than doing it in two separate AUX reads. */
1781 uint8_t tmp
[DP_SINK_STATUS_ESI
- DP_SINK_COUNT_ESI
+ 1];
1783 retval
= core_link_read_dpcd(
1789 if (retval
!= DC_OK
)
1792 irq_data
->bytes
.sink_cnt
.raw
= tmp
[DP_SINK_COUNT_ESI
- DP_SINK_COUNT_ESI
];
1793 irq_data
->bytes
.device_service_irq
.raw
= tmp
[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0
- DP_SINK_COUNT_ESI
];
1794 irq_data
->bytes
.lane01_status
.raw
= tmp
[DP_LANE0_1_STATUS_ESI
- DP_SINK_COUNT_ESI
];
1795 irq_data
->bytes
.lane23_status
.raw
= tmp
[DP_LANE2_3_STATUS_ESI
- DP_SINK_COUNT_ESI
];
1796 irq_data
->bytes
.lane_status_updated
.raw
= tmp
[DP_LANE_ALIGN_STATUS_UPDATED_ESI
- DP_SINK_COUNT_ESI
];
1797 irq_data
->bytes
.sink_status
.raw
= tmp
[DP_SINK_STATUS_ESI
- DP_SINK_COUNT_ESI
];
1803 static bool hpd_rx_irq_check_link_loss_status(
1804 struct dc_link
*link
,
1805 union hpd_irq_data
*hpd_irq_dpcd_data
)
1807 uint8_t irq_reg_rx_power_state
= 0;
1808 enum dc_status dpcd_result
= DC_ERROR_UNEXPECTED
;
1809 union lane_status lane_status
;
1811 bool sink_status_changed
;
1814 sink_status_changed
= false;
1815 return_code
= false;
1817 if (link
->cur_link_settings
.lane_count
== 0)
1820 /*1. Check that Link Status changed, before re-training.*/
1822 /*parse lane status*/
1823 for (lane
= 0; lane
< link
->cur_link_settings
.lane_count
; lane
++) {
1824 /* check status of lanes 0,1
1825 * changed DpcdAddress_Lane01Status (0x202)
1827 lane_status
.raw
= get_nibble_at_index(
1828 &hpd_irq_dpcd_data
->bytes
.lane01_status
.raw
,
1831 if (!lane_status
.bits
.CHANNEL_EQ_DONE_0
||
1832 !lane_status
.bits
.CR_DONE_0
||
1833 !lane_status
.bits
.SYMBOL_LOCKED_0
) {
1834 /* if one of the channel equalization, clock
1835 * recovery or symbol lock is dropped
1836 * consider it as (link has been
1837 * dropped) dp sink status has changed
1839 sink_status_changed
= true;
1844 /* Check interlane align.*/
1845 if (sink_status_changed
||
1846 !hpd_irq_dpcd_data
->bytes
.lane_status_updated
.bits
.INTERLANE_ALIGN_DONE
) {
1848 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__
);
1852 /*2. Check that we can handle interrupt: Not in FS DOS,
1853 * Not in "Display Timeout" state, Link is trained.
1855 dpcd_result
= core_link_read_dpcd(link
,
1857 &irq_reg_rx_power_state
,
1858 sizeof(irq_reg_rx_power_state
));
1860 if (dpcd_result
!= DC_OK
) {
1861 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1864 if (irq_reg_rx_power_state
!= DP_SET_POWER_D0
)
1865 return_code
= false;
1872 bool dp_verify_link_cap(
1873 struct dc_link
*link
,
1874 struct dc_link_settings
*known_limit_link_setting
,
1877 struct dc_link_settings max_link_cap
= {0};
1878 struct dc_link_settings cur_link_setting
= {0};
1879 struct dc_link_settings
*cur
= &cur_link_setting
;
1880 struct dc_link_settings initial_link_settings
= {0};
1882 bool skip_link_training
;
1883 bool skip_video_pattern
;
1884 enum clock_source_id dp_cs_id
= CLOCK_SOURCE_ID_EXTERNAL
;
1885 enum link_training_result status
;
1886 union hpd_irq_data irq_data
;
1888 if (link
->dc
->debug
.skip_detection_link_training
) {
1889 link
->verified_link_cap
= *known_limit_link_setting
;
1893 memset(&irq_data
, 0, sizeof(irq_data
));
1895 skip_link_training
= false;
1897 max_link_cap
= get_max_link_cap(link
);
1899 /* Grant extended timeout request */
1900 if (!link
->is_lttpr_mode_transparent
&& link
->dpcd_caps
.lttpr_caps
.max_ext_timeout
> 0) {
1901 uint8_t grant
= link
->dpcd_caps
.lttpr_caps
.max_ext_timeout
& 0x80;
1903 core_link_write_dpcd(link
, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT
, &grant
, sizeof(grant
));
1906 /* TODO implement override and monitor patch later */
1908 /* try to train the link from high to low to
1909 * find the physical link capability
1911 /* disable PHY done possible by BIOS, will be done by driver itself */
1912 dp_disable_link_phy(link
, link
->connector_signal
);
1914 dp_cs_id
= get_clock_source_id(link
);
1916 /* link training starts with the maximum common settings
1917 * supported by both sink and ASIC.
1919 initial_link_settings
= get_common_supported_link_settings(
1920 *known_limit_link_setting
,
1922 cur_link_setting
= initial_link_settings
;
1924 /* Temporary Renoir-specific workaround for SWDEV-215184;
1925 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
1926 * so add extra cycle of enabling and disabling the PHY before first link training.
1928 if (link
->link_enc
->features
.flags
.bits
.DP_IS_USB_C
&&
1929 link
->dc
->debug
.usbc_combo_phy_reset_wa
) {
1930 dp_enable_link_phy(link
, link
->connector_signal
, dp_cs_id
, cur
);
1931 dp_disable_link_phy(link
, link
->connector_signal
);
1935 skip_video_pattern
= true;
1937 if (cur
->link_rate
== LINK_RATE_LOW
)
1938 skip_video_pattern
= false;
1942 link
->connector_signal
,
1947 if (skip_link_training
)
1950 status
= dc_link_dp_perform_link_training(
1953 skip_video_pattern
);
1954 if (status
== LINK_TRAINING_SUCCESS
)
1961 link
->verified_link_cap
= *cur
;
1963 if (read_hpd_rx_irq_data(link
, &irq_data
) == DC_OK
)
1964 if (hpd_rx_irq_check_link_loss_status(
1969 /* always disable the link before trying another
1970 * setting or before returning we'll enable it later
1971 * based on the actual mode we're driving
1973 dp_disable_link_phy(link
, link
->connector_signal
);
1974 } while (!success
&& decide_fallback_link_setting(
1975 initial_link_settings
, cur
, status
));
1977 /* Link Training failed for all Link Settings
1978 * (Lane Count is still unknown)
1981 /* If all LT fails for all settings,
1982 * set verified = failed safe (1 lane low)
1984 link
->verified_link_cap
.lane_count
= LANE_COUNT_ONE
;
1985 link
->verified_link_cap
.link_rate
= LINK_RATE_LOW
;
1987 link
->verified_link_cap
.link_spread
=
1988 LINK_SPREAD_DISABLED
;
1995 bool dp_verify_link_cap_with_retries(
1996 struct dc_link
*link
,
1997 struct dc_link_settings
*known_limit_link_setting
,
2001 bool success
= false;
2003 for (i
= 0; i
< attempts
; i
++) {
2005 enum dc_connection_type type
= dc_connection_none
;
2007 memset(&link
->verified_link_cap
, 0,
2008 sizeof(struct dc_link_settings
));
2009 if (!dc_link_detect_sink(link
, &type
) || type
== dc_connection_none
) {
2010 link
->verified_link_cap
.lane_count
= LANE_COUNT_ONE
;
2011 link
->verified_link_cap
.link_rate
= LINK_RATE_LOW
;
2012 link
->verified_link_cap
.link_spread
= LINK_SPREAD_DISABLED
;
2014 } else if (dp_verify_link_cap(link
,
2015 &link
->reported_link_cap
,
2016 &fail_count
) && fail_count
== 0) {
2025 bool dp_verify_mst_link_cap(
2026 struct dc_link
*link
)
2028 struct dc_link_settings max_link_cap
= {0};
2030 max_link_cap
= get_max_link_cap(link
);
2031 link
->verified_link_cap
= get_common_supported_link_settings(
2032 link
->reported_link_cap
,
2038 static struct dc_link_settings
get_common_supported_link_settings(
2039 struct dc_link_settings link_setting_a
,
2040 struct dc_link_settings link_setting_b
)
2042 struct dc_link_settings link_settings
= {0};
2044 link_settings
.lane_count
=
2045 (link_setting_a
.lane_count
<=
2046 link_setting_b
.lane_count
) ?
2047 link_setting_a
.lane_count
:
2048 link_setting_b
.lane_count
;
2049 link_settings
.link_rate
=
2050 (link_setting_a
.link_rate
<=
2051 link_setting_b
.link_rate
) ?
2052 link_setting_a
.link_rate
:
2053 link_setting_b
.link_rate
;
2054 link_settings
.link_spread
= LINK_SPREAD_DISABLED
;
2056 /* in DP compliance test, DPR-120 may have
2057 * a random value in its MAX_LINK_BW dpcd field.
2058 * We map it to the maximum supported link rate that
2059 * is smaller than MAX_LINK_BW in this case.
2061 if (link_settings
.link_rate
> LINK_RATE_HIGH3
) {
2062 link_settings
.link_rate
= LINK_RATE_HIGH3
;
2063 } else if (link_settings
.link_rate
< LINK_RATE_HIGH3
2064 && link_settings
.link_rate
> LINK_RATE_HIGH2
) {
2065 link_settings
.link_rate
= LINK_RATE_HIGH2
;
2066 } else if (link_settings
.link_rate
< LINK_RATE_HIGH2
2067 && link_settings
.link_rate
> LINK_RATE_HIGH
) {
2068 link_settings
.link_rate
= LINK_RATE_HIGH
;
2069 } else if (link_settings
.link_rate
< LINK_RATE_HIGH
2070 && link_settings
.link_rate
> LINK_RATE_LOW
) {
2071 link_settings
.link_rate
= LINK_RATE_LOW
;
2072 } else if (link_settings
.link_rate
< LINK_RATE_LOW
) {
2073 link_settings
.link_rate
= LINK_RATE_UNKNOWN
;
2076 return link_settings
;
2079 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count
)
2081 return lane_count
<= LANE_COUNT_ONE
;
2084 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate
)
2086 return link_rate
<= LINK_RATE_LOW
;
2089 static enum dc_lane_count
reduce_lane_count(enum dc_lane_count lane_count
)
2091 switch (lane_count
) {
2092 case LANE_COUNT_FOUR
:
2093 return LANE_COUNT_TWO
;
2094 case LANE_COUNT_TWO
:
2095 return LANE_COUNT_ONE
;
2096 case LANE_COUNT_ONE
:
2097 return LANE_COUNT_UNKNOWN
;
2099 return LANE_COUNT_UNKNOWN
;
2103 static enum dc_link_rate
reduce_link_rate(enum dc_link_rate link_rate
)
2105 switch (link_rate
) {
2106 case LINK_RATE_HIGH3
:
2107 return LINK_RATE_HIGH2
;
2108 case LINK_RATE_HIGH2
:
2109 return LINK_RATE_HIGH
;
2110 case LINK_RATE_HIGH
:
2111 return LINK_RATE_LOW
;
2113 return LINK_RATE_UNKNOWN
;
2115 return LINK_RATE_UNKNOWN
;
2119 static enum dc_lane_count
increase_lane_count(enum dc_lane_count lane_count
)
2121 switch (lane_count
) {
2122 case LANE_COUNT_ONE
:
2123 return LANE_COUNT_TWO
;
2124 case LANE_COUNT_TWO
:
2125 return LANE_COUNT_FOUR
;
2127 return LANE_COUNT_UNKNOWN
;
2131 static enum dc_link_rate
increase_link_rate(enum dc_link_rate link_rate
)
2133 switch (link_rate
) {
2135 return LINK_RATE_HIGH
;
2136 case LINK_RATE_HIGH
:
2137 return LINK_RATE_HIGH2
;
2138 case LINK_RATE_HIGH2
:
2139 return LINK_RATE_HIGH3
;
2141 return LINK_RATE_UNKNOWN
;
2146 * function: set link rate and lane count fallback based
2147 * on current link setting and last link training result
2149 * true - link setting could be set
2150 * false - has reached minimum setting
2151 * and no further fallback could be done
2153 static bool decide_fallback_link_setting(
2154 struct dc_link_settings initial_link_settings
,
2155 struct dc_link_settings
*current_link_setting
,
2156 enum link_training_result training_result
)
2158 if (!current_link_setting
)
2161 switch (training_result
) {
2162 case LINK_TRAINING_CR_FAIL_LANE0
:
2163 case LINK_TRAINING_CR_FAIL_LANE1
:
2164 case LINK_TRAINING_CR_FAIL_LANE23
:
2165 case LINK_TRAINING_LQA_FAIL
:
2167 if (!reached_minimum_link_rate
2168 (current_link_setting
->link_rate
)) {
2169 current_link_setting
->link_rate
=
2171 current_link_setting
->link_rate
);
2172 } else if (!reached_minimum_lane_count
2173 (current_link_setting
->lane_count
)) {
2174 current_link_setting
->link_rate
=
2175 initial_link_settings
.link_rate
;
2176 if (training_result
== LINK_TRAINING_CR_FAIL_LANE0
)
2178 else if (training_result
== LINK_TRAINING_CR_FAIL_LANE1
)
2179 current_link_setting
->lane_count
=
2181 else if (training_result
==
2182 LINK_TRAINING_CR_FAIL_LANE23
)
2183 current_link_setting
->lane_count
=
2186 current_link_setting
->lane_count
=
2188 current_link_setting
->lane_count
);
2194 case LINK_TRAINING_EQ_FAIL_EQ
:
2196 if (!reached_minimum_lane_count
2197 (current_link_setting
->lane_count
)) {
2198 current_link_setting
->lane_count
=
2200 current_link_setting
->lane_count
);
2201 } else if (!reached_minimum_link_rate
2202 (current_link_setting
->link_rate
)) {
2203 current_link_setting
->link_rate
=
2205 current_link_setting
->link_rate
);
2211 case LINK_TRAINING_EQ_FAIL_CR
:
2213 if (!reached_minimum_link_rate
2214 (current_link_setting
->link_rate
)) {
2215 current_link_setting
->link_rate
=
2217 current_link_setting
->link_rate
);
2229 bool dp_validate_mode_timing(
2230 struct dc_link
*link
,
2231 const struct dc_crtc_timing
*timing
)
2236 const struct dc_link_settings
*link_setting
;
2238 /*always DP fail safe mode*/
2239 if ((timing
->pix_clk_100hz
/ 10) == (uint32_t) 25175 &&
2240 timing
->h_addressable
== (uint32_t) 640 &&
2241 timing
->v_addressable
== (uint32_t) 480)
2244 link_setting
= dc_link_get_link_cap(link
);
2246 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2247 /*if (flags.DYNAMIC_VALIDATION == 1 &&
2248 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2249 link_setting = &link->verified_link_cap;
2252 req_bw
= dc_bandwidth_in_kbps_from_timing(timing
);
2253 max_bw
= dc_link_bandwidth_kbps(link
, link_setting
);
2255 if (req_bw
<= max_bw
) {
2256 /* remember the biggest mode here, during
2257 * initial link training (to get
2258 * verified_link_cap), LS sends event about
2259 * cannot train at reported cap to upper
2260 * layer and upper layer will re-enumerate modes.
2261 * this is not necessary if the lower
2262 * verified_link_cap is enough to drive
2265 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2266 /* if (flags.DYNAMIC_VALIDATION == 1)
2267 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2268 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2274 static bool decide_dp_link_settings(struct dc_link
*link
, struct dc_link_settings
*link_setting
, uint32_t req_bw
)
2276 struct dc_link_settings initial_link_setting
= {
2277 LANE_COUNT_ONE
, LINK_RATE_LOW
, LINK_SPREAD_DISABLED
, false, 0};
2278 struct dc_link_settings current_link_setting
=
2279 initial_link_setting
;
2282 /* search for the minimum link setting that:
2283 * 1. is supported according to the link training result
2284 * 2. could support the b/w requested by the timing
2286 while (current_link_setting
.link_rate
<=
2287 link
->verified_link_cap
.link_rate
) {
2288 link_bw
= dc_link_bandwidth_kbps(
2290 ¤t_link_setting
);
2291 if (req_bw
<= link_bw
) {
2292 *link_setting
= current_link_setting
;
2296 if (current_link_setting
.lane_count
<
2297 link
->verified_link_cap
.lane_count
) {
2298 current_link_setting
.lane_count
=
2299 increase_lane_count(
2300 current_link_setting
.lane_count
);
2302 current_link_setting
.link_rate
=
2304 current_link_setting
.link_rate
);
2305 current_link_setting
.lane_count
=
2306 initial_link_setting
.lane_count
;
2313 static bool decide_edp_link_settings(struct dc_link
*link
, struct dc_link_settings
*link_setting
, uint32_t req_bw
)
2315 struct dc_link_settings initial_link_setting
;
2316 struct dc_link_settings current_link_setting
;
2319 if (link
->dpcd_caps
.dpcd_rev
.raw
< DPCD_REV_14
||
2320 link
->dpcd_caps
.edp_supported_link_rates_count
== 0) {
2321 *link_setting
= link
->verified_link_cap
;
2325 memset(&initial_link_setting
, 0, sizeof(initial_link_setting
));
2326 initial_link_setting
.lane_count
= LANE_COUNT_ONE
;
2327 initial_link_setting
.link_rate
= link
->dpcd_caps
.edp_supported_link_rates
[0];
2328 initial_link_setting
.link_spread
= LINK_SPREAD_DISABLED
;
2329 initial_link_setting
.use_link_rate_set
= true;
2330 initial_link_setting
.link_rate_set
= 0;
2331 current_link_setting
= initial_link_setting
;
2333 /* search for the minimum link setting that:
2334 * 1. is supported according to the link training result
2335 * 2. could support the b/w requested by the timing
2337 while (current_link_setting
.link_rate
<=
2338 link
->verified_link_cap
.link_rate
) {
2339 link_bw
= dc_link_bandwidth_kbps(
2341 ¤t_link_setting
);
2342 if (req_bw
<= link_bw
) {
2343 *link_setting
= current_link_setting
;
2347 if (current_link_setting
.lane_count
<
2348 link
->verified_link_cap
.lane_count
) {
2349 current_link_setting
.lane_count
=
2350 increase_lane_count(
2351 current_link_setting
.lane_count
);
2353 if (current_link_setting
.link_rate_set
< link
->dpcd_caps
.edp_supported_link_rates_count
) {
2354 current_link_setting
.link_rate_set
++;
2355 current_link_setting
.link_rate
=
2356 link
->dpcd_caps
.edp_supported_link_rates
[current_link_setting
.link_rate_set
];
2357 current_link_setting
.lane_count
=
2358 initial_link_setting
.lane_count
;
2366 void decide_link_settings(struct dc_stream_state
*stream
,
2367 struct dc_link_settings
*link_setting
)
2369 struct dc_link
*link
;
2372 req_bw
= dc_bandwidth_in_kbps_from_timing(&stream
->timing
);
2374 link
= stream
->link
;
2376 /* if preferred is specified through AMDDP, use it, if it's enough
2379 if (link
->preferred_link_setting
.lane_count
!=
2380 LANE_COUNT_UNKNOWN
&&
2381 link
->preferred_link_setting
.link_rate
!=
2382 LINK_RATE_UNKNOWN
) {
2383 *link_setting
= link
->preferred_link_setting
;
2387 /* MST doesn't perform link training for now
2388 * TODO: add MST specific link training routine
2390 if (stream
->signal
== SIGNAL_TYPE_DISPLAY_PORT_MST
) {
2391 *link_setting
= link
->verified_link_cap
;
2395 if (link
->connector_signal
== SIGNAL_TYPE_EDP
) {
2396 if (decide_edp_link_settings(link
, link_setting
, req_bw
))
2398 } else if (decide_dp_link_settings(link
, link_setting
, req_bw
))
2401 BREAK_TO_DEBUGGER();
2402 ASSERT(link
->verified_link_cap
.lane_count
!= LANE_COUNT_UNKNOWN
);
2404 *link_setting
= link
->verified_link_cap
;
2407 /*************************Short Pulse IRQ***************************/
2408 static bool allow_hpd_rx_irq(const struct dc_link
*link
)
2411 * Don't handle RX IRQ unless one of following is met:
2412 * 1) The link is established (cur_link_settings != unknown)
2413 * 2) We kicked off MST detection
2414 * 3) We know we're dealing with an active dongle
2417 if ((link
->cur_link_settings
.lane_count
!= LANE_COUNT_UNKNOWN
) ||
2418 (link
->type
== dc_connection_mst_branch
) ||
2419 is_dp_active_dongle(link
))
2425 static bool handle_hpd_irq_psr_sink(struct dc_link
*link
)
2427 union dpcd_psr_configuration psr_configuration
;
2429 if (!link
->psr_feature_enabled
)
2432 dm_helpers_dp_read_dpcd(
2435 368,/*DpcdAddress_PSR_Enable_Cfg*/
2436 &psr_configuration
.raw
,
2437 sizeof(psr_configuration
.raw
));
2440 if (psr_configuration
.bits
.ENABLE
) {
2441 unsigned char dpcdbuf
[3] = {0};
2442 union psr_error_status psr_error_status
;
2443 union psr_sink_psr_status psr_sink_psr_status
;
2445 dm_helpers_dp_read_dpcd(
2448 0x2006, /*DpcdAddress_PSR_Error_Status*/
2449 (unsigned char *) dpcdbuf
,
2452 /*DPCD 2006h ERROR STATUS*/
2453 psr_error_status
.raw
= dpcdbuf
[0];
2454 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2455 psr_sink_psr_status
.raw
= dpcdbuf
[2];
2457 if (psr_error_status
.bits
.LINK_CRC_ERROR
||
2458 psr_error_status
.bits
.RFB_STORAGE_ERROR
) {
2459 /* Acknowledge and clear error bits */
2460 dm_helpers_dp_write_dpcd(
2463 8198,/*DpcdAddress_PSR_Error_Status*/
2464 &psr_error_status
.raw
,
2465 sizeof(psr_error_status
.raw
));
2467 /* PSR error, disable and re-enable PSR */
2468 dc_link_set_psr_allow_active(link
, false, true);
2469 dc_link_set_psr_allow_active(link
, true, true);
2472 } else if (psr_sink_psr_status
.bits
.SINK_SELF_REFRESH_STATUS
==
2473 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB
){
2474 /* No error is detect, PSR is active.
2475 * We should return with IRQ_HPD handled without
2476 * checking for loss of sync since PSR would have
2477 * powered down main link.
2485 static void dp_test_send_link_training(struct dc_link
*link
)
2487 struct dc_link_settings link_settings
= {0};
2489 core_link_read_dpcd(
2492 (unsigned char *)(&link_settings
.lane_count
),
2494 core_link_read_dpcd(
2497 (unsigned char *)(&link_settings
.link_rate
),
2500 /* Set preferred link settings */
2501 link
->verified_link_cap
.lane_count
= link_settings
.lane_count
;
2502 link
->verified_link_cap
.link_rate
= link_settings
.link_rate
;
2504 dp_retrain_link_dp_test(link
, &link_settings
, false);
2507 /* TODO Raven hbr2 compliance eye output is unstable
2508 * (toggling on and off) with debugger break
2509 * This caueses intermittent PHY automation failure
2510 * Need to look into the root cause */
2511 static void dp_test_send_phy_test_pattern(struct dc_link
*link
)
2513 union phy_test_pattern dpcd_test_pattern
;
2514 union lane_adjust dpcd_lane_adjustment
[2];
2515 unsigned char dpcd_post_cursor_2_adjustment
= 0;
2516 unsigned char test_80_bit_pattern
[
2517 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72
-
2518 DP_TEST_80BIT_CUSTOM_PATTERN_7_0
)+1] = {0};
2519 enum dp_test_pattern test_pattern
;
2520 struct dc_link_training_settings link_settings
;
2521 union lane_adjust dpcd_lane_adjust
;
2523 struct link_training_settings link_training_settings
;
2526 dpcd_test_pattern
.raw
= 0;
2527 memset(dpcd_lane_adjustment
, 0, sizeof(dpcd_lane_adjustment
));
2528 memset(&link_settings
, 0, sizeof(link_settings
));
2530 /* get phy test pattern and pattern parameters from DP receiver */
2531 core_link_read_dpcd(
2533 DP_TEST_PHY_PATTERN
,
2534 &dpcd_test_pattern
.raw
,
2535 sizeof(dpcd_test_pattern
));
2536 core_link_read_dpcd(
2538 DP_ADJUST_REQUEST_LANE0_1
,
2539 &dpcd_lane_adjustment
[0].raw
,
2540 sizeof(dpcd_lane_adjustment
));
2542 /*get post cursor 2 parameters
2543 * For DP 1.1a or eariler, this DPCD register's value is 0
2544 * For DP 1.2 or later:
2545 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2546 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2548 core_link_read_dpcd(
2550 DP_ADJUST_REQUEST_POST_CURSOR2
,
2551 &dpcd_post_cursor_2_adjustment
,
2552 sizeof(dpcd_post_cursor_2_adjustment
));
2554 /* translate request */
2555 switch (dpcd_test_pattern
.bits
.PATTERN
) {
2556 case PHY_TEST_PATTERN_D10_2
:
2557 test_pattern
= DP_TEST_PATTERN_D102
;
2559 case PHY_TEST_PATTERN_SYMBOL_ERROR
:
2560 test_pattern
= DP_TEST_PATTERN_SYMBOL_ERROR
;
2562 case PHY_TEST_PATTERN_PRBS7
:
2563 test_pattern
= DP_TEST_PATTERN_PRBS7
;
2565 case PHY_TEST_PATTERN_80BIT_CUSTOM
:
2566 test_pattern
= DP_TEST_PATTERN_80BIT_CUSTOM
;
2568 case PHY_TEST_PATTERN_CP2520_1
:
2569 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2570 test_pattern
= (link
->dc
->caps
.force_dp_tps4_for_cp2520
== 1) ?
2571 DP_TEST_PATTERN_TRAINING_PATTERN4
:
2572 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
;
2574 case PHY_TEST_PATTERN_CP2520_2
:
2575 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2576 test_pattern
= (link
->dc
->caps
.force_dp_tps4_for_cp2520
== 1) ?
2577 DP_TEST_PATTERN_TRAINING_PATTERN4
:
2578 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
;
2580 case PHY_TEST_PATTERN_CP2520_3
:
2581 test_pattern
= DP_TEST_PATTERN_TRAINING_PATTERN4
;
2584 test_pattern
= DP_TEST_PATTERN_VIDEO_MODE
;
2588 if (test_pattern
== DP_TEST_PATTERN_80BIT_CUSTOM
)
2589 core_link_read_dpcd(
2591 DP_TEST_80BIT_CUSTOM_PATTERN_7_0
,
2592 test_80_bit_pattern
,
2593 sizeof(test_80_bit_pattern
));
2595 /* prepare link training settings */
2596 link_settings
.link
= link
->cur_link_settings
;
2598 for (lane
= 0; lane
<
2599 (unsigned int)(link
->cur_link_settings
.lane_count
);
2601 dpcd_lane_adjust
.raw
=
2602 get_nibble_at_index(&dpcd_lane_adjustment
[0].raw
, lane
);
2603 link_settings
.lane_settings
[lane
].VOLTAGE_SWING
=
2604 (enum dc_voltage_swing
)
2605 (dpcd_lane_adjust
.bits
.VOLTAGE_SWING_LANE
);
2606 link_settings
.lane_settings
[lane
].PRE_EMPHASIS
=
2607 (enum dc_pre_emphasis
)
2608 (dpcd_lane_adjust
.bits
.PRE_EMPHASIS_LANE
);
2609 link_settings
.lane_settings
[lane
].POST_CURSOR2
=
2610 (enum dc_post_cursor2
)
2611 ((dpcd_post_cursor_2_adjustment
>> (lane
* 2)) & 0x03);
2614 for (i
= 0; i
< 4; i
++)
2615 link_training_settings
.lane_settings
[i
] =
2616 link_settings
.lane_settings
[i
];
2617 link_training_settings
.link_settings
= link_settings
.link
;
2618 link_training_settings
.allow_invalid_msa_timing_param
= false;
2619 /*Usage: Measure DP physical lane signal
2620 * by DP SI test equipment automatically.
2621 * PHY test pattern request is generated by equipment via HPD interrupt.
2622 * HPD needs to be active all the time. HPD should be active
2623 * all the time. Do not touch it.
2624 * forward request to DS
2626 dc_link_dp_set_test_pattern(
2629 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
,
2630 &link_training_settings
,
2631 test_80_bit_pattern
,
2632 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72
-
2633 DP_TEST_80BIT_CUSTOM_PATTERN_7_0
)+1);
2636 static void dp_test_send_link_test_pattern(struct dc_link
*link
)
2638 union link_test_pattern dpcd_test_pattern
;
2639 union test_misc dpcd_test_params
;
2640 enum dp_test_pattern test_pattern
;
2641 enum dp_test_pattern_color_space test_pattern_color_space
=
2642 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
;
2644 memset(&dpcd_test_pattern
, 0, sizeof(dpcd_test_pattern
));
2645 memset(&dpcd_test_params
, 0, sizeof(dpcd_test_params
));
2647 /* get link test pattern and pattern parameters */
2648 core_link_read_dpcd(
2651 &dpcd_test_pattern
.raw
,
2652 sizeof(dpcd_test_pattern
));
2653 core_link_read_dpcd(
2656 &dpcd_test_params
.raw
,
2657 sizeof(dpcd_test_params
));
2659 switch (dpcd_test_pattern
.bits
.PATTERN
) {
2660 case LINK_TEST_PATTERN_COLOR_RAMP
:
2661 test_pattern
= DP_TEST_PATTERN_COLOR_RAMP
;
2663 case LINK_TEST_PATTERN_VERTICAL_BARS
:
2664 test_pattern
= DP_TEST_PATTERN_VERTICAL_BARS
;
2665 break; /* black and white */
2666 case LINK_TEST_PATTERN_COLOR_SQUARES
:
2667 test_pattern
= (dpcd_test_params
.bits
.DYN_RANGE
==
2668 TEST_DYN_RANGE_VESA
?
2669 DP_TEST_PATTERN_COLOR_SQUARES
:
2670 DP_TEST_PATTERN_COLOR_SQUARES_CEA
);
2673 test_pattern
= DP_TEST_PATTERN_VIDEO_MODE
;
2677 if (dpcd_test_params
.bits
.CLR_FORMAT
== 0)
2678 test_pattern_color_space
= DP_TEST_PATTERN_COLOR_SPACE_RGB
;
2680 test_pattern_color_space
= dpcd_test_params
.bits
.YCBCR_COEFS
?
2681 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709
:
2682 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601
;
2684 dc_link_dp_set_test_pattern(
2687 test_pattern_color_space
,
2693 static void dp_test_get_audio_test_data(struct dc_link
*link
, bool disable_video
)
2695 union audio_test_mode dpcd_test_mode
= {0};
2696 struct audio_test_pattern_type dpcd_pattern_type
= {0};
2697 union audio_test_pattern_period dpcd_pattern_period
[AUDIO_CHANNELS_COUNT
] = {0};
2698 enum dp_test_pattern test_pattern
= DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED
;
2700 struct pipe_ctx
*pipes
= link
->dc
->current_state
->res_ctx
.pipe_ctx
;
2701 struct pipe_ctx
*pipe_ctx
= &pipes
[0];
2702 unsigned int channel_count
;
2703 unsigned int channel
= 0;
2704 unsigned int modes
= 0;
2705 unsigned int sampling_rate_in_hz
= 0;
2707 // get audio test mode and test pattern parameters
2708 core_link_read_dpcd(
2711 &dpcd_test_mode
.raw
,
2712 sizeof(dpcd_test_mode
));
2714 core_link_read_dpcd(
2716 DP_TEST_AUDIO_PATTERN_TYPE
,
2717 &dpcd_pattern_type
.value
,
2718 sizeof(dpcd_pattern_type
));
2720 channel_count
= dpcd_test_mode
.bits
.channel_count
+ 1;
2722 // read pattern periods for requested channels when sawTooth pattern is requested
2723 if (dpcd_pattern_type
.value
== AUDIO_TEST_PATTERN_SAWTOOTH
||
2724 dpcd_pattern_type
.value
== AUDIO_TEST_PATTERN_OPERATOR_DEFINED
) {
2726 test_pattern
= (dpcd_pattern_type
.value
== AUDIO_TEST_PATTERN_SAWTOOTH
) ?
2727 DP_TEST_PATTERN_AUDIO_SAWTOOTH
: DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED
;
2728 // read period for each channel
2729 for (channel
= 0; channel
< channel_count
; channel
++) {
2730 core_link_read_dpcd(
2732 DP_TEST_AUDIO_PERIOD_CH1
+ channel
,
2733 &dpcd_pattern_period
[channel
].raw
,
2734 sizeof(dpcd_pattern_period
[channel
]));
2738 // translate sampling rate
2739 switch (dpcd_test_mode
.bits
.sampling_rate
) {
2740 case AUDIO_SAMPLING_RATE_32KHZ
:
2741 sampling_rate_in_hz
= 32000;
2743 case AUDIO_SAMPLING_RATE_44_1KHZ
:
2744 sampling_rate_in_hz
= 44100;
2746 case AUDIO_SAMPLING_RATE_48KHZ
:
2747 sampling_rate_in_hz
= 48000;
2749 case AUDIO_SAMPLING_RATE_88_2KHZ
:
2750 sampling_rate_in_hz
= 88200;
2752 case AUDIO_SAMPLING_RATE_96KHZ
:
2753 sampling_rate_in_hz
= 96000;
2755 case AUDIO_SAMPLING_RATE_176_4KHZ
:
2756 sampling_rate_in_hz
= 176400;
2758 case AUDIO_SAMPLING_RATE_192KHZ
:
2759 sampling_rate_in_hz
= 192000;
2762 sampling_rate_in_hz
= 0;
2766 link
->audio_test_data
.flags
.test_requested
= 1;
2767 link
->audio_test_data
.flags
.disable_video
= disable_video
;
2768 link
->audio_test_data
.sampling_rate
= sampling_rate_in_hz
;
2769 link
->audio_test_data
.channel_count
= channel_count
;
2770 link
->audio_test_data
.pattern_type
= test_pattern
;
2772 if (test_pattern
== DP_TEST_PATTERN_AUDIO_SAWTOOTH
) {
2773 for (modes
= 0; modes
< pipe_ctx
->stream
->audio_info
.mode_count
; modes
++) {
2774 link
->audio_test_data
.pattern_period
[modes
] = dpcd_pattern_period
[modes
].bits
.pattern_period
;
2779 static void handle_automated_test(struct dc_link
*link
)
2781 union test_request test_request
;
2782 union test_response test_response
;
2784 memset(&test_request
, 0, sizeof(test_request
));
2785 memset(&test_response
, 0, sizeof(test_response
));
2787 core_link_read_dpcd(
2791 sizeof(union test_request
));
2792 if (test_request
.bits
.LINK_TRAINING
) {
2793 /* ACK first to let DP RX test box monitor LT sequence */
2794 test_response
.bits
.ACK
= 1;
2795 core_link_write_dpcd(
2799 sizeof(test_response
));
2800 dp_test_send_link_training(link
);
2801 /* no acknowledge request is needed again */
2802 test_response
.bits
.ACK
= 0;
2804 if (test_request
.bits
.LINK_TEST_PATTRN
) {
2805 dp_test_send_link_test_pattern(link
);
2806 test_response
.bits
.ACK
= 1;
2809 if (test_request
.bits
.AUDIO_TEST_PATTERN
) {
2810 dp_test_get_audio_test_data(link
, test_request
.bits
.TEST_AUDIO_DISABLED_VIDEO
);
2811 test_response
.bits
.ACK
= 1;
2814 if (test_request
.bits
.PHY_TEST_PATTERN
) {
2815 dp_test_send_phy_test_pattern(link
);
2816 test_response
.bits
.ACK
= 1;
2819 /* send request acknowledgment */
2820 if (test_response
.bits
.ACK
)
2821 core_link_write_dpcd(
2825 sizeof(test_response
));
2828 bool dc_link_handle_hpd_rx_irq(struct dc_link
*link
, union hpd_irq_data
*out_hpd_irq_dpcd_data
, bool *out_link_loss
)
2830 union hpd_irq_data hpd_irq_dpcd_data
= { { { {0} } } };
2831 union device_service_irq device_service_clear
= { { 0 } };
2832 enum dc_status result
;
2833 bool status
= false;
2834 struct pipe_ctx
*pipe_ctx
;
2835 struct dc_link_settings previous_link_settings
;
2839 *out_link_loss
= false;
2840 /* For use cases related to down stream connection status change,
2841 * PSR and device auto test, refer to function handle_sst_hpd_irq
2844 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2845 __func__
, link
->link_index
);
2848 /* All the "handle_hpd_irq_xxx()" methods
2849 * should be called only after
2850 * dal_dpsst_ls_read_hpd_irq_data
2851 * Order of calls is important too
2853 result
= read_hpd_rx_irq_data(link
, &hpd_irq_dpcd_data
);
2854 if (out_hpd_irq_dpcd_data
)
2855 *out_hpd_irq_dpcd_data
= hpd_irq_dpcd_data
;
2857 if (result
!= DC_OK
) {
2858 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2863 if (hpd_irq_dpcd_data
.bytes
.device_service_irq
.bits
.AUTOMATED_TEST
) {
2864 device_service_clear
.bits
.AUTOMATED_TEST
= 1;
2865 core_link_write_dpcd(
2867 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2868 &device_service_clear
.raw
,
2869 sizeof(device_service_clear
.raw
));
2870 device_service_clear
.raw
= 0;
2871 handle_automated_test(link
);
2875 if (!allow_hpd_rx_irq(link
)) {
2876 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
2877 __func__
, link
->link_index
);
2881 if (handle_hpd_irq_psr_sink(link
))
2882 /* PSR-related error was detected and handled */
2885 /* If PSR-related error handled, Main link may be off,
2886 * so do not handle as a normal sink status change interrupt.
2889 if (hpd_irq_dpcd_data
.bytes
.device_service_irq
.bits
.UP_REQ_MSG_RDY
)
2892 /* check if we have MST msg and return since we poll for it */
2893 if (hpd_irq_dpcd_data
.bytes
.device_service_irq
.bits
.DOWN_REP_MSG_RDY
)
2896 /* For now we only handle 'Downstream port status' case.
2897 * If we got sink count changed it means
2898 * Downstream port status changed,
2899 * then DM should call DC to do the detection.
2900 * NOTE: Do not handle link loss on eDP since it is internal link*/
2901 if ((link
->connector_signal
!= SIGNAL_TYPE_EDP
) &&
2902 hpd_rx_irq_check_link_loss_status(
2904 &hpd_irq_dpcd_data
)) {
2905 /* Connectivity log: link loss */
2906 CONN_DATA_LINK_LOSS(link
,
2907 hpd_irq_dpcd_data
.raw
,
2908 sizeof(hpd_irq_dpcd_data
),
2911 for (i
= 0; i
< MAX_PIPES
; i
++) {
2912 pipe_ctx
= &link
->dc
->current_state
->res_ctx
.pipe_ctx
[i
];
2913 if (pipe_ctx
&& pipe_ctx
->stream
&& pipe_ctx
->stream
->link
== link
)
2914 link
->dc
->hwss
.blank_stream(pipe_ctx
);
2917 for (i
= 0; i
< MAX_PIPES
; i
++) {
2918 pipe_ctx
= &link
->dc
->current_state
->res_ctx
.pipe_ctx
[i
];
2919 if (pipe_ctx
&& pipe_ctx
->stream
&& pipe_ctx
->stream
->link
== link
)
2923 if (pipe_ctx
== NULL
|| pipe_ctx
->stream
== NULL
)
2926 previous_link_settings
= link
->cur_link_settings
;
2928 perform_link_training_with_retries(&previous_link_settings
,
2929 true, LINK_TRAINING_ATTEMPTS
,
2931 pipe_ctx
->stream
->signal
);
2933 if (pipe_ctx
->stream
->signal
== SIGNAL_TYPE_DISPLAY_PORT_MST
)
2934 dc_link_reallocate_mst_payload(link
);
2936 for (i
= 0; i
< MAX_PIPES
; i
++) {
2937 pipe_ctx
= &link
->dc
->current_state
->res_ctx
.pipe_ctx
[i
];
2938 if (pipe_ctx
&& pipe_ctx
->stream
&& pipe_ctx
->stream
->link
== link
)
2939 link
->dc
->hwss
.unblank_stream(pipe_ctx
, &previous_link_settings
);
2944 *out_link_loss
= true;
2947 if (link
->type
== dc_connection_active_dongle
&&
2948 hpd_irq_dpcd_data
.bytes
.sink_cnt
.bits
.SINK_COUNT
2949 != link
->dpcd_sink_count
)
2952 /* reasons for HPD RX:
2953 * 1. Link Loss - ie Re-train the Link
2954 * 2. MST sideband message
2955 * 3. Automated Test - ie. Internal Commit
2956 * 4. CP (copy protection) - (not interesting for DM???)
2958 * 6. Downstream Port status changed
2959 * -ie. Detect - this the only one
2960 * which is interesting for DM because
2961 * it must call dc_link_detect.
2966 /*query dpcd for version and mst cap addresses*/
2967 bool is_mst_supported(struct dc_link
*link
)
2970 enum dc_status st
= DC_OK
;
2974 if (link
->preferred_training_settings
.mst_enable
&&
2975 *link
->preferred_training_settings
.mst_enable
== false) {
2982 st
= core_link_read_dpcd(link
, DP_DPCD_REV
, &rev
.raw
,
2985 if (st
== DC_OK
&& rev
.raw
>= DPCD_REV_12
) {
2987 st
= core_link_read_dpcd(link
, DP_MSTM_CAP
,
2988 &cap
.raw
, sizeof(cap
));
2989 if (st
== DC_OK
&& cap
.bits
.MST_CAP
== 1)
2996 bool is_dp_active_dongle(const struct dc_link
*link
)
2998 return link
->dpcd_caps
.is_branch_dev
;
3001 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc
)
3004 case DOWN_STREAM_MAX_8BPC
:
3006 case DOWN_STREAM_MAX_10BPC
:
3008 case DOWN_STREAM_MAX_12BPC
:
3010 case DOWN_STREAM_MAX_16BPC
:
3019 static void read_dp_device_vendor_id(struct dc_link
*link
)
3021 struct dp_device_vendor_id dp_id
;
3023 /* read IEEE branch device id */
3024 core_link_read_dpcd(
3030 link
->dpcd_caps
.branch_dev_id
=
3031 (dp_id
.ieee_oui
[0] << 16) +
3032 (dp_id
.ieee_oui
[1] << 8) +
3036 link
->dpcd_caps
.branch_dev_name
,
3037 dp_id
.ieee_device_id
,
3038 sizeof(dp_id
.ieee_device_id
));
3043 static void get_active_converter_info(
3044 uint8_t data
, struct dc_link
*link
)
3046 union dp_downstream_port_present ds_port
= { .byte
= data
};
3047 memset(&link
->dpcd_caps
.dongle_caps
, 0, sizeof(link
->dpcd_caps
.dongle_caps
));
3049 /* decode converter info*/
3050 if (!ds_port
.fields
.PORT_PRESENT
) {
3051 link
->dpcd_caps
.dongle_type
= DISPLAY_DONGLE_NONE
;
3052 ddc_service_set_dongle_type(link
->ddc
,
3053 link
->dpcd_caps
.dongle_type
);
3054 link
->dpcd_caps
.is_branch_dev
= false;
3058 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3059 if (ds_port
.fields
.PORT_TYPE
== DOWNSTREAM_DP
) {
3060 link
->dpcd_caps
.is_branch_dev
= false;
3064 link
->dpcd_caps
.is_branch_dev
= ds_port
.fields
.PORT_PRESENT
;
3067 switch (ds_port
.fields
.PORT_TYPE
) {
3068 case DOWNSTREAM_VGA
:
3069 link
->dpcd_caps
.dongle_type
= DISPLAY_DONGLE_DP_VGA_CONVERTER
;
3071 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS
:
3072 /* At this point we don't know is it DVI or HDMI or DP++,
3074 link
->dpcd_caps
.dongle_type
= DISPLAY_DONGLE_DP_DVI_CONVERTER
;
3077 link
->dpcd_caps
.dongle_type
= DISPLAY_DONGLE_NONE
;
3081 if (link
->dpcd_caps
.dpcd_rev
.raw
>= DPCD_REV_11
) {
3082 uint8_t det_caps
[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3083 union dwnstream_port_caps_byte0
*port_caps
=
3084 (union dwnstream_port_caps_byte0
*)det_caps
;
3085 core_link_read_dpcd(link
, DP_DOWNSTREAM_PORT_0
,
3086 det_caps
, sizeof(det_caps
));
3088 switch (port_caps
->bits
.DWN_STRM_PORTX_TYPE
) {
3089 /*Handle DP case as DONGLE_NONE*/
3090 case DOWN_STREAM_DETAILED_DP
:
3091 link
->dpcd_caps
.dongle_type
= DISPLAY_DONGLE_NONE
;
3093 case DOWN_STREAM_DETAILED_VGA
:
3094 link
->dpcd_caps
.dongle_type
=
3095 DISPLAY_DONGLE_DP_VGA_CONVERTER
;
3097 case DOWN_STREAM_DETAILED_DVI
:
3098 link
->dpcd_caps
.dongle_type
=
3099 DISPLAY_DONGLE_DP_DVI_CONVERTER
;
3101 case DOWN_STREAM_DETAILED_HDMI
:
3102 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS
:
3103 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3104 link
->dpcd_caps
.dongle_type
=
3105 DISPLAY_DONGLE_DP_HDMI_CONVERTER
;
3107 link
->dpcd_caps
.dongle_caps
.dongle_type
= link
->dpcd_caps
.dongle_type
;
3108 if (ds_port
.fields
.DETAILED_CAPS
) {
3110 union dwnstream_port_caps_byte3_hdmi
3111 hdmi_caps
= {.raw
= det_caps
[3] };
3112 union dwnstream_port_caps_byte2
3113 hdmi_color_caps
= {.raw
= det_caps
[2] };
3114 link
->dpcd_caps
.dongle_caps
.dp_hdmi_max_pixel_clk_in_khz
=
3117 link
->dpcd_caps
.dongle_caps
.is_dp_hdmi_s3d_converter
=
3118 hdmi_caps
.bits
.FRAME_SEQ_TO_FRAME_PACK
;
3119 /*YCBCR capability only for HDMI case*/
3120 if (port_caps
->bits
.DWN_STRM_PORTX_TYPE
3121 == DOWN_STREAM_DETAILED_HDMI
) {
3122 link
->dpcd_caps
.dongle_caps
.is_dp_hdmi_ycbcr422_pass_through
=
3123 hdmi_caps
.bits
.YCrCr422_PASS_THROUGH
;
3124 link
->dpcd_caps
.dongle_caps
.is_dp_hdmi_ycbcr420_pass_through
=
3125 hdmi_caps
.bits
.YCrCr420_PASS_THROUGH
;
3126 link
->dpcd_caps
.dongle_caps
.is_dp_hdmi_ycbcr422_converter
=
3127 hdmi_caps
.bits
.YCrCr422_CONVERSION
;
3128 link
->dpcd_caps
.dongle_caps
.is_dp_hdmi_ycbcr420_converter
=
3129 hdmi_caps
.bits
.YCrCr420_CONVERSION
;
3132 link
->dpcd_caps
.dongle_caps
.dp_hdmi_max_bpc
=
3133 translate_dpcd_max_bpc(
3134 hdmi_color_caps
.bits
.MAX_BITS_PER_COLOR_COMPONENT
);
3136 if (link
->dpcd_caps
.dongle_caps
.dp_hdmi_max_pixel_clk_in_khz
!= 0)
3137 link
->dpcd_caps
.dongle_caps
.extendedCapValid
= true;
3144 ddc_service_set_dongle_type(link
->ddc
, link
->dpcd_caps
.dongle_type
);
3147 struct dp_sink_hw_fw_revision dp_hw_fw_revision
;
3149 core_link_read_dpcd(
3151 DP_BRANCH_REVISION_START
,
3152 (uint8_t *)&dp_hw_fw_revision
,
3153 sizeof(dp_hw_fw_revision
));
3155 link
->dpcd_caps
.branch_hw_revision
=
3156 dp_hw_fw_revision
.ieee_hw_rev
;
3159 link
->dpcd_caps
.branch_fw_revision
,
3160 dp_hw_fw_revision
.ieee_fw_rev
,
3161 sizeof(dp_hw_fw_revision
.ieee_fw_rev
));
3165 static void dp_wa_power_up_0010FA(struct dc_link
*link
, uint8_t *dpcd_data
,
3170 if (!link
->dpcd_caps
.dpcd_rev
.raw
) {
3172 dp_receiver_power_ctrl(link
, true);
3173 core_link_read_dpcd(link
, DP_DPCD_REV
,
3175 link
->dpcd_caps
.dpcd_rev
.raw
= dpcd_data
[
3178 } while (retry
++ < 4 && !link
->dpcd_caps
.dpcd_rev
.raw
);
3181 if (link
->dpcd_caps
.dongle_type
== DISPLAY_DONGLE_DP_VGA_CONVERTER
) {
3182 switch (link
->dpcd_caps
.branch_dev_id
) {
3183 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3184 * all internal circuits including AUX communication preventing
3185 * reading DPCD table and EDID (spec violation).
3186 * Encoder will skip DP RX power down on disable_output to
3187 * keep receiver powered all the time.*/
3188 case DP_BRANCH_DEVICE_ID_0010FA
:
3189 case DP_BRANCH_DEVICE_ID_0080E1
:
3190 case DP_BRANCH_DEVICE_ID_00E04C
:
3191 link
->wa_flags
.dp_keep_receiver_powered
= true;
3194 /* TODO: May need work around for other dongles. */
3196 link
->wa_flags
.dp_keep_receiver_powered
= false;
3200 link
->wa_flags
.dp_keep_receiver_powered
= false;
3203 /* Read additional sink caps defined in source specific DPCD area
3204 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3206 static bool dpcd_read_sink_ext_caps(struct dc_link
*link
)
3213 if (core_link_read_dpcd(link
, DP_SOURCE_SINK_CAP
, &dpcd_data
, 1) != DC_OK
)
3216 link
->dpcd_sink_ext_caps
.raw
= dpcd_data
;
3220 static bool retrieve_link_cap(struct dc_link
*link
)
3222 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3223 * which means size 16 will be good for both of those DPCD register block reads
3225 uint8_t dpcd_data
[16];
3226 uint8_t lttpr_dpcd_data
[6];
3228 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3230 uint8_t dpcd_dprx_data
= '\0';
3231 uint8_t dpcd_power_state
= '\0';
3233 struct dp_device_vendor_id sink_id
;
3234 union down_stream_port_count down_strm_port_count
;
3235 union edp_configuration_cap edp_config_cap
;
3236 union dp_downstream_port_present ds_port
= { 0 };
3237 enum dc_status status
= DC_ERROR_UNEXPECTED
;
3238 uint32_t read_dpcd_retry_cnt
= 3;
3240 struct dp_sink_hw_fw_revision dp_hw_fw_revision
;
3242 /* Set default timeout to 3.2ms and read LTTPR capabilities */
3243 bool ext_timeout_support
= link
->dc
->caps
.extended_aux_timeout_support
&&
3244 !link
->dc
->config
.disable_extended_timeout_support
;
3246 link
->is_lttpr_mode_transparent
= true;
3248 if (ext_timeout_support
) {
3249 dc_link_aux_configure_timeout(link
->ddc
,
3250 LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD
);
3253 memset(dpcd_data
, '\0', sizeof(dpcd_data
));
3254 memset(lttpr_dpcd_data
, '\0', sizeof(lttpr_dpcd_data
));
3255 memset(&down_strm_port_count
,
3256 '\0', sizeof(union down_stream_port_count
));
3257 memset(&edp_config_cap
, '\0',
3258 sizeof(union edp_configuration_cap
));
3260 status
= core_link_read_dpcd(link
, DP_SET_POWER
,
3261 &dpcd_power_state
, sizeof(dpcd_power_state
));
3263 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3264 * section 2.3.1.2, if AUX CH may be powered down due to
3265 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3266 * signal and may need up to 1 ms before being able to reply.
3268 if (status
!= DC_OK
|| dpcd_power_state
== DP_SET_POWER_D3
)
3271 for (i
= 0; i
< read_dpcd_retry_cnt
; i
++) {
3272 status
= core_link_read_dpcd(
3277 if (status
== DC_OK
)
3281 if (status
!= DC_OK
) {
3282 dm_error("%s: Read dpcd data failed.\n", __func__
);
3286 if (ext_timeout_support
) {
3288 status
= core_link_read_dpcd(
3290 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV
,
3292 sizeof(lttpr_dpcd_data
));
3294 link
->dpcd_caps
.lttpr_caps
.revision
.raw
=
3295 lttpr_dpcd_data
[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV
-
3296 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV
];
3298 link
->dpcd_caps
.lttpr_caps
.max_link_rate
=
3299 lttpr_dpcd_data
[DP_MAX_LINK_RATE_PHY_REPEATER
-
3300 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV
];
3302 link
->dpcd_caps
.lttpr_caps
.phy_repeater_cnt
=
3303 lttpr_dpcd_data
[DP_PHY_REPEATER_CNT
-
3304 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV
];
3306 link
->dpcd_caps
.lttpr_caps
.max_lane_count
=
3307 lttpr_dpcd_data
[DP_MAX_LANE_COUNT_PHY_REPEATER
-
3308 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV
];
3310 link
->dpcd_caps
.lttpr_caps
.mode
=
3311 lttpr_dpcd_data
[DP_PHY_REPEATER_MODE
-
3312 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV
];
3314 link
->dpcd_caps
.lttpr_caps
.max_ext_timeout
=
3315 lttpr_dpcd_data
[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT
-
3316 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV
];
3318 if (link
->dpcd_caps
.lttpr_caps
.phy_repeater_cnt
> 0 &&
3319 link
->dpcd_caps
.lttpr_caps
.max_lane_count
> 0 &&
3320 link
->dpcd_caps
.lttpr_caps
.max_lane_count
<= 4 &&
3321 link
->dpcd_caps
.lttpr_caps
.revision
.raw
>= 0x14) {
3322 link
->is_lttpr_mode_transparent
= false;
3324 /*No lttpr reset timeout to its default value*/
3325 link
->is_lttpr_mode_transparent
= true;
3326 dc_link_aux_configure_timeout(link
->ddc
, LINK_AUX_DEFAULT_TIMEOUT_PERIOD
);
3329 CONN_DATA_DETECT(link
, lttpr_dpcd_data
, sizeof(lttpr_dpcd_data
), "LTTPR Caps: ");
3333 union training_aux_rd_interval aux_rd_interval
;
3335 aux_rd_interval
.raw
=
3336 dpcd_data
[DP_TRAINING_AUX_RD_INTERVAL
];
3338 link
->dpcd_caps
.ext_receiver_cap_field_present
=
3339 aux_rd_interval
.bits
.EXT_RECEIVER_CAP_FIELD_PRESENT
== 1;
3341 if (aux_rd_interval
.bits
.EXT_RECEIVER_CAP_FIELD_PRESENT
== 1) {
3342 uint8_t ext_cap_data
[16];
3344 memset(ext_cap_data
, '\0', sizeof(ext_cap_data
));
3345 for (i
= 0; i
< read_dpcd_retry_cnt
; i
++) {
3346 status
= core_link_read_dpcd(
3350 sizeof(ext_cap_data
));
3351 if (status
== DC_OK
) {
3352 memcpy(dpcd_data
, ext_cap_data
, sizeof(dpcd_data
));
3356 if (status
!= DC_OK
)
3357 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__
);
3361 link
->dpcd_caps
.dpcd_rev
.raw
=
3362 dpcd_data
[DP_DPCD_REV
- DP_DPCD_REV
];
3364 if (link
->dpcd_caps
.dpcd_rev
.raw
>= 0x14) {
3365 for (i
= 0; i
< read_dpcd_retry_cnt
; i
++) {
3366 status
= core_link_read_dpcd(
3368 DP_DPRX_FEATURE_ENUMERATION_LIST
,
3370 sizeof(dpcd_dprx_data
));
3371 if (status
== DC_OK
)
3375 link
->dpcd_caps
.dprx_feature
.raw
= dpcd_dprx_data
;
3377 if (status
!= DC_OK
)
3378 dm_error("%s: Read DPRX caps data failed.\n", __func__
);
3382 link
->dpcd_caps
.dprx_feature
.raw
= 0;
3386 /* Error condition checking...
3387 * It is impossible for Sink to report Max Lane Count = 0.
3388 * It is possible for Sink to report Max Link Rate = 0, if it is
3389 * an eDP device that is reporting specialized link rates in the
3390 * SUPPORTED_LINK_RATE table.
3392 if (dpcd_data
[DP_MAX_LANE_COUNT
- DP_DPCD_REV
] == 0)
3395 ds_port
.byte
= dpcd_data
[DP_DOWNSTREAMPORT_PRESENT
-
3398 read_dp_device_vendor_id(link
);
3400 get_active_converter_info(ds_port
.byte
, link
);
3402 dp_wa_power_up_0010FA(link
, dpcd_data
, sizeof(dpcd_data
));
3404 down_strm_port_count
.raw
= dpcd_data
[DP_DOWN_STREAM_PORT_COUNT
-
3407 link
->dpcd_caps
.allow_invalid_MSA_timing_param
=
3408 down_strm_port_count
.bits
.IGNORE_MSA_TIMING_PARAM
;
3410 link
->dpcd_caps
.max_ln_count
.raw
= dpcd_data
[
3411 DP_MAX_LANE_COUNT
- DP_DPCD_REV
];
3413 link
->dpcd_caps
.max_down_spread
.raw
= dpcd_data
[
3414 DP_MAX_DOWNSPREAD
- DP_DPCD_REV
];
3416 link
->reported_link_cap
.lane_count
=
3417 link
->dpcd_caps
.max_ln_count
.bits
.MAX_LANE_COUNT
;
3418 link
->reported_link_cap
.link_rate
= dpcd_data
[
3419 DP_MAX_LINK_RATE
- DP_DPCD_REV
];
3420 link
->reported_link_cap
.link_spread
=
3421 link
->dpcd_caps
.max_down_spread
.bits
.MAX_DOWN_SPREAD
?
3422 LINK_SPREAD_05_DOWNSPREAD_30KHZ
: LINK_SPREAD_DISABLED
;
3424 edp_config_cap
.raw
= dpcd_data
[
3425 DP_EDP_CONFIGURATION_CAP
- DP_DPCD_REV
];
3426 link
->dpcd_caps
.panel_mode_edp
=
3427 edp_config_cap
.bits
.ALT_SCRAMBLER_RESET
;
3428 link
->dpcd_caps
.dpcd_display_control_capable
=
3429 edp_config_cap
.bits
.DPCD_DISPLAY_CONTROL_CAPABLE
;
3431 link
->test_pattern_enabled
= false;
3432 link
->compliance_test_state
.raw
= 0;
3434 /* read sink count */
3435 core_link_read_dpcd(link
,
3437 &link
->dpcd_caps
.sink_count
.raw
,
3438 sizeof(link
->dpcd_caps
.sink_count
.raw
));
3440 /* read sink ieee oui */
3441 core_link_read_dpcd(link
,
3443 (uint8_t *)(&sink_id
),
3446 link
->dpcd_caps
.sink_dev_id
=
3447 (sink_id
.ieee_oui
[0] << 16) +
3448 (sink_id
.ieee_oui
[1] << 8) +
3449 (sink_id
.ieee_oui
[2]);
3452 link
->dpcd_caps
.sink_dev_id_str
,
3453 sink_id
.ieee_device_id
,
3454 sizeof(sink_id
.ieee_device_id
));
3456 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3458 uint8_t str_mbp_2017
[] = { 101, 68, 21, 101, 98, 97 };
3460 if ((link
->dpcd_caps
.sink_dev_id
== 0x0010fa) &&
3461 !memcmp(link
->dpcd_caps
.sink_dev_id_str
, str_mbp_2017
,
3462 sizeof(str_mbp_2017
))) {
3463 link
->reported_link_cap
.link_rate
= 0x0c;
3467 core_link_read_dpcd(
3469 DP_SINK_HW_REVISION_START
,
3470 (uint8_t *)&dp_hw_fw_revision
,
3471 sizeof(dp_hw_fw_revision
));
3473 link
->dpcd_caps
.sink_hw_revision
=
3474 dp_hw_fw_revision
.ieee_hw_rev
;
3477 link
->dpcd_caps
.sink_fw_revision
,
3478 dp_hw_fw_revision
.ieee_fw_rev
,
3479 sizeof(dp_hw_fw_revision
.ieee_fw_rev
));
3481 memset(&link
->dpcd_caps
.dsc_caps
, '\0',
3482 sizeof(link
->dpcd_caps
.dsc_caps
));
3483 memset(&link
->dpcd_caps
.fec_cap
, '\0', sizeof(link
->dpcd_caps
.fec_cap
));
3484 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3485 if (link
->dpcd_caps
.dpcd_rev
.raw
>= DPCD_REV_14
) {
3486 status
= core_link_read_dpcd(
3489 &link
->dpcd_caps
.fec_cap
.raw
,
3490 sizeof(link
->dpcd_caps
.fec_cap
.raw
));
3491 status
= core_link_read_dpcd(
3494 link
->dpcd_caps
.dsc_caps
.dsc_basic_caps
.raw
,
3495 sizeof(link
->dpcd_caps
.dsc_caps
.dsc_basic_caps
.raw
));
3496 status
= core_link_read_dpcd(
3498 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0
,
3499 link
->dpcd_caps
.dsc_caps
.dsc_ext_caps
.raw
,
3500 sizeof(link
->dpcd_caps
.dsc_caps
.dsc_ext_caps
.raw
));
3503 if (!dpcd_read_sink_ext_caps(link
))
3504 link
->dpcd_sink_ext_caps
.raw
= 0;
3506 /* Connectivity log: detection */
3507 CONN_DATA_DETECT(link
, dpcd_data
, sizeof(dpcd_data
), "Rx Caps: ");
3512 bool dp_overwrite_extended_receiver_cap(struct dc_link
*link
)
3514 uint8_t dpcd_data
[16];
3515 uint32_t read_dpcd_retry_cnt
= 3;
3516 enum dc_status status
= DC_ERROR_UNEXPECTED
;
3517 union dp_downstream_port_present ds_port
= { 0 };
3518 union down_stream_port_count down_strm_port_count
;
3519 union edp_configuration_cap edp_config_cap
;
3523 for (i
= 0; i
< read_dpcd_retry_cnt
; i
++) {
3524 status
= core_link_read_dpcd(
3529 if (status
== DC_OK
)
3533 link
->dpcd_caps
.dpcd_rev
.raw
=
3534 dpcd_data
[DP_DPCD_REV
- DP_DPCD_REV
];
3536 if (dpcd_data
[DP_MAX_LANE_COUNT
- DP_DPCD_REV
] == 0)
3539 ds_port
.byte
= dpcd_data
[DP_DOWNSTREAMPORT_PRESENT
-
3542 get_active_converter_info(ds_port
.byte
, link
);
3544 down_strm_port_count
.raw
= dpcd_data
[DP_DOWN_STREAM_PORT_COUNT
-
3547 link
->dpcd_caps
.allow_invalid_MSA_timing_param
=
3548 down_strm_port_count
.bits
.IGNORE_MSA_TIMING_PARAM
;
3550 link
->dpcd_caps
.max_ln_count
.raw
= dpcd_data
[
3551 DP_MAX_LANE_COUNT
- DP_DPCD_REV
];
3553 link
->dpcd_caps
.max_down_spread
.raw
= dpcd_data
[
3554 DP_MAX_DOWNSPREAD
- DP_DPCD_REV
];
3556 link
->reported_link_cap
.lane_count
=
3557 link
->dpcd_caps
.max_ln_count
.bits
.MAX_LANE_COUNT
;
3558 link
->reported_link_cap
.link_rate
= dpcd_data
[
3559 DP_MAX_LINK_RATE
- DP_DPCD_REV
];
3560 link
->reported_link_cap
.link_spread
=
3561 link
->dpcd_caps
.max_down_spread
.bits
.MAX_DOWN_SPREAD
?
3562 LINK_SPREAD_05_DOWNSPREAD_30KHZ
: LINK_SPREAD_DISABLED
;
3564 edp_config_cap
.raw
= dpcd_data
[
3565 DP_EDP_CONFIGURATION_CAP
- DP_DPCD_REV
];
3566 link
->dpcd_caps
.panel_mode_edp
=
3567 edp_config_cap
.bits
.ALT_SCRAMBLER_RESET
;
3568 link
->dpcd_caps
.dpcd_display_control_capable
=
3569 edp_config_cap
.bits
.DPCD_DISPLAY_CONTROL_CAPABLE
;
3574 bool detect_dp_sink_caps(struct dc_link
*link
)
3576 return retrieve_link_cap(link
);
3578 /* dc init_hw has power encoder using default
3579 * signal for connector. For native DP, no
3580 * need to power up encoder again. If not native
3581 * DP, hw_init may need check signal or power up
3584 /* TODO save sink caps in link->sink */
3587 enum dc_link_rate
linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz
)
3589 enum dc_link_rate link_rate
;
3590 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3591 switch (link_rate_in_khz
) {
3593 link_rate
= LINK_RATE_LOW
; // Rate_1 (RBR) - 1.62 Gbps/Lane
3596 link_rate
= LINK_RATE_RATE_2
; // Rate_2 - 2.16 Gbps/Lane
3599 link_rate
= LINK_RATE_RATE_3
; // Rate_3 - 2.43 Gbps/Lane
3602 link_rate
= LINK_RATE_HIGH
; // Rate_4 (HBR) - 2.70 Gbps/Lane
3605 link_rate
= LINK_RATE_RBR2
; // Rate_5 (RBR2) - 3.24 Gbps/Lane
3608 link_rate
= LINK_RATE_RATE_6
; // Rate_6 - 4.32 Gbps/Lane
3611 link_rate
= LINK_RATE_HIGH2
; // Rate_7 (HBR2) - 5.40 Gbps/Lane
3614 link_rate
= LINK_RATE_HIGH3
; // Rate_8 (HBR3) - 8.10 Gbps/Lane
3617 link_rate
= LINK_RATE_UNKNOWN
;
3623 void detect_edp_sink_caps(struct dc_link
*link
)
3625 uint8_t supported_link_rates
[16];
3627 uint32_t link_rate_in_khz
;
3628 enum dc_link_rate link_rate
= LINK_RATE_UNKNOWN
;
3630 retrieve_link_cap(link
);
3631 link
->dpcd_caps
.edp_supported_link_rates_count
= 0;
3632 memset(supported_link_rates
, 0, sizeof(supported_link_rates
));
3634 if (link
->dpcd_caps
.dpcd_rev
.raw
>= DPCD_REV_14
&&
3635 (link
->dc
->config
.optimize_edp_link_rate
||
3636 link
->reported_link_cap
.link_rate
== LINK_RATE_UNKNOWN
)) {
3637 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3638 core_link_read_dpcd(link
, DP_SUPPORTED_LINK_RATES
,
3639 supported_link_rates
, sizeof(supported_link_rates
));
3641 for (entry
= 0; entry
< 16; entry
+= 2) {
3642 // DPCD register reports per-lane link rate = 16-bit link rate capability
3643 // value X 200 kHz. Need multiplier to find link rate in kHz.
3644 link_rate_in_khz
= (supported_link_rates
[entry
+1] * 0x100 +
3645 supported_link_rates
[entry
]) * 200;
3647 if (link_rate_in_khz
!= 0) {
3648 link_rate
= linkRateInKHzToLinkRateMultiplier(link_rate_in_khz
);
3649 link
->dpcd_caps
.edp_supported_link_rates
[link
->dpcd_caps
.edp_supported_link_rates_count
] = link_rate
;
3650 link
->dpcd_caps
.edp_supported_link_rates_count
++;
3652 if (link
->reported_link_cap
.link_rate
< link_rate
)
3653 link
->reported_link_cap
.link_rate
= link_rate
;
3657 link
->verified_link_cap
= link
->reported_link_cap
;
3659 dc_link_set_default_brightness_aux(link
);
3662 void dc_link_dp_enable_hpd(const struct dc_link
*link
)
3664 struct link_encoder
*encoder
= link
->link_enc
;
3666 if (encoder
!= NULL
&& encoder
->funcs
->enable_hpd
!= NULL
)
3667 encoder
->funcs
->enable_hpd(encoder
);
3670 void dc_link_dp_disable_hpd(const struct dc_link
*link
)
3672 struct link_encoder
*encoder
= link
->link_enc
;
3674 if (encoder
!= NULL
&& encoder
->funcs
->enable_hpd
!= NULL
)
3675 encoder
->funcs
->disable_hpd(encoder
);
3678 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern
)
3680 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN
<= test_pattern
&&
3681 test_pattern
<= DP_TEST_PATTERN_PHY_PATTERN_END
) ||
3682 test_pattern
== DP_TEST_PATTERN_VIDEO_MODE
)
3688 static void set_crtc_test_pattern(struct dc_link
*link
,
3689 struct pipe_ctx
*pipe_ctx
,
3690 enum dp_test_pattern test_pattern
,
3691 enum dp_test_pattern_color_space test_pattern_color_space
)
3693 enum controller_dp_test_pattern controller_test_pattern
;
3694 enum dc_color_depth color_depth
= pipe_ctx
->
3695 stream
->timing
.display_color_depth
;
3696 struct bit_depth_reduction_params params
;
3697 struct output_pixel_processor
*opp
= pipe_ctx
->stream_res
.opp
;
3698 int width
= pipe_ctx
->stream
->timing
.h_addressable
+
3699 pipe_ctx
->stream
->timing
.h_border_left
+
3700 pipe_ctx
->stream
->timing
.h_border_right
;
3701 int height
= pipe_ctx
->stream
->timing
.v_addressable
+
3702 pipe_ctx
->stream
->timing
.v_border_bottom
+
3703 pipe_ctx
->stream
->timing
.v_border_top
;
3705 memset(¶ms
, 0, sizeof(params
));
3707 switch (test_pattern
) {
3708 case DP_TEST_PATTERN_COLOR_SQUARES
:
3709 controller_test_pattern
=
3710 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES
;
3712 case DP_TEST_PATTERN_COLOR_SQUARES_CEA
:
3713 controller_test_pattern
=
3714 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
;
3716 case DP_TEST_PATTERN_VERTICAL_BARS
:
3717 controller_test_pattern
=
3718 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS
;
3720 case DP_TEST_PATTERN_HORIZONTAL_BARS
:
3721 controller_test_pattern
=
3722 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS
;
3724 case DP_TEST_PATTERN_COLOR_RAMP
:
3725 controller_test_pattern
=
3726 CONTROLLER_DP_TEST_PATTERN_COLORRAMP
;
3729 controller_test_pattern
=
3730 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE
;
3734 switch (test_pattern
) {
3735 case DP_TEST_PATTERN_COLOR_SQUARES
:
3736 case DP_TEST_PATTERN_COLOR_SQUARES_CEA
:
3737 case DP_TEST_PATTERN_VERTICAL_BARS
:
3738 case DP_TEST_PATTERN_HORIZONTAL_BARS
:
3739 case DP_TEST_PATTERN_COLOR_RAMP
:
3741 /* disable bit depth reduction */
3742 pipe_ctx
->stream
->bit_depth_params
= params
;
3743 opp
->funcs
->opp_program_bit_depth_reduction(opp
, ¶ms
);
3744 if (pipe_ctx
->stream_res
.tg
->funcs
->set_test_pattern
)
3745 pipe_ctx
->stream_res
.tg
->funcs
->set_test_pattern(pipe_ctx
->stream_res
.tg
,
3746 controller_test_pattern
, color_depth
);
3747 else if (opp
->funcs
->opp_set_disp_pattern_generator
) {
3748 struct pipe_ctx
*odm_pipe
;
3749 enum controller_dp_color_space controller_color_space
;
3752 int dpg_width
= width
;
3754 switch (test_pattern_color_space
) {
3755 case DP_TEST_PATTERN_COLOR_SPACE_RGB
:
3756 controller_color_space
= CONTROLLER_DP_COLOR_SPACE_RGB
;
3758 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601
:
3759 controller_color_space
= CONTROLLER_DP_COLOR_SPACE_YCBCR601
;
3761 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709
:
3762 controller_color_space
= CONTROLLER_DP_COLOR_SPACE_YCBCR709
;
3764 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
:
3766 controller_color_space
= CONTROLLER_DP_COLOR_SPACE_UDEFINED
;
3767 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__
);
3772 for (odm_pipe
= pipe_ctx
->next_odm_pipe
; odm_pipe
; odm_pipe
= odm_pipe
->next_odm_pipe
)
3774 dpg_width
= width
/ opp_cnt
;
3777 opp
->funcs
->opp_set_disp_pattern_generator(opp
,
3778 controller_test_pattern
,
3779 controller_color_space
,
3786 for (odm_pipe
= pipe_ctx
->next_odm_pipe
; odm_pipe
; odm_pipe
= odm_pipe
->next_odm_pipe
) {
3787 struct output_pixel_processor
*odm_opp
= odm_pipe
->stream_res
.opp
;
3788 odm_opp
->funcs
->opp_program_bit_depth_reduction(odm_opp
, ¶ms
);
3789 odm_opp
->funcs
->opp_set_disp_pattern_generator(odm_opp
,
3790 controller_test_pattern
,
3791 controller_color_space
,
3802 case DP_TEST_PATTERN_VIDEO_MODE
:
3804 /* restore bitdepth reduction */
3805 resource_build_bit_depth_reduction_params(pipe_ctx
->stream
, ¶ms
);
3806 pipe_ctx
->stream
->bit_depth_params
= params
;
3807 opp
->funcs
->opp_program_bit_depth_reduction(opp
, ¶ms
);
3808 if (pipe_ctx
->stream_res
.tg
->funcs
->set_test_pattern
)
3809 pipe_ctx
->stream_res
.tg
->funcs
->set_test_pattern(pipe_ctx
->stream_res
.tg
,
3810 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE
,
3812 else if (opp
->funcs
->opp_set_disp_pattern_generator
) {
3813 struct pipe_ctx
*odm_pipe
;
3815 int dpg_width
= width
;
3817 for (odm_pipe
= pipe_ctx
->next_odm_pipe
; odm_pipe
; odm_pipe
= odm_pipe
->next_odm_pipe
)
3820 dpg_width
= width
/ opp_cnt
;
3821 for (odm_pipe
= pipe_ctx
->next_odm_pipe
; odm_pipe
; odm_pipe
= odm_pipe
->next_odm_pipe
) {
3822 struct output_pixel_processor
*odm_opp
= odm_pipe
->stream_res
.opp
;
3824 odm_opp
->funcs
->opp_program_bit_depth_reduction(odm_opp
, ¶ms
);
3825 odm_opp
->funcs
->opp_set_disp_pattern_generator(odm_opp
,
3826 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE
,
3827 CONTROLLER_DP_COLOR_SPACE_UDEFINED
,
3834 opp
->funcs
->opp_set_disp_pattern_generator(opp
,
3835 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE
,
3836 CONTROLLER_DP_COLOR_SPACE_UDEFINED
,
3851 bool dc_link_dp_set_test_pattern(
3852 struct dc_link
*link
,
3853 enum dp_test_pattern test_pattern
,
3854 enum dp_test_pattern_color_space test_pattern_color_space
,
3855 const struct link_training_settings
*p_link_settings
,
3856 const unsigned char *p_custom_pattern
,
3857 unsigned int cust_pattern_size
)
3859 struct pipe_ctx
*pipes
= link
->dc
->current_state
->res_ctx
.pipe_ctx
;
3860 struct pipe_ctx
*pipe_ctx
= &pipes
[0];
3863 unsigned char link_qual_pattern
[LANE_COUNT_DP_MAX
] = {0};
3864 union dpcd_training_pattern training_pattern
;
3865 enum dpcd_phy_test_patterns pattern
;
3867 memset(&training_pattern
, 0, sizeof(training_pattern
));
3869 for (i
= 0; i
< MAX_PIPES
; i
++) {
3870 if (pipes
[i
].stream
->link
== link
&& !pipes
[i
].top_pipe
&& !pipes
[i
].prev_odm_pipe
) {
3871 pipe_ctx
= &pipes
[i
];
3876 /* Reset CRTC Test Pattern if it is currently running and request
3877 * is VideoMode Reset DP Phy Test Pattern if it is currently running
3878 * and request is VideoMode
3880 if (link
->test_pattern_enabled
&& test_pattern
==
3881 DP_TEST_PATTERN_VIDEO_MODE
) {
3882 /* Set CRTC Test Pattern */
3883 set_crtc_test_pattern(link
, pipe_ctx
, test_pattern
, test_pattern_color_space
);
3884 dp_set_hw_test_pattern(link
, test_pattern
,
3885 (uint8_t *)p_custom_pattern
,
3886 (uint32_t)cust_pattern_size
);
3888 /* Unblank Stream */
3889 link
->dc
->hwss
.unblank_stream(
3891 &link
->verified_link_cap
);
3892 /* TODO:m_pHwss->MuteAudioEndpoint
3893 * (pPathMode->pDisplayPath, false);
3896 /* Reset Test Pattern state */
3897 link
->test_pattern_enabled
= false;
3902 /* Check for PHY Test Patterns */
3903 if (is_dp_phy_pattern(test_pattern
)) {
3904 /* Set DPCD Lane Settings before running test pattern */
3905 if (p_link_settings
!= NULL
) {
3906 dp_set_hw_lane_settings(link
, p_link_settings
, DPRX
);
3907 dpcd_set_lane_settings(link
, p_link_settings
, DPRX
);
3910 /* Blank stream if running test pattern */
3911 if (test_pattern
!= DP_TEST_PATTERN_VIDEO_MODE
) {
3914 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
3917 pipes
->stream_res
.stream_enc
->funcs
->dp_blank(pipe_ctx
->stream_res
.stream_enc
);
3920 dp_set_hw_test_pattern(link
, test_pattern
,
3921 (uint8_t *)p_custom_pattern
,
3922 (uint32_t)cust_pattern_size
);
3924 if (test_pattern
!= DP_TEST_PATTERN_VIDEO_MODE
) {
3925 /* Set Test Pattern state */
3926 link
->test_pattern_enabled
= true;
3927 if (p_link_settings
!= NULL
)
3928 dpcd_set_link_settings(link
,
3932 switch (test_pattern
) {
3933 case DP_TEST_PATTERN_VIDEO_MODE
:
3934 pattern
= PHY_TEST_PATTERN_NONE
;
3936 case DP_TEST_PATTERN_D102
:
3937 pattern
= PHY_TEST_PATTERN_D10_2
;
3939 case DP_TEST_PATTERN_SYMBOL_ERROR
:
3940 pattern
= PHY_TEST_PATTERN_SYMBOL_ERROR
;
3942 case DP_TEST_PATTERN_PRBS7
:
3943 pattern
= PHY_TEST_PATTERN_PRBS7
;
3945 case DP_TEST_PATTERN_80BIT_CUSTOM
:
3946 pattern
= PHY_TEST_PATTERN_80BIT_CUSTOM
;
3948 case DP_TEST_PATTERN_CP2520_1
:
3949 pattern
= PHY_TEST_PATTERN_CP2520_1
;
3951 case DP_TEST_PATTERN_CP2520_2
:
3952 pattern
= PHY_TEST_PATTERN_CP2520_2
;
3954 case DP_TEST_PATTERN_CP2520_3
:
3955 pattern
= PHY_TEST_PATTERN_CP2520_3
;
3961 if (test_pattern
== DP_TEST_PATTERN_VIDEO_MODE
3962 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
3965 if (link
->dpcd_caps
.dpcd_rev
.raw
>= DPCD_REV_12
) {
3966 /* tell receiver that we are sending qualification
3967 * pattern DP 1.2 or later - DP receiver's link quality
3968 * pattern is set using DPCD LINK_QUAL_LANEx_SET
3969 * register (0x10B~0x10E)\
3971 for (lane
= 0; lane
< LANE_COUNT_DP_MAX
; lane
++)
3972 link_qual_pattern
[lane
] =
3973 (unsigned char)(pattern
);
3975 core_link_write_dpcd(link
,
3976 DP_LINK_QUAL_LANE0_SET
,
3978 sizeof(link_qual_pattern
));
3979 } else if (link
->dpcd_caps
.dpcd_rev
.raw
>= DPCD_REV_10
||
3980 link
->dpcd_caps
.dpcd_rev
.raw
== 0) {
3981 /* tell receiver that we are sending qualification
3982 * pattern DP 1.1a or earlier - DP receiver's link
3983 * quality pattern is set using
3984 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
3985 * register (0x102). We will use v_1.3 when we are
3986 * setting test pattern for DP 1.1.
3988 core_link_read_dpcd(link
, DP_TRAINING_PATTERN_SET
,
3989 &training_pattern
.raw
,
3990 sizeof(training_pattern
));
3991 training_pattern
.v1_3
.LINK_QUAL_PATTERN_SET
= pattern
;
3992 core_link_write_dpcd(link
, DP_TRAINING_PATTERN_SET
,
3993 &training_pattern
.raw
,
3994 sizeof(training_pattern
));
3997 enum dc_color_space color_space
= COLOR_SPACE_UNKNOWN
;
3999 switch (test_pattern_color_space
) {
4000 case DP_TEST_PATTERN_COLOR_SPACE_RGB
:
4001 color_space
= COLOR_SPACE_SRGB
;
4002 if (test_pattern
== DP_TEST_PATTERN_COLOR_SQUARES_CEA
)
4003 color_space
= COLOR_SPACE_SRGB_LIMITED
;
4006 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601
:
4007 color_space
= COLOR_SPACE_YCBCR601
;
4008 if (test_pattern
== DP_TEST_PATTERN_COLOR_SQUARES_CEA
)
4009 color_space
= COLOR_SPACE_YCBCR601_LIMITED
;
4011 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709
:
4012 color_space
= COLOR_SPACE_YCBCR709
;
4013 if (test_pattern
== DP_TEST_PATTERN_COLOR_SQUARES_CEA
)
4014 color_space
= COLOR_SPACE_YCBCR709_LIMITED
;
4020 if (pipe_ctx
->stream_res
.tg
->funcs
->lock_doublebuffer_enable
)
4021 pipe_ctx
->stream_res
.tg
->funcs
->lock_doublebuffer_enable(
4022 pipe_ctx
->stream_res
.tg
);
4023 pipe_ctx
->stream_res
.tg
->funcs
->lock(pipe_ctx
->stream_res
.tg
);
4024 /* update MSA to requested color space */
4025 pipe_ctx
->stream_res
.stream_enc
->funcs
->dp_set_stream_attribute(pipe_ctx
->stream_res
.stream_enc
,
4026 &pipe_ctx
->stream
->timing
,
4028 pipe_ctx
->stream
->use_vsc_sdp_for_colorimetry
,
4029 link
->dpcd_caps
.dprx_feature
.bits
.SST_SPLIT_SDP_CAP
);
4031 if (pipe_ctx
->stream
->use_vsc_sdp_for_colorimetry
) {
4032 if (test_pattern
== DP_TEST_PATTERN_COLOR_SQUARES_CEA
)
4033 pipe_ctx
->stream
->vsc_infopacket
.sb
[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4035 pipe_ctx
->stream
->vsc_infopacket
.sb
[17] &= ~(1 << 7);
4036 resource_build_info_frame(pipe_ctx
);
4037 link
->dc
->hwss
.update_info_frame(pipe_ctx
);
4041 set_crtc_test_pattern(link
, pipe_ctx
, test_pattern
, test_pattern_color_space
);
4042 pipe_ctx
->stream_res
.tg
->funcs
->unlock(pipe_ctx
->stream_res
.tg
);
4043 pipe_ctx
->stream_res
.tg
->funcs
->wait_for_state(pipe_ctx
->stream_res
.tg
,
4044 CRTC_STATE_VACTIVE
);
4045 pipe_ctx
->stream_res
.tg
->funcs
->wait_for_state(pipe_ctx
->stream_res
.tg
,
4047 pipe_ctx
->stream_res
.tg
->funcs
->wait_for_state(pipe_ctx
->stream_res
.tg
,
4048 CRTC_STATE_VACTIVE
);
4049 if (pipe_ctx
->stream_res
.tg
->funcs
->lock_doublebuffer_disable
)
4050 pipe_ctx
->stream_res
.tg
->funcs
->lock_doublebuffer_disable(
4051 pipe_ctx
->stream_res
.tg
);
4052 /* Set Test Pattern state */
4053 link
->test_pattern_enabled
= true;
4059 void dp_enable_mst_on_sink(struct dc_link
*link
, bool enable
)
4061 unsigned char mstmCntl
;
4063 core_link_read_dpcd(link
, DP_MSTM_CTRL
, &mstmCntl
, 1);
4065 mstmCntl
|= DP_MST_EN
;
4067 mstmCntl
&= (~DP_MST_EN
);
4069 core_link_write_dpcd(link
, DP_MSTM_CTRL
, &mstmCntl
, 1);
4072 void dp_set_panel_mode(struct dc_link
*link
, enum dp_panel_mode panel_mode
)
4074 union dpcd_edp_config edp_config_set
;
4075 bool panel_mode_edp
= false;
4077 memset(&edp_config_set
, '\0', sizeof(union dpcd_edp_config
));
4079 if (panel_mode
!= DP_PANEL_MODE_DEFAULT
) {
4081 switch (panel_mode
) {
4082 case DP_PANEL_MODE_EDP
:
4083 case DP_PANEL_MODE_SPECIAL
:
4084 panel_mode_edp
= true;
4091 /*set edp panel mode in receiver*/
4092 core_link_read_dpcd(
4094 DP_EDP_CONFIGURATION_SET
,
4095 &edp_config_set
.raw
,
4096 sizeof(edp_config_set
.raw
));
4098 if (edp_config_set
.bits
.PANEL_MODE_EDP
4099 != panel_mode_edp
) {
4100 enum ddc_result result
= DDC_RESULT_UNKNOWN
;
4102 edp_config_set
.bits
.PANEL_MODE_EDP
=
4104 result
= core_link_write_dpcd(
4106 DP_EDP_CONFIGURATION_SET
,
4107 &edp_config_set
.raw
,
4108 sizeof(edp_config_set
.raw
));
4110 ASSERT(result
== DDC_RESULT_SUCESSFULL
);
4113 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4114 "eDP panel mode enabled: %d \n",
4116 link
->dpcd_caps
.panel_mode_edp
,
4120 enum dp_panel_mode
dp_get_panel_mode(struct dc_link
*link
)
4122 /* We need to explicitly check that connector
4123 * is not DP. Some Travis_VGA get reported
4124 * by video bios as DP.
4126 if (link
->connector_signal
!= SIGNAL_TYPE_DISPLAY_PORT
) {
4128 switch (link
->dpcd_caps
.branch_dev_id
) {
4129 case DP_BRANCH_DEVICE_ID_0022B9
:
4130 /* alternate scrambler reset is required for Travis
4131 * for the case when external chip does not
4132 * provide sink device id, alternate scrambler
4133 * scheme will be overriden later by querying
4137 link
->dpcd_caps
.branch_dev_name
,
4138 DP_VGA_LVDS_CONVERTER_ID_2
,
4141 branch_dev_name
)) == 0) {
4142 return DP_PANEL_MODE_SPECIAL
;
4145 case DP_BRANCH_DEVICE_ID_00001A
:
4146 /* alternate scrambler reset is required for Travis
4147 * for the case when external chip does not provide
4148 * sink device id, alternate scrambler scheme will
4149 * be overriden later by querying Encoder feature
4151 if (strncmp(link
->dpcd_caps
.branch_dev_name
,
4152 DP_VGA_LVDS_CONVERTER_ID_3
,
4155 branch_dev_name
)) == 0) {
4156 return DP_PANEL_MODE_SPECIAL
;
4164 if (link
->dpcd_caps
.panel_mode_edp
) {
4165 return DP_PANEL_MODE_EDP
;
4168 return DP_PANEL_MODE_DEFAULT
;
4171 void dp_set_fec_ready(struct dc_link
*link
, bool ready
)
4173 /* FEC has to be "set ready" before the link training.
4174 * The policy is to always train with FEC
4175 * if the sink supports it and leave it enabled on link.
4176 * If FEC is not supported, disable it.
4178 struct link_encoder
*link_enc
= link
->link_enc
;
4179 uint8_t fec_config
= 0;
4181 if (!dc_link_is_fec_supported(link
) || link
->dc
->debug
.disable_fec
)
4184 if (link_enc
->funcs
->fec_set_ready
&&
4185 link
->dpcd_caps
.fec_cap
.bits
.FEC_CAPABLE
) {
4188 if (core_link_write_dpcd(link
,
4189 DP_FEC_CONFIGURATION
,
4191 sizeof(fec_config
)) == DC_OK
) {
4192 link_enc
->funcs
->fec_set_ready(link_enc
, true);
4193 link
->fec_state
= dc_link_fec_ready
;
4195 link
->link_enc
->funcs
->fec_set_ready(link
->link_enc
, false);
4196 link
->fec_state
= dc_link_fec_not_ready
;
4197 dm_error("dpcd write failed to set fec_ready");
4199 } else if (link
->fec_state
== dc_link_fec_ready
) {
4201 core_link_write_dpcd(link
,
4202 DP_FEC_CONFIGURATION
,
4204 sizeof(fec_config
));
4205 link
->link_enc
->funcs
->fec_set_ready(
4206 link
->link_enc
, false);
4207 link
->fec_state
= dc_link_fec_not_ready
;
4212 void dp_set_fec_enable(struct dc_link
*link
, bool enable
)
4214 struct link_encoder
*link_enc
= link
->link_enc
;
4216 if (!dc_link_is_fec_supported(link
) || link
->dc
->debug
.disable_fec
)
4219 if (link_enc
->funcs
->fec_set_enable
&&
4220 link
->dpcd_caps
.fec_cap
.bits
.FEC_CAPABLE
) {
4221 if (link
->fec_state
== dc_link_fec_ready
&& enable
) {
4222 /* Accord to DP spec, FEC enable sequence can first
4223 * be transmitted anytime after 1000 LL codes have
4224 * been transmitted on the link after link training
4225 * completion. Using 1 lane RBR should have the maximum
4226 * time for transmitting 1000 LL codes which is 6.173 us.
4227 * So use 7 microseconds delay instead.
4230 link_enc
->funcs
->fec_set_enable(link_enc
, true);
4231 link
->fec_state
= dc_link_fec_enabled
;
4232 } else if (link
->fec_state
== dc_link_fec_enabled
&& !enable
) {
4233 link_enc
->funcs
->fec_set_enable(link_enc
, false);
4234 link
->fec_state
= dc_link_fec_ready
;
4239 void dpcd_set_source_specific_data(struct dc_link
*link
)
4241 const uint32_t post_oui_delay
= 30; // 30ms
4243 enum dc_status ret
= DC_ERROR_UNEXPECTED
;
4245 ret
= core_link_read_dpcd(link
, DP_DOWN_STREAM_PORT_COUNT
, &dspc
,
4249 DC_LOG_ERROR("Error in DP aux read transaction,"
4250 " not writing source specific data\n");
4254 /* Return if OUI unsupported */
4255 if (!(dspc
& DP_OUI_SUPPORT
))
4258 if (!link
->dc
->vendor_signature
.is_valid
) {
4259 struct dpcd_amd_signature amd_signature
;
4260 amd_signature
.AMD_IEEE_TxSignature_byte1
= 0x0;
4261 amd_signature
.AMD_IEEE_TxSignature_byte2
= 0x0;
4262 amd_signature
.AMD_IEEE_TxSignature_byte3
= 0x1A;
4263 amd_signature
.device_id_byte1
=
4264 (uint8_t)(link
->ctx
->asic_id
.chip_id
);
4265 amd_signature
.device_id_byte2
=
4266 (uint8_t)(link
->ctx
->asic_id
.chip_id
>> 8);
4267 memset(&amd_signature
.zero
, 0, 4);
4268 amd_signature
.dce_version
=
4269 (uint8_t)(link
->ctx
->dce_version
);
4270 amd_signature
.dal_version_byte1
= 0x0; // needed? where to get?
4271 amd_signature
.dal_version_byte2
= 0x0; // needed? where to get?
4273 core_link_write_dpcd(link
, DP_SOURCE_OUI
,
4274 (uint8_t *)(&amd_signature
),
4275 sizeof(amd_signature
));
4278 core_link_write_dpcd(link
, DP_SOURCE_OUI
,
4279 link
->dc
->vendor_signature
.data
.raw
,
4280 sizeof(link
->dc
->vendor_signature
.data
.raw
));
4283 // Sink may need to configure internals based on vendor, so allow some
4284 // time before proceeding with possibly vendor specific transactions
4285 msleep(post_oui_delay
);
4288 bool dc_link_set_backlight_level_nits(struct dc_link
*link
,
4290 uint32_t backlight_millinits
,
4291 uint32_t transition_time_in_ms
)
4293 struct dpcd_source_backlight_set dpcd_backlight_set
;
4294 uint8_t backlight_control
= isHDR
? 1 : 0;
4296 if (!link
|| (link
->connector_signal
!= SIGNAL_TYPE_EDP
&&
4297 link
->connector_signal
!= SIGNAL_TYPE_DISPLAY_PORT
))
4300 // OLEDs have no PWM, they can only use AUX
4301 if (link
->dpcd_sink_ext_caps
.bits
.oled
== 1)
4302 backlight_control
= 1;
4304 *(uint32_t *)&dpcd_backlight_set
.backlight_level_millinits
= backlight_millinits
;
4305 *(uint16_t *)&dpcd_backlight_set
.backlight_transition_time_ms
= (uint16_t)transition_time_in_ms
;
4308 if (core_link_write_dpcd(link
, DP_SOURCE_BACKLIGHT_LEVEL
,
4309 (uint8_t *)(&dpcd_backlight_set
),
4310 sizeof(dpcd_backlight_set
)) != DC_OK
)
4313 if (core_link_write_dpcd(link
, DP_SOURCE_BACKLIGHT_CONTROL
,
4314 &backlight_control
, 1) != DC_OK
)
4320 bool dc_link_get_backlight_level_nits(struct dc_link
*link
,
4321 uint32_t *backlight_millinits_avg
,
4322 uint32_t *backlight_millinits_peak
)
4324 union dpcd_source_backlight_get dpcd_backlight_get
;
4326 memset(&dpcd_backlight_get
, 0, sizeof(union dpcd_source_backlight_get
));
4328 if (!link
|| (link
->connector_signal
!= SIGNAL_TYPE_EDP
&&
4329 link
->connector_signal
!= SIGNAL_TYPE_DISPLAY_PORT
))
4332 if (!core_link_read_dpcd(link
, DP_SOURCE_BACKLIGHT_CURRENT_PEAK
,
4333 dpcd_backlight_get
.raw
,
4334 sizeof(union dpcd_source_backlight_get
)))
4337 *backlight_millinits_avg
=
4338 dpcd_backlight_get
.bytes
.backlight_millinits_avg
;
4339 *backlight_millinits_peak
=
4340 dpcd_backlight_get
.bytes
.backlight_millinits_peak
;
4342 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4343 if (*backlight_millinits_avg
== 0 ||
4344 *backlight_millinits_avg
> *backlight_millinits_peak
)
4350 bool dc_link_backlight_enable_aux(struct dc_link
*link
, bool enable
)
4352 uint8_t backlight_enable
= enable
? 1 : 0;
4354 if (!link
|| (link
->connector_signal
!= SIGNAL_TYPE_EDP
&&
4355 link
->connector_signal
!= SIGNAL_TYPE_DISPLAY_PORT
))
4358 if (core_link_write_dpcd(link
, DP_SOURCE_BACKLIGHT_ENABLE
,
4359 &backlight_enable
, 1) != DC_OK
)
4365 // we read default from 0x320 because we expect BIOS wrote it there
4366 // regular get_backlight_nit reads from panel set at 0x326
4367 bool dc_link_read_default_bl_aux(struct dc_link
*link
, uint32_t *backlight_millinits
)
4369 if (!link
|| (link
->connector_signal
!= SIGNAL_TYPE_EDP
&&
4370 link
->connector_signal
!= SIGNAL_TYPE_DISPLAY_PORT
))
4373 if (!core_link_read_dpcd(link
, DP_SOURCE_BACKLIGHT_LEVEL
,
4374 (uint8_t *) backlight_millinits
,
4381 bool dc_link_set_default_brightness_aux(struct dc_link
*link
)
4383 uint32_t default_backlight
;
4386 (link
->dpcd_sink_ext_caps
.bits
.hdr_aux_backlight_control
== 1 ||
4387 link
->dpcd_sink_ext_caps
.bits
.sdr_aux_backlight_control
== 1)) {
4388 if (!dc_link_read_default_bl_aux(link
, &default_backlight
))
4389 default_backlight
= 150000;
4390 // if < 5 nits or > 5000, it might be wrong readback
4391 if (default_backlight
< 5000 || default_backlight
> 5000000)
4392 default_backlight
= 150000; //
4394 return dc_link_set_backlight_level_nits(link
, true,
4395 default_backlight
, 0);