drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DAL_AUX_ENGINE_DCE110_H__
  27 #define __DAL_AUX_ENGINE_DCE110_H__
  28
  29 #include "i2caux_interface.h"
  30 #include "inc/hw/aux_engine.h"
  31
  32 #define AUX_COMMON_REG_LIST(id)\
  33         SRI(AUX_CONTROL, DP_AUX, id), \
  34         SRI(AUX_ARB_CONTROL, DP_AUX, id), \
  35         SRI(AUX_SW_DATA, DP_AUX, id), \
  36         SRI(AUX_SW_CONTROL, DP_AUX, id), \
  37         SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
  38         SRI(AUX_SW_STATUS, DP_AUX, id), \
  39         SR(AUXN_IMPCAL), \
  40         SR(AUXP_IMPCAL)
  41
  42 struct dce110_aux_registers {
  43         uint32_t AUX_CONTROL;
  44         uint32_t AUX_ARB_CONTROL;
  45         uint32_t AUX_SW_DATA;
  46         uint32_t AUX_SW_CONTROL;
  47         uint32_t AUX_INTERRUPT_CONTROL;
  48         uint32_t AUX_SW_STATUS;
  49         uint32_t AUXN_IMPCAL;
  50         uint32_t AUXP_IMPCAL;
  51
  52         uint32_t AUX_RESET_MASK;
  53 };
  54
  55 enum {  /* This is the timeout as defined in DP 1.2a,
  56          * 2.3.4 "Detailed uPacket TX AUX CH State Description".
  57          */
  58         AUX_TIMEOUT_PERIOD = 400,
  59
  60         /* Ideally, the SW timeout should be just above 550usec
  61          * which is programmed in HW.
  62          * But the SW timeout of 600usec is not reliable,
  63          * because on some systems, delay_in_microseconds()
  64          * returns faster than it should.
  65          * EPR #379763: by trial-and-error on different systems,
  66          * 700usec is the minimum reliable SW timeout for polling
  67          * the AUX_SW_STATUS.AUX_SW_DONE bit.
  68          * This timeout expires *only* when there is
  69          * AUX Error or AUX Timeout conditions - not during normal operation.
  70          * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
  71          * at most within ~240usec. That means,
  72          * increasing this timeout will not affect normal operation,
  73          * and we'll timeout after
  74          * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
  75          * This timeout is especially important for
  76          * resume from S3 and CTS.
  77          */
  78         SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
  79 };
  80
  81 struct dce_aux {
  82         uint32_t inst;
  83         struct ddc *ddc;
  84         struct dc_context *ctx;
  85         /* following values are expressed in milliseconds */
  86         uint32_t delay;
  87         uint32_t max_defer_write_retry;
  88
  89         bool acquire_reset;
  90 };
  91
  92 struct aux_engine_dce110 {
  93         struct dce_aux base;
  94         const struct dce110_aux_registers *regs;
  95         struct {
  96                 uint32_t aux_control;
  97                 uint32_t aux_arb_control;
  98                 uint32_t aux_sw_data;
  99                 uint32_t aux_sw_control;
 100                 uint32_t aux_interrupt_control;
 101                 uint32_t aux_sw_status;
 102         } addr;
 103         uint32_t timeout_period;
 104 };
 105
 106 struct aux_engine_dce110_init_data {
 107         uint32_t engine_id;
 108         uint32_t timeout_period;
 109         struct dc_context *ctx;
 110         const struct dce110_aux_registers *regs;
 111 };
 112
 113 struct dce_aux *dce110_aux_engine_construct(
 114                 struct aux_engine_dce110 *aux_engine110,
 115                 struct dc_context *ctx,
 116                 uint32_t inst,
 117                 uint32_t timeout_period,
 118                 const struct dce110_aux_registers *regs);
 119
 120 void dce110_engine_destroy(struct dce_aux **engine);
 121
 122 bool dce110_aux_engine_acquire(
 123         struct dce_aux *aux_engine,
 124         struct ddc *ddc);
 125
 126 int dce_aux_transfer(struct ddc_service *ddc,
 127                 struct aux_payload *cmd);
 128
 129 bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 130                 struct aux_payload *cmd);
 131 #endif