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Merge tag 'drm/tegra/for-5.7-fixes' of git://anongit.freedesktop.org/tegra/linux...
[thirdparty/linux.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/delay.h>
27
28 #include "dm_services.h"
29 #include "dc.h"
30 #include "dc_bios_types.h"
31 #include "core_types.h"
32 #include "core_status.h"
33 #include "resource.h"
34 #include "dm_helpers.h"
35 #include "dce110_hw_sequencer.h"
36 #include "dce110_timing_generator.h"
37 #include "dce/dce_hwseq.h"
38 #include "gpio_service_interface.h"
39
40 #include "dce110_compressor.h"
41
42 #include "bios/bios_parser_helper.h"
43 #include "timing_generator.h"
44 #include "mem_input.h"
45 #include "opp.h"
46 #include "ipp.h"
47 #include "transform.h"
48 #include "stream_encoder.h"
49 #include "link_encoder.h"
50 #include "link_hwss.h"
51 #include "clock_source.h"
52 #include "clk_mgr.h"
53 #include "abm.h"
54 #include "audio.h"
55 #include "reg_helper.h"
56
57 /* include DCE11 register header files */
58 #include "dce/dce_11_0_d.h"
59 #include "dce/dce_11_0_sh_mask.h"
60 #include "custom_float.h"
61
62 #include "atomfirmware.h"
63
64 #define GAMMA_HW_POINTS_NUM 256
65
66 /*
67 * All values are in milliseconds;
68 * For eDP, after power-up/power/down,
69 * 300/500 msec max. delay from LCDVCC to black video generation
70 */
71 #define PANEL_POWER_UP_TIMEOUT 300
72 #define PANEL_POWER_DOWN_TIMEOUT 500
73 #define HPD_CHECK_INTERVAL 10
74 #define OLED_POST_T7_DELAY 100
75 #define OLED_PRE_T11_DELAY 150
76
77 #define CTX \
78 hws->ctx
79
80 #define DC_LOGGER_INIT()
81
82 #define REG(reg)\
83 hws->regs->reg
84
85 #undef FN
86 #define FN(reg_name, field_name) \
87 hws->shifts->field_name, hws->masks->field_name
88
89 struct dce110_hw_seq_reg_offsets {
90 uint32_t crtc;
91 };
92
93 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
94 {
95 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
96 },
97 {
98 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
99 },
100 {
101 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
102 },
103 {
104 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
105 }
106 };
107
108 #define HW_REG_BLND(reg, id)\
109 (reg + reg_offsets[id].blnd)
110
111 #define HW_REG_CRTC(reg, id)\
112 (reg + reg_offsets[id].crtc)
113
114 #define MAX_WATERMARK 0xFFFF
115 #define SAFE_NBP_MARK 0x7FFF
116
117 /*******************************************************************************
118 * Private definitions
119 ******************************************************************************/
120 /***************************PIPE_CONTROL***********************************/
121 static void dce110_init_pte(struct dc_context *ctx)
122 {
123 uint32_t addr;
124 uint32_t value = 0;
125 uint32_t chunk_int = 0;
126 uint32_t chunk_mul = 0;
127
128 addr = mmUNP_DVMM_PTE_CONTROL;
129 value = dm_read_reg(ctx, addr);
130
131 set_reg_field_value(
132 value,
133 0,
134 DVMM_PTE_CONTROL,
135 DVMM_USE_SINGLE_PTE);
136
137 set_reg_field_value(
138 value,
139 1,
140 DVMM_PTE_CONTROL,
141 DVMM_PTE_BUFFER_MODE0);
142
143 set_reg_field_value(
144 value,
145 1,
146 DVMM_PTE_CONTROL,
147 DVMM_PTE_BUFFER_MODE1);
148
149 dm_write_reg(ctx, addr, value);
150
151 addr = mmDVMM_PTE_REQ;
152 value = dm_read_reg(ctx, addr);
153
154 chunk_int = get_reg_field_value(
155 value,
156 DVMM_PTE_REQ,
157 HFLIP_PTEREQ_PER_CHUNK_INT);
158
159 chunk_mul = get_reg_field_value(
160 value,
161 DVMM_PTE_REQ,
162 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
163
164 if (chunk_int != 0x4 || chunk_mul != 0x4) {
165
166 set_reg_field_value(
167 value,
168 255,
169 DVMM_PTE_REQ,
170 MAX_PTEREQ_TO_ISSUE);
171
172 set_reg_field_value(
173 value,
174 4,
175 DVMM_PTE_REQ,
176 HFLIP_PTEREQ_PER_CHUNK_INT);
177
178 set_reg_field_value(
179 value,
180 4,
181 DVMM_PTE_REQ,
182 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
183
184 dm_write_reg(ctx, addr, value);
185 }
186 }
187 /**************************************************************************/
188
189 static void enable_display_pipe_clock_gating(
190 struct dc_context *ctx,
191 bool clock_gating)
192 {
193 /*TODO*/
194 }
195
196 static bool dce110_enable_display_power_gating(
197 struct dc *dc,
198 uint8_t controller_id,
199 struct dc_bios *dcb,
200 enum pipe_gating_control power_gating)
201 {
202 enum bp_result bp_result = BP_RESULT_OK;
203 enum bp_pipe_control_action cntl;
204 struct dc_context *ctx = dc->ctx;
205 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
206
207 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
208 return true;
209
210 if (power_gating == PIPE_GATING_CONTROL_INIT)
211 cntl = ASIC_PIPE_INIT;
212 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
213 cntl = ASIC_PIPE_ENABLE;
214 else
215 cntl = ASIC_PIPE_DISABLE;
216
217 if (controller_id == underlay_idx)
218 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
219
220 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
221
222 bp_result = dcb->funcs->enable_disp_power_gating(
223 dcb, controller_id + 1, cntl);
224
225 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
226 * by default when command table is called
227 *
228 * Bios parser accepts controller_id = 6 as indicative of
229 * underlay pipe in dce110. But we do not support more
230 * than 3.
231 */
232 if (controller_id < CONTROLLER_ID_MAX - 1)
233 dm_write_reg(ctx,
234 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
235 0);
236 }
237
238 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
239 dce110_init_pte(ctx);
240
241 if (bp_result == BP_RESULT_OK)
242 return true;
243 else
244 return false;
245 }
246
247 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
248 const struct dc_plane_state *plane_state)
249 {
250 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
251
252 switch (plane_state->format) {
253 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
254 prescale_params->scale = 0x2082;
255 break;
256 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
257 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
258 prescale_params->scale = 0x2020;
259 break;
260 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
261 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
262 prescale_params->scale = 0x2008;
263 break;
264 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
265 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
266 prescale_params->scale = 0x2000;
267 break;
268 default:
269 ASSERT(false);
270 break;
271 }
272 }
273
274 static bool
275 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
276 const struct dc_plane_state *plane_state)
277 {
278 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
279 const struct dc_transfer_func *tf = NULL;
280 struct ipp_prescale_params prescale_params = { 0 };
281 bool result = true;
282
283 if (ipp == NULL)
284 return false;
285
286 if (plane_state->in_transfer_func)
287 tf = plane_state->in_transfer_func;
288
289 build_prescale_params(&prescale_params, plane_state);
290 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
291
292 if (plane_state->gamma_correction &&
293 !plane_state->gamma_correction->is_identity &&
294 dce_use_lut(plane_state->format))
295 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
296
297 if (tf == NULL) {
298 /* Default case if no input transfer function specified */
299 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
300 } else if (tf->type == TF_TYPE_PREDEFINED) {
301 switch (tf->tf) {
302 case TRANSFER_FUNCTION_SRGB:
303 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
304 break;
305 case TRANSFER_FUNCTION_BT709:
306 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
307 break;
308 case TRANSFER_FUNCTION_LINEAR:
309 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
310 break;
311 case TRANSFER_FUNCTION_PQ:
312 default:
313 result = false;
314 break;
315 }
316 } else if (tf->type == TF_TYPE_BYPASS) {
317 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
318 } else {
319 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
320 result = false;
321 }
322
323 return result;
324 }
325
326 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
327 struct curve_points *arr_points,
328 uint32_t hw_points_num)
329 {
330 struct custom_float_format fmt;
331
332 struct pwl_result_data *rgb = rgb_resulted;
333
334 uint32_t i = 0;
335
336 fmt.exponenta_bits = 6;
337 fmt.mantissa_bits = 12;
338 fmt.sign = true;
339
340 if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
341 &arr_points[0].custom_float_x)) {
342 BREAK_TO_DEBUGGER();
343 return false;
344 }
345
346 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
347 &arr_points[0].custom_float_offset)) {
348 BREAK_TO_DEBUGGER();
349 return false;
350 }
351
352 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
353 &arr_points[0].custom_float_slope)) {
354 BREAK_TO_DEBUGGER();
355 return false;
356 }
357
358 fmt.mantissa_bits = 10;
359 fmt.sign = false;
360
361 if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
362 &arr_points[1].custom_float_x)) {
363 BREAK_TO_DEBUGGER();
364 return false;
365 }
366
367 if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
368 &arr_points[1].custom_float_y)) {
369 BREAK_TO_DEBUGGER();
370 return false;
371 }
372
373 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
374 &arr_points[1].custom_float_slope)) {
375 BREAK_TO_DEBUGGER();
376 return false;
377 }
378
379 fmt.mantissa_bits = 12;
380 fmt.sign = true;
381
382 while (i != hw_points_num) {
383 if (!convert_to_custom_float_format(rgb->red, &fmt,
384 &rgb->red_reg)) {
385 BREAK_TO_DEBUGGER();
386 return false;
387 }
388
389 if (!convert_to_custom_float_format(rgb->green, &fmt,
390 &rgb->green_reg)) {
391 BREAK_TO_DEBUGGER();
392 return false;
393 }
394
395 if (!convert_to_custom_float_format(rgb->blue, &fmt,
396 &rgb->blue_reg)) {
397 BREAK_TO_DEBUGGER();
398 return false;
399 }
400
401 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
402 &rgb->delta_red_reg)) {
403 BREAK_TO_DEBUGGER();
404 return false;
405 }
406
407 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
408 &rgb->delta_green_reg)) {
409 BREAK_TO_DEBUGGER();
410 return false;
411 }
412
413 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
414 &rgb->delta_blue_reg)) {
415 BREAK_TO_DEBUGGER();
416 return false;
417 }
418
419 ++rgb;
420 ++i;
421 }
422
423 return true;
424 }
425
426 #define MAX_LOW_POINT 25
427 #define NUMBER_REGIONS 16
428 #define NUMBER_SW_SEGMENTS 16
429
430 static bool
431 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
432 struct pwl_params *regamma_params)
433 {
434 struct curve_points *arr_points;
435 struct pwl_result_data *rgb_resulted;
436 struct pwl_result_data *rgb;
437 struct pwl_result_data *rgb_plus_1;
438 struct fixed31_32 y_r;
439 struct fixed31_32 y_g;
440 struct fixed31_32 y_b;
441 struct fixed31_32 y1_min;
442 struct fixed31_32 y3_max;
443
444 int32_t region_start, region_end;
445 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
446
447 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
448 return false;
449
450 arr_points = regamma_params->arr_points;
451 rgb_resulted = regamma_params->rgb_resulted;
452 hw_points = 0;
453
454 memset(regamma_params, 0, sizeof(struct pwl_params));
455
456 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
457 /* 16 segments
458 * segments are from 2^-11 to 2^5
459 */
460 region_start = -11;
461 region_end = region_start + NUMBER_REGIONS;
462
463 for (i = 0; i < NUMBER_REGIONS; i++)
464 seg_distr[i] = 4;
465
466 } else {
467 /* 10 segments
468 * segment is from 2^-10 to 2^1
469 * We include an extra segment for range [2^0, 2^1). This is to
470 * ensure that colors with normalized values of 1 don't miss the
471 * LUT.
472 */
473 region_start = -10;
474 region_end = 1;
475
476 seg_distr[0] = 4;
477 seg_distr[1] = 4;
478 seg_distr[2] = 4;
479 seg_distr[3] = 4;
480 seg_distr[4] = 4;
481 seg_distr[5] = 4;
482 seg_distr[6] = 4;
483 seg_distr[7] = 4;
484 seg_distr[8] = 4;
485 seg_distr[9] = 4;
486 seg_distr[10] = 0;
487 seg_distr[11] = -1;
488 seg_distr[12] = -1;
489 seg_distr[13] = -1;
490 seg_distr[14] = -1;
491 seg_distr[15] = -1;
492 }
493
494 for (k = 0; k < 16; k++) {
495 if (seg_distr[k] != -1)
496 hw_points += (1 << seg_distr[k]);
497 }
498
499 j = 0;
500 for (k = 0; k < (region_end - region_start); k++) {
501 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
502 start_index = (region_start + k + MAX_LOW_POINT) *
503 NUMBER_SW_SEGMENTS;
504 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
505 i += increment) {
506 if (j == hw_points - 1)
507 break;
508 rgb_resulted[j].red = output_tf->tf_pts.red[i];
509 rgb_resulted[j].green = output_tf->tf_pts.green[i];
510 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
511 j++;
512 }
513 }
514
515 /* last point */
516 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
517 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
518 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
519 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
520
521 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
522 dc_fixpt_from_int(region_start));
523 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
524 dc_fixpt_from_int(region_end));
525
526 y_r = rgb_resulted[0].red;
527 y_g = rgb_resulted[0].green;
528 y_b = rgb_resulted[0].blue;
529
530 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
531
532 arr_points[0].y = y1_min;
533 arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
534 arr_points[0].x);
535
536 y_r = rgb_resulted[hw_points - 1].red;
537 y_g = rgb_resulted[hw_points - 1].green;
538 y_b = rgb_resulted[hw_points - 1].blue;
539
540 /* see comment above, m_arrPoints[1].y should be the Y value for the
541 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
542 */
543 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
544
545 arr_points[1].y = y3_max;
546
547 arr_points[1].slope = dc_fixpt_zero;
548
549 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
550 /* for PQ, we want to have a straight line from last HW X point,
551 * and the slope to be such that we hit 1.0 at 10000 nits.
552 */
553 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
554
555 arr_points[1].slope = dc_fixpt_div(
556 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
557 dc_fixpt_sub(end_value, arr_points[1].x));
558 }
559
560 regamma_params->hw_points_num = hw_points;
561
562 k = 0;
563 for (i = 1; i < 16; i++) {
564 if (seg_distr[k] != -1) {
565 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
566 regamma_params->arr_curve_points[i].offset =
567 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
568 }
569 k++;
570 }
571
572 if (seg_distr[k] != -1)
573 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
574
575 rgb = rgb_resulted;
576 rgb_plus_1 = rgb_resulted + 1;
577
578 i = 1;
579
580 while (i != hw_points + 1) {
581 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
582 rgb_plus_1->red = rgb->red;
583 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
584 rgb_plus_1->green = rgb->green;
585 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
586 rgb_plus_1->blue = rgb->blue;
587
588 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
589 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
590 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
591
592 ++rgb_plus_1;
593 ++rgb;
594 ++i;
595 }
596
597 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
598
599 return true;
600 }
601
602 static bool
603 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
604 const struct dc_stream_state *stream)
605 {
606 struct transform *xfm = pipe_ctx->plane_res.xfm;
607
608 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
609 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
610
611 if (stream->out_transfer_func &&
612 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
613 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
614 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
615 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
616 &xfm->regamma_params)) {
617 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
618 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
619 } else {
620 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
621 }
622
623 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
624
625 return true;
626 }
627
628 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
629 {
630 bool is_hdmi_tmds;
631 bool is_dp;
632
633 ASSERT(pipe_ctx->stream);
634
635 if (pipe_ctx->stream_res.stream_enc == NULL)
636 return; /* this is not root pipe */
637
638 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
639 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
640
641 if (!is_hdmi_tmds && !is_dp)
642 return;
643
644 if (is_hdmi_tmds)
645 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
646 pipe_ctx->stream_res.stream_enc,
647 &pipe_ctx->stream_res.encoder_info_frame);
648 else
649 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
650 pipe_ctx->stream_res.stream_enc,
651 &pipe_ctx->stream_res.encoder_info_frame);
652 }
653
654 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
655 {
656 enum dc_lane_count lane_count =
657 pipe_ctx->stream->link->cur_link_settings.lane_count;
658 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
659 struct dc_link *link = pipe_ctx->stream->link;
660 const struct dc *dc = link->dc;
661
662 uint32_t active_total_with_borders;
663 uint32_t early_control = 0;
664 struct timing_generator *tg = pipe_ctx->stream_res.tg;
665
666 /* For MST, there are multiply stream go to only one link.
667 * connect DIG back_end to front_end while enable_stream and
668 * disconnect them during disable_stream
669 * BY this, it is logic clean to separate stream and link */
670 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
671 pipe_ctx->stream_res.stream_enc->id, true);
672
673 dc->hwss.update_info_frame(pipe_ctx);
674
675 /* enable early control to avoid corruption on DP monitor*/
676 active_total_with_borders =
677 timing->h_addressable
678 + timing->h_border_left
679 + timing->h_border_right;
680
681 if (lane_count != 0)
682 early_control = active_total_with_borders % lane_count;
683
684 if (early_control == 0)
685 early_control = lane_count;
686
687 tg->funcs->set_early_control(tg, early_control);
688
689 /* enable audio only within mode set */
690 if (pipe_ctx->stream_res.audio != NULL) {
691 if (dc_is_dp_signal(pipe_ctx->stream->signal))
692 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
693 }
694
695
696
697
698 }
699
700 /*todo: cloned in stream enc, fix*/
701 bool dce110_is_panel_backlight_on(struct dc_link *link)
702 {
703 struct dc_context *ctx = link->ctx;
704 struct dce_hwseq *hws = ctx->dc->hwseq;
705 uint32_t value;
706
707 REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
708
709 return value;
710 }
711
712 bool dce110_is_panel_powered_on(struct dc_link *link)
713 {
714 struct dc_context *ctx = link->ctx;
715 struct dce_hwseq *hws = ctx->dc->hwseq;
716 uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
717
718 REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
719
720 REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
721
722 return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
723 }
724
725 static enum bp_result link_transmitter_control(
726 struct dc_bios *bios,
727 struct bp_transmitter_control *cntl)
728 {
729 enum bp_result result;
730
731 result = bios->funcs->transmitter_control(bios, cntl);
732
733 return result;
734 }
735
736 /*
737 * @brief
738 * eDP only.
739 */
740 void dce110_edp_wait_for_hpd_ready(
741 struct dc_link *link,
742 bool power_up)
743 {
744 struct dc_context *ctx = link->ctx;
745 struct graphics_object_id connector = link->link_enc->connector;
746 struct gpio *hpd;
747 bool edp_hpd_high = false;
748 uint32_t time_elapsed = 0;
749 uint32_t timeout = power_up ?
750 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
751
752 if (dal_graphics_object_id_get_connector_id(connector)
753 != CONNECTOR_ID_EDP) {
754 BREAK_TO_DEBUGGER();
755 return;
756 }
757
758 if (!power_up)
759 /*
760 * From KV, we will not HPD low after turning off VCC -
761 * instead, we will check the SW timer in power_up().
762 */
763 return;
764
765 /*
766 * When we power on/off the eDP panel,
767 * we need to wait until SENSE bit is high/low.
768 */
769
770 /* obtain HPD */
771 /* TODO what to do with this? */
772 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
773
774 if (!hpd) {
775 BREAK_TO_DEBUGGER();
776 return;
777 }
778
779 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
780
781 /* wait until timeout or panel detected */
782
783 do {
784 uint32_t detected = 0;
785
786 dal_gpio_get_value(hpd, &detected);
787
788 if (!(detected ^ power_up)) {
789 edp_hpd_high = true;
790 break;
791 }
792
793 msleep(HPD_CHECK_INTERVAL);
794
795 time_elapsed += HPD_CHECK_INTERVAL;
796 } while (time_elapsed < timeout);
797
798 dal_gpio_close(hpd);
799
800 dal_gpio_destroy_irq(&hpd);
801
802 if (false == edp_hpd_high) {
803 DC_LOG_ERROR(
804 "%s: wait timed out!\n", __func__);
805 }
806 }
807
808 void dce110_edp_power_control(
809 struct dc_link *link,
810 bool power_up)
811 {
812 struct dc_context *ctx = link->ctx;
813 struct dce_hwseq *hwseq = ctx->dc->hwseq;
814 struct bp_transmitter_control cntl = { 0 };
815 enum bp_result bp_result;
816
817
818 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
819 != CONNECTOR_ID_EDP) {
820 BREAK_TO_DEBUGGER();
821 return;
822 }
823
824 if (power_up != hwseq->funcs.is_panel_powered_on(link)) {
825 /* Send VBIOS command to prompt eDP panel power */
826 if (power_up) {
827 unsigned long long current_ts = dm_get_timestamp(ctx);
828 unsigned long long duration_in_ms =
829 div64_u64(dm_get_elapse_time_in_ns(
830 ctx,
831 current_ts,
832 link->link_trace.time_stamp.edp_poweroff), 1000000);
833 unsigned long long wait_time_ms = 0;
834
835 /* max 500ms from LCDVDD off to on */
836 unsigned long long edp_poweroff_time_ms = 500;
837
838 if (link->local_sink != NULL)
839 edp_poweroff_time_ms =
840 500 + link->local_sink->edid_caps.panel_patch.extra_t12_ms;
841 if (link->link_trace.time_stamp.edp_poweroff == 0)
842 wait_time_ms = edp_poweroff_time_ms;
843 else if (duration_in_ms < edp_poweroff_time_ms)
844 wait_time_ms = edp_poweroff_time_ms - duration_in_ms;
845
846 if (wait_time_ms) {
847 msleep(wait_time_ms);
848 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
849 __func__, wait_time_ms);
850 }
851
852 }
853
854 DC_LOG_HW_RESUME_S3(
855 "%s: Panel Power action: %s\n",
856 __func__, (power_up ? "On":"Off"));
857
858 cntl.action = power_up ?
859 TRANSMITTER_CONTROL_POWER_ON :
860 TRANSMITTER_CONTROL_POWER_OFF;
861 cntl.transmitter = link->link_enc->transmitter;
862 cntl.connector_obj_id = link->link_enc->connector;
863 cntl.coherent = false;
864 cntl.lanes_number = LANE_COUNT_FOUR;
865 cntl.hpd_sel = link->link_enc->hpd_source;
866 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
867
868 if (!power_up)
869 /*save driver power off time stamp*/
870 link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
871 else
872 link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
873
874 if (bp_result != BP_RESULT_OK)
875 DC_LOG_ERROR(
876 "%s: Panel Power bp_result: %d\n",
877 __func__, bp_result);
878 } else {
879 DC_LOG_HW_RESUME_S3(
880 "%s: Skipping Panel Power action: %s\n",
881 __func__, (power_up ? "On":"Off"));
882 }
883 }
884
885 /*todo: cloned in stream enc, fix*/
886 /*
887 * @brief
888 * eDP only. Control the backlight of the eDP panel
889 */
890 void dce110_edp_backlight_control(
891 struct dc_link *link,
892 bool enable)
893 {
894 struct dc_context *ctx = link->ctx;
895 struct dce_hwseq *hws = ctx->dc->hwseq;
896 struct bp_transmitter_control cntl = { 0 };
897
898 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
899 != CONNECTOR_ID_EDP) {
900 BREAK_TO_DEBUGGER();
901 return;
902 }
903
904 if (enable && hws->funcs.is_panel_backlight_on(link)) {
905 DC_LOG_HW_RESUME_S3(
906 "%s: panel already powered up. Do nothing.\n",
907 __func__);
908 return;
909 }
910
911 /* Send VBIOS command to control eDP panel backlight */
912
913 DC_LOG_HW_RESUME_S3(
914 "%s: backlight action: %s\n",
915 __func__, (enable ? "On":"Off"));
916
917 cntl.action = enable ?
918 TRANSMITTER_CONTROL_BACKLIGHT_ON :
919 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
920
921 /*cntl.engine_id = ctx->engine;*/
922 cntl.transmitter = link->link_enc->transmitter;
923 cntl.connector_obj_id = link->link_enc->connector;
924 /*todo: unhardcode*/
925 cntl.lanes_number = LANE_COUNT_FOUR;
926 cntl.hpd_sel = link->link_enc->hpd_source;
927 cntl.signal = SIGNAL_TYPE_EDP;
928
929 /* For eDP, the following delays might need to be considered
930 * after link training completed:
931 * idle period - min. accounts for required BS-Idle pattern,
932 * max. allows for source frame synchronization);
933 * 50 msec max. delay from valid video data from source
934 * to video on dislpay or backlight enable.
935 *
936 * Disable the delay for now.
937 * Enable it in the future if necessary.
938 */
939 /* dc_service_sleep_in_milliseconds(50); */
940 /*edp 1.2*/
941 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
942 edp_receiver_ready_T7(link);
943 link_transmitter_control(ctx->dc_bios, &cntl);
944
945 if (enable && link->dpcd_sink_ext_caps.bits.oled)
946 msleep(OLED_POST_T7_DELAY);
947
948 if (link->dpcd_sink_ext_caps.bits.oled ||
949 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
950 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
951 dc_link_backlight_enable_aux(link, enable);
952
953 /*edp 1.2*/
954 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
955 edp_receiver_ready_T9(link);
956
957 if (!enable && link->dpcd_sink_ext_caps.bits.oled)
958 msleep(OLED_PRE_T11_DELAY);
959 }
960
961 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
962 {
963 /* notify audio driver for audio modes of monitor */
964 struct dc *dc;
965 struct clk_mgr *clk_mgr;
966 unsigned int i, num_audio = 1;
967
968 if (!pipe_ctx->stream)
969 return;
970
971 dc = pipe_ctx->stream->ctx->dc;
972 clk_mgr = dc->clk_mgr;
973
974 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
975 return;
976
977 if (pipe_ctx->stream_res.audio) {
978 for (i = 0; i < MAX_PIPES; i++) {
979 /*current_state not updated yet*/
980 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
981 num_audio++;
982 }
983
984 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
985
986 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
987 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
988 clk_mgr->funcs->enable_pme_wa(clk_mgr);
989 /* un-mute audio */
990 /* TODO: audio should be per stream rather than per link */
991 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
992 pipe_ctx->stream_res.stream_enc, false);
993 if (pipe_ctx->stream_res.audio)
994 pipe_ctx->stream_res.audio->enabled = true;
995 }
996 }
997
998 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
999 {
1000 struct dc *dc;
1001 struct clk_mgr *clk_mgr;
1002
1003 if (!pipe_ctx || !pipe_ctx->stream)
1004 return;
1005
1006 dc = pipe_ctx->stream->ctx->dc;
1007 clk_mgr = dc->clk_mgr;
1008
1009 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1010 return;
1011
1012 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1013 pipe_ctx->stream_res.stream_enc, true);
1014 if (pipe_ctx->stream_res.audio) {
1015 pipe_ctx->stream_res.audio->enabled = false;
1016
1017 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1018 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1019 pipe_ctx->stream_res.stream_enc);
1020 else
1021 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1022 pipe_ctx->stream_res.stream_enc);
1023
1024 if (clk_mgr->funcs->enable_pme_wa)
1025 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1026 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1027
1028 /* TODO: notify audio driver for if audio modes list changed
1029 * add audio mode list change flag */
1030 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1031 * stream->stream_engine_id);
1032 */
1033 }
1034 }
1035
1036 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1037 {
1038 struct dc_stream_state *stream = pipe_ctx->stream;
1039 struct dc_link *link = stream->link;
1040 struct dc *dc = pipe_ctx->stream->ctx->dc;
1041
1042 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1043 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1044 pipe_ctx->stream_res.stream_enc);
1045 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1046 pipe_ctx->stream_res.stream_enc);
1047 }
1048
1049 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1050 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1051 pipe_ctx->stream_res.stream_enc);
1052
1053 dc->hwss.disable_audio_stream(pipe_ctx);
1054
1055 link->link_enc->funcs->connect_dig_be_to_fe(
1056 link->link_enc,
1057 pipe_ctx->stream_res.stream_enc->id,
1058 false);
1059
1060 }
1061
1062 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1063 struct dc_link_settings *link_settings)
1064 {
1065 struct encoder_unblank_param params = { { 0 } };
1066 struct dc_stream_state *stream = pipe_ctx->stream;
1067 struct dc_link *link = stream->link;
1068 struct dce_hwseq *hws = link->dc->hwseq;
1069
1070 /* only 3 items below are used by unblank */
1071 params.timing = pipe_ctx->stream->timing;
1072 params.link_settings.link_rate = link_settings->link_rate;
1073
1074 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1075 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1076
1077 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1078 hws->funcs.edp_backlight_control(link, true);
1079 }
1080 }
1081
1082 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1083 {
1084 struct dc_stream_state *stream = pipe_ctx->stream;
1085 struct dc_link *link = stream->link;
1086 struct dce_hwseq *hws = link->dc->hwseq;
1087
1088 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1089 hws->funcs.edp_backlight_control(link, false);
1090 dc_link_set_abm_disable(link);
1091 }
1092
1093 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1094 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1095 }
1096
1097
1098 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1099 {
1100 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1101 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1102 }
1103
1104 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1105 {
1106 switch (crtc_id) {
1107 case CONTROLLER_ID_D0:
1108 return DTO_SOURCE_ID0;
1109 case CONTROLLER_ID_D1:
1110 return DTO_SOURCE_ID1;
1111 case CONTROLLER_ID_D2:
1112 return DTO_SOURCE_ID2;
1113 case CONTROLLER_ID_D3:
1114 return DTO_SOURCE_ID3;
1115 case CONTROLLER_ID_D4:
1116 return DTO_SOURCE_ID4;
1117 case CONTROLLER_ID_D5:
1118 return DTO_SOURCE_ID5;
1119 default:
1120 return DTO_SOURCE_UNKNOWN;
1121 }
1122 }
1123
1124 static void build_audio_output(
1125 struct dc_state *state,
1126 const struct pipe_ctx *pipe_ctx,
1127 struct audio_output *audio_output)
1128 {
1129 const struct dc_stream_state *stream = pipe_ctx->stream;
1130 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1131
1132 audio_output->signal = pipe_ctx->stream->signal;
1133
1134 /* audio_crtc_info */
1135
1136 audio_output->crtc_info.h_total =
1137 stream->timing.h_total;
1138
1139 /*
1140 * Audio packets are sent during actual CRTC blank physical signal, we
1141 * need to specify actual active signal portion
1142 */
1143 audio_output->crtc_info.h_active =
1144 stream->timing.h_addressable
1145 + stream->timing.h_border_left
1146 + stream->timing.h_border_right;
1147
1148 audio_output->crtc_info.v_active =
1149 stream->timing.v_addressable
1150 + stream->timing.v_border_top
1151 + stream->timing.v_border_bottom;
1152
1153 audio_output->crtc_info.pixel_repetition = 1;
1154
1155 audio_output->crtc_info.interlaced =
1156 stream->timing.flags.INTERLACE;
1157
1158 audio_output->crtc_info.refresh_rate =
1159 (stream->timing.pix_clk_100hz*100)/
1160 (stream->timing.h_total*stream->timing.v_total);
1161
1162 audio_output->crtc_info.color_depth =
1163 stream->timing.display_color_depth;
1164
1165 audio_output->crtc_info.requested_pixel_clock_100Hz =
1166 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1167
1168 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1169 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1170
1171 /*for HDMI, audio ACR is with deep color ratio factor*/
1172 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1173 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1174 (stream->timing.pix_clk_100hz)) {
1175 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1176 audio_output->crtc_info.requested_pixel_clock_100Hz =
1177 audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1178 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1179 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1180
1181 }
1182 }
1183
1184 if (state->clk_mgr &&
1185 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1186 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1187 audio_output->pll_info.dp_dto_source_clock_in_khz =
1188 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1189 state->clk_mgr);
1190 }
1191
1192 audio_output->pll_info.feed_back_divider =
1193 pipe_ctx->pll_settings.feedback_divider;
1194
1195 audio_output->pll_info.dto_source =
1196 translate_to_dto_source(
1197 pipe_ctx->stream_res.tg->inst + 1);
1198
1199 /* TODO hard code to enable for now. Need get from stream */
1200 audio_output->pll_info.ss_enabled = true;
1201
1202 audio_output->pll_info.ss_percentage =
1203 pipe_ctx->pll_settings.ss_percentage;
1204 }
1205
1206 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1207 struct tg_color *color)
1208 {
1209 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1210
1211 switch (pipe_ctx->plane_res.scl_data.format) {
1212 case PIXEL_FORMAT_ARGB8888:
1213 /* set boarder color to red */
1214 color->color_r_cr = color_value;
1215 break;
1216
1217 case PIXEL_FORMAT_ARGB2101010:
1218 /* set boarder color to blue */
1219 color->color_b_cb = color_value;
1220 break;
1221 case PIXEL_FORMAT_420BPP8:
1222 /* set boarder color to green */
1223 color->color_g_y = color_value;
1224 break;
1225 case PIXEL_FORMAT_420BPP10:
1226 /* set boarder color to yellow */
1227 color->color_g_y = color_value;
1228 color->color_r_cr = color_value;
1229 break;
1230 case PIXEL_FORMAT_FP16:
1231 /* set boarder color to white */
1232 color->color_r_cr = color_value;
1233 color->color_b_cb = color_value;
1234 color->color_g_y = color_value;
1235 break;
1236 default:
1237 break;
1238 }
1239 }
1240
1241 static void program_scaler(const struct dc *dc,
1242 const struct pipe_ctx *pipe_ctx)
1243 {
1244 struct tg_color color = {0};
1245
1246 #if defined(CONFIG_DRM_AMD_DC_DCN)
1247 /* TOFPGA */
1248 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1249 return;
1250 #endif
1251
1252 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1253 get_surface_visual_confirm_color(pipe_ctx, &color);
1254 else
1255 color_space_to_black_color(dc,
1256 pipe_ctx->stream->output_color_space,
1257 &color);
1258
1259 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1260 pipe_ctx->plane_res.xfm,
1261 pipe_ctx->plane_res.scl_data.lb_params.depth,
1262 &pipe_ctx->stream->bit_depth_params);
1263
1264 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1265 /*
1266 * The way 420 is packed, 2 channels carry Y component, 1 channel
1267 * alternate between Cb and Cr, so both channels need the pixel
1268 * value for Y
1269 */
1270 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1271 color.color_r_cr = color.color_g_y;
1272
1273 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1274 pipe_ctx->stream_res.tg,
1275 &color);
1276 }
1277
1278 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1279 &pipe_ctx->plane_res.scl_data);
1280 }
1281
1282 static enum dc_status dce110_enable_stream_timing(
1283 struct pipe_ctx *pipe_ctx,
1284 struct dc_state *context,
1285 struct dc *dc)
1286 {
1287 struct dc_stream_state *stream = pipe_ctx->stream;
1288 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1289 pipe_ctx[pipe_ctx->pipe_idx];
1290 struct tg_color black_color = {0};
1291
1292 if (!pipe_ctx_old->stream) {
1293
1294 /* program blank color */
1295 color_space_to_black_color(dc,
1296 stream->output_color_space, &black_color);
1297 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1298 pipe_ctx->stream_res.tg,
1299 &black_color);
1300
1301 /*
1302 * Must blank CRTC after disabling power gating and before any
1303 * programming, otherwise CRTC will be hung in bad state
1304 */
1305 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1306
1307 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1308 pipe_ctx->clock_source,
1309 &pipe_ctx->stream_res.pix_clk_params,
1310 &pipe_ctx->pll_settings)) {
1311 BREAK_TO_DEBUGGER();
1312 return DC_ERROR_UNEXPECTED;
1313 }
1314
1315 pipe_ctx->stream_res.tg->funcs->program_timing(
1316 pipe_ctx->stream_res.tg,
1317 &stream->timing,
1318 0,
1319 0,
1320 0,
1321 0,
1322 pipe_ctx->stream->signal,
1323 true);
1324 }
1325
1326 if (!pipe_ctx_old->stream) {
1327 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1328 pipe_ctx->stream_res.tg)) {
1329 BREAK_TO_DEBUGGER();
1330 return DC_ERROR_UNEXPECTED;
1331 }
1332 }
1333
1334 return DC_OK;
1335 }
1336
1337 static enum dc_status apply_single_controller_ctx_to_hw(
1338 struct pipe_ctx *pipe_ctx,
1339 struct dc_state *context,
1340 struct dc *dc)
1341 {
1342 struct dc_stream_state *stream = pipe_ctx->stream;
1343 struct drr_params params = {0};
1344 unsigned int event_triggers = 0;
1345 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1346 struct dce_hwseq *hws = dc->hwseq;
1347
1348 if (hws->funcs.disable_stream_gating) {
1349 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1350 }
1351
1352 if (pipe_ctx->stream_res.audio != NULL) {
1353 struct audio_output audio_output;
1354
1355 build_audio_output(context, pipe_ctx, &audio_output);
1356
1357 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1358 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1359 pipe_ctx->stream_res.stream_enc,
1360 pipe_ctx->stream_res.audio->inst,
1361 &pipe_ctx->stream->audio_info);
1362 else
1363 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1364 pipe_ctx->stream_res.stream_enc,
1365 pipe_ctx->stream_res.audio->inst,
1366 &pipe_ctx->stream->audio_info,
1367 &audio_output.crtc_info);
1368
1369 pipe_ctx->stream_res.audio->funcs->az_configure(
1370 pipe_ctx->stream_res.audio,
1371 pipe_ctx->stream->signal,
1372 &audio_output.crtc_info,
1373 &pipe_ctx->stream->audio_info);
1374 }
1375
1376 /* */
1377 /* Do not touch stream timing on seamless boot optimization. */
1378 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1379 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1380
1381 if (hws->funcs.setup_vupdate_interrupt)
1382 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1383
1384 params.vertical_total_min = stream->adjust.v_total_min;
1385 params.vertical_total_max = stream->adjust.v_total_max;
1386 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1387 pipe_ctx->stream_res.tg->funcs->set_drr(
1388 pipe_ctx->stream_res.tg, &params);
1389
1390 // DRR should set trigger event to monitor surface update event
1391 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1392 event_triggers = 0x80;
1393 /* Event triggers and num frames initialized for DRR, but can be
1394 * later updated for PSR use. Note DRR trigger events are generated
1395 * regardless of whether num frames met.
1396 */
1397 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1398 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1399 pipe_ctx->stream_res.tg, event_triggers, 2);
1400
1401 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1402 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1403 pipe_ctx->stream_res.stream_enc,
1404 pipe_ctx->stream_res.tg->inst);
1405
1406 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1407 pipe_ctx->stream_res.opp,
1408 COLOR_SPACE_YCBCR601,
1409 stream->timing.display_color_depth,
1410 stream->signal);
1411
1412 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1413 pipe_ctx->stream_res.opp,
1414 &stream->bit_depth_params,
1415 &stream->clamping);
1416 while (odm_pipe) {
1417 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1418 odm_pipe->stream_res.opp,
1419 COLOR_SPACE_YCBCR601,
1420 stream->timing.display_color_depth,
1421 stream->signal);
1422
1423 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1424 odm_pipe->stream_res.opp,
1425 &stream->bit_depth_params,
1426 &stream->clamping);
1427 odm_pipe = odm_pipe->next_odm_pipe;
1428 }
1429
1430 if (!stream->dpms_off)
1431 core_link_enable_stream(context, pipe_ctx);
1432
1433 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1434
1435 pipe_ctx->stream->link->psr_feature_enabled = false;
1436
1437 return DC_OK;
1438 }
1439
1440 /******************************************************************************/
1441
1442 static void power_down_encoders(struct dc *dc)
1443 {
1444 int i;
1445
1446 /* do not know BIOS back-front mapping, simply blank all. It will not
1447 * hurt for non-DP
1448 */
1449 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1450 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1451 dc->res_pool->stream_enc[i]);
1452 }
1453
1454 for (i = 0; i < dc->link_count; i++) {
1455 enum signal_type signal = dc->links[i]->connector_signal;
1456
1457 if ((signal == SIGNAL_TYPE_EDP) ||
1458 (signal == SIGNAL_TYPE_DISPLAY_PORT))
1459 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1460 dp_receiver_power_ctrl(dc->links[i], false);
1461
1462 if (signal != SIGNAL_TYPE_EDP)
1463 signal = SIGNAL_TYPE_NONE;
1464
1465 dc->links[i]->link_enc->funcs->disable_output(
1466 dc->links[i]->link_enc, signal);
1467 }
1468 }
1469
1470 static void power_down_controllers(struct dc *dc)
1471 {
1472 int i;
1473
1474 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1475 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1476 dc->res_pool->timing_generators[i]);
1477 }
1478 }
1479
1480 static void power_down_clock_sources(struct dc *dc)
1481 {
1482 int i;
1483
1484 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1485 dc->res_pool->dp_clock_source) == false)
1486 dm_error("Failed to power down pll! (dp clk src)\n");
1487
1488 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1489 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1490 dc->res_pool->clock_sources[i]) == false)
1491 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1492 }
1493 }
1494
1495 static void power_down_all_hw_blocks(struct dc *dc)
1496 {
1497 power_down_encoders(dc);
1498
1499 power_down_controllers(dc);
1500
1501 power_down_clock_sources(dc);
1502
1503 if (dc->fbc_compressor)
1504 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1505 }
1506
1507 static void disable_vga_and_power_gate_all_controllers(
1508 struct dc *dc)
1509 {
1510 int i;
1511 struct timing_generator *tg;
1512 struct dc_context *ctx = dc->ctx;
1513
1514 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1515 tg = dc->res_pool->timing_generators[i];
1516
1517 if (tg->funcs->disable_vga)
1518 tg->funcs->disable_vga(tg);
1519 }
1520 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1521 /* Enable CLOCK gating for each pipe BEFORE controller
1522 * powergating. */
1523 enable_display_pipe_clock_gating(ctx,
1524 true);
1525
1526 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1527 dc->hwss.disable_plane(dc,
1528 &dc->current_state->res_ctx.pipe_ctx[i]);
1529 }
1530 }
1531
1532
1533 static struct dc_stream_state *get_edp_stream(struct dc_state *context)
1534 {
1535 int i;
1536
1537 for (i = 0; i < context->stream_count; i++) {
1538 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1539 return context->streams[i];
1540 }
1541 return NULL;
1542 }
1543
1544 static struct dc_link *get_edp_link_with_sink(
1545 struct dc *dc,
1546 struct dc_state *context)
1547 {
1548 int i;
1549 struct dc_link *link = NULL;
1550
1551 /* check if there is an eDP panel not in use */
1552 for (i = 0; i < dc->link_count; i++) {
1553 if (dc->links[i]->local_sink &&
1554 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1555 link = dc->links[i];
1556 break;
1557 }
1558 }
1559
1560 return link;
1561 }
1562
1563 /**
1564 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1565 * 1. Power down all DC HW blocks
1566 * 2. Disable VGA engine on all controllers
1567 * 3. Enable power gating for controller
1568 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1569 */
1570 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1571 {
1572 int i;
1573 struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context);
1574 struct dc_link *edp_link = get_edp_link(dc);
1575 struct dc_stream_state *edp_stream = NULL;
1576 bool can_apply_edp_fast_boot = false;
1577 bool can_apply_seamless_boot = false;
1578 bool keep_edp_vdd_on = false;
1579 struct dce_hwseq *hws = dc->hwseq;
1580
1581 if (hws->funcs.init_pipes)
1582 hws->funcs.init_pipes(dc, context);
1583
1584 edp_stream = get_edp_stream(context);
1585
1586 // Check fastboot support, disable on DCE8 because of blank screens
1587 if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1588 dc->ctx->dce_version != DCE_VERSION_8_1 &&
1589 dc->ctx->dce_version != DCE_VERSION_8_3) {
1590
1591 // enable fastboot if backend is enabled on eDP
1592 if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
1593 /* Set optimization flag on eDP stream*/
1594 if (edp_stream) {
1595 edp_stream->apply_edp_fast_boot_optimization = true;
1596 can_apply_edp_fast_boot = true;
1597 }
1598 }
1599
1600 // We are trying to enable eDP, don't power down VDD
1601 if (edp_stream)
1602 keep_edp_vdd_on = true;
1603 }
1604
1605 // Check seamless boot support
1606 for (i = 0; i < context->stream_count; i++) {
1607 if (context->streams[i]->apply_seamless_boot_optimization) {
1608 can_apply_seamless_boot = true;
1609 break;
1610 }
1611 }
1612
1613 /* eDP should not have stream in resume from S4 and so even with VBios post
1614 * it should get turned off
1615 */
1616 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1617 if (edp_link_with_sink && !keep_edp_vdd_on) {
1618 /*turn off backlight before DP_blank and encoder powered down*/
1619 hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1620 }
1621 /*resume from S3, no vbios posting, no need to power down again*/
1622 power_down_all_hw_blocks(dc);
1623 disable_vga_and_power_gate_all_controllers(dc);
1624 if (edp_link_with_sink && !keep_edp_vdd_on)
1625 dc->hwss.edp_power_control(edp_link_with_sink, false);
1626 }
1627 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1628 }
1629
1630 static uint32_t compute_pstate_blackout_duration(
1631 struct bw_fixed blackout_duration,
1632 const struct dc_stream_state *stream)
1633 {
1634 uint32_t total_dest_line_time_ns;
1635 uint32_t pstate_blackout_duration_ns;
1636
1637 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1638
1639 total_dest_line_time_ns = 1000000UL *
1640 (stream->timing.h_total * 10) /
1641 stream->timing.pix_clk_100hz +
1642 pstate_blackout_duration_ns;
1643
1644 return total_dest_line_time_ns;
1645 }
1646
1647 static void dce110_set_displaymarks(
1648 const struct dc *dc,
1649 struct dc_state *context)
1650 {
1651 uint8_t i, num_pipes;
1652 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1653
1654 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1655 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1656 uint32_t total_dest_line_time_ns;
1657
1658 if (pipe_ctx->stream == NULL)
1659 continue;
1660
1661 total_dest_line_time_ns = compute_pstate_blackout_duration(
1662 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1663 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1664 pipe_ctx->plane_res.mi,
1665 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1666 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1667 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1668 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1669 total_dest_line_time_ns);
1670 if (i == underlay_idx) {
1671 num_pipes++;
1672 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1673 pipe_ctx->plane_res.mi,
1674 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1675 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1676 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1677 total_dest_line_time_ns);
1678 }
1679 num_pipes++;
1680 }
1681 }
1682
1683 void dce110_set_safe_displaymarks(
1684 struct resource_context *res_ctx,
1685 const struct resource_pool *pool)
1686 {
1687 int i;
1688 int underlay_idx = pool->underlay_pipe_index;
1689 struct dce_watermarks max_marks = {
1690 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1691 struct dce_watermarks nbp_marks = {
1692 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1693 struct dce_watermarks min_marks = { 0, 0, 0, 0};
1694
1695 for (i = 0; i < MAX_PIPES; i++) {
1696 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1697 continue;
1698
1699 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1700 res_ctx->pipe_ctx[i].plane_res.mi,
1701 nbp_marks,
1702 max_marks,
1703 min_marks,
1704 max_marks,
1705 MAX_WATERMARK);
1706
1707 if (i == underlay_idx)
1708 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1709 res_ctx->pipe_ctx[i].plane_res.mi,
1710 nbp_marks,
1711 max_marks,
1712 max_marks,
1713 MAX_WATERMARK);
1714
1715 }
1716 }
1717
1718 /*******************************************************************************
1719 * Public functions
1720 ******************************************************************************/
1721
1722 static void set_drr(struct pipe_ctx **pipe_ctx,
1723 int num_pipes, unsigned int vmin, unsigned int vmax,
1724 unsigned int vmid, unsigned int vmid_frame_number)
1725 {
1726 int i = 0;
1727 struct drr_params params = {0};
1728 // DRR should set trigger event to monitor surface update event
1729 unsigned int event_triggers = 0x80;
1730 // Note DRR trigger events are generated regardless of whether num frames met.
1731 unsigned int num_frames = 2;
1732
1733 params.vertical_total_max = vmax;
1734 params.vertical_total_min = vmin;
1735
1736 /* TODO: If multiple pipes are to be supported, you need
1737 * some GSL stuff. Static screen triggers may be programmed differently
1738 * as well.
1739 */
1740 for (i = 0; i < num_pipes; i++) {
1741 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1742 pipe_ctx[i]->stream_res.tg, &params);
1743
1744 if (vmax != 0 && vmin != 0)
1745 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1746 pipe_ctx[i]->stream_res.tg,
1747 event_triggers, num_frames);
1748 }
1749 }
1750
1751 static void get_position(struct pipe_ctx **pipe_ctx,
1752 int num_pipes,
1753 struct crtc_position *position)
1754 {
1755 int i = 0;
1756
1757 /* TODO: handle pipes > 1
1758 */
1759 for (i = 0; i < num_pipes; i++)
1760 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1761 }
1762
1763 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1764 int num_pipes, const struct dc_static_screen_params *params)
1765 {
1766 unsigned int i;
1767 unsigned int triggers = 0;
1768
1769 if (params->triggers.overlay_update)
1770 triggers |= 0x100;
1771 if (params->triggers.surface_update)
1772 triggers |= 0x80;
1773 if (params->triggers.cursor_update)
1774 triggers |= 0x2;
1775 if (params->triggers.force_trigger)
1776 triggers |= 0x1;
1777
1778 if (num_pipes) {
1779 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1780
1781 if (dc->fbc_compressor)
1782 triggers |= 0x84;
1783 }
1784
1785 for (i = 0; i < num_pipes; i++)
1786 pipe_ctx[i]->stream_res.tg->funcs->
1787 set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1788 triggers, params->num_frames);
1789 }
1790
1791 /*
1792 * Check if FBC can be enabled
1793 */
1794 static bool should_enable_fbc(struct dc *dc,
1795 struct dc_state *context,
1796 uint32_t *pipe_idx)
1797 {
1798 uint32_t i;
1799 struct pipe_ctx *pipe_ctx = NULL;
1800 struct resource_context *res_ctx = &context->res_ctx;
1801 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1802
1803
1804 ASSERT(dc->fbc_compressor);
1805
1806 /* FBC memory should be allocated */
1807 if (!dc->ctx->fbc_gpu_addr)
1808 return false;
1809
1810 /* Only supports single display */
1811 if (context->stream_count != 1)
1812 return false;
1813
1814 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1815 if (res_ctx->pipe_ctx[i].stream) {
1816
1817 pipe_ctx = &res_ctx->pipe_ctx[i];
1818
1819 if (!pipe_ctx)
1820 continue;
1821
1822 /* fbc not applicable on underlay pipe */
1823 if (pipe_ctx->pipe_idx != underlay_idx) {
1824 *pipe_idx = i;
1825 break;
1826 }
1827 }
1828 }
1829
1830 if (i == dc->res_pool->pipe_count)
1831 return false;
1832
1833 if (!pipe_ctx->stream->link)
1834 return false;
1835
1836 /* Only supports eDP */
1837 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
1838 return false;
1839
1840 /* PSR should not be enabled */
1841 if (pipe_ctx->stream->link->psr_feature_enabled)
1842 return false;
1843
1844 /* Nothing to compress */
1845 if (!pipe_ctx->plane_state)
1846 return false;
1847
1848 /* Only for non-linear tiling */
1849 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1850 return false;
1851
1852 return true;
1853 }
1854
1855 /*
1856 * Enable FBC
1857 */
1858 static void enable_fbc(
1859 struct dc *dc,
1860 struct dc_state *context)
1861 {
1862 uint32_t pipe_idx = 0;
1863
1864 if (should_enable_fbc(dc, context, &pipe_idx)) {
1865 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1866 struct compr_addr_and_pitch_params params = {0, 0, 0};
1867 struct compressor *compr = dc->fbc_compressor;
1868 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1869
1870 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1871 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1872 params.inst = pipe_ctx->stream_res.tg->inst;
1873 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1874
1875 compr->funcs->surface_address_and_pitch(compr, &params);
1876 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1877
1878 compr->funcs->enable_fbc(compr, &params);
1879 }
1880 }
1881
1882 static void dce110_reset_hw_ctx_wrap(
1883 struct dc *dc,
1884 struct dc_state *context)
1885 {
1886 int i;
1887
1888 /* Reset old context */
1889 /* look up the targets that have been removed since last commit */
1890 for (i = 0; i < MAX_PIPES; i++) {
1891 struct pipe_ctx *pipe_ctx_old =
1892 &dc->current_state->res_ctx.pipe_ctx[i];
1893 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1894
1895 /* Note: We need to disable output if clock sources change,
1896 * since bios does optimization and doesn't apply if changing
1897 * PHY when not already disabled.
1898 */
1899
1900 /* Skip underlay pipe since it will be handled in commit surface*/
1901 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1902 continue;
1903
1904 if (!pipe_ctx->stream ||
1905 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1906 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1907
1908 /* Disable if new stream is null. O/w, if stream is
1909 * disabled already, no need to disable again.
1910 */
1911 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
1912 core_link_disable_stream(pipe_ctx_old);
1913
1914 /* free acquired resources*/
1915 if (pipe_ctx_old->stream_res.audio) {
1916 /*disable az_endpoint*/
1917 pipe_ctx_old->stream_res.audio->funcs->
1918 az_disable(pipe_ctx_old->stream_res.audio);
1919
1920 /*free audio*/
1921 if (dc->caps.dynamic_audio == true) {
1922 /*we have to dynamic arbitrate the audio endpoints*/
1923 /*we free the resource, need reset is_audio_acquired*/
1924 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
1925 pipe_ctx_old->stream_res.audio, false);
1926 pipe_ctx_old->stream_res.audio = NULL;
1927 }
1928 }
1929 }
1930
1931 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1932 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1933 dm_error("DC: failed to blank crtc!\n");
1934 BREAK_TO_DEBUGGER();
1935 }
1936 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1937 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1938 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1939
1940 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
1941 dc->res_pool,
1942 old_clk))
1943 old_clk->funcs->cs_power_down(old_clk);
1944
1945 dc->hwss.disable_plane(dc, pipe_ctx_old);
1946
1947 pipe_ctx_old->stream = NULL;
1948 }
1949 }
1950 }
1951
1952 static void dce110_setup_audio_dto(
1953 struct dc *dc,
1954 struct dc_state *context)
1955 {
1956 int i;
1957
1958 /* program audio wall clock. use HDMI as clock source if HDMI
1959 * audio active. Otherwise, use DP as clock source
1960 * first, loop to find any HDMI audio, if not, loop find DP audio
1961 */
1962 /* Setup audio rate clock source */
1963 /* Issue:
1964 * Audio lag happened on DP monitor when unplug a HDMI monitor
1965 *
1966 * Cause:
1967 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1968 * is set to either dto0 or dto1, audio should work fine.
1969 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1970 * set to dto0 will cause audio lag.
1971 *
1972 * Solution:
1973 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1974 * find first available pipe with audio, setup audio wall DTO per topology
1975 * instead of per pipe.
1976 */
1977 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1978 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1979
1980 if (pipe_ctx->stream == NULL)
1981 continue;
1982
1983 if (pipe_ctx->top_pipe)
1984 continue;
1985
1986 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1987 continue;
1988
1989 if (pipe_ctx->stream_res.audio != NULL) {
1990 struct audio_output audio_output;
1991
1992 build_audio_output(context, pipe_ctx, &audio_output);
1993
1994 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1995 pipe_ctx->stream_res.audio,
1996 pipe_ctx->stream->signal,
1997 &audio_output.crtc_info,
1998 &audio_output.pll_info);
1999 break;
2000 }
2001 }
2002
2003 /* no HDMI audio is found, try DP audio */
2004 if (i == dc->res_pool->pipe_count) {
2005 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2006 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2007
2008 if (pipe_ctx->stream == NULL)
2009 continue;
2010
2011 if (pipe_ctx->top_pipe)
2012 continue;
2013
2014 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2015 continue;
2016
2017 if (pipe_ctx->stream_res.audio != NULL) {
2018 struct audio_output audio_output;
2019
2020 build_audio_output(context, pipe_ctx, &audio_output);
2021
2022 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2023 pipe_ctx->stream_res.audio,
2024 pipe_ctx->stream->signal,
2025 &audio_output.crtc_info,
2026 &audio_output.pll_info);
2027 break;
2028 }
2029 }
2030 }
2031 }
2032
2033 enum dc_status dce110_apply_ctx_to_hw(
2034 struct dc *dc,
2035 struct dc_state *context)
2036 {
2037 struct dce_hwseq *hws = dc->hwseq;
2038 struct dc_bios *dcb = dc->ctx->dc_bios;
2039 enum dc_status status;
2040 int i;
2041
2042 /* Reset old context */
2043 /* look up the targets that have been removed since last commit */
2044 hws->funcs.reset_hw_ctx_wrap(dc, context);
2045
2046 /* Skip applying if no targets */
2047 if (context->stream_count <= 0)
2048 return DC_OK;
2049
2050 /* Apply new context */
2051 dcb->funcs->set_scratch_critical_state(dcb, true);
2052
2053 /* below is for real asic only */
2054 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2055 struct pipe_ctx *pipe_ctx_old =
2056 &dc->current_state->res_ctx.pipe_ctx[i];
2057 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2058
2059 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2060 continue;
2061
2062 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2063 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2064 dce_crtc_switch_to_clk_src(dc->hwseq,
2065 pipe_ctx->clock_source, i);
2066 continue;
2067 }
2068
2069 hws->funcs.enable_display_power_gating(
2070 dc, i, dc->ctx->dc_bios,
2071 PIPE_GATING_CONTROL_DISABLE);
2072 }
2073
2074 if (dc->fbc_compressor)
2075 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2076
2077 dce110_setup_audio_dto(dc, context);
2078
2079 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2080 struct pipe_ctx *pipe_ctx_old =
2081 &dc->current_state->res_ctx.pipe_ctx[i];
2082 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2083
2084 if (pipe_ctx->stream == NULL)
2085 continue;
2086
2087 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2088 pipe_ctx->stream->link->link_state_valid) {
2089 continue;
2090 }
2091
2092 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2093 continue;
2094
2095 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2096 continue;
2097
2098 status = apply_single_controller_ctx_to_hw(
2099 pipe_ctx,
2100 context,
2101 dc);
2102
2103 if (DC_OK != status)
2104 return status;
2105 }
2106
2107 if (dc->fbc_compressor)
2108 enable_fbc(dc, dc->current_state);
2109
2110 dcb->funcs->set_scratch_critical_state(dcb, false);
2111
2112 return DC_OK;
2113 }
2114
2115 /*******************************************************************************
2116 * Front End programming
2117 ******************************************************************************/
2118 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2119 {
2120 struct default_adjustment default_adjust = { 0 };
2121
2122 default_adjust.force_hw_default = false;
2123 default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2124 default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2125 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2126 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2127
2128 /* display color depth */
2129 default_adjust.color_depth =
2130 pipe_ctx->stream->timing.display_color_depth;
2131
2132 /* Lb color depth */
2133 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2134
2135 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2136 pipe_ctx->plane_res.xfm, &default_adjust);
2137 }
2138
2139
2140 /*******************************************************************************
2141 * In order to turn on/off specific surface we will program
2142 * Blender + CRTC
2143 *
2144 * In case that we have two surfaces and they have a different visibility
2145 * we can't turn off the CRTC since it will turn off the entire display
2146 *
2147 * |----------------------------------------------- |
2148 * |bottom pipe|curr pipe | | |
2149 * |Surface |Surface | Blender | CRCT |
2150 * |visibility |visibility | Configuration| |
2151 * |------------------------------------------------|
2152 * | off | off | CURRENT_PIPE | blank |
2153 * | off | on | CURRENT_PIPE | unblank |
2154 * | on | off | OTHER_PIPE | unblank |
2155 * | on | on | BLENDING | unblank |
2156 * -------------------------------------------------|
2157 *
2158 ******************************************************************************/
2159 static void program_surface_visibility(const struct dc *dc,
2160 struct pipe_ctx *pipe_ctx)
2161 {
2162 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2163 bool blank_target = false;
2164
2165 if (pipe_ctx->bottom_pipe) {
2166
2167 /* For now we are supporting only two pipes */
2168 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2169
2170 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2171 if (pipe_ctx->plane_state->visible)
2172 blender_mode = BLND_MODE_BLENDING;
2173 else
2174 blender_mode = BLND_MODE_OTHER_PIPE;
2175
2176 } else if (!pipe_ctx->plane_state->visible)
2177 blank_target = true;
2178
2179 } else if (!pipe_ctx->plane_state->visible)
2180 blank_target = true;
2181
2182 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2183 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2184
2185 }
2186
2187 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2188 {
2189 int i = 0;
2190 struct xfm_grph_csc_adjustment adjust;
2191 memset(&adjust, 0, sizeof(adjust));
2192 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2193
2194
2195 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2196 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2197
2198 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2199 adjust.temperature_matrix[i] =
2200 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2201 }
2202
2203 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2204 }
2205 static void update_plane_addr(const struct dc *dc,
2206 struct pipe_ctx *pipe_ctx)
2207 {
2208 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2209
2210 if (plane_state == NULL)
2211 return;
2212
2213 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2214 pipe_ctx->plane_res.mi,
2215 &plane_state->address,
2216 plane_state->flip_immediate);
2217
2218 plane_state->status.requested_address = plane_state->address;
2219 }
2220
2221 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2222 {
2223 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2224
2225 if (plane_state == NULL)
2226 return;
2227
2228 plane_state->status.is_flip_pending =
2229 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2230 pipe_ctx->plane_res.mi);
2231
2232 if (plane_state->status.is_flip_pending && !plane_state->visible)
2233 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2234
2235 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2236 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2237 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2238 plane_state->status.is_right_eye =\
2239 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2240 }
2241 }
2242
2243 void dce110_power_down(struct dc *dc)
2244 {
2245 power_down_all_hw_blocks(dc);
2246 disable_vga_and_power_gate_all_controllers(dc);
2247 }
2248
2249 static bool wait_for_reset_trigger_to_occur(
2250 struct dc_context *dc_ctx,
2251 struct timing_generator *tg)
2252 {
2253 bool rc = false;
2254
2255 /* To avoid endless loop we wait at most
2256 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2257 const uint32_t frames_to_wait_on_triggered_reset = 10;
2258 uint32_t i;
2259
2260 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2261
2262 if (!tg->funcs->is_counter_moving(tg)) {
2263 DC_ERROR("TG counter is not moving!\n");
2264 break;
2265 }
2266
2267 if (tg->funcs->did_triggered_reset_occur(tg)) {
2268 rc = true;
2269 /* usually occurs at i=1 */
2270 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2271 i);
2272 break;
2273 }
2274
2275 /* Wait for one frame. */
2276 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2277 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2278 }
2279
2280 if (false == rc)
2281 DC_ERROR("GSL: Timeout on reset trigger!\n");
2282
2283 return rc;
2284 }
2285
2286 /* Enable timing synchronization for a group of Timing Generators. */
2287 static void dce110_enable_timing_synchronization(
2288 struct dc *dc,
2289 int group_index,
2290 int group_size,
2291 struct pipe_ctx *grouped_pipes[])
2292 {
2293 struct dc_context *dc_ctx = dc->ctx;
2294 struct dcp_gsl_params gsl_params = { 0 };
2295 int i;
2296
2297 DC_SYNC_INFO("GSL: Setting-up...\n");
2298
2299 /* Designate a single TG in the group as a master.
2300 * Since HW doesn't care which one, we always assign
2301 * the 1st one in the group. */
2302 gsl_params.gsl_group = 0;
2303 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2304
2305 for (i = 0; i < group_size; i++)
2306 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2307 grouped_pipes[i]->stream_res.tg, &gsl_params);
2308
2309 /* Reset slave controllers on master VSync */
2310 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2311
2312 for (i = 1 /* skip the master */; i < group_size; i++)
2313 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2314 grouped_pipes[i]->stream_res.tg,
2315 gsl_params.gsl_group);
2316
2317 for (i = 1 /* skip the master */; i < group_size; i++) {
2318 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2319 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2320 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2321 grouped_pipes[i]->stream_res.tg);
2322 }
2323
2324 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2325 * is that the sync'ed displays will not drift out of sync over time*/
2326 DC_SYNC_INFO("GSL: Restoring register states.\n");
2327 for (i = 0; i < group_size; i++)
2328 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2329
2330 DC_SYNC_INFO("GSL: Set-up complete.\n");
2331 }
2332
2333 static void dce110_enable_per_frame_crtc_position_reset(
2334 struct dc *dc,
2335 int group_size,
2336 struct pipe_ctx *grouped_pipes[])
2337 {
2338 struct dc_context *dc_ctx = dc->ctx;
2339 struct dcp_gsl_params gsl_params = { 0 };
2340 int i;
2341
2342 gsl_params.gsl_group = 0;
2343 gsl_params.gsl_master = 0;
2344
2345 for (i = 0; i < group_size; i++)
2346 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2347 grouped_pipes[i]->stream_res.tg, &gsl_params);
2348
2349 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2350
2351 for (i = 1; i < group_size; i++)
2352 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2353 grouped_pipes[i]->stream_res.tg,
2354 gsl_params.gsl_master,
2355 &grouped_pipes[i]->stream->triggered_crtc_reset);
2356
2357 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2358 for (i = 1; i < group_size; i++)
2359 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2360
2361 for (i = 0; i < group_size; i++)
2362 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2363
2364 }
2365
2366 static void init_pipes(struct dc *dc, struct dc_state *context)
2367 {
2368 // Do nothing
2369 }
2370
2371 static void init_hw(struct dc *dc)
2372 {
2373 int i;
2374 struct dc_bios *bp;
2375 struct transform *xfm;
2376 struct abm *abm;
2377 struct dmcu *dmcu;
2378 struct dce_hwseq *hws = dc->hwseq;
2379
2380 bp = dc->ctx->dc_bios;
2381 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2382 xfm = dc->res_pool->transforms[i];
2383 xfm->funcs->transform_reset(xfm);
2384
2385 hws->funcs.enable_display_power_gating(
2386 dc, i, bp,
2387 PIPE_GATING_CONTROL_INIT);
2388 hws->funcs.enable_display_power_gating(
2389 dc, i, bp,
2390 PIPE_GATING_CONTROL_DISABLE);
2391 hws->funcs.enable_display_pipe_clock_gating(
2392 dc->ctx,
2393 true);
2394 }
2395
2396 dce_clock_gating_power_up(dc->hwseq, false);
2397 /***************************************/
2398
2399 for (i = 0; i < dc->link_count; i++) {
2400 /****************************************/
2401 /* Power up AND update implementation according to the
2402 * required signal (which may be different from the
2403 * default signal on connector). */
2404 struct dc_link *link = dc->links[i];
2405
2406 link->link_enc->funcs->hw_init(link->link_enc);
2407 }
2408
2409 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2410 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2411
2412 tg->funcs->disable_vga(tg);
2413
2414 /* Blank controller using driver code instead of
2415 * command table. */
2416 tg->funcs->set_blank(tg, true);
2417 hwss_wait_for_blank_complete(tg);
2418 }
2419
2420 for (i = 0; i < dc->res_pool->audio_count; i++) {
2421 struct audio *audio = dc->res_pool->audios[i];
2422 audio->funcs->hw_init(audio);
2423 }
2424
2425 abm = dc->res_pool->abm;
2426 if (abm != NULL) {
2427 abm->funcs->init_backlight(abm);
2428 abm->funcs->abm_init(abm);
2429 }
2430
2431 dmcu = dc->res_pool->dmcu;
2432 if (dmcu != NULL && abm != NULL)
2433 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2434
2435 if (dc->fbc_compressor)
2436 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2437
2438 }
2439
2440
2441 void dce110_prepare_bandwidth(
2442 struct dc *dc,
2443 struct dc_state *context)
2444 {
2445 struct clk_mgr *dccg = dc->clk_mgr;
2446
2447 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2448
2449 dccg->funcs->update_clocks(
2450 dccg,
2451 context,
2452 false);
2453 }
2454
2455 void dce110_optimize_bandwidth(
2456 struct dc *dc,
2457 struct dc_state *context)
2458 {
2459 struct clk_mgr *dccg = dc->clk_mgr;
2460
2461 dce110_set_displaymarks(dc, context);
2462
2463 dccg->funcs->update_clocks(
2464 dccg,
2465 context,
2466 true);
2467 }
2468
2469 static void dce110_program_front_end_for_pipe(
2470 struct dc *dc, struct pipe_ctx *pipe_ctx)
2471 {
2472 struct mem_input *mi = pipe_ctx->plane_res.mi;
2473 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2474 struct xfm_grph_csc_adjustment adjust;
2475 struct out_csc_color_matrix tbl_entry;
2476 unsigned int i;
2477 struct dce_hwseq *hws = dc->hwseq;
2478
2479 DC_LOGGER_INIT();
2480 memset(&tbl_entry, 0, sizeof(tbl_entry));
2481
2482 memset(&adjust, 0, sizeof(adjust));
2483 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2484
2485 dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2486
2487 set_default_colors(pipe_ctx);
2488 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2489 == true) {
2490 tbl_entry.color_space =
2491 pipe_ctx->stream->output_color_space;
2492
2493 for (i = 0; i < 12; i++)
2494 tbl_entry.regval[i] =
2495 pipe_ctx->stream->csc_color_matrix.matrix[i];
2496
2497 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2498 (pipe_ctx->plane_res.xfm, &tbl_entry);
2499 }
2500
2501 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2502 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2503
2504 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2505 adjust.temperature_matrix[i] =
2506 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2507 }
2508
2509 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2510
2511 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2512
2513 program_scaler(dc, pipe_ctx);
2514
2515 mi->funcs->mem_input_program_surface_config(
2516 mi,
2517 plane_state->format,
2518 &plane_state->tiling_info,
2519 &plane_state->plane_size,
2520 plane_state->rotation,
2521 NULL,
2522 false);
2523 if (mi->funcs->set_blank)
2524 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2525
2526 if (dc->config.gpu_vm_support)
2527 mi->funcs->mem_input_program_pte_vm(
2528 pipe_ctx->plane_res.mi,
2529 plane_state->format,
2530 &plane_state->tiling_info,
2531 plane_state->rotation);
2532
2533 /* Moved programming gamma from dc to hwss */
2534 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2535 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2536 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2537 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2538
2539 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2540 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2541
2542 DC_LOG_SURFACE(
2543 "Pipe:%d %p: addr hi:0x%x, "
2544 "addr low:0x%x, "
2545 "src: %d, %d, %d,"
2546 " %d; dst: %d, %d, %d, %d;"
2547 "clip: %d, %d, %d, %d\n",
2548 pipe_ctx->pipe_idx,
2549 (void *) pipe_ctx->plane_state,
2550 pipe_ctx->plane_state->address.grph.addr.high_part,
2551 pipe_ctx->plane_state->address.grph.addr.low_part,
2552 pipe_ctx->plane_state->src_rect.x,
2553 pipe_ctx->plane_state->src_rect.y,
2554 pipe_ctx->plane_state->src_rect.width,
2555 pipe_ctx->plane_state->src_rect.height,
2556 pipe_ctx->plane_state->dst_rect.x,
2557 pipe_ctx->plane_state->dst_rect.y,
2558 pipe_ctx->plane_state->dst_rect.width,
2559 pipe_ctx->plane_state->dst_rect.height,
2560 pipe_ctx->plane_state->clip_rect.x,
2561 pipe_ctx->plane_state->clip_rect.y,
2562 pipe_ctx->plane_state->clip_rect.width,
2563 pipe_ctx->plane_state->clip_rect.height);
2564
2565 DC_LOG_SURFACE(
2566 "Pipe %d: width, height, x, y\n"
2567 "viewport:%d, %d, %d, %d\n"
2568 "recout: %d, %d, %d, %d\n",
2569 pipe_ctx->pipe_idx,
2570 pipe_ctx->plane_res.scl_data.viewport.width,
2571 pipe_ctx->plane_res.scl_data.viewport.height,
2572 pipe_ctx->plane_res.scl_data.viewport.x,
2573 pipe_ctx->plane_res.scl_data.viewport.y,
2574 pipe_ctx->plane_res.scl_data.recout.width,
2575 pipe_ctx->plane_res.scl_data.recout.height,
2576 pipe_ctx->plane_res.scl_data.recout.x,
2577 pipe_ctx->plane_res.scl_data.recout.y);
2578 }
2579
2580 static void dce110_apply_ctx_for_surface(
2581 struct dc *dc,
2582 const struct dc_stream_state *stream,
2583 int num_planes,
2584 struct dc_state *context)
2585 {
2586 int i;
2587
2588 if (num_planes == 0)
2589 return;
2590
2591 if (dc->fbc_compressor)
2592 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2593
2594 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2595 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2596
2597 if (pipe_ctx->stream != stream)
2598 continue;
2599
2600 /* Need to allocate mem before program front end for Fiji */
2601 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2602 pipe_ctx->plane_res.mi,
2603 pipe_ctx->stream->timing.h_total,
2604 pipe_ctx->stream->timing.v_total,
2605 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2606 context->stream_count);
2607
2608 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2609
2610 dc->hwss.update_plane_addr(dc, pipe_ctx);
2611
2612 program_surface_visibility(dc, pipe_ctx);
2613
2614 }
2615
2616 if (dc->fbc_compressor)
2617 enable_fbc(dc, context);
2618 }
2619
2620 static void dce110_post_unlock_program_front_end(
2621 struct dc *dc,
2622 struct dc_state *context)
2623 {
2624 }
2625
2626 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2627 {
2628 struct dce_hwseq *hws = dc->hwseq;
2629 int fe_idx = pipe_ctx->plane_res.mi ?
2630 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2631
2632 /* Do not power down fe when stream is active on dce*/
2633 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2634 return;
2635
2636 hws->funcs.enable_display_power_gating(
2637 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2638
2639 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2640 dc->res_pool->transforms[fe_idx]);
2641 }
2642
2643 static void dce110_wait_for_mpcc_disconnect(
2644 struct dc *dc,
2645 struct resource_pool *res_pool,
2646 struct pipe_ctx *pipe_ctx)
2647 {
2648 /* do nothing*/
2649 }
2650
2651 static void program_output_csc(struct dc *dc,
2652 struct pipe_ctx *pipe_ctx,
2653 enum dc_color_space colorspace,
2654 uint16_t *matrix,
2655 int opp_id)
2656 {
2657 int i;
2658 struct out_csc_color_matrix tbl_entry;
2659
2660 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2661 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2662
2663 for (i = 0; i < 12; i++)
2664 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2665
2666 tbl_entry.color_space = color_space;
2667
2668 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2669 pipe_ctx->plane_res.xfm, &tbl_entry);
2670 }
2671 }
2672
2673 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2674 {
2675 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2676 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2677 struct mem_input *mi = pipe_ctx->plane_res.mi;
2678 struct dc_cursor_mi_param param = {
2679 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2680 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2681 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2682 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2683 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2684 .rotation = pipe_ctx->plane_state->rotation,
2685 .mirror = pipe_ctx->plane_state->horizontal_mirror
2686 };
2687
2688 /**
2689 * If the cursor's source viewport is clipped then we need to
2690 * translate the cursor to appear in the correct position on
2691 * the screen.
2692 *
2693 * This translation isn't affected by scaling so it needs to be
2694 * done *after* we adjust the position for the scale factor.
2695 *
2696 * This is only done by opt-in for now since there are still
2697 * some usecases like tiled display that might enable the
2698 * cursor on both streams while expecting dc to clip it.
2699 */
2700 if (pos_cpy.translate_by_source) {
2701 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2702 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2703 }
2704
2705 if (pipe_ctx->plane_state->address.type
2706 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2707 pos_cpy.enable = false;
2708
2709 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2710 pos_cpy.enable = false;
2711
2712 if (ipp->funcs->ipp_cursor_set_position)
2713 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2714 if (mi->funcs->set_cursor_position)
2715 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2716 }
2717
2718 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2719 {
2720 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2721
2722 if (pipe_ctx->plane_res.ipp &&
2723 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2724 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2725 pipe_ctx->plane_res.ipp, attributes);
2726
2727 if (pipe_ctx->plane_res.mi &&
2728 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2729 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2730 pipe_ctx->plane_res.mi, attributes);
2731
2732 if (pipe_ctx->plane_res.xfm &&
2733 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2734 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2735 pipe_ctx->plane_res.xfm, attributes);
2736 }
2737
2738 static const struct hw_sequencer_funcs dce110_funcs = {
2739 .program_gamut_remap = program_gamut_remap,
2740 .program_output_csc = program_output_csc,
2741 .init_hw = init_hw,
2742 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2743 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2744 .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
2745 .update_plane_addr = update_plane_addr,
2746 .update_pending_status = dce110_update_pending_status,
2747 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2748 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2749 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2750 .update_info_frame = dce110_update_info_frame,
2751 .enable_stream = dce110_enable_stream,
2752 .disable_stream = dce110_disable_stream,
2753 .unblank_stream = dce110_unblank_stream,
2754 .blank_stream = dce110_blank_stream,
2755 .enable_audio_stream = dce110_enable_audio_stream,
2756 .disable_audio_stream = dce110_disable_audio_stream,
2757 .disable_plane = dce110_power_down_fe,
2758 .pipe_control_lock = dce_pipe_control_lock,
2759 .interdependent_update_lock = NULL,
2760 .cursor_lock = dce_pipe_control_lock,
2761 .prepare_bandwidth = dce110_prepare_bandwidth,
2762 .optimize_bandwidth = dce110_optimize_bandwidth,
2763 .set_drr = set_drr,
2764 .get_position = get_position,
2765 .set_static_screen_control = set_static_screen_control,
2766 .setup_stereo = NULL,
2767 .set_avmute = dce110_set_avmute,
2768 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2769 .edp_power_control = dce110_edp_power_control,
2770 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
2771 .set_cursor_position = dce110_set_cursor_position,
2772 .set_cursor_attribute = dce110_set_cursor_attribute
2773 };
2774
2775 static const struct hwseq_private_funcs dce110_private_funcs = {
2776 .init_pipes = init_pipes,
2777 .update_plane_addr = update_plane_addr,
2778 .set_input_transfer_func = dce110_set_input_transfer_func,
2779 .set_output_transfer_func = dce110_set_output_transfer_func,
2780 .power_down = dce110_power_down,
2781 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2782 .enable_display_power_gating = dce110_enable_display_power_gating,
2783 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2784 .enable_stream_timing = dce110_enable_stream_timing,
2785 .disable_stream_gating = NULL,
2786 .enable_stream_gating = NULL,
2787 .edp_backlight_control = dce110_edp_backlight_control,
2788 .is_panel_backlight_on = dce110_is_panel_backlight_on,
2789 .is_panel_powered_on = dce110_is_panel_powered_on,
2790 };
2791
2792 void dce110_hw_sequencer_construct(struct dc *dc)
2793 {
2794 dc->hwss = dce110_funcs;
2795 dc->hwseq->funcs = dce110_private_funcs;
2796 }
2797
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