]> git.ipfire.org Git - thirdparty/kernel/stable.git/blob - drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
projects / thirdparty / kernel / stable.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'kvm-x86-generic-6.8' of https://github.com/kvm-x86/linux into HEAD
[thirdparty/kernel/stable.git] / drivers / gpu / drm / amd / display / dc / dml / dcn20 / dcn20_fpu.c
1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2021 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "resource.h"
28 #include "clk_mgr.h"
29 #include "dchubbub.h"
30 #include "dcn20/dcn20_resource.h"
31 #include "dcn21/dcn21_resource.h"
32 #include "clk_mgr/dcn21/rn_clk_mgr.h"
33
34 #include "link.h"
35 #include "dcn20_fpu.h"
36
37 #define DC_LOGGER \
38 dc->ctx->logger
39 #define DC_LOGGER_INIT(logger)
40
41 #ifndef MAX
42 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
43 #endif
44 #ifndef MIN
45 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
46 #endif
47
48 /* Constant */
49 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
50
51 /**
52 * DOC: DCN2x FPU manipulation Overview
53 *
54 * The DCN architecture relies on FPU operations, which require special
55 * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
56 * want to avoid spreading FPU access across multiple files. With this idea in
57 * mind, this file aims to centralize all DCN20 and DCN2.1 (DCN2x) functions
58 * that require FPU access in a single place. Code in this file follows the
59 * following code pattern:
60 *
61 * 1. Functions that use FPU operations should be isolated in static functions.
62 * 2. The FPU functions should have the noinline attribute to ensure anything
63 * that deals with FP register is contained within this call.
64 * 3. All function that needs to be accessed outside this file requires a
65 * public interface that not uses any FPU reference.
66 * 4. Developers **must not** use DC_FP_START/END in this file, but they need
67 * to ensure that the caller invokes it before access any function available
68 * in this file. For this reason, public functions in this file must invoke
69 * dc_assert_fp_enabled();
70 *
71 * Let's expand a little bit more the idea in the code pattern. To fully
72 * isolate FPU operations in a single place, we must avoid situations where
73 * compilers spill FP values to registers due to FP enable in a specific C
74 * file. Note that even if we isolate all FPU functions in a single file and
75 * call its interface from other files, the compiler might enable the use of
76 * FPU before we call DC_FP_START. Nevertheless, it is the programmer's
77 * responsibility to invoke DC_FP_START/END in the correct place. To highlight
78 * situations where developers forgot to use the FP protection before calling
79 * the DC FPU interface functions, we introduce a helper that checks if the
80 * function is invoked under FP protection. If not, it will trigger a kernel
81 * warning.
82 */
83
84 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
85 .odm_capable = 1,
86 .gpuvm_enable = 0,
87 .hostvm_enable = 0,
88 .gpuvm_max_page_table_levels = 4,
89 .hostvm_max_page_table_levels = 4,
90 .hostvm_cached_page_table_levels = 0,
91 .pte_group_size_bytes = 2048,
92 .num_dsc = 6,
93 .rob_buffer_size_kbytes = 168,
94 .det_buffer_size_kbytes = 164,
95 .dpte_buffer_size_in_pte_reqs_luma = 84,
96 .pde_proc_buffer_size_64k_reqs = 48,
97 .dpp_output_buffer_pixels = 2560,
98 .opp_output_buffer_lines = 1,
99 .pixel_chunk_size_kbytes = 8,
100 .pte_chunk_size_kbytes = 2,
101 .meta_chunk_size_kbytes = 2,
102 .writeback_chunk_size_kbytes = 2,
103 .line_buffer_size_bits = 789504,
104 .is_line_buffer_bpp_fixed = 0,
105 .line_buffer_fixed_bpp = 0,
106 .dcc_supported = true,
107 .max_line_buffer_lines = 12,
108 .writeback_luma_buffer_size_kbytes = 12,
109 .writeback_chroma_buffer_size_kbytes = 8,
110 .writeback_chroma_line_buffer_width_pixels = 4,
111 .writeback_max_hscl_ratio = 1,
112 .writeback_max_vscl_ratio = 1,
113 .writeback_min_hscl_ratio = 1,
114 .writeback_min_vscl_ratio = 1,
115 .writeback_max_hscl_taps = 12,
116 .writeback_max_vscl_taps = 12,
117 .writeback_line_buffer_luma_buffer_size = 0,
118 .writeback_line_buffer_chroma_buffer_size = 14643,
119 .cursor_buffer_size = 8,
120 .cursor_chunk_size = 2,
121 .max_num_otg = 6,
122 .max_num_dpp = 6,
123 .max_num_wb = 1,
124 .max_dchub_pscl_bw_pix_per_clk = 4,
125 .max_pscl_lb_bw_pix_per_clk = 2,
126 .max_lb_vscl_bw_pix_per_clk = 4,
127 .max_vscl_hscl_bw_pix_per_clk = 4,
128 .max_hscl_ratio = 8,
129 .max_vscl_ratio = 8,
130 .hscl_mults = 4,
131 .vscl_mults = 4,
132 .max_hscl_taps = 8,
133 .max_vscl_taps = 8,
134 .dispclk_ramp_margin_percent = 1,
135 .underscan_factor = 1.10,
136 .min_vblank_lines = 32, //
137 .dppclk_delay_subtotal = 77, //
138 .dppclk_delay_scl_lb_only = 16,
139 .dppclk_delay_scl = 50,
140 .dppclk_delay_cnvc_formatter = 8,
141 .dppclk_delay_cnvc_cursor = 6,
142 .dispclk_delay_subtotal = 87, //
143 .dcfclk_cstate_latency = 10, // SRExitTime
144 .max_inter_dcn_tile_repeaters = 8,
145 .xfc_supported = true,
146 .xfc_fill_bw_overhead_percent = 10.0,
147 .xfc_fill_constant_bytes = 0,
148 .number_of_cursors = 1,
149 };
150
151 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
152 .odm_capable = 1,
153 .gpuvm_enable = 0,
154 .hostvm_enable = 0,
155 .gpuvm_max_page_table_levels = 4,
156 .hostvm_max_page_table_levels = 4,
157 .hostvm_cached_page_table_levels = 0,
158 .num_dsc = 5,
159 .rob_buffer_size_kbytes = 168,
160 .det_buffer_size_kbytes = 164,
161 .dpte_buffer_size_in_pte_reqs_luma = 84,
162 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
163 .dpp_output_buffer_pixels = 2560,
164 .opp_output_buffer_lines = 1,
165 .pixel_chunk_size_kbytes = 8,
166 .pte_enable = 1,
167 .max_page_table_levels = 4,
168 .pte_chunk_size_kbytes = 2,
169 .meta_chunk_size_kbytes = 2,
170 .writeback_chunk_size_kbytes = 2,
171 .line_buffer_size_bits = 789504,
172 .is_line_buffer_bpp_fixed = 0,
173 .line_buffer_fixed_bpp = 0,
174 .dcc_supported = true,
175 .max_line_buffer_lines = 12,
176 .writeback_luma_buffer_size_kbytes = 12,
177 .writeback_chroma_buffer_size_kbytes = 8,
178 .writeback_chroma_line_buffer_width_pixels = 4,
179 .writeback_max_hscl_ratio = 1,
180 .writeback_max_vscl_ratio = 1,
181 .writeback_min_hscl_ratio = 1,
182 .writeback_min_vscl_ratio = 1,
183 .writeback_max_hscl_taps = 12,
184 .writeback_max_vscl_taps = 12,
185 .writeback_line_buffer_luma_buffer_size = 0,
186 .writeback_line_buffer_chroma_buffer_size = 14643,
187 .cursor_buffer_size = 8,
188 .cursor_chunk_size = 2,
189 .max_num_otg = 5,
190 .max_num_dpp = 5,
191 .max_num_wb = 1,
192 .max_dchub_pscl_bw_pix_per_clk = 4,
193 .max_pscl_lb_bw_pix_per_clk = 2,
194 .max_lb_vscl_bw_pix_per_clk = 4,
195 .max_vscl_hscl_bw_pix_per_clk = 4,
196 .max_hscl_ratio = 8,
197 .max_vscl_ratio = 8,
198 .hscl_mults = 4,
199 .vscl_mults = 4,
200 .max_hscl_taps = 8,
201 .max_vscl_taps = 8,
202 .dispclk_ramp_margin_percent = 1,
203 .underscan_factor = 1.10,
204 .min_vblank_lines = 32, //
205 .dppclk_delay_subtotal = 77, //
206 .dppclk_delay_scl_lb_only = 16,
207 .dppclk_delay_scl = 50,
208 .dppclk_delay_cnvc_formatter = 8,
209 .dppclk_delay_cnvc_cursor = 6,
210 .dispclk_delay_subtotal = 87, //
211 .dcfclk_cstate_latency = 10, // SRExitTime
212 .max_inter_dcn_tile_repeaters = 8,
213 .xfc_supported = true,
214 .xfc_fill_bw_overhead_percent = 10.0,
215 .xfc_fill_constant_bytes = 0,
216 .ptoi_supported = 0,
217 .number_of_cursors = 1,
218 };
219
220 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
221 /* Defaults that get patched on driver load from firmware. */
222 .clock_limits = {
223 {
224 .state = 0,
225 .dcfclk_mhz = 560.0,
226 .fabricclk_mhz = 560.0,
227 .dispclk_mhz = 513.0,
228 .dppclk_mhz = 513.0,
229 .phyclk_mhz = 540.0,
230 .socclk_mhz = 560.0,
231 .dscclk_mhz = 171.0,
232 .dram_speed_mts = 8960.0,
233 },
234 {
235 .state = 1,
236 .dcfclk_mhz = 694.0,
237 .fabricclk_mhz = 694.0,
238 .dispclk_mhz = 642.0,
239 .dppclk_mhz = 642.0,
240 .phyclk_mhz = 600.0,
241 .socclk_mhz = 694.0,
242 .dscclk_mhz = 214.0,
243 .dram_speed_mts = 11104.0,
244 },
245 {
246 .state = 2,
247 .dcfclk_mhz = 875.0,
248 .fabricclk_mhz = 875.0,
249 .dispclk_mhz = 734.0,
250 .dppclk_mhz = 734.0,
251 .phyclk_mhz = 810.0,
252 .socclk_mhz = 875.0,
253 .dscclk_mhz = 245.0,
254 .dram_speed_mts = 14000.0,
255 },
256 {
257 .state = 3,
258 .dcfclk_mhz = 1000.0,
259 .fabricclk_mhz = 1000.0,
260 .dispclk_mhz = 1100.0,
261 .dppclk_mhz = 1100.0,
262 .phyclk_mhz = 810.0,
263 .socclk_mhz = 1000.0,
264 .dscclk_mhz = 367.0,
265 .dram_speed_mts = 16000.0,
266 },
267 {
268 .state = 4,
269 .dcfclk_mhz = 1200.0,
270 .fabricclk_mhz = 1200.0,
271 .dispclk_mhz = 1284.0,
272 .dppclk_mhz = 1284.0,
273 .phyclk_mhz = 810.0,
274 .socclk_mhz = 1200.0,
275 .dscclk_mhz = 428.0,
276 .dram_speed_mts = 16000.0,
277 },
278 /*Extra state, no dispclk ramping*/
279 {
280 .state = 5,
281 .dcfclk_mhz = 1200.0,
282 .fabricclk_mhz = 1200.0,
283 .dispclk_mhz = 1284.0,
284 .dppclk_mhz = 1284.0,
285 .phyclk_mhz = 810.0,
286 .socclk_mhz = 1200.0,
287 .dscclk_mhz = 428.0,
288 .dram_speed_mts = 16000.0,
289 },
290 },
291 .num_states = 5,
292 .sr_exit_time_us = 8.6,
293 .sr_enter_plus_exit_time_us = 10.9,
294 .urgent_latency_us = 4.0,
295 .urgent_latency_pixel_data_only_us = 4.0,
296 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
297 .urgent_latency_vm_data_only_us = 4.0,
298 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
299 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
300 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
301 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
302 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
303 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
304 .max_avg_sdp_bw_use_normal_percent = 40.0,
305 .max_avg_dram_bw_use_normal_percent = 40.0,
306 .writeback_latency_us = 12.0,
307 .ideal_dram_bw_after_urgent_percent = 40.0,
308 .max_request_size_bytes = 256,
309 .dram_channel_width_bytes = 2,
310 .fabric_datapath_to_dcn_data_return_bytes = 64,
311 .dcn_downspread_percent = 0.5,
312 .downspread_percent = 0.38,
313 .dram_page_open_time_ns = 50.0,
314 .dram_rw_turnaround_time_ns = 17.5,
315 .dram_return_buffer_per_channel_bytes = 8192,
316 .round_trip_ping_latency_dcfclk_cycles = 131,
317 .urgent_out_of_order_return_per_channel_bytes = 256,
318 .channel_interleave_bytes = 256,
319 .num_banks = 8,
320 .num_chans = 16,
321 .vmm_page_size_bytes = 4096,
322 .dram_clock_change_latency_us = 404.0,
323 .dummy_pstate_latency_us = 5.0,
324 .writeback_dram_clock_change_latency_us = 23.0,
325 .return_bus_width_bytes = 64,
326 .dispclk_dppclk_vco_speed_mhz = 3850,
327 .xfc_bus_transport_time_us = 20,
328 .xfc_xbuf_latency_tolerance_us = 4,
329 .use_urgent_burst_bw = 0
330 };
331
332 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
333 .clock_limits = {
334 {
335 .state = 0,
336 .dcfclk_mhz = 560.0,
337 .fabricclk_mhz = 560.0,
338 .dispclk_mhz = 513.0,
339 .dppclk_mhz = 513.0,
340 .phyclk_mhz = 540.0,
341 .socclk_mhz = 560.0,
342 .dscclk_mhz = 171.0,
343 .dram_speed_mts = 8960.0,
344 },
345 {
346 .state = 1,
347 .dcfclk_mhz = 694.0,
348 .fabricclk_mhz = 694.0,
349 .dispclk_mhz = 642.0,
350 .dppclk_mhz = 642.0,
351 .phyclk_mhz = 600.0,
352 .socclk_mhz = 694.0,
353 .dscclk_mhz = 214.0,
354 .dram_speed_mts = 11104.0,
355 },
356 {
357 .state = 2,
358 .dcfclk_mhz = 875.0,
359 .fabricclk_mhz = 875.0,
360 .dispclk_mhz = 734.0,
361 .dppclk_mhz = 734.0,
362 .phyclk_mhz = 810.0,
363 .socclk_mhz = 875.0,
364 .dscclk_mhz = 245.0,
365 .dram_speed_mts = 14000.0,
366 },
367 {
368 .state = 3,
369 .dcfclk_mhz = 1000.0,
370 .fabricclk_mhz = 1000.0,
371 .dispclk_mhz = 1100.0,
372 .dppclk_mhz = 1100.0,
373 .phyclk_mhz = 810.0,
374 .socclk_mhz = 1000.0,
375 .dscclk_mhz = 367.0,
376 .dram_speed_mts = 16000.0,
377 },
378 {
379 .state = 4,
380 .dcfclk_mhz = 1200.0,
381 .fabricclk_mhz = 1200.0,
382 .dispclk_mhz = 1284.0,
383 .dppclk_mhz = 1284.0,
384 .phyclk_mhz = 810.0,
385 .socclk_mhz = 1200.0,
386 .dscclk_mhz = 428.0,
387 .dram_speed_mts = 16000.0,
388 },
389 /*Extra state, no dispclk ramping*/
390 {
391 .state = 5,
392 .dcfclk_mhz = 1200.0,
393 .fabricclk_mhz = 1200.0,
394 .dispclk_mhz = 1284.0,
395 .dppclk_mhz = 1284.0,
396 .phyclk_mhz = 810.0,
397 .socclk_mhz = 1200.0,
398 .dscclk_mhz = 428.0,
399 .dram_speed_mts = 16000.0,
400 },
401 },
402 .num_states = 5,
403 .sr_exit_time_us = 11.6,
404 .sr_enter_plus_exit_time_us = 13.9,
405 .urgent_latency_us = 4.0,
406 .urgent_latency_pixel_data_only_us = 4.0,
407 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
408 .urgent_latency_vm_data_only_us = 4.0,
409 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
410 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
411 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
412 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
413 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
414 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
415 .max_avg_sdp_bw_use_normal_percent = 40.0,
416 .max_avg_dram_bw_use_normal_percent = 40.0,
417 .writeback_latency_us = 12.0,
418 .ideal_dram_bw_after_urgent_percent = 40.0,
419 .max_request_size_bytes = 256,
420 .dram_channel_width_bytes = 2,
421 .fabric_datapath_to_dcn_data_return_bytes = 64,
422 .dcn_downspread_percent = 0.5,
423 .downspread_percent = 0.38,
424 .dram_page_open_time_ns = 50.0,
425 .dram_rw_turnaround_time_ns = 17.5,
426 .dram_return_buffer_per_channel_bytes = 8192,
427 .round_trip_ping_latency_dcfclk_cycles = 131,
428 .urgent_out_of_order_return_per_channel_bytes = 256,
429 .channel_interleave_bytes = 256,
430 .num_banks = 8,
431 .num_chans = 8,
432 .vmm_page_size_bytes = 4096,
433 .dram_clock_change_latency_us = 404.0,
434 .dummy_pstate_latency_us = 5.0,
435 .writeback_dram_clock_change_latency_us = 23.0,
436 .return_bus_width_bytes = 64,
437 .dispclk_dppclk_vco_speed_mhz = 3850,
438 .xfc_bus_transport_time_us = 20,
439 .xfc_xbuf_latency_tolerance_us = 4,
440 .use_urgent_burst_bw = 0
441 };
442
443 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
444
445 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
446 .odm_capable = 1,
447 .gpuvm_enable = 1,
448 .hostvm_enable = 1,
449 .gpuvm_max_page_table_levels = 1,
450 .hostvm_max_page_table_levels = 4,
451 .hostvm_cached_page_table_levels = 2,
452 .num_dsc = 3,
453 .rob_buffer_size_kbytes = 168,
454 .det_buffer_size_kbytes = 164,
455 .dpte_buffer_size_in_pte_reqs_luma = 44,
456 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
457 .dpp_output_buffer_pixels = 2560,
458 .opp_output_buffer_lines = 1,
459 .pixel_chunk_size_kbytes = 8,
460 .pte_enable = 1,
461 .max_page_table_levels = 4,
462 .pte_chunk_size_kbytes = 2,
463 .meta_chunk_size_kbytes = 2,
464 .min_meta_chunk_size_bytes = 256,
465 .writeback_chunk_size_kbytes = 2,
466 .line_buffer_size_bits = 789504,
467 .is_line_buffer_bpp_fixed = 0,
468 .line_buffer_fixed_bpp = 0,
469 .dcc_supported = true,
470 .max_line_buffer_lines = 12,
471 .writeback_luma_buffer_size_kbytes = 12,
472 .writeback_chroma_buffer_size_kbytes = 8,
473 .writeback_chroma_line_buffer_width_pixels = 4,
474 .writeback_max_hscl_ratio = 1,
475 .writeback_max_vscl_ratio = 1,
476 .writeback_min_hscl_ratio = 1,
477 .writeback_min_vscl_ratio = 1,
478 .writeback_max_hscl_taps = 12,
479 .writeback_max_vscl_taps = 12,
480 .writeback_line_buffer_luma_buffer_size = 0,
481 .writeback_line_buffer_chroma_buffer_size = 14643,
482 .cursor_buffer_size = 8,
483 .cursor_chunk_size = 2,
484 .max_num_otg = 4,
485 .max_num_dpp = 4,
486 .max_num_wb = 1,
487 .max_dchub_pscl_bw_pix_per_clk = 4,
488 .max_pscl_lb_bw_pix_per_clk = 2,
489 .max_lb_vscl_bw_pix_per_clk = 4,
490 .max_vscl_hscl_bw_pix_per_clk = 4,
491 .max_hscl_ratio = 4,
492 .max_vscl_ratio = 4,
493 .hscl_mults = 4,
494 .vscl_mults = 4,
495 .max_hscl_taps = 8,
496 .max_vscl_taps = 8,
497 .dispclk_ramp_margin_percent = 1,
498 .underscan_factor = 1.10,
499 .min_vblank_lines = 32, //
500 .dppclk_delay_subtotal = 77, //
501 .dppclk_delay_scl_lb_only = 16,
502 .dppclk_delay_scl = 50,
503 .dppclk_delay_cnvc_formatter = 8,
504 .dppclk_delay_cnvc_cursor = 6,
505 .dispclk_delay_subtotal = 87, //
506 .dcfclk_cstate_latency = 10, // SRExitTime
507 .max_inter_dcn_tile_repeaters = 8,
508
509 .xfc_supported = false,
510 .xfc_fill_bw_overhead_percent = 10.0,
511 .xfc_fill_constant_bytes = 0,
512 .ptoi_supported = 0,
513 .number_of_cursors = 1,
514 };
515
516 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
517 .clock_limits = {
518 {
519 .state = 0,
520 .dcfclk_mhz = 400.0,
521 .fabricclk_mhz = 400.0,
522 .dispclk_mhz = 600.0,
523 .dppclk_mhz = 400.00,
524 .phyclk_mhz = 600.0,
525 .socclk_mhz = 278.0,
526 .dscclk_mhz = 205.67,
527 .dram_speed_mts = 1600.0,
528 },
529 {
530 .state = 1,
531 .dcfclk_mhz = 464.52,
532 .fabricclk_mhz = 800.0,
533 .dispclk_mhz = 654.55,
534 .dppclk_mhz = 626.09,
535 .phyclk_mhz = 600.0,
536 .socclk_mhz = 278.0,
537 .dscclk_mhz = 205.67,
538 .dram_speed_mts = 1600.0,
539 },
540 {
541 .state = 2,
542 .dcfclk_mhz = 514.29,
543 .fabricclk_mhz = 933.0,
544 .dispclk_mhz = 757.89,
545 .dppclk_mhz = 685.71,
546 .phyclk_mhz = 600.0,
547 .socclk_mhz = 278.0,
548 .dscclk_mhz = 287.67,
549 .dram_speed_mts = 1866.0,
550 },
551 {
552 .state = 3,
553 .dcfclk_mhz = 576.00,
554 .fabricclk_mhz = 1067.0,
555 .dispclk_mhz = 847.06,
556 .dppclk_mhz = 757.89,
557 .phyclk_mhz = 600.0,
558 .socclk_mhz = 715.0,
559 .dscclk_mhz = 318.334,
560 .dram_speed_mts = 2134.0,
561 },
562 {
563 .state = 4,
564 .dcfclk_mhz = 626.09,
565 .fabricclk_mhz = 1200.0,
566 .dispclk_mhz = 900.00,
567 .dppclk_mhz = 847.06,
568 .phyclk_mhz = 810.0,
569 .socclk_mhz = 953.0,
570 .dscclk_mhz = 300.0,
571 .dram_speed_mts = 2400.0,
572 },
573 {
574 .state = 5,
575 .dcfclk_mhz = 685.71,
576 .fabricclk_mhz = 1333.0,
577 .dispclk_mhz = 1028.57,
578 .dppclk_mhz = 960.00,
579 .phyclk_mhz = 810.0,
580 .socclk_mhz = 278.0,
581 .dscclk_mhz = 342.86,
582 .dram_speed_mts = 2666.0,
583 },
584 {
585 .state = 6,
586 .dcfclk_mhz = 757.89,
587 .fabricclk_mhz = 1467.0,
588 .dispclk_mhz = 1107.69,
589 .dppclk_mhz = 1028.57,
590 .phyclk_mhz = 810.0,
591 .socclk_mhz = 715.0,
592 .dscclk_mhz = 369.23,
593 .dram_speed_mts = 3200.0,
594 },
595 {
596 .state = 7,
597 .dcfclk_mhz = 847.06,
598 .fabricclk_mhz = 1600.0,
599 .dispclk_mhz = 1395.0,
600 .dppclk_mhz = 1285.00,
601 .phyclk_mhz = 1325.0,
602 .socclk_mhz = 953.0,
603 .dscclk_mhz = 489.0,
604 .dram_speed_mts = 4266.0,
605 },
606 /*Extra state, no dispclk ramping*/
607 {
608 .state = 8,
609 .dcfclk_mhz = 847.06,
610 .fabricclk_mhz = 1600.0,
611 .dispclk_mhz = 1395.0,
612 .dppclk_mhz = 1285.0,
613 .phyclk_mhz = 1325.0,
614 .socclk_mhz = 953.0,
615 .dscclk_mhz = 489.0,
616 .dram_speed_mts = 4266.0,
617 },
618
619 },
620
621 .sr_exit_time_us = 12.5,
622 .sr_enter_plus_exit_time_us = 17.0,
623 .urgent_latency_us = 4.0,
624 .urgent_latency_pixel_data_only_us = 4.0,
625 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
626 .urgent_latency_vm_data_only_us = 4.0,
627 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
628 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
629 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
630 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
631 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
632 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
633 .max_avg_sdp_bw_use_normal_percent = 60.0,
634 .max_avg_dram_bw_use_normal_percent = 100.0,
635 .writeback_latency_us = 12.0,
636 .max_request_size_bytes = 256,
637 .dram_channel_width_bytes = 4,
638 .fabric_datapath_to_dcn_data_return_bytes = 32,
639 .dcn_downspread_percent = 0.5,
640 .downspread_percent = 0.38,
641 .dram_page_open_time_ns = 50.0,
642 .dram_rw_turnaround_time_ns = 17.5,
643 .dram_return_buffer_per_channel_bytes = 8192,
644 .round_trip_ping_latency_dcfclk_cycles = 128,
645 .urgent_out_of_order_return_per_channel_bytes = 4096,
646 .channel_interleave_bytes = 256,
647 .num_banks = 8,
648 .num_chans = 4,
649 .vmm_page_size_bytes = 4096,
650 .dram_clock_change_latency_us = 23.84,
651 .return_bus_width_bytes = 64,
652 .dispclk_dppclk_vco_speed_mhz = 3600,
653 .xfc_bus_transport_time_us = 4,
654 .xfc_xbuf_latency_tolerance_us = 4,
655 .use_urgent_burst_bw = 1,
656 .num_states = 8
657 };
658
659 struct wm_table ddr4_wm_table_gs = {
660 .entries = {
661 {
662 .wm_inst = WM_A,
663 .wm_type = WM_TYPE_PSTATE_CHG,
664 .pstate_latency_us = 11.72,
665 .sr_exit_time_us = 7.09,
666 .sr_enter_plus_exit_time_us = 8.14,
667 .valid = true,
668 },
669 {
670 .wm_inst = WM_B,
671 .wm_type = WM_TYPE_PSTATE_CHG,
672 .pstate_latency_us = 11.72,
673 .sr_exit_time_us = 10.12,
674 .sr_enter_plus_exit_time_us = 11.48,
675 .valid = true,
676 },
677 {
678 .wm_inst = WM_C,
679 .wm_type = WM_TYPE_PSTATE_CHG,
680 .pstate_latency_us = 11.72,
681 .sr_exit_time_us = 10.12,
682 .sr_enter_plus_exit_time_us = 11.48,
683 .valid = true,
684 },
685 {
686 .wm_inst = WM_D,
687 .wm_type = WM_TYPE_PSTATE_CHG,
688 .pstate_latency_us = 11.72,
689 .sr_exit_time_us = 10.12,
690 .sr_enter_plus_exit_time_us = 11.48,
691 .valid = true,
692 },
693 }
694 };
695
696 struct wm_table lpddr4_wm_table_gs = {
697 .entries = {
698 {
699 .wm_inst = WM_A,
700 .wm_type = WM_TYPE_PSTATE_CHG,
701 .pstate_latency_us = 11.65333,
702 .sr_exit_time_us = 5.32,
703 .sr_enter_plus_exit_time_us = 6.38,
704 .valid = true,
705 },
706 {
707 .wm_inst = WM_B,
708 .wm_type = WM_TYPE_PSTATE_CHG,
709 .pstate_latency_us = 11.65333,
710 .sr_exit_time_us = 9.82,
711 .sr_enter_plus_exit_time_us = 11.196,
712 .valid = true,
713 },
714 {
715 .wm_inst = WM_C,
716 .wm_type = WM_TYPE_PSTATE_CHG,
717 .pstate_latency_us = 11.65333,
718 .sr_exit_time_us = 9.89,
719 .sr_enter_plus_exit_time_us = 11.24,
720 .valid = true,
721 },
722 {
723 .wm_inst = WM_D,
724 .wm_type = WM_TYPE_PSTATE_CHG,
725 .pstate_latency_us = 11.65333,
726 .sr_exit_time_us = 9.748,
727 .sr_enter_plus_exit_time_us = 11.102,
728 .valid = true,
729 },
730 }
731 };
732
733 struct wm_table lpddr4_wm_table_with_disabled_ppt = {
734 .entries = {
735 {
736 .wm_inst = WM_A,
737 .wm_type = WM_TYPE_PSTATE_CHG,
738 .pstate_latency_us = 11.65333,
739 .sr_exit_time_us = 8.32,
740 .sr_enter_plus_exit_time_us = 9.38,
741 .valid = true,
742 },
743 {
744 .wm_inst = WM_B,
745 .wm_type = WM_TYPE_PSTATE_CHG,
746 .pstate_latency_us = 11.65333,
747 .sr_exit_time_us = 9.82,
748 .sr_enter_plus_exit_time_us = 11.196,
749 .valid = true,
750 },
751 {
752 .wm_inst = WM_C,
753 .wm_type = WM_TYPE_PSTATE_CHG,
754 .pstate_latency_us = 11.65333,
755 .sr_exit_time_us = 9.89,
756 .sr_enter_plus_exit_time_us = 11.24,
757 .valid = true,
758 },
759 {
760 .wm_inst = WM_D,
761 .wm_type = WM_TYPE_PSTATE_CHG,
762 .pstate_latency_us = 11.65333,
763 .sr_exit_time_us = 9.748,
764 .sr_enter_plus_exit_time_us = 11.102,
765 .valid = true,
766 },
767 }
768 };
769
770 struct wm_table ddr4_wm_table_rn = {
771 .entries = {
772 {
773 .wm_inst = WM_A,
774 .wm_type = WM_TYPE_PSTATE_CHG,
775 .pstate_latency_us = 11.72,
776 .sr_exit_time_us = 11.90,
777 .sr_enter_plus_exit_time_us = 12.80,
778 .valid = true,
779 },
780 {
781 .wm_inst = WM_B,
782 .wm_type = WM_TYPE_PSTATE_CHG,
783 .pstate_latency_us = 11.72,
784 .sr_exit_time_us = 13.18,
785 .sr_enter_plus_exit_time_us = 14.30,
786 .valid = true,
787 },
788 {
789 .wm_inst = WM_C,
790 .wm_type = WM_TYPE_PSTATE_CHG,
791 .pstate_latency_us = 11.72,
792 .sr_exit_time_us = 13.18,
793 .sr_enter_plus_exit_time_us = 14.30,
794 .valid = true,
795 },
796 {
797 .wm_inst = WM_D,
798 .wm_type = WM_TYPE_PSTATE_CHG,
799 .pstate_latency_us = 11.72,
800 .sr_exit_time_us = 13.18,
801 .sr_enter_plus_exit_time_us = 14.30,
802 .valid = true,
803 },
804 }
805 };
806
807 struct wm_table ddr4_1R_wm_table_rn = {
808 .entries = {
809 {
810 .wm_inst = WM_A,
811 .wm_type = WM_TYPE_PSTATE_CHG,
812 .pstate_latency_us = 11.72,
813 .sr_exit_time_us = 13.90,
814 .sr_enter_plus_exit_time_us = 14.80,
815 .valid = true,
816 },
817 {
818 .wm_inst = WM_B,
819 .wm_type = WM_TYPE_PSTATE_CHG,
820 .pstate_latency_us = 11.72,
821 .sr_exit_time_us = 13.90,
822 .sr_enter_plus_exit_time_us = 14.80,
823 .valid = true,
824 },
825 {
826 .wm_inst = WM_C,
827 .wm_type = WM_TYPE_PSTATE_CHG,
828 .pstate_latency_us = 11.72,
829 .sr_exit_time_us = 13.90,
830 .sr_enter_plus_exit_time_us = 14.80,
831 .valid = true,
832 },
833 {
834 .wm_inst = WM_D,
835 .wm_type = WM_TYPE_PSTATE_CHG,
836 .pstate_latency_us = 11.72,
837 .sr_exit_time_us = 13.90,
838 .sr_enter_plus_exit_time_us = 14.80,
839 .valid = true,
840 },
841 }
842 };
843
844 struct wm_table lpddr4_wm_table_rn = {
845 .entries = {
846 {
847 .wm_inst = WM_A,
848 .wm_type = WM_TYPE_PSTATE_CHG,
849 .pstate_latency_us = 11.65333,
850 .sr_exit_time_us = 7.32,
851 .sr_enter_plus_exit_time_us = 8.38,
852 .valid = true,
853 },
854 {
855 .wm_inst = WM_B,
856 .wm_type = WM_TYPE_PSTATE_CHG,
857 .pstate_latency_us = 11.65333,
858 .sr_exit_time_us = 9.82,
859 .sr_enter_plus_exit_time_us = 11.196,
860 .valid = true,
861 },
862 {
863 .wm_inst = WM_C,
864 .wm_type = WM_TYPE_PSTATE_CHG,
865 .pstate_latency_us = 11.65333,
866 .sr_exit_time_us = 9.89,
867 .sr_enter_plus_exit_time_us = 11.24,
868 .valid = true,
869 },
870 {
871 .wm_inst = WM_D,
872 .wm_type = WM_TYPE_PSTATE_CHG,
873 .pstate_latency_us = 11.65333,
874 .sr_exit_time_us = 9.748,
875 .sr_enter_plus_exit_time_us = 11.102,
876 .valid = true,
877 },
878 }
879 };
880
881 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
882 struct resource_context *res_ctx,
883 display_e2e_pipe_params_st *pipes)
884 {
885 int pipe_cnt, i;
886
887 dc_assert_fp_enabled();
888
889 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
890 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
891
892 if (!res_ctx->pipe_ctx[i].stream)
893 continue;
894
895 /* Set writeback information */
896 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
897 pipes[pipe_cnt].dout.num_active_wb++;
898 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
899 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
900 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
901 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
902 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
903 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
904 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
905 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
906 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
907 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
908 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
909 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
910 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
911 else
912 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
913 } else {
914 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
915 }
916
917 pipe_cnt++;
918 }
919 }
920
921 void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
922 struct dc_state *context,
923 display_e2e_pipe_params_st *pipes,
924 int pipe_cnt, int i)
925 {
926 int k;
927
928 dc_assert_fp_enabled();
929
930 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
931 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
932 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
933 }
934 wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */
935 }
936
937 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
938 {
939 int i;
940 for (i = 0; i < dc->res_pool->pipe_count; i++) {
941 if (!context->res_ctx.pipe_ctx[i].stream)
942 continue;
943 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
944 return true;
945 }
946 return false;
947 }
948
949 static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context)
950 {
951 int plane_count;
952 int i;
953
954 plane_count = 0;
955 for (i = 0; i < dc->res_pool->pipe_count; i++) {
956 if (context->res_ctx.pipe_ctx[i].plane_state)
957 plane_count++;
958 }
959
960 /*
961 * Z9 and Z10 allowed cases:
962 * 1. 0 Planes enabled
963 * 2. single eDP, on link 0, 1 plane and stutter period > 5ms
964 * Z10 only cases:
965 * 1. single eDP, on link 0, 1 plane and stutter period >= 5ms
966 * Z8 cases:
967 * 1. stutter period sufficient
968 * Zstate not allowed cases:
969 * 1. Everything else
970 */
971 if (plane_count == 0)
972 return DCN_ZSTATE_SUPPORT_ALLOW;
973 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
974 struct dc_link *link = context->streams[0]->sink->link;
975 struct dc_stream_status *stream_status = &context->stream_status[0];
976 int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
977 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
978 bool is_pwrseq0 = link->link_index == 0;
979
980 /* Don't support multi-plane configurations */
981 if (stream_status->plane_count > 1)
982 return DCN_ZSTATE_SUPPORT_DISALLOW;
983
984 if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
985 return DCN_ZSTATE_SUPPORT_ALLOW;
986 else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr)
987 return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
988 else
989 return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW;
990 } else {
991 return DCN_ZSTATE_SUPPORT_DISALLOW;
992 }
993 }
994
995 static void dcn20_adjust_freesync_v_startup(
996 const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start)
997 {
998 struct dc_crtc_timing patched_crtc_timing;
999 uint32_t asic_blank_end = 0;
1000 uint32_t asic_blank_start = 0;
1001 uint32_t newVstartup = 0;
1002
1003 patched_crtc_timing = *dc_crtc_timing;
1004
1005 if (patched_crtc_timing.flags.INTERLACE == 1) {
1006 if (patched_crtc_timing.v_front_porch < 2)
1007 patched_crtc_timing.v_front_porch = 2;
1008 } else {
1009 if (patched_crtc_timing.v_front_porch < 1)
1010 patched_crtc_timing.v_front_porch = 1;
1011 }
1012
1013 /* blank_start = frame end - front porch */
1014 asic_blank_start = patched_crtc_timing.v_total -
1015 patched_crtc_timing.v_front_porch;
1016
1017 /* blank_end = blank_start - active */
1018 asic_blank_end = asic_blank_start -
1019 patched_crtc_timing.v_border_bottom -
1020 patched_crtc_timing.v_addressable -
1021 patched_crtc_timing.v_border_top;
1022
1023 newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start);
1024
1025 *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start);
1026 }
1027
1028 void dcn20_calculate_dlg_params(struct dc *dc,
1029 struct dc_state *context,
1030 display_e2e_pipe_params_st *pipes,
1031 int pipe_cnt,
1032 int vlevel)
1033 {
1034 int i, pipe_idx, active_hubp_count = 0;
1035
1036 dc_assert_fp_enabled();
1037
1038 /* Writeback MCIF_WB arbitration parameters */
1039 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1040
1041 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1042 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1043 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1044 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1045
1046 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
1047 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
1048
1049 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1050 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1051 context->bw_ctx.bw.dcn.clk.p_state_change_support =
1052 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1053 != dm_dram_clock_change_unsupported;
1054
1055 /* Pstate change might not be supported by hardware, but it might be
1056 * possible with firmware driven vertical blank stretching.
1057 */
1058 context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
1059
1060 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1061
1062 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1063
1064 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1065 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1066
1067 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1068 if (!context->res_ctx.pipe_ctx[i].stream)
1069 continue;
1070 if (context->res_ctx.pipe_ctx[i].plane_state)
1071 active_hubp_count++;
1072 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1073 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1074 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1075 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1076
1077 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1078 // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1079 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1080 context->res_ctx.pipe_ctx[i].unbounded_req = false;
1081 } else {
1082 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
1083 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
1084 }
1085
1086 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1087 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1088 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
1089 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1090 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1091 if (dc->ctx->dce_version < DCN_VERSION_3_1 &&
1092 context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
1093 dcn20_adjust_freesync_v_startup(
1094 &context->res_ctx.pipe_ctx[i].stream->timing,
1095 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
1096
1097 pipe_idx++;
1098 }
1099 /* If DCN isn't making memory requests we can allow pstate change */
1100 if (!active_hubp_count) {
1101 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
1102 }
1103 /*save a original dppclock copy*/
1104 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1105 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1106 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
1107 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
1108
1109 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
1110 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
1111
1112 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1113 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
1114
1115 if (!context->res_ctx.pipe_ctx[i].stream)
1116 continue;
1117
1118 /* cstate disabled on 201 */
1119 if (dc->ctx->dce_version == DCN_VERSION_2_01)
1120 cstate_en = false;
1121
1122 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
1123 &context->res_ctx.pipe_ctx[i].dlg_regs,
1124 &context->res_ctx.pipe_ctx[i].ttu_regs,
1125 pipes,
1126 pipe_cnt,
1127 pipe_idx,
1128 cstate_en,
1129 context->bw_ctx.bw.dcn.clk.p_state_change_support,
1130 false, false, true);
1131
1132 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
1133 &context->res_ctx.pipe_ctx[i].rq_regs,
1134 &pipes[pipe_idx].pipe);
1135 pipe_idx++;
1136 }
1137 context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
1138 }
1139
1140 static void swizzle_to_dml_params(
1141 enum swizzle_mode_values swizzle,
1142 unsigned int *sw_mode)
1143 {
1144 switch (swizzle) {
1145 case DC_SW_LINEAR:
1146 *sw_mode = dm_sw_linear;
1147 break;
1148 case DC_SW_4KB_S:
1149 *sw_mode = dm_sw_4kb_s;
1150 break;
1151 case DC_SW_4KB_S_X:
1152 *sw_mode = dm_sw_4kb_s_x;
1153 break;
1154 case DC_SW_4KB_D:
1155 *sw_mode = dm_sw_4kb_d;
1156 break;
1157 case DC_SW_4KB_D_X:
1158 *sw_mode = dm_sw_4kb_d_x;
1159 break;
1160 case DC_SW_64KB_S:
1161 *sw_mode = dm_sw_64kb_s;
1162 break;
1163 case DC_SW_64KB_S_X:
1164 *sw_mode = dm_sw_64kb_s_x;
1165 break;
1166 case DC_SW_64KB_S_T:
1167 *sw_mode = dm_sw_64kb_s_t;
1168 break;
1169 case DC_SW_64KB_D:
1170 *sw_mode = dm_sw_64kb_d;
1171 break;
1172 case DC_SW_64KB_D_X:
1173 *sw_mode = dm_sw_64kb_d_x;
1174 break;
1175 case DC_SW_64KB_D_T:
1176 *sw_mode = dm_sw_64kb_d_t;
1177 break;
1178 case DC_SW_64KB_R_X:
1179 *sw_mode = dm_sw_64kb_r_x;
1180 break;
1181 case DC_SW_VAR_S:
1182 *sw_mode = dm_sw_var_s;
1183 break;
1184 case DC_SW_VAR_S_X:
1185 *sw_mode = dm_sw_var_s_x;
1186 break;
1187 case DC_SW_VAR_D:
1188 *sw_mode = dm_sw_var_d;
1189 break;
1190 case DC_SW_VAR_D_X:
1191 *sw_mode = dm_sw_var_d_x;
1192 break;
1193 case DC_SW_VAR_R_X:
1194 *sw_mode = dm_sw_var_r_x;
1195 break;
1196 default:
1197 ASSERT(0); /* Not supported */
1198 break;
1199 }
1200 }
1201
1202 int dcn20_populate_dml_pipes_from_context(struct dc *dc,
1203 struct dc_state *context,
1204 display_e2e_pipe_params_st *pipes,
1205 bool fast_validate)
1206 {
1207 int pipe_cnt, i;
1208 bool synchronized_vblank = true;
1209 struct resource_context *res_ctx = &context->res_ctx;
1210
1211 dc_assert_fp_enabled();
1212
1213 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1214 if (!res_ctx->pipe_ctx[i].stream)
1215 continue;
1216
1217 if (pipe_cnt < 0) {
1218 pipe_cnt = i;
1219 continue;
1220 }
1221
1222 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
1223 continue;
1224
1225 if (dc->debug.disable_timing_sync ||
1226 (!resource_are_streams_timing_synchronizable(
1227 res_ctx->pipe_ctx[pipe_cnt].stream,
1228 res_ctx->pipe_ctx[i].stream) &&
1229 !resource_are_vblanks_synchronizable(
1230 res_ctx->pipe_ctx[pipe_cnt].stream,
1231 res_ctx->pipe_ctx[i].stream))) {
1232 synchronized_vblank = false;
1233 break;
1234 }
1235 }
1236
1237 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1238 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1239 unsigned int v_total;
1240 unsigned int front_porch;
1241 int output_bpc;
1242 struct audio_check aud_check = {0};
1243
1244 if (!res_ctx->pipe_ctx[i].stream)
1245 continue;
1246
1247 v_total = timing->v_total;
1248 front_porch = timing->v_front_porch;
1249
1250 /* todo:
1251 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1252 pipes[pipe_cnt].pipe.src.dcc = 0;
1253 pipes[pipe_cnt].pipe.src.vm = 0;*/
1254
1255 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1256
1257 pipes[pipe_cnt].pipe.dest.use_maximum_vstartup = dc->ctx->dce_version == DCN_VERSION_2_01;
1258
1259 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1260 /* todo: rotation?*/
1261 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1262 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1263 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1264 /* 1/2 vblank */
1265 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1266 (v_total - timing->v_addressable
1267 - timing->v_border_top - timing->v_border_bottom) / 2;
1268 /* 36 bytes dp, 32 hdmi */
1269 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1270 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1271 }
1272 pipes[pipe_cnt].pipe.src.dcc = false;
1273 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1274 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1275 pipes[pipe_cnt].pipe.dest.synchronize_timings = synchronized_vblank;
1276 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1277 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1278 - timing->h_addressable
1279 - timing->h_border_left
1280 - timing->h_border_right;
1281 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
1282 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1283 - timing->v_addressable
1284 - timing->v_border_top
1285 - timing->v_border_bottom;
1286 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1287 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
1288 pipes[pipe_cnt].pipe.dest.hactive =
1289 timing->h_addressable + timing->h_border_left + timing->h_border_right;
1290 pipes[pipe_cnt].pipe.dest.vactive =
1291 timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1292 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1293 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1294 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1295 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1296 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1297 pipes[pipe_cnt].dout.dp_lanes = 4;
1298 pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
1299 pipes[pipe_cnt].dout.is_virtual = 0;
1300 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1301 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1302 switch (resource_get_odm_slice_count(&res_ctx->pipe_ctx[i])) {
1303 case 2:
1304 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
1305 break;
1306 case 4:
1307 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
1308 break;
1309 default:
1310 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
1311 }
1312 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1313 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1314 == res_ctx->pipe_ctx[i].plane_state) {
1315 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
1316 int split_idx = 0;
1317
1318 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
1319 == res_ctx->pipe_ctx[i].plane_state) {
1320 first_pipe = first_pipe->top_pipe;
1321 split_idx++;
1322 }
1323 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
1324 if (split_idx == 0)
1325 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1326 else if (split_idx == 1)
1327 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1328 else if (split_idx == 2)
1329 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1330 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1331 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1332
1333 while (first_pipe->prev_odm_pipe)
1334 first_pipe = first_pipe->prev_odm_pipe;
1335 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1336 }
1337
1338 switch (res_ctx->pipe_ctx[i].stream->signal) {
1339 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1340 case SIGNAL_TYPE_DISPLAY_PORT:
1341 pipes[pipe_cnt].dout.output_type = dm_dp;
1342 if (dc->link_srv->dp_is_128b_132b_signal(&res_ctx->pipe_ctx[i]))
1343 pipes[pipe_cnt].dout.output_type = dm_dp2p0;
1344 break;
1345 case SIGNAL_TYPE_EDP:
1346 pipes[pipe_cnt].dout.output_type = dm_edp;
1347 break;
1348 case SIGNAL_TYPE_HDMI_TYPE_A:
1349 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1350 case SIGNAL_TYPE_DVI_DUAL_LINK:
1351 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1352 break;
1353 default:
1354 /* In case there is no signal, set dp with 4 lanes to allow max config */
1355 pipes[pipe_cnt].dout.is_virtual = 1;
1356 pipes[pipe_cnt].dout.output_type = dm_dp;
1357 pipes[pipe_cnt].dout.dp_lanes = 4;
1358 }
1359
1360 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1361 case COLOR_DEPTH_666:
1362 output_bpc = 6;
1363 break;
1364 case COLOR_DEPTH_888:
1365 output_bpc = 8;
1366 break;
1367 case COLOR_DEPTH_101010:
1368 output_bpc = 10;
1369 break;
1370 case COLOR_DEPTH_121212:
1371 output_bpc = 12;
1372 break;
1373 case COLOR_DEPTH_141414:
1374 output_bpc = 14;
1375 break;
1376 case COLOR_DEPTH_161616:
1377 output_bpc = 16;
1378 break;
1379 case COLOR_DEPTH_999:
1380 output_bpc = 9;
1381 break;
1382 case COLOR_DEPTH_111111:
1383 output_bpc = 11;
1384 break;
1385 default:
1386 output_bpc = 8;
1387 break;
1388 }
1389
1390 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1391 case PIXEL_ENCODING_RGB:
1392 case PIXEL_ENCODING_YCBCR444:
1393 pipes[pipe_cnt].dout.output_format = dm_444;
1394 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1395 break;
1396 case PIXEL_ENCODING_YCBCR420:
1397 pipes[pipe_cnt].dout.output_format = dm_420;
1398 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
1399 break;
1400 case PIXEL_ENCODING_YCBCR422:
1401 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
1402 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
1403 pipes[pipe_cnt].dout.output_format = dm_n422;
1404 else
1405 pipes[pipe_cnt].dout.output_format = dm_s422;
1406 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
1407 break;
1408 default:
1409 pipes[pipe_cnt].dout.output_format = dm_444;
1410 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1411 }
1412
1413 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
1414 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
1415
1416 /* todo: default max for now, until there is logic reflecting this in dc*/
1417 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1418 /*fill up the audio sample rate (unit in kHz)*/
1419 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
1420 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
1421 /*
1422 * For graphic plane, cursor number is 1, nv12 is 0
1423 * bw calculations due to cursor on/off
1424 */
1425 if (res_ctx->pipe_ctx[i].plane_state &&
1426 (res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||
1427 res_ctx->pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM))
1428 pipes[pipe_cnt].pipe.src.num_cursors = 0;
1429 else
1430 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
1431
1432 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1433 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1434
1435 if (!res_ctx->pipe_ctx[i].plane_state) {
1436 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1437 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1438 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1439 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
1440 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1441 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1442 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1443 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1444 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1445 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1446 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1447 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
1448 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
1449 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
1450 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
1451 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
1452 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1453 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1454 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1455 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
1456 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1457 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1458 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1459 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1460 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1461 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1462 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1463 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
1464 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
1465
1466 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
1467 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
1468 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
1469 } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
1470 pipes[pipe_cnt].pipe.src.viewport_width /= 4;
1471 pipes[pipe_cnt].pipe.dest.recout_width /= 4;
1472 }
1473 } else {
1474 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1475 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1476
1477 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1478 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1479 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
1480 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1481
1482 /* stereo is not split */
1483 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
1484 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
1485 pipes[pipe_cnt].pipe.src.is_hsplit = false;
1486 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1487 }
1488
1489 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1490 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1491 switch (pln->rotation) {
1492 case ROTATION_ANGLE_0:
1493 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1494 break;
1495 case ROTATION_ANGLE_90:
1496 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_90;
1497 break;
1498 case ROTATION_ANGLE_180:
1499 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_180;
1500 break;
1501 case ROTATION_ANGLE_270:
1502 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_270;
1503 break;
1504 default:
1505 break;
1506 }
1507
1508 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1509 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1510 pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x;
1511 pipes[pipe_cnt].pipe.src.viewport_x_c = scl->viewport_c.x;
1512 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1513 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1514 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1515 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1516 pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
1517 pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
1518 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
1519 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
1520 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
1521 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
1522 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
1523 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1524 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1525 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
1526 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1527 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
1528 } else {
1529 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1530 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1531 }
1532 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1533 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1534 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1535 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1536 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1537 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
1538 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
1539 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
1540 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
1541 else {
1542 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
1543
1544 while (split_pipe && split_pipe->plane_state == pln) {
1545 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1546 split_pipe = split_pipe->bottom_pipe;
1547 }
1548 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
1549 while (split_pipe && split_pipe->plane_state == pln) {
1550 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1551 split_pipe = split_pipe->top_pipe;
1552 }
1553 }
1554
1555 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1556 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1557 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1558 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1559 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1560 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1561 scl->ratios.vert.value != dc_fixpt_one.value
1562 || scl->ratios.horz.value != dc_fixpt_one.value
1563 || scl->ratios.vert_c.value != dc_fixpt_one.value
1564 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1565 || dc->debug.always_scale; /*support always scale*/
1566 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1567 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1568 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1569 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1570
1571 pipes[pipe_cnt].pipe.src.macro_tile_size =
1572 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
1573 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1574 &pipes[pipe_cnt].pipe.src.sw_mode);
1575
1576 switch (pln->format) {
1577 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1578 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1579 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1580 break;
1581 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1582 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1583 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1584 break;
1585 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1586 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
1587 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1588 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1589 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1590 break;
1591 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1592 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1593 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1594 break;
1595 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1596 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1597 break;
1598 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
1599 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
1600 break;
1601 default:
1602 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1603 break;
1604 }
1605 }
1606
1607 pipe_cnt++;
1608 }
1609
1610 /* populate writeback information */
1611 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1612
1613 return pipe_cnt;
1614 }
1615
1616 void dcn20_calculate_wm(struct dc *dc, struct dc_state *context,
1617 display_e2e_pipe_params_st *pipes,
1618 int *out_pipe_cnt,
1619 int *pipe_split_from,
1620 int vlevel,
1621 bool fast_validate)
1622 {
1623 int pipe_cnt, i, pipe_idx;
1624
1625 dc_assert_fp_enabled();
1626
1627 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1628 if (!context->res_ctx.pipe_ctx[i].stream)
1629 continue;
1630
1631 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1632 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1633
1634 if (pipe_split_from[i] < 0) {
1635 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1636 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1637 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1638 pipes[pipe_cnt].pipe.dest.odm_combine =
1639 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
1640 else
1641 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1642 pipe_idx++;
1643 } else {
1644 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1645 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1646 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1647 pipes[pipe_cnt].pipe.dest.odm_combine =
1648 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
1649 else
1650 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1651 }
1652
1653 if (dc->config.forced_clocks) {
1654 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1655 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1656 }
1657 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
1658 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1659 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
1660 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1661
1662 pipe_cnt++;
1663 }
1664
1665 if (pipe_cnt != pipe_idx) {
1666 if (dc->res_pool->funcs->populate_dml_pipes)
1667 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1668 context, pipes, fast_validate);
1669 else
1670 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
1671 context, pipes, fast_validate);
1672 }
1673
1674 *out_pipe_cnt = pipe_cnt;
1675
1676 pipes[0].clks_cfg.voltage = vlevel;
1677 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1678 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1679
1680 /* only pipe 0 is read for voltage and dcf/soc clocks */
1681 if (vlevel < 1) {
1682 pipes[0].clks_cfg.voltage = 1;
1683 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
1684 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
1685 }
1686 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1687 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1688 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1689 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1690 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1691 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1692 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1693 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1694
1695 if (vlevel < 2) {
1696 pipes[0].clks_cfg.voltage = 2;
1697 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1698 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1699 }
1700 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1701 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1702 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1703 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1704 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1705 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1706 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1707
1708 if (vlevel < 3) {
1709 pipes[0].clks_cfg.voltage = 3;
1710 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1711 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1712 }
1713 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1714 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1715 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1716 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1717 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1718 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1719 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1720
1721 pipes[0].clks_cfg.voltage = vlevel;
1722 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1723 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1724 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1725 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1726 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1727 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1728 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1729 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1730 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1731 }
1732
1733 void dcn20_update_bounding_box(struct dc *dc,
1734 struct _vcs_dpi_soc_bounding_box_st *bb,
1735 struct pp_smu_nv_clock_table *max_clocks,
1736 unsigned int *uclk_states,
1737 unsigned int num_states)
1738 {
1739 int num_calculated_states = 0;
1740 int min_dcfclk = 0;
1741 int i;
1742
1743 dc_assert_fp_enabled();
1744
1745 if (num_states == 0)
1746 return;
1747
1748 memset(bb->clock_limits, 0, sizeof(bb->clock_limits));
1749
1750 if (dc->bb_overrides.min_dcfclk_mhz > 0) {
1751 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
1752 } else {
1753 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
1754 min_dcfclk = 310;
1755 else
1756 // Accounting for SOC/DCF relationship, we can go as high as
1757 // 506Mhz in Vmin.
1758 min_dcfclk = 506;
1759 }
1760
1761 for (i = 0; i < num_states; i++) {
1762 int min_fclk_required_by_uclk;
1763 bb->clock_limits[i].state = i;
1764 bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
1765
1766 // FCLK:UCLK ratio is 1.08
1767 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
1768 1000000);
1769
1770 bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
1771 min_dcfclk : min_fclk_required_by_uclk;
1772
1773 bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
1774 max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
1775
1776 bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
1777 max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
1778
1779 bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
1780 bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
1781 bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
1782
1783 bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
1784
1785 num_calculated_states++;
1786 }
1787
1788 bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
1789 bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
1790 bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
1791
1792 bb->num_states = num_calculated_states;
1793
1794 // Duplicate the last state, DML always an extra state identical to max state to work
1795 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
1796 bb->clock_limits[num_calculated_states].state = bb->num_states;
1797 }
1798
1799 void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,
1800 struct pp_smu_nv_clock_table max_clocks)
1801 {
1802 int i;
1803
1804 dc_assert_fp_enabled();
1805
1806 // First pass - cap all clocks higher than the reported max
1807 for (i = 0; i < bb->num_states; i++) {
1808 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
1809 && max_clocks.dcfClockInKhz != 0)
1810 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
1811
1812 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
1813 && max_clocks.uClockInKhz != 0)
1814 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
1815
1816 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
1817 && max_clocks.fabricClockInKhz != 0)
1818 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
1819
1820 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
1821 && max_clocks.displayClockInKhz != 0)
1822 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
1823
1824 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
1825 && max_clocks.dppClockInKhz != 0)
1826 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
1827
1828 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
1829 && max_clocks.phyClockInKhz != 0)
1830 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
1831
1832 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
1833 && max_clocks.socClockInKhz != 0)
1834 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
1835
1836 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
1837 && max_clocks.dscClockInKhz != 0)
1838 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
1839 }
1840
1841 // Second pass - remove all duplicate clock states
1842 for (i = bb->num_states - 1; i > 1; i--) {
1843 bool duplicate = true;
1844
1845 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
1846 duplicate = false;
1847 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
1848 duplicate = false;
1849 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
1850 duplicate = false;
1851 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
1852 duplicate = false;
1853 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
1854 duplicate = false;
1855 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
1856 duplicate = false;
1857 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
1858 duplicate = false;
1859 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
1860 duplicate = false;
1861
1862 if (duplicate)
1863 bb->num_states--;
1864 }
1865 }
1866
1867 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1868 {
1869 dc_assert_fp_enabled();
1870
1871 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
1872 && dc->bb_overrides.sr_exit_time_ns) {
1873 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
1874 }
1875
1876 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
1877 != dc->bb_overrides.sr_enter_plus_exit_time_ns
1878 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1879 bb->sr_enter_plus_exit_time_us =
1880 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1881 }
1882
1883 if ((int)(bb->sr_exit_z8_time_us * 1000)
1884 != dc->bb_overrides.sr_exit_z8_time_ns
1885 && dc->bb_overrides.sr_exit_z8_time_ns) {
1886 bb->sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;
1887 }
1888
1889 if ((int)(bb->sr_enter_plus_exit_z8_time_us * 1000)
1890 != dc->bb_overrides.sr_enter_plus_exit_z8_time_ns
1891 && dc->bb_overrides.sr_enter_plus_exit_z8_time_ns) {
1892 bb->sr_enter_plus_exit_z8_time_us = dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;
1893 }
1894 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
1895 && dc->bb_overrides.urgent_latency_ns) {
1896 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1897 }
1898
1899 if ((int)(bb->dram_clock_change_latency_us * 1000)
1900 != dc->bb_overrides.dram_clock_change_latency_ns
1901 && dc->bb_overrides.dram_clock_change_latency_ns) {
1902 bb->dram_clock_change_latency_us =
1903 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1904 }
1905
1906 if ((int)(bb->dummy_pstate_latency_us * 1000)
1907 != dc->bb_overrides.dummy_clock_change_latency_ns
1908 && dc->bb_overrides.dummy_clock_change_latency_ns) {
1909 bb->dummy_pstate_latency_us =
1910 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
1911 }
1912 }
1913
1914 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
1915 bool fast_validate, display_e2e_pipe_params_st *pipes)
1916 {
1917 bool out = false;
1918
1919 BW_VAL_TRACE_SETUP();
1920
1921 int vlevel = 0;
1922 int pipe_split_from[MAX_PIPES];
1923 int pipe_cnt = 0;
1924 DC_LOGGER_INIT(dc->ctx->logger);
1925
1926 BW_VAL_TRACE_COUNT();
1927
1928 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1929
1930 if (pipe_cnt == 0)
1931 goto validate_out;
1932
1933 if (!out)
1934 goto validate_fail;
1935
1936 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1937
1938 if (fast_validate) {
1939 BW_VAL_TRACE_SKIP(fast);
1940 goto validate_out;
1941 }
1942
1943 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1944 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1945
1946 BW_VAL_TRACE_END_WATERMARKS();
1947
1948 goto validate_out;
1949
1950 validate_fail:
1951 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1952 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1953
1954 BW_VAL_TRACE_SKIP(fail);
1955 out = false;
1956
1957 validate_out:
1958
1959 BW_VAL_TRACE_FINISH();
1960
1961 return out;
1962 }
1963
1964 bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
1965 bool fast_validate, display_e2e_pipe_params_st *pipes)
1966 {
1967 bool voltage_supported = false;
1968 bool full_pstate_supported = false;
1969 bool dummy_pstate_supported = false;
1970 double p_state_latency_us;
1971
1972 dc_assert_fp_enabled();
1973
1974 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
1975 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
1976 dc->debug.disable_dram_clock_change_vactive_support;
1977 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
1978 dc->debug.enable_dram_clock_change_one_display_vactive;
1979
1980 /*Unsafe due to current pipe merge and split logic*/
1981 ASSERT(context != dc->current_state);
1982
1983 if (fast_validate) {
1984 return dcn20_validate_bandwidth_internal(dc, context, true, pipes);
1985 }
1986
1987 // Best case, we support full UCLK switch latency
1988 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
1989 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1990
1991 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
1992 (voltage_supported && full_pstate_supported)) {
1993 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
1994 goto restore_dml_state;
1995 }
1996
1997 // Fallback: Try to only support G6 temperature read latency
1998 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
1999
2000 memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st));
2001 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
2002 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2003
2004 if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
2005 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
2006 goto restore_dml_state;
2007 }
2008
2009 // ERROR: fallback is supposed to always work.
2010 ASSERT(false);
2011
2012 restore_dml_state:
2013 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
2014 return voltage_supported;
2015 }
2016
2017 void dcn20_fpu_set_wm_ranges(int i,
2018 struct pp_smu_wm_range_sets *ranges,
2019 struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
2020 {
2021 dc_assert_fp_enabled();
2022
2023 ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
2024 ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
2025 }
2026
2027 void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
2028 int vlevel,
2029 int max_mpc_comb,
2030 int pipe_idx,
2031 bool is_validating_bw)
2032 {
2033 dc_assert_fp_enabled();
2034
2035 if (is_validating_bw)
2036 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2;
2037 else
2038 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
2039 }
2040
2041 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
2042 struct dc_state *context,
2043 display_e2e_pipe_params_st *pipes,
2044 bool fast_validate)
2045 {
2046 uint32_t pipe_cnt;
2047 int i;
2048
2049 dc_assert_fp_enabled();
2050
2051 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
2052
2053 for (i = 0; i < pipe_cnt; i++) {
2054
2055 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
2056 pipes[i].pipe.src.gpuvm = 1;
2057 }
2058
2059 return pipe_cnt;
2060 }
2061
2062 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
2063 {
2064 int i;
2065
2066 if (dc->bb_overrides.sr_exit_time_ns) {
2067 for (i = 0; i < WM_SET_COUNT; i++) {
2068 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
2069 dc->bb_overrides.sr_exit_time_ns / 1000.0;
2070 }
2071 }
2072
2073 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2074 for (i = 0; i < WM_SET_COUNT; i++) {
2075 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
2076 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2077 }
2078 }
2079
2080 if (dc->bb_overrides.urgent_latency_ns) {
2081 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2082 }
2083
2084 if (dc->bb_overrides.dram_clock_change_latency_ns) {
2085 for (i = 0; i < WM_SET_COUNT; i++) {
2086 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
2087 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2088 }
2089 }
2090 }
2091
2092 static void calculate_wm_set_for_vlevel(int vlevel,
2093 struct wm_range_table_entry *table_entry,
2094 struct dcn_watermarks *wm_set,
2095 struct display_mode_lib *dml,
2096 display_e2e_pipe_params_st *pipes,
2097 int pipe_cnt)
2098 {
2099 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
2100
2101 ASSERT(vlevel < dml->soc.num_states);
2102 /* only pipe 0 is read for voltage and dcf/soc clocks */
2103 pipes[0].clks_cfg.voltage = vlevel;
2104 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
2105 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
2106
2107 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
2108 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
2109 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
2110
2111 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
2112 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
2113 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
2114 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
2115 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
2116 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
2117 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
2118 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
2119 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
2120 }
2121
2122 static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,
2123 display_e2e_pipe_params_st *pipes,
2124 int *out_pipe_cnt,
2125 int *pipe_split_from,
2126 int vlevel_req,
2127 bool fast_validate)
2128 {
2129 int pipe_cnt, i, pipe_idx;
2130 int vlevel, vlevel_max;
2131 struct wm_range_table_entry *table_entry;
2132 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
2133
2134 ASSERT(bw_params);
2135
2136 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
2137
2138 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2139 if (!context->res_ctx.pipe_ctx[i].stream)
2140 continue;
2141
2142 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2143 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
2144
2145 if (pipe_split_from[i] < 0) {
2146 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2147 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2148 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2149 pipes[pipe_cnt].pipe.dest.odm_combine =
2150 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
2151 else
2152 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2153 pipe_idx++;
2154 } else {
2155 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2156 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2157 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2158 pipes[pipe_cnt].pipe.dest.odm_combine =
2159 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
2160 else
2161 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2162 }
2163 pipe_cnt++;
2164 }
2165
2166 if (pipe_cnt != pipe_idx) {
2167 if (dc->res_pool->funcs->populate_dml_pipes)
2168 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2169 context, pipes, fast_validate);
2170 else
2171 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
2172 context, pipes, fast_validate);
2173 }
2174
2175 *out_pipe_cnt = pipe_cnt;
2176
2177 vlevel_max = bw_params->clk_table.num_entries - 1;
2178
2179
2180 /* WM Set D */
2181 table_entry = &bw_params->wm_table.entries[WM_D];
2182 if (table_entry->wm_type == WM_TYPE_RETRAINING)
2183 vlevel = 0;
2184 else
2185 vlevel = vlevel_max;
2186 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
2187 &context->bw_ctx.dml, pipes, pipe_cnt);
2188 /* WM Set C */
2189 table_entry = &bw_params->wm_table.entries[WM_C];
2190 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
2191 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
2192 &context->bw_ctx.dml, pipes, pipe_cnt);
2193 /* WM Set B */
2194 table_entry = &bw_params->wm_table.entries[WM_B];
2195 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
2196 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
2197 &context->bw_ctx.dml, pipes, pipe_cnt);
2198
2199 /* WM Set A */
2200 table_entry = &bw_params->wm_table.entries[WM_A];
2201 vlevel = MIN(vlevel_req, vlevel_max);
2202 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
2203 &context->bw_ctx.dml, pipes, pipe_cnt);
2204 }
2205
2206 bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
2207 bool fast_validate, display_e2e_pipe_params_st *pipes)
2208 {
2209 bool out = false;
2210
2211 BW_VAL_TRACE_SETUP();
2212
2213 int vlevel = 0;
2214 int pipe_split_from[MAX_PIPES];
2215 int pipe_cnt = 0;
2216 DC_LOGGER_INIT(dc->ctx->logger);
2217
2218 BW_VAL_TRACE_COUNT();
2219
2220 dc_assert_fp_enabled();
2221
2222 /*Unsafe due to current pipe merge and split logic*/
2223 ASSERT(context != dc->current_state);
2224
2225 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
2226
2227 if (pipe_cnt == 0)
2228 goto validate_out;
2229
2230 if (!out)
2231 goto validate_fail;
2232
2233 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2234
2235 if (fast_validate) {
2236 BW_VAL_TRACE_SKIP(fast);
2237 goto validate_out;
2238 }
2239
2240 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
2241 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2242
2243 BW_VAL_TRACE_END_WATERMARKS();
2244
2245 goto validate_out;
2246
2247 validate_fail:
2248 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2249 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2250
2251 BW_VAL_TRACE_SKIP(fail);
2252 out = false;
2253
2254 validate_out:
2255
2256 BW_VAL_TRACE_FINISH();
2257
2258 return out;
2259 }
2260
2261 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
2262 {
2263 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
2264 int i;
2265
2266 low_pstate_lvl.state = 1;
2267 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
2268 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
2269 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
2270 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
2271
2272 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
2273 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
2274 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
2275 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
2276 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
2277 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
2278 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
2279
2280 for (i = clk_table->num_entries; i > 1; i--)
2281 clk_table->entries[i] = clk_table->entries[i-1];
2282 clk_table->entries[1] = clk_table->entries[0];
2283 clk_table->num_entries++;
2284
2285 return low_pstate_lvl;
2286 }
2287
2288 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2289 {
2290 struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;
2291 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
2292 struct clk_limit_table *clk_table = &bw_params->clk_table;
2293 unsigned int i, closest_clk_lvl = 0, k = 0;
2294 int j;
2295
2296 dc_assert_fp_enabled();
2297
2298 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
2299 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
2300 dcn2_1_soc.num_chans = bw_params->num_channels;
2301
2302 ASSERT(clk_table->num_entries);
2303 /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
2304 memcpy(s, dcn2_1_soc.clock_limits, sizeof(dcn2_1_soc.clock_limits));
2305
2306 for (i = 0; i < clk_table->num_entries; i++) {
2307 /* loop backwards*/
2308 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
2309 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2310 closest_clk_lvl = j;
2311 break;
2312 }
2313 }
2314
2315 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */
2316 if (i == 1)
2317 k++;
2318
2319 s[k].state = k;
2320 s[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2321 s[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2322 s[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
2323 s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
2324
2325 s[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2326 s[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2327 s[k].dram_bw_per_chan_gbps =
2328 dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2329 s[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2330 s[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2331 s[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2332 s[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2333
2334 k++;
2335 }
2336
2337 memcpy(&dcn2_1_soc.clock_limits, s, sizeof(dcn2_1_soc.clock_limits));
2338
2339 if (clk_table->num_entries) {
2340 dcn2_1_soc.num_states = clk_table->num_entries + 1;
2341 /* fill in min DF PState */
2342 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
2343 /* duplicate last level */
2344 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
2345 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
2346 }
2347
2348 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2349 }
2350
2351 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params)
2352 {
2353 dc_assert_fp_enabled();
2354
2355 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
2356 bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
2357 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
2358 bw_params->wm_table.entries[WM_D].valid = true;
2359 }
2360
2361 void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,
2362 struct resource_context *res_ctx,
2363 display_e2e_pipe_params_st *pipes)
2364 {
2365 int pipe_cnt, i, j;
2366 double max_calc_writeback_dispclk;
2367 double writeback_dispclk;
2368 struct writeback_st dout_wb;
2369
2370 dc_assert_fp_enabled();
2371
2372 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2373 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
2374
2375 if (!stream)
2376 continue;
2377 max_calc_writeback_dispclk = 0;
2378
2379 /* Set writeback information */
2380 pipes[pipe_cnt].dout.wb_enable = 0;
2381 pipes[pipe_cnt].dout.num_active_wb = 0;
2382 for (j = 0; j < stream->num_wb_info; j++) {
2383 struct dc_writeback_info *wb_info = &stream->writeback_info[j];
2384
2385 if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
2386 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
2387 pipes[pipe_cnt].dout.wb_enable = 1;
2388 pipes[pipe_cnt].dout.num_active_wb++;
2389 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
2390 wb_info->dwb_params.cnv_params.crop_height :
2391 wb_info->dwb_params.cnv_params.src_height;
2392 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
2393 wb_info->dwb_params.cnv_params.crop_width :
2394 wb_info->dwb_params.cnv_params.src_width;
2395 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
2396 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
2397 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
2398 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
2399 dout_wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
2400 dout_wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
2401 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
2402 (double)wb_info->dwb_params.cnv_params.crop_width /
2403 (double)wb_info->dwb_params.dest_width :
2404 (double)wb_info->dwb_params.cnv_params.src_width /
2405 (double)wb_info->dwb_params.dest_width;
2406 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
2407 (double)wb_info->dwb_params.cnv_params.crop_height /
2408 (double)wb_info->dwb_params.dest_height :
2409 (double)wb_info->dwb_params.cnv_params.src_height /
2410 (double)wb_info->dwb_params.dest_height;
2411 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
2412 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2413 dout_wb.wb_pixel_format = dm_420_8;
2414 else
2415 dout_wb.wb_pixel_format = dm_420_10;
2416 } else
2417 dout_wb.wb_pixel_format = dm_444_32;
2418
2419 /* Workaround for cases where multiple writebacks are connected to same plane
2420 * In which case, need to compute worst case and set the associated writeback parameters
2421 * This workaround is necessary due to DML computation assuming only 1 set of writeback
2422 * parameters per pipe */
2423 writeback_dispclk = CalculateWriteBackDISPCLK(
2424 dout_wb.wb_pixel_format,
2425 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
2426 dout_wb.wb_hratio,
2427 dout_wb.wb_vratio,
2428 dout_wb.wb_htaps_luma,
2429 dout_wb.wb_vtaps_luma,
2430 dout_wb.wb_htaps_chroma,
2431 dout_wb.wb_vtaps_chroma,
2432 dout_wb.wb_dst_width,
2433 pipes[pipe_cnt].pipe.dest.htotal,
2434 2);
2435
2436 if (writeback_dispclk > max_calc_writeback_dispclk) {
2437 max_calc_writeback_dispclk = writeback_dispclk;
2438 pipes[pipe_cnt].dout.wb = dout_wb;
2439 }
2440 }
2441 }
2442
2443 pipe_cnt++;
2444 }
2445
2446 }
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git