drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DML20_DISPLAY_RQ_DLG_CALC_H__
  27 #define __DML20_DISPLAY_RQ_DLG_CALC_H__
  28
  29 #include "../dml_common_defs.h"
  30 #include "../display_rq_dlg_helpers.h"
  31
  32 struct display_mode_lib;
  33
  34
  35 // Function: dml_rq_dlg_get_rq_reg
  36 //  Main entry point for test to get the register values out of this DML class.
  37 //  This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
  38 //  and then populate the rq_regs struct
  39 // Input:
  40 //  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
  41 // Output:
  42 //  rq_regs - struct that holds all the RQ registers field value.
  43 //            See also: <display_rq_regs_st>
  44 void dml20_rq_dlg_get_rq_reg(
  45                 struct display_mode_lib *mode_lib,
  46                 display_rq_regs_st *rq_regs,
  47                 const display_pipe_params_st pipe_param);
  48
  49
  50 // Function: dml_rq_dlg_get_dlg_reg
  51 //   Calculate and return DLG and TTU register struct given the system setting
  52 // Output:
  53 //  dlg_regs - output DLG register struct
  54 //  ttu_regs - output DLG TTU register struct
  55 // Input:
  56 //  e2e_pipe_param - "compacted" array of e2e pipe param struct
  57 //  num_pipes - num of active "pipe" or "route"
  58 //  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
  59 //  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
  60 //           Added for legacy or unrealistic timing tests.
  61 void dml20_rq_dlg_get_dlg_reg(
  62                 struct display_mode_lib *mode_lib,
  63                 display_dlg_regs_st *dlg_regs,
  64                 display_ttu_regs_st *ttu_regs,
  65                 display_e2e_pipe_params_st *e2e_pipe_param,
  66                 const unsigned int num_pipes,
  67                 const unsigned int pipe_idx,
  68                 const bool cstate_en,
  69                 const bool pstate_en,
  70                 const bool vm_en,
  71                 const bool ignore_viewport_pos,
  72                 const bool immediate_flip_support);
  73
  74 #endif