1 /* SPDX-License-Identifier: MIT */
3 * Copyright 2023 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "display_mode_core.h"
28 #include "dml2_internal_types.h"
29 #include "dml2_translation_helper.h"
31 #define NUM_DCFCLK_STAS 5
33 void dml2_init_ip_params(struct dml2_context
*dml2
, const struct dc
*in_dc
, struct ip_params_st
*out
)
35 switch (dml2
->v20
.dml_core_ctx
.project
) {
37 case dml_project_dcn32
:
38 case dml_project_dcn321
:
40 // Hardcoded values for DCN32x
41 out
->vblank_nom_default_us
= 600;
42 out
->rob_buffer_size_kbytes
= 128;
43 out
->config_return_buffer_size_in_kbytes
= 1280;
44 out
->config_return_buffer_segment_size_in_kbytes
= 64;
45 out
->compressed_buffer_segment_size_in_kbytes
= 64;
46 out
->meta_fifo_size_in_kentries
= 22;
47 out
->zero_size_buffer_entries
= 512;
48 out
->dpte_buffer_size_in_pte_reqs_luma
= 68;
49 out
->dpte_buffer_size_in_pte_reqs_chroma
= 36;
50 out
->dcc_meta_buffer_size_bytes
= 6272;
51 out
->gpuvm_max_page_table_levels
= 4;
52 out
->hostvm_max_page_table_levels
= 0;
53 out
->pixel_chunk_size_kbytes
= 8;
54 //out->alpha_pixel_chunk_size_kbytes;
55 out
->min_pixel_chunk_size_bytes
= 1024;
56 out
->meta_chunk_size_kbytes
= 2;
57 out
->min_meta_chunk_size_bytes
= 256;
58 out
->writeback_chunk_size_kbytes
= 8;
59 out
->line_buffer_size_bits
= 1171920;
60 out
->max_line_buffer_lines
= 32;
61 out
->writeback_interface_buffer_size_kbytes
= 90;
62 //Number of pipes after DCN Pipe harvesting
63 out
->max_num_dpp
= dml2
->config
.dcn_pipe_count
;
64 out
->max_num_otg
= dml2
->config
.dcn_pipe_count
;
66 out
->max_dchub_pscl_bw_pix_per_clk
= 4;
67 out
->max_pscl_lb_bw_pix_per_clk
= 2;
68 out
->max_lb_vscl_bw_pix_per_clk
= 4;
69 out
->max_vscl_hscl_bw_pix_per_clk
= 4;
70 out
->max_hscl_ratio
= 6;
71 out
->max_vscl_ratio
= 6;
72 out
->max_hscl_taps
= 8;
73 out
->max_vscl_taps
= 8;
74 out
->dispclk_ramp_margin_percent
= 1;
75 out
->dppclk_delay_subtotal
= 47;
76 out
->dppclk_delay_scl
= 50;
77 out
->dppclk_delay_scl_lb_only
= 16;
78 out
->dppclk_delay_cnvc_formatter
= 28;
79 out
->dppclk_delay_cnvc_cursor
= 6;
80 out
->cursor_buffer_size
= 16;
81 out
->cursor_chunk_size
= 2;
82 out
->dispclk_delay_subtotal
= 125;
83 out
->max_inter_dcn_tile_repeaters
= 8;
84 out
->writeback_max_hscl_ratio
= 1;
85 out
->writeback_max_vscl_ratio
= 1;
86 out
->writeback_min_hscl_ratio
= 1;
87 out
->writeback_min_vscl_ratio
= 1;
88 out
->writeback_max_hscl_taps
= 1;
89 out
->writeback_max_vscl_taps
= 1;
90 out
->writeback_line_buffer_buffer_size
= 0;
92 out
->maximum_dsc_bits_per_component
= 12;
93 out
->maximum_pixels_per_line_per_dsc_unit
= 6016;
94 out
->dsc422_native_support
= true;
95 out
->dcc_supported
= true;
96 out
->ptoi_supported
= false;
98 out
->gpuvm_enable
= false;
99 out
->hostvm_enable
= false;
100 out
->cursor_64bpp_support
= false;
101 out
->dynamic_metadata_vm_enabled
= false;
103 out
->max_num_hdmi_frl_outputs
= 1;
104 out
->max_num_dp2p0_outputs
= 2;
105 out
->max_num_dp2p0_streams
= 4;
108 case dml_project_dcn35
:
109 case dml_project_dcn351
:
110 out
->rob_buffer_size_kbytes
= 64;
111 out
->config_return_buffer_size_in_kbytes
= 1792;
112 out
->compressed_buffer_segment_size_in_kbytes
= 64;
113 out
->meta_fifo_size_in_kentries
= 32;
114 out
->zero_size_buffer_entries
= 512;
115 out
->pixel_chunk_size_kbytes
= 8;
116 out
->alpha_pixel_chunk_size_kbytes
= 4;
117 out
->min_pixel_chunk_size_bytes
= 1024;
118 out
->meta_chunk_size_kbytes
= 2;
119 out
->min_meta_chunk_size_bytes
= 256;
120 out
->writeback_chunk_size_kbytes
= 8;
121 out
->dpte_buffer_size_in_pte_reqs_luma
= 68;
122 out
->dpte_buffer_size_in_pte_reqs_chroma
= 36;
123 out
->dcc_meta_buffer_size_bytes
= 6272;
124 out
->gpuvm_enable
= 1;
125 out
->hostvm_enable
= 1;
126 out
->gpuvm_max_page_table_levels
= 1;
127 out
->hostvm_max_page_table_levels
= 2;
129 out
->maximum_dsc_bits_per_component
= 12;
130 out
->maximum_pixels_per_line_per_dsc_unit
= 6016;
131 out
->dsc422_native_support
= 1;
132 out
->line_buffer_size_bits
= 986880;
133 out
->dcc_supported
= 1;
134 out
->max_line_buffer_lines
= 32;
135 out
->writeback_interface_buffer_size_kbytes
= 90;
136 out
->max_num_dpp
= 4;
137 out
->max_num_otg
= 4;
138 out
->max_num_hdmi_frl_outputs
= 1;
139 out
->max_num_dp2p0_outputs
= 2;
140 out
->max_num_dp2p0_streams
= 4;
143 out
->max_dchub_pscl_bw_pix_per_clk
= 4;
144 out
->max_pscl_lb_bw_pix_per_clk
= 2;
145 out
->max_lb_vscl_bw_pix_per_clk
= 4;
146 out
->max_vscl_hscl_bw_pix_per_clk
= 4;
147 out
->max_hscl_ratio
= 6;
148 out
->max_vscl_ratio
= 6;
149 out
->max_hscl_taps
= 8;
150 out
->max_vscl_taps
= 8;
151 out
->dispclk_ramp_margin_percent
= 1.11;
153 out
->dppclk_delay_subtotal
= 47;
154 out
->dppclk_delay_scl
= 50;
155 out
->dppclk_delay_scl_lb_only
= 16;
156 out
->dppclk_delay_cnvc_formatter
= 28;
157 out
->dppclk_delay_cnvc_cursor
= 6;
158 out
->dispclk_delay_subtotal
= 125;
160 out
->dynamic_metadata_vm_enabled
= false;
161 out
->max_inter_dcn_tile_repeaters
= 8;
162 out
->cursor_buffer_size
= 16; // kBytes
163 out
->cursor_chunk_size
= 2; // kBytes
165 out
->writeback_line_buffer_buffer_size
= 0;
166 out
->writeback_max_hscl_ratio
= 1;
167 out
->writeback_max_vscl_ratio
= 1;
168 out
->writeback_min_hscl_ratio
= 1;
169 out
->writeback_min_vscl_ratio
= 1;
170 out
->writeback_max_hscl_taps
= 1;
171 out
->writeback_max_vscl_taps
= 1;
172 out
->ptoi_supported
= 0;
174 out
->vblank_nom_default_us
= 668; /*not in dml, but in programming guide, hard coded in dml2_translate_ip_params*/
175 out
->config_return_buffer_segment_size_in_kbytes
= 64; /*required, but not exist,, hard coded in dml2_translate_ip_params*/
181 void dml2_init_socbb_params(struct dml2_context
*dml2
, const struct dc
*in_dc
, struct soc_bounding_box_st
*out
)
183 out
->dprefclk_mhz
= dml2
->config
.bbox_overrides
.dprefclk_mhz
;
184 out
->xtalclk_mhz
= dml2
->config
.bbox_overrides
.xtalclk_mhz
;
185 out
->pcierefclk_mhz
= 100;
186 out
->refclk_mhz
= dml2
->config
.bbox_overrides
.dchub_refclk_mhz
;
188 out
->max_outstanding_reqs
= 512;
189 out
->pct_ideal_sdp_bw_after_urgent
= 100;
190 out
->pct_ideal_fabric_bw_after_urgent
= 67;
191 out
->pct_ideal_dram_bw_after_urgent_pixel_only
= 20;
192 out
->pct_ideal_dram_bw_after_urgent_pixel_and_vm
= 60;
193 out
->pct_ideal_dram_bw_after_urgent_vm_only
= 30;
194 out
->pct_ideal_dram_bw_after_urgent_strobe
= 67;
195 out
->max_avg_sdp_bw_use_normal_percent
= 80;
196 out
->max_avg_fabric_bw_use_normal_percent
= 60;
197 out
->max_avg_dram_bw_use_normal_percent
= 15;
198 out
->max_avg_dram_bw_use_normal_strobe_percent
= 50;
200 out
->urgent_out_of_order_return_per_channel_pixel_only_bytes
= 4096;
201 out
->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes
= 4096;
202 out
->urgent_out_of_order_return_per_channel_vm_only_bytes
= 4096;
203 out
->return_bus_width_bytes
= 64;
204 out
->dram_channel_width_bytes
= 2;
205 out
->fabric_datapath_to_dcn_data_return_bytes
= 64;
206 out
->hostvm_min_page_size_kbytes
= 0;
207 out
->gpuvm_min_page_size_kbytes
= 256;
208 out
->phy_downspread_percent
= 0.38;
209 out
->dcn_downspread_percent
= 0.5;
210 out
->dispclk_dppclk_vco_speed_mhz
= dml2
->config
.bbox_overrides
.disp_pll_vco_speed_mhz
;
211 out
->mall_allocated_for_dcn_mbytes
= dml2
->config
.mall_cfg
.max_cab_allocation_bytes
/ 1048576; // 64 or 32 MB;
213 out
->do_urgent_latency_adjustment
= true;
215 switch (dml2
->v20
.dml_core_ctx
.project
) {
217 case dml_project_dcn32
:
220 out
->round_trip_ping_latency_dcfclk_cycles
= 263;
221 out
->smn_latency_us
= 2;
224 case dml_project_dcn321
:
226 out
->round_trip_ping_latency_dcfclk_cycles
= 207;
227 out
->smn_latency_us
= 0;
230 case dml_project_dcn35
:
232 out
->round_trip_ping_latency_dcfclk_cycles
= 106;
233 out
->smn_latency_us
= 2;
234 out
->dispclk_dppclk_vco_speed_mhz
= 3600;
237 case dml_project_dcn351
:
239 out
->round_trip_ping_latency_dcfclk_cycles
= 1100;
240 out
->smn_latency_us
= 2;
243 /* ---Overrides if available--- */
244 if (dml2
->config
.bbox_overrides
.dram_num_chan
)
245 out
->num_chans
= dml2
->config
.bbox_overrides
.dram_num_chan
;
247 if (dml2
->config
.bbox_overrides
.dram_chanel_width_bytes
)
248 out
->dram_channel_width_bytes
= dml2
->config
.bbox_overrides
.dram_chanel_width_bytes
;
251 void dml2_init_soc_states(struct dml2_context
*dml2
, const struct dc
*in_dc
,
252 const struct soc_bounding_box_st
*in_bbox
, struct soc_states_st
*out
)
254 struct dml2_policy_build_synthetic_soc_states_scratch
*s
= &dml2
->v20
.scratch
.create_scratch
.build_synthetic_socbb_scratch
;
255 struct dml2_policy_build_synthetic_soc_states_params
*p
= &dml2
->v20
.scratch
.build_synthetic_socbb_params
;
256 unsigned int dcfclk_stas_mhz
[NUM_DCFCLK_STAS
];
258 unsigned int transactions_per_mem_clock
= 16; // project specific, depends on used Memory type
260 p
->dcfclk_stas_mhz
= dcfclk_stas_mhz
;
261 p
->num_dcfclk_stas
= NUM_DCFCLK_STAS
;
262 p
->in_bbox
= in_bbox
;
264 p
->in_states
= &dml2
->v20
.scratch
.create_scratch
.in_states
;
267 /* Initial hardcoded values */
268 switch (dml2
->v20
.dml_core_ctx
.project
) {
270 case dml_project_dcn32
:
272 p
->in_states
->num_states
= 2;
273 transactions_per_mem_clock
= 16;
274 p
->in_states
->state_array
[0].socclk_mhz
= 620.0;
275 p
->in_states
->state_array
[0].dscclk_mhz
= 716.667;
276 p
->in_states
->state_array
[0].phyclk_mhz
= 810;
277 p
->in_states
->state_array
[0].phyclk_d18_mhz
= 667;
278 p
->in_states
->state_array
[0].phyclk_d32_mhz
= 625;
279 p
->in_states
->state_array
[0].dtbclk_mhz
= 1564.0;
280 p
->in_states
->state_array
[0].fabricclk_mhz
= 450.0;
281 p
->in_states
->state_array
[0].dcfclk_mhz
= 300.0;
282 p
->in_states
->state_array
[0].dispclk_mhz
= 2150.0;
283 p
->in_states
->state_array
[0].dppclk_mhz
= 2150.0;
284 p
->in_states
->state_array
[0].dram_speed_mts
= 100 * transactions_per_mem_clock
;
286 p
->in_states
->state_array
[0].urgent_latency_pixel_data_only_us
= 4;
287 p
->in_states
->state_array
[0].urgent_latency_pixel_mixed_with_vm_data_us
= 0;
288 p
->in_states
->state_array
[0].urgent_latency_vm_data_only_us
= 0;
289 p
->in_states
->state_array
[0].writeback_latency_us
= 12;
290 p
->in_states
->state_array
[0].urgent_latency_adjustment_fabric_clock_component_us
= 1;
291 p
->in_states
->state_array
[0].urgent_latency_adjustment_fabric_clock_reference_mhz
= 3000;
292 p
->in_states
->state_array
[0].sr_exit_z8_time_us
= 0;
293 p
->in_states
->state_array
[0].sr_enter_plus_exit_z8_time_us
= 0;
294 p
->in_states
->state_array
[0].dram_clock_change_latency_us
= 400;
295 p
->in_states
->state_array
[0].use_ideal_dram_bw_strobe
= true;
296 p
->in_states
->state_array
[0].sr_exit_time_us
= 42.97;
297 p
->in_states
->state_array
[0].sr_enter_plus_exit_time_us
= 49.94;
298 p
->in_states
->state_array
[0].fclk_change_latency_us
= 20;
299 p
->in_states
->state_array
[0].usr_retraining_latency_us
= 2;
301 p
->in_states
->state_array
[1].socclk_mhz
= 1200.0;
302 p
->in_states
->state_array
[1].fabricclk_mhz
= 2500.0;
303 p
->in_states
->state_array
[1].dcfclk_mhz
= 1564.0;
304 p
->in_states
->state_array
[1].dram_speed_mts
= 1125 * transactions_per_mem_clock
;
307 case dml_project_dcn321
:
308 p
->in_states
->num_states
= 2;
309 transactions_per_mem_clock
= 16;
310 p
->in_states
->state_array
[0].socclk_mhz
= 582.0;
311 p
->in_states
->state_array
[0].dscclk_mhz
= 573.333;
312 p
->in_states
->state_array
[0].phyclk_mhz
= 810;
313 p
->in_states
->state_array
[0].phyclk_d18_mhz
= 667;
314 p
->in_states
->state_array
[0].phyclk_d32_mhz
= 313;
315 p
->in_states
->state_array
[0].dtbclk_mhz
= 1564.0;
316 p
->in_states
->state_array
[0].fabricclk_mhz
= 450.0;
317 p
->in_states
->state_array
[0].dcfclk_mhz
= 300.0;
318 p
->in_states
->state_array
[0].dispclk_mhz
= 1720.0;
319 p
->in_states
->state_array
[0].dppclk_mhz
= 1720.0;
320 p
->in_states
->state_array
[0].dram_speed_mts
= 100 * transactions_per_mem_clock
;
322 p
->in_states
->state_array
[0].urgent_latency_pixel_data_only_us
= 4;
323 p
->in_states
->state_array
[0].urgent_latency_pixel_mixed_with_vm_data_us
= 0;
324 p
->in_states
->state_array
[0].urgent_latency_vm_data_only_us
= 0;
325 p
->in_states
->state_array
[0].writeback_latency_us
= 12;
326 p
->in_states
->state_array
[0].urgent_latency_adjustment_fabric_clock_component_us
= 1;
327 p
->in_states
->state_array
[0].urgent_latency_adjustment_fabric_clock_reference_mhz
= 3000;
328 p
->in_states
->state_array
[0].sr_exit_z8_time_us
= 0;
329 p
->in_states
->state_array
[0].sr_enter_plus_exit_z8_time_us
= 0;
330 p
->in_states
->state_array
[0].dram_clock_change_latency_us
= 400;
331 p
->in_states
->state_array
[0].use_ideal_dram_bw_strobe
= true;
332 p
->in_states
->state_array
[0].sr_exit_time_us
= 19.95;
333 p
->in_states
->state_array
[0].sr_enter_plus_exit_time_us
= 24.36;
334 p
->in_states
->state_array
[0].fclk_change_latency_us
= 7;
335 p
->in_states
->state_array
[0].usr_retraining_latency_us
= 0;
337 p
->in_states
->state_array
[1].socclk_mhz
= 1200.0;
338 p
->in_states
->state_array
[1].fabricclk_mhz
= 2250.0;
339 p
->in_states
->state_array
[1].dcfclk_mhz
= 1434.0;
340 p
->in_states
->state_array
[1].dram_speed_mts
= 1000 * transactions_per_mem_clock
;
344 /* Override from passed values, mainly for debugging purposes, if available */
345 if (dml2
->config
.bbox_overrides
.sr_exit_latency_us
) {
346 p
->in_states
->state_array
[0].sr_exit_time_us
= dml2
->config
.bbox_overrides
.sr_exit_latency_us
;
349 if (dml2
->config
.bbox_overrides
.sr_enter_plus_exit_latency_us
) {
350 p
->in_states
->state_array
[0].sr_enter_plus_exit_time_us
= dml2
->config
.bbox_overrides
.sr_enter_plus_exit_latency_us
;
353 if (dml2
->config
.bbox_overrides
.urgent_latency_us
) {
354 p
->in_states
->state_array
[0].urgent_latency_pixel_data_only_us
= dml2
->config
.bbox_overrides
.urgent_latency_us
;
357 if (dml2
->config
.bbox_overrides
.dram_clock_change_latency_us
) {
358 p
->in_states
->state_array
[0].dram_clock_change_latency_us
= dml2
->config
.bbox_overrides
.dram_clock_change_latency_us
;
361 if (dml2
->config
.bbox_overrides
.fclk_change_latency_us
) {
362 p
->in_states
->state_array
[0].fclk_change_latency_us
= dml2
->config
.bbox_overrides
.fclk_change_latency_us
;
365 /* DCFCLK stas values are project specific */
366 if ((dml2
->v20
.dml_core_ctx
.project
== dml_project_dcn32
) ||
367 (dml2
->v20
.dml_core_ctx
.project
== dml_project_dcn321
)) {
368 p
->dcfclk_stas_mhz
[0] = p
->in_states
->state_array
[0].dcfclk_mhz
;
369 p
->dcfclk_stas_mhz
[1] = 615;
370 p
->dcfclk_stas_mhz
[2] = 906;
371 p
->dcfclk_stas_mhz
[3] = 1324;
372 p
->dcfclk_stas_mhz
[4] = p
->in_states
->state_array
[1].dcfclk_mhz
;
373 } else if (dml2
->v20
.dml_core_ctx
.project
!= dml_project_dcn35
&&
374 dml2
->v20
.dml_core_ctx
.project
!= dml_project_dcn351
) {
375 p
->dcfclk_stas_mhz
[0] = 300;
376 p
->dcfclk_stas_mhz
[1] = 615;
377 p
->dcfclk_stas_mhz
[2] = 906;
378 p
->dcfclk_stas_mhz
[3] = 1324;
379 p
->dcfclk_stas_mhz
[4] = 1500;
381 /* Copy clocks tables entries, if available */
382 if (dml2
->config
.bbox_overrides
.clks_table
.num_states
) {
383 p
->in_states
->num_states
= dml2
->config
.bbox_overrides
.clks_table
.num_states
;
385 for (i
= 0; i
< dml2
->config
.bbox_overrides
.clks_table
.num_entries_per_clk
.num_dcfclk_levels
; i
++) {
386 p
->in_states
->state_array
[i
].dcfclk_mhz
= dml2
->config
.bbox_overrides
.clks_table
.clk_entries
[i
].dcfclk_mhz
;
389 p
->dcfclk_stas_mhz
[0] = dml2
->config
.bbox_overrides
.clks_table
.clk_entries
[0].dcfclk_mhz
;
391 p
->dcfclk_stas_mhz
[4] = dml2
->config
.bbox_overrides
.clks_table
.clk_entries
[i
-1].dcfclk_mhz
;
393 for (i
= 0; i
< dml2
->config
.bbox_overrides
.clks_table
.num_entries_per_clk
.num_fclk_levels
; i
++) {
394 p
->in_states
->state_array
[i
].fabricclk_mhz
=
395 dml2
->config
.bbox_overrides
.clks_table
.clk_entries
[i
].fclk_mhz
;
398 for (i
= 0; i
< dml2
->config
.bbox_overrides
.clks_table
.num_entries_per_clk
.num_memclk_levels
; i
++) {
399 p
->in_states
->state_array
[i
].dram_speed_mts
=
400 dml2
->config
.bbox_overrides
.clks_table
.clk_entries
[i
].memclk_mhz
* transactions_per_mem_clock
;
403 for (i
= 0; i
< dml2
->config
.bbox_overrides
.clks_table
.num_entries_per_clk
.num_socclk_levels
; i
++) {
404 p
->in_states
->state_array
[i
].socclk_mhz
=
405 dml2
->config
.bbox_overrides
.clks_table
.clk_entries
[i
].socclk_mhz
;
408 for (i
= 0; i
< dml2
->config
.bbox_overrides
.clks_table
.num_entries_per_clk
.num_dtbclk_levels
; i
++) {
409 p
->in_states
->state_array
[i
].dtbclk_mhz
=
410 dml2
->config
.bbox_overrides
.clks_table
.clk_entries
[i
].dtbclk_mhz
;
413 for (i
= 0; i
< dml2
->config
.bbox_overrides
.clks_table
.num_entries_per_clk
.num_dispclk_levels
; i
++) {
414 p
->in_states
->state_array
[i
].dispclk_mhz
=
415 dml2
->config
.bbox_overrides
.clks_table
.clk_entries
[i
].dispclk_mhz
;
416 p
->in_states
->state_array
[i
].dppclk_mhz
=
417 dml2
->config
.bbox_overrides
.clks_table
.clk_entries
[i
].dppclk_mhz
;
421 dml2_policy_build_synthetic_soc_states(s
, p
);
424 void dml2_translate_ip_params(const struct dc
*in
, struct ip_params_st
*out
)
426 const struct _vcs_dpi_ip_params_st
*in_ip_params
= &in
->dml
.ip
;
427 /* Copy over the IP params tp dml2_ctx */
428 out
->compressed_buffer_segment_size_in_kbytes
= in_ip_params
->compressed_buffer_segment_size_in_kbytes
;
429 out
->config_return_buffer_size_in_kbytes
= in_ip_params
->config_return_buffer_size_in_kbytes
;
430 out
->cursor_buffer_size
= in_ip_params
->cursor_buffer_size
;
431 out
->cursor_chunk_size
= in_ip_params
->cursor_chunk_size
;
432 out
->dcc_meta_buffer_size_bytes
= in_ip_params
->dcc_meta_buffer_size_bytes
;
433 out
->dcc_supported
= in_ip_params
->dcc_supported
;
434 out
->dispclk_delay_subtotal
= in_ip_params
->dispclk_delay_subtotal
;
435 out
->dispclk_ramp_margin_percent
= in_ip_params
->dispclk_ramp_margin_percent
;
436 out
->dppclk_delay_cnvc_cursor
= in_ip_params
->dppclk_delay_cnvc_cursor
;
437 out
->dppclk_delay_cnvc_formatter
= in_ip_params
->dppclk_delay_cnvc_formatter
;
438 out
->dppclk_delay_scl
= in_ip_params
->dppclk_delay_scl
;
439 out
->dppclk_delay_scl_lb_only
= in_ip_params
->dppclk_delay_scl_lb_only
;
440 out
->dppclk_delay_subtotal
= in_ip_params
->dppclk_delay_subtotal
;
441 out
->dpte_buffer_size_in_pte_reqs_chroma
= in_ip_params
->dpte_buffer_size_in_pte_reqs_chroma
;
442 out
->dpte_buffer_size_in_pte_reqs_luma
= in_ip_params
->dpte_buffer_size_in_pte_reqs_luma
;
443 out
->dsc422_native_support
= in_ip_params
->dsc422_native_support
;
444 out
->dynamic_metadata_vm_enabled
= in_ip_params
->dynamic_metadata_vm_enabled
;
445 out
->gpuvm_enable
= in_ip_params
->gpuvm_enable
;
446 out
->gpuvm_max_page_table_levels
= in_ip_params
->gpuvm_max_page_table_levels
;
447 out
->hostvm_enable
= in_ip_params
->hostvm_enable
;
448 out
->hostvm_max_page_table_levels
= in_ip_params
->hostvm_max_page_table_levels
;
449 out
->line_buffer_size_bits
= in_ip_params
->line_buffer_size_bits
;
450 out
->maximum_dsc_bits_per_component
= in_ip_params
->maximum_dsc_bits_per_component
;
451 out
->maximum_pixels_per_line_per_dsc_unit
= in_ip_params
->maximum_pixels_per_line_per_dsc_unit
;
452 out
->max_dchub_pscl_bw_pix_per_clk
= in_ip_params
->max_dchub_pscl_bw_pix_per_clk
;
453 out
->max_hscl_ratio
= in_ip_params
->max_hscl_ratio
;
454 out
->max_hscl_taps
= in_ip_params
->max_hscl_taps
;
455 out
->max_inter_dcn_tile_repeaters
= in_ip_params
->max_inter_dcn_tile_repeaters
;
456 out
->max_lb_vscl_bw_pix_per_clk
= in_ip_params
->max_lb_vscl_bw_pix_per_clk
;
457 out
->max_line_buffer_lines
= in_ip_params
->max_line_buffer_lines
;
458 out
->max_num_dp2p0_outputs
= in_ip_params
->max_num_dp2p0_outputs
;
459 out
->max_num_dp2p0_streams
= in_ip_params
->max_num_dp2p0_streams
;
460 out
->max_num_dpp
= in_ip_params
->max_num_dpp
;
461 out
->max_num_hdmi_frl_outputs
= in_ip_params
->max_num_hdmi_frl_outputs
;
462 out
->max_num_otg
= in_ip_params
->max_num_otg
;
463 out
->max_num_wb
= in_ip_params
->max_num_wb
;
464 out
->max_pscl_lb_bw_pix_per_clk
= in_ip_params
->max_pscl_lb_bw_pix_per_clk
;
465 out
->max_vscl_hscl_bw_pix_per_clk
= in_ip_params
->max_vscl_hscl_bw_pix_per_clk
;
466 out
->max_vscl_ratio
= in_ip_params
->max_vscl_ratio
;
467 out
->max_vscl_taps
= in_ip_params
->max_vscl_taps
;
468 out
->meta_chunk_size_kbytes
= in_ip_params
->meta_chunk_size_kbytes
;
469 out
->meta_fifo_size_in_kentries
= in_ip_params
->meta_fifo_size_in_kentries
;
470 out
->min_meta_chunk_size_bytes
= in_ip_params
->min_meta_chunk_size_bytes
;
471 out
->min_pixel_chunk_size_bytes
= in_ip_params
->min_pixel_chunk_size_bytes
;
472 out
->num_dsc
= in_ip_params
->num_dsc
;
473 out
->pixel_chunk_size_kbytes
= in_ip_params
->pixel_chunk_size_kbytes
;
474 out
->ptoi_supported
= in_ip_params
->ptoi_supported
;
475 out
->rob_buffer_size_kbytes
= in_ip_params
->rob_buffer_size_kbytes
;
476 out
->writeback_chunk_size_kbytes
= in_ip_params
->writeback_chunk_size_kbytes
;
477 out
->writeback_interface_buffer_size_kbytes
= in_ip_params
->writeback_interface_buffer_size_kbytes
;
478 out
->writeback_line_buffer_buffer_size
= in_ip_params
->writeback_line_buffer_buffer_size
;
479 out
->writeback_max_hscl_ratio
= in_ip_params
->writeback_max_hscl_ratio
;
480 out
->writeback_max_hscl_taps
= in_ip_params
->writeback_max_hscl_taps
;
481 out
->writeback_max_vscl_ratio
= in_ip_params
->writeback_max_vscl_ratio
;
482 out
->writeback_max_vscl_taps
= in_ip_params
->writeback_max_vscl_taps
;
483 out
->writeback_min_hscl_ratio
= in_ip_params
->writeback_min_hscl_ratio
;
484 out
->writeback_min_vscl_ratio
= in_ip_params
->writeback_min_vscl_ratio
;
485 out
->zero_size_buffer_entries
= in_ip_params
->zero_size_buffer_entries
;
487 /* As per hardcoded reference / discussions */
488 out
->config_return_buffer_segment_size_in_kbytes
= 64;
489 //out->vblank_nom_default_us = 600;
490 out
->vblank_nom_default_us
= in_ip_params
->VBlankNomDefaultUS
;
493 void dml2_translate_socbb_params(const struct dc
*in
, struct soc_bounding_box_st
*out
)
495 const struct _vcs_dpi_soc_bounding_box_st
*in_soc_params
= &in
->dml
.soc
;
496 /* Copy over the SOCBB params to dml2_ctx */
497 out
->dispclk_dppclk_vco_speed_mhz
= in_soc_params
->dispclk_dppclk_vco_speed_mhz
;
498 out
->do_urgent_latency_adjustment
= in_soc_params
->do_urgent_latency_adjustment
;
499 out
->dram_channel_width_bytes
= (dml_uint_t
)in_soc_params
->dram_channel_width_bytes
;
500 out
->fabric_datapath_to_dcn_data_return_bytes
= (dml_uint_t
)in_soc_params
->fabric_datapath_to_dcn_data_return_bytes
;
501 out
->gpuvm_min_page_size_kbytes
= in_soc_params
->gpuvm_min_page_size_bytes
* 1024;
502 out
->hostvm_min_page_size_kbytes
= in_soc_params
->hostvm_min_page_size_bytes
* 1024;
503 out
->mall_allocated_for_dcn_mbytes
= (dml_uint_t
)in_soc_params
->mall_allocated_for_dcn_mbytes
;
504 out
->max_avg_dram_bw_use_normal_percent
= in_soc_params
->max_avg_dram_bw_use_normal_percent
;
505 out
->max_avg_fabric_bw_use_normal_percent
= in_soc_params
->max_avg_fabric_bw_use_normal_percent
;
506 out
->max_avg_dram_bw_use_normal_strobe_percent
= in_soc_params
->max_avg_dram_bw_use_normal_strobe_percent
;
507 out
->max_avg_sdp_bw_use_normal_percent
= in_soc_params
->max_avg_sdp_bw_use_normal_percent
;
508 out
->max_outstanding_reqs
= in_soc_params
->max_request_size_bytes
;
509 out
->num_chans
= in_soc_params
->num_chans
;
510 out
->pct_ideal_dram_bw_after_urgent_strobe
= in_soc_params
->pct_ideal_dram_bw_after_urgent_strobe
;
511 out
->pct_ideal_dram_bw_after_urgent_vm_only
= in_soc_params
->pct_ideal_dram_sdp_bw_after_urgent_vm_only
;
512 out
->pct_ideal_fabric_bw_after_urgent
= in_soc_params
->pct_ideal_fabric_bw_after_urgent
;
513 out
->pct_ideal_sdp_bw_after_urgent
= in_soc_params
->pct_ideal_sdp_bw_after_urgent
;
514 out
->phy_downspread_percent
= in_soc_params
->downspread_percent
;
515 out
->refclk_mhz
= 50; // As per hardcoded reference.
516 out
->return_bus_width_bytes
= in_soc_params
->return_bus_width_bytes
;
517 out
->round_trip_ping_latency_dcfclk_cycles
= in_soc_params
->round_trip_ping_latency_dcfclk_cycles
;
518 out
->smn_latency_us
= in_soc_params
->smn_latency_us
;
519 out
->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes
= in_soc_params
->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes
;
520 out
->urgent_out_of_order_return_per_channel_pixel_only_bytes
= in_soc_params
->urgent_out_of_order_return_per_channel_pixel_only_bytes
;
521 out
->urgent_out_of_order_return_per_channel_vm_only_bytes
= in_soc_params
->urgent_out_of_order_return_per_channel_vm_only_bytes
;
522 out
->pct_ideal_dram_bw_after_urgent_pixel_and_vm
= in_soc_params
->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm
;
523 out
->pct_ideal_dram_bw_after_urgent_pixel_only
= in_soc_params
->pct_ideal_dram_sdp_bw_after_urgent_pixel_only
;
524 out
->dcn_downspread_percent
= in_soc_params
->dcn_downspread_percent
;
527 void dml2_translate_soc_states(const struct dc
*dc
, struct soc_states_st
*out
, int num_states
)
530 out
->num_states
= num_states
;
532 for (i
= 0; i
< out
->num_states
; i
++) {
533 out
->state_array
[i
].dcfclk_mhz
= dc
->dml
.soc
.clock_limits
[i
].dcfclk_mhz
;
534 out
->state_array
[i
].dispclk_mhz
= dc
->dml
.soc
.clock_limits
[i
].dispclk_mhz
;
535 out
->state_array
[i
].dppclk_mhz
= dc
->dml
.soc
.clock_limits
[i
].dppclk_mhz
;
536 out
->state_array
[i
].dram_speed_mts
= dc
->dml
.soc
.clock_limits
[i
].dram_speed_mts
;
537 out
->state_array
[i
].dtbclk_mhz
= dc
->dml
.soc
.clock_limits
[i
].dtbclk_mhz
;
538 out
->state_array
[i
].socclk_mhz
= dc
->dml
.soc
.clock_limits
[i
].socclk_mhz
;
539 out
->state_array
[i
].fabricclk_mhz
= dc
->dml
.soc
.clock_limits
[i
].fabricclk_mhz
;
540 out
->state_array
[i
].dscclk_mhz
= dc
->dml
.soc
.clock_limits
[i
].dscclk_mhz
;
541 out
->state_array
[i
].phyclk_d18_mhz
= dc
->dml
.soc
.clock_limits
[i
].phyclk_d18_mhz
;
542 out
->state_array
[i
].phyclk_d32_mhz
= dc
->dml
.soc
.clock_limits
[i
].phyclk_d32_mhz
;
543 out
->state_array
[i
].phyclk_mhz
= dc
->dml
.soc
.clock_limits
[i
].phyclk_mhz
;
544 out
->state_array
[i
].sr_enter_plus_exit_time_us
= dc
->dml
.soc
.sr_enter_plus_exit_time_us
;
545 out
->state_array
[i
].sr_exit_time_us
= dc
->dml
.soc
.sr_exit_time_us
;
546 out
->state_array
[i
].fclk_change_latency_us
= dc
->dml
.soc
.fclk_change_latency_us
;
547 out
->state_array
[i
].dram_clock_change_latency_us
= dc
->dml
.soc
.dram_clock_change_latency_us
;
548 out
->state_array
[i
].usr_retraining_latency_us
= dc
->dml
.soc
.usr_retraining_latency_us
;
549 out
->state_array
[i
].writeback_latency_us
= dc
->dml
.soc
.writeback_latency_us
;
550 /* Driver initialized values for these are different than the spreadsheet. Use the
551 * spreadsheet ones for now. We need to decided which ones to use.
553 out
->state_array
[i
].sr_exit_z8_time_us
= dc
->dml
.soc
.sr_exit_z8_time_us
;
554 out
->state_array
[i
].sr_enter_plus_exit_z8_time_us
= dc
->dml
.soc
.sr_enter_plus_exit_z8_time_us
;
555 //out->state_array[i].sr_exit_z8_time_us = 5.20;
556 //out->state_array[i].sr_enter_plus_exit_z8_time_us = 9.60;
557 out
->state_array
[i
].use_ideal_dram_bw_strobe
= true;
558 out
->state_array
[i
].urgent_latency_pixel_data_only_us
= dc
->dml
.soc
.urgent_latency_pixel_data_only_us
;
559 out
->state_array
[i
].urgent_latency_pixel_mixed_with_vm_data_us
= dc
->dml
.soc
.urgent_latency_pixel_mixed_with_vm_data_us
;
560 out
->state_array
[i
].urgent_latency_vm_data_only_us
= dc
->dml
.soc
.urgent_latency_vm_data_only_us
;
561 out
->state_array
[i
].urgent_latency_adjustment_fabric_clock_component_us
= dc
->dml
.soc
.urgent_latency_adjustment_fabric_clock_component_us
;
562 out
->state_array
[i
].urgent_latency_adjustment_fabric_clock_reference_mhz
= dc
->dml
.soc
.urgent_latency_adjustment_fabric_clock_reference_mhz
;
566 static void populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st
*out
, unsigned int location
, const struct dc_stream_state
*in
)
568 dml_uint_t hblank_start
, vblank_start
;
570 out
->HActive
[location
] = in
->timing
.h_addressable
+ in
->timing
.h_border_left
+ in
->timing
.h_border_right
;
571 out
->VActive
[location
] = in
->timing
.v_addressable
+ in
->timing
.v_border_bottom
+ in
->timing
.v_border_top
;
572 out
->RefreshRate
[location
] = ((in
->timing
.pix_clk_100hz
* 100) / in
->timing
.h_total
) / in
->timing
.v_total
;
573 out
->VFrontPorch
[location
] = in
->timing
.v_front_porch
;
574 out
->PixelClock
[location
] = in
->timing
.pix_clk_100hz
/ 10000.00;
575 if (in
->timing
.timing_3d_format
== TIMING_3D_FORMAT_HW_FRAME_PACKING
)
576 out
->PixelClock
[location
] *= 2;
577 out
->HTotal
[location
] = in
->timing
.h_total
;
578 out
->VTotal
[location
] = in
->timing
.v_total
;
579 out
->Interlace
[location
] = in
->timing
.flags
.INTERLACE
;
580 hblank_start
= in
->timing
.h_total
- in
->timing
.h_front_porch
;
581 out
->HBlankEnd
[location
] = hblank_start
582 - in
->timing
.h_addressable
583 - in
->timing
.h_border_left
584 - in
->timing
.h_border_right
;
585 vblank_start
= in
->timing
.v_total
- in
->timing
.v_front_porch
;
586 out
->VBlankEnd
[location
] = vblank_start
587 - in
->timing
.v_addressable
588 - in
->timing
.v_border_top
589 - in
->timing
.v_border_bottom
;
590 out
->DRRDisplay
[location
] = false;
593 static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st
*out
, unsigned int location
,
594 const struct dc_stream_state
*in
, const struct pipe_ctx
*pipe
)
596 unsigned int output_bpc
;
598 out
->DSCEnable
[location
] = (enum dml_dsc_enable
)in
->timing
.flags
.DSC
;
599 out
->OutputLinkDPLanes
[location
] = 4; // As per code in dcn20_resource.c
600 out
->DSCInputBitPerComponent
[location
] = 12; // As per code in dcn20_resource.c
602 switch (in
->signal
) {
603 case SIGNAL_TYPE_DISPLAY_PORT_MST
:
604 case SIGNAL_TYPE_DISPLAY_PORT
:
605 out
->OutputEncoder
[location
] = dml_dp
;
606 if (is_dp2p0_output_encoder(pipe
))
607 out
->OutputEncoder
[location
] = dml_dp2p0
;
609 out
->OutputEncoder
[location
] = dml_edp
;
610 case SIGNAL_TYPE_EDP
:
612 case SIGNAL_TYPE_HDMI_TYPE_A
:
613 case SIGNAL_TYPE_DVI_SINGLE_LINK
:
614 case SIGNAL_TYPE_DVI_DUAL_LINK
:
615 out
->OutputEncoder
[location
] = dml_hdmi
;
618 out
->OutputEncoder
[location
] = dml_dp
;
621 switch (in
->timing
.display_color_depth
) {
622 case COLOR_DEPTH_666
:
625 case COLOR_DEPTH_888
:
628 case COLOR_DEPTH_101010
:
631 case COLOR_DEPTH_121212
:
634 case COLOR_DEPTH_141414
:
637 case COLOR_DEPTH_161616
:
640 case COLOR_DEPTH_999
:
643 case COLOR_DEPTH_111111
:
651 switch (in
->timing
.pixel_encoding
) {
652 case PIXEL_ENCODING_RGB
:
653 case PIXEL_ENCODING_YCBCR444
:
654 out
->OutputFormat
[location
] = dml_444
;
655 out
->OutputBpp
[location
] = (dml_float_t
)output_bpc
* 3;
657 case PIXEL_ENCODING_YCBCR420
:
658 out
->OutputFormat
[location
] = dml_420
;
659 out
->OutputBpp
[location
] = (output_bpc
* 3.0) / 2;
661 case PIXEL_ENCODING_YCBCR422
:
662 if (in
->timing
.flags
.DSC
&& !in
->timing
.dsc_cfg
.ycbcr422_simple
)
663 out
->OutputFormat
[location
] = dml_n422
;
665 out
->OutputFormat
[location
] = dml_s422
;
666 out
->OutputBpp
[location
] = (dml_float_t
)output_bpc
* 2;
669 out
->OutputFormat
[location
] = dml_444
;
670 out
->OutputBpp
[location
] = (dml_float_t
)output_bpc
* 3;
674 if (in
->timing
.flags
.DSC
) {
675 out
->OutputBpp
[location
] = in
->timing
.dsc_cfg
.bits_per_pixel
/ 16.0;
678 // This has been false throughout DCN32x development. If needed we can change this later on.
679 out
->OutputMultistreamEn
[location
] = false;
681 switch (in
->signal
) {
682 case SIGNAL_TYPE_NONE
:
683 case SIGNAL_TYPE_DVI_SINGLE_LINK
:
684 case SIGNAL_TYPE_DVI_DUAL_LINK
:
685 case SIGNAL_TYPE_HDMI_TYPE_A
:
686 case SIGNAL_TYPE_LVDS
:
687 case SIGNAL_TYPE_RGB
:
688 case SIGNAL_TYPE_DISPLAY_PORT
:
689 case SIGNAL_TYPE_DISPLAY_PORT_MST
:
690 case SIGNAL_TYPE_EDP
:
691 case SIGNAL_TYPE_VIRTUAL
:
693 out
->OutputLinkDPRate
[location
] = dml_dp_rate_na
;
697 out
->PixelClockBackEnd
[location
] = in
->timing
.pix_clk_100hz
/ 10000.00;
699 out
->AudioSampleLayout
[location
] = in
->audio_info
.modes
->sample_size
;
700 out
->AudioSampleRate
[location
] = in
->audio_info
.modes
->max_bit_rate
;
702 out
->OutputDisabled
[location
] = true;
705 static void populate_dummy_dml_surface_cfg(struct dml_surface_cfg_st
*out
, unsigned int location
, const struct dc_stream_state
*in
)
707 out
->SurfaceWidthY
[location
] = in
->timing
.h_addressable
;
708 out
->SurfaceHeightY
[location
] = in
->timing
.v_addressable
;
709 out
->SurfaceWidthC
[location
] = in
->timing
.h_addressable
;
710 out
->SurfaceHeightC
[location
] = in
->timing
.v_addressable
;
711 out
->PitchY
[location
] = ((out
->SurfaceWidthY
[location
] + 127) / 128) * 128;
712 out
->PitchC
[location
] = 0;
713 out
->DCCEnable
[location
] = false;
714 out
->DCCMetaPitchY
[location
] = 0;
715 out
->DCCMetaPitchC
[location
] = 0;
716 out
->DCCRateLuma
[location
] = 1.0;
717 out
->DCCRateChroma
[location
] = 1.0;
718 out
->DCCFractionOfZeroSizeRequestsLuma
[location
] = 0;
719 out
->DCCFractionOfZeroSizeRequestsChroma
[location
] = 0;
720 out
->SurfaceTiling
[location
] = dml_sw_64kb_r_x
;
721 out
->SourcePixelFormat
[location
] = dml_444_32
;
724 static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_project
, struct dml_surface_cfg_st
*out
, unsigned int location
, const struct dc_plane_state
*in
)
726 out
->PitchY
[location
] = in
->plane_size
.surface_pitch
;
727 out
->SurfaceHeightY
[location
] = in
->plane_size
.surface_size
.height
;
728 out
->SurfaceWidthY
[location
] = in
->plane_size
.surface_size
.width
;
729 out
->SurfaceHeightC
[location
] = in
->plane_size
.chroma_size
.height
;
730 out
->SurfaceWidthC
[location
] = in
->plane_size
.chroma_size
.width
;
731 out
->PitchC
[location
] = in
->plane_size
.chroma_pitch
;
732 out
->DCCEnable
[location
] = in
->dcc
.enable
;
733 out
->DCCMetaPitchY
[location
] = in
->dcc
.meta_pitch
;
734 out
->DCCMetaPitchC
[location
] = in
->dcc
.meta_pitch_c
;
735 out
->DCCRateLuma
[location
] = 1.0;
736 out
->DCCRateChroma
[location
] = 1.0;
737 out
->DCCFractionOfZeroSizeRequestsLuma
[location
] = in
->dcc
.independent_64b_blks
;
738 out
->DCCFractionOfZeroSizeRequestsChroma
[location
] = in
->dcc
.independent_64b_blks_c
;
740 switch (dml2_project
) {
742 out
->SurfaceTiling
[location
] = (enum dml_swizzle_mode
)in
->tiling_info
.gfx9
.swizzle
;
746 switch (in
->format
) {
747 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr
:
748 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb
:
749 out
->SourcePixelFormat
[location
] = dml_420_8
;
751 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr
:
752 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb
:
753 out
->SourcePixelFormat
[location
] = dml_420_10
;
755 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616
:
756 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F
:
757 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
:
758 out
->SourcePixelFormat
[location
] = dml_444_64
;
760 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555
:
761 case SURFACE_PIXEL_FORMAT_GRPH_RGB565
:
762 out
->SourcePixelFormat
[location
] = dml_444_16
;
764 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS
:
765 out
->SourcePixelFormat
[location
] = dml_444_8
;
767 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
:
768 out
->SourcePixelFormat
[location
] = dml_rgbe_alpha
;
771 out
->SourcePixelFormat
[location
] = dml_444_32
;
776 /*TODO no support for mpc combine, need rework - should calculate scaling params based on plane+stream*/
777 static struct scaler_data
get_scaler_data_for_plane(const struct dc_plane_state
*in
, const struct dc_state
*context
)
780 struct scaler_data data
= { 0 };
782 for (i
= 0; i
< MAX_PIPES
; i
++) {
783 const struct pipe_ctx
*pipe
= &context
->res_ctx
.pipe_ctx
[i
];
785 if (pipe
->plane_state
== in
&& !pipe
->prev_odm_pipe
) {
786 const struct pipe_ctx
*next_pipe
= pipe
->next_odm_pipe
;
788 data
= context
->res_ctx
.pipe_ctx
[i
].plane_res
.scl_data
;
790 data
.h_active
+= next_pipe
->plane_res
.scl_data
.h_active
;
791 data
.recout
.width
+= next_pipe
->plane_res
.scl_data
.recout
.width
;
792 if (in
->rotation
== ROTATION_ANGLE_0
|| in
->rotation
== ROTATION_ANGLE_180
) {
793 data
.viewport
.width
+= next_pipe
->plane_res
.scl_data
.viewport
.width
;
795 data
.viewport
.height
+= next_pipe
->plane_res
.scl_data
.viewport
.height
;
797 next_pipe
= next_pipe
->next_odm_pipe
;
803 ASSERT(i
< MAX_PIPES
);
807 static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st
*out
, unsigned int location
, const struct dc_stream_state
*in
)
809 out
->CursorBPP
[location
] = dml_cur_32bit
;
810 out
->CursorWidth
[location
] = 256;
812 out
->GPUVMMinPageSizeKBytes
[location
] = 256;
814 out
->ViewportWidth
[location
] = in
->timing
.h_addressable
;
815 out
->ViewportHeight
[location
] = in
->timing
.v_addressable
;
816 out
->ViewportStationary
[location
] = false;
817 out
->ViewportWidthChroma
[location
] = 0;
818 out
->ViewportHeightChroma
[location
] = 0;
819 out
->ViewportXStart
[location
] = 0;
820 out
->ViewportXStartC
[location
] = 0;
821 out
->ViewportYStart
[location
] = 0;
822 out
->ViewportYStartC
[location
] = 0;
824 out
->ScalerEnabled
[location
] = false;
825 out
->HRatio
[location
] = 1.0;
826 out
->VRatio
[location
] = 1.0;
827 out
->HRatioChroma
[location
] = 0;
828 out
->VRatioChroma
[location
] = 0;
829 out
->HTaps
[location
] = 1;
830 out
->VTaps
[location
] = 1;
831 out
->HTapsChroma
[location
] = 0;
832 out
->VTapsChroma
[location
] = 0;
833 out
->SourceScan
[location
] = dml_rotation_0
;
834 out
->ScalerRecoutWidth
[location
] = in
->timing
.h_addressable
;
836 out
->LBBitPerPixel
[location
] = 57;
838 out
->DynamicMetadataEnable
[location
] = false;
840 out
->NumberOfCursors
[location
] = 1;
841 out
->UseMALLForStaticScreen
[location
] = dml_use_mall_static_screen_disable
;
842 out
->UseMALLForPStateChange
[location
] = dml_use_mall_pstate_change_disable
;
844 out
->DETSizeOverride
[location
] = 256;
846 out
->ScalerEnabled
[location
] = false;
849 static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st
*out
, unsigned int location
, const struct dc_plane_state
*in
, const struct dc_state
*context
)
851 const struct scaler_data scaler_data
= get_scaler_data_for_plane(in
, context
);
853 out
->CursorBPP
[location
] = dml_cur_32bit
;
854 out
->CursorWidth
[location
] = 256;
856 out
->GPUVMMinPageSizeKBytes
[location
] = 256;
858 out
->ViewportWidth
[location
] = scaler_data
.viewport
.width
;
859 out
->ViewportHeight
[location
] = scaler_data
.viewport
.height
;
860 out
->ViewportWidthChroma
[location
] = scaler_data
.viewport_c
.width
;
861 out
->ViewportHeightChroma
[location
] = scaler_data
.viewport_c
.height
;
862 out
->ViewportXStart
[location
] = scaler_data
.viewport
.x
;
863 out
->ViewportYStart
[location
] = scaler_data
.viewport
.y
;
864 out
->ViewportXStartC
[location
] = scaler_data
.viewport_c
.x
;
865 out
->ViewportYStartC
[location
] = scaler_data
.viewport_c
.y
;
866 out
->ViewportStationary
[location
] = false;
868 out
->ScalerEnabled
[location
] = scaler_data
.ratios
.horz
.value
!= dc_fixpt_one
.value
||
869 scaler_data
.ratios
.horz_c
.value
!= dc_fixpt_one
.value
||
870 scaler_data
.ratios
.vert
.value
!= dc_fixpt_one
.value
||
871 scaler_data
.ratios
.vert_c
.value
!= dc_fixpt_one
.value
;
873 /* Current driver code base uses LBBitPerPixel as 57. There is a discrepancy
874 * from the HW/DML teams about this value. Initialize LBBitPerPixel with the
875 * value current used in Navi3x .
878 out
->LBBitPerPixel
[location
] = 57;
880 if (out
->ScalerEnabled
[location
] == false) {
881 out
->HRatio
[location
] = 1;
882 out
->HRatioChroma
[location
] = 1;
883 out
->VRatio
[location
] = 1;
884 out
->VRatioChroma
[location
] = 1;
886 /* Follow the original dml_wrapper.c code direction to fix scaling issues */
887 out
->HRatio
[location
] = (dml_float_t
)scaler_data
.ratios
.horz
.value
/ (1ULL << 32);
888 out
->HRatioChroma
[location
] = (dml_float_t
)scaler_data
.ratios
.horz_c
.value
/ (1ULL << 32);
889 out
->VRatio
[location
] = (dml_float_t
)scaler_data
.ratios
.vert
.value
/ (1ULL << 32);
890 out
->VRatioChroma
[location
] = (dml_float_t
)scaler_data
.ratios
.vert_c
.value
/ (1ULL << 32);
893 if (!scaler_data
.taps
.h_taps
) {
894 out
->HTaps
[location
] = 1;
895 out
->HTapsChroma
[location
] = 1;
897 out
->HTaps
[location
] = scaler_data
.taps
.h_taps
;
898 out
->HTapsChroma
[location
] = scaler_data
.taps
.h_taps_c
;
900 if (!scaler_data
.taps
.v_taps
) {
901 out
->VTaps
[location
] = 1;
902 out
->VTapsChroma
[location
] = 1;
904 out
->VTaps
[location
] = scaler_data
.taps
.v_taps
;
905 out
->VTapsChroma
[location
] = scaler_data
.taps
.v_taps_c
;
908 out
->SourceScan
[location
] = (enum dml_rotation_angle
)in
->rotation
;
909 out
->ScalerRecoutWidth
[location
] = in
->dst_rect
.width
;
911 out
->DynamicMetadataEnable
[location
] = false;
912 out
->DynamicMetadataLinesBeforeActiveRequired
[location
] = 0;
913 out
->DynamicMetadataTransmittedBytes
[location
] = 0;
915 out
->NumberOfCursors
[location
] = 1;
918 static unsigned int map_stream_to_dml_display_cfg(const struct dml2_context
*dml2
,
919 const struct dc_stream_state
*stream
, const struct dml_display_cfg_st
*dml_dispcfg
)
924 for (i
= 0; i
< __DML2_WRAPPER_MAX_STREAMS_PLANES__
; i
++) {
925 if (dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_stream_id_valid
[i
] && dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_stream_id
[i
] == stream
->stream_id
) {
934 static bool get_plane_id(struct dml2_context
*dml2
, const struct dc_state
*context
, const struct dc_plane_state
*plane
,
935 unsigned int stream_id
, unsigned int plane_index
, unsigned int *plane_id
)
938 bool is_plane_duplicate
= dml2
->v20
.scratch
.plane_duplicate_exists
;
943 for (i
= 0; i
< context
->stream_count
; i
++) {
944 if (context
->streams
[i
]->stream_id
== stream_id
) {
945 for (j
= 0; j
< context
->stream_status
[i
].plane_count
; j
++) {
946 if (context
->stream_status
[i
].plane_states
[j
] == plane
&&
947 (!is_plane_duplicate
|| (is_plane_duplicate
&& (j
== plane_index
)))) {
948 *plane_id
= (i
<< 16) | j
;
958 static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context
*dml2
, const struct dc_plane_state
*plane
,
959 const struct dc_state
*context
, const struct dml_display_cfg_st
*dml_dispcfg
, unsigned int stream_id
, int plane_index
)
961 unsigned int plane_id
;
965 if (!get_plane_id(context
->bw_ctx
.dml2
, context
, plane
, stream_id
, plane_index
, &plane_id
)) {
970 for (i
= 0; i
< __DML2_WRAPPER_MAX_STREAMS_PLANES__
; i
++) {
971 if (dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_plane_id_valid
[i
] && dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_plane_id
[i
] == plane_id
) {
980 static void apply_legacy_svp_drr_settings(struct dml2_context
*dml2
, const struct dc_state
*state
, struct dml_display_cfg_st
*dml_dispcfg
)
984 if (state
->bw_ctx
.bw
.dcn
.clk
.fw_based_mclk_switching
) {
985 ASSERT(state
->stream_count
== 1);
986 dml_dispcfg
->timing
.DRRDisplay
[0] = true;
987 } else if (state
->bw_ctx
.bw
.dcn
.legacy_svp_drr_stream_index_valid
) {
989 for (i
= 0; i
< dml_dispcfg
->num_timings
; i
++) {
990 if (dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_stream_id
[i
] == state
->streams
[state
->bw_ctx
.bw
.dcn
.legacy_svp_drr_stream_index
]->stream_id
)
991 dml_dispcfg
->timing
.DRRDisplay
[i
] = true;
996 static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context
*dml2
, struct dc_state
*state
)
999 unsigned int pipe_index
= 0;
1000 unsigned int plane_index
= 0;
1001 struct dml2_dml_to_dc_pipe_mapping
*dml_to_dc_pipe_mapping
= &dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
;
1003 for (i
= 0; i
< __DML2_WRAPPER_MAX_STREAMS_PLANES__
; i
++) {
1004 dml_to_dc_pipe_mapping
->dml_pipe_idx_to_plane_index_valid
[i
] = false;
1005 dml_to_dc_pipe_mapping
->dml_pipe_idx_to_plane_index
[i
] = 0;
1008 for (i
= 0; i
< __DML2_WRAPPER_MAX_STREAMS_PLANES__
; i
++) {
1009 struct pipe_ctx
*pipe
= &state
->res_ctx
.pipe_ctx
[i
];
1011 if (!pipe
|| !pipe
->stream
|| !pipe
->plane_state
)
1015 pipe_index
= pipe
->pipe_idx
;
1017 if (pipe
->stream
&& dml_to_dc_pipe_mapping
->dml_pipe_idx_to_plane_index_valid
[pipe_index
] == false) {
1018 dml_to_dc_pipe_mapping
->dml_pipe_idx_to_plane_index
[pipe_index
] = plane_index
;
1020 dml_to_dc_pipe_mapping
->dml_pipe_idx_to_plane_index_valid
[pipe_index
] = true;
1023 pipe
= pipe
->bottom_pipe
;
1030 void map_dc_state_into_dml_display_cfg(struct dml2_context
*dml2
, struct dc_state
*context
, struct dml_display_cfg_st
*dml_dispcfg
)
1033 int disp_cfg_stream_location
, disp_cfg_plane_location
;
1035 for (i
= 0; i
< __DML2_WRAPPER_MAX_STREAMS_PLANES__
; i
++) {
1036 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_stream_id_valid
[i
] = false;
1037 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_plane_id_valid
[i
] = false;
1038 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.dml_pipe_idx_to_stream_id_valid
[i
] = false;
1039 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.dml_pipe_idx_to_plane_id_valid
[i
] = false;
1042 //Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file
1043 dml_dispcfg
->plane
.GPUVMEnable
= true;
1044 dml_dispcfg
->plane
.GPUVMMaxPageTableLevels
= 4;
1045 dml_dispcfg
->plane
.HostVMEnable
= false;
1047 dml2_populate_pipe_to_plane_index_mapping(dml2
, context
);
1049 for (i
= 0; i
< context
->stream_count
; i
++) {
1050 disp_cfg_stream_location
= map_stream_to_dml_display_cfg(dml2
, context
->streams
[i
], dml_dispcfg
);
1052 if (disp_cfg_stream_location
< 0)
1053 disp_cfg_stream_location
= dml_dispcfg
->num_timings
++;
1055 ASSERT(disp_cfg_stream_location
>= 0 && disp_cfg_stream_location
<= __DML2_WRAPPER_MAX_STREAMS_PLANES__
);
1057 populate_dml_timing_cfg_from_stream_state(&dml_dispcfg
->timing
, disp_cfg_stream_location
, context
->streams
[i
]);
1058 populate_dml_output_cfg_from_stream_state(&dml_dispcfg
->output
, disp_cfg_stream_location
, context
->streams
[i
], &context
->res_ctx
.pipe_ctx
[i
]);
1059 switch (context
->streams
[i
]->debug
.force_odm_combine_segments
) {
1061 dml2
->v20
.dml_core_ctx
.policy
.ODMUse
[disp_cfg_stream_location
] = dml_odm_use_policy_combine_2to1
;
1064 dml2
->v20
.dml_core_ctx
.policy
.ODMUse
[disp_cfg_stream_location
] = dml_odm_use_policy_combine_4to1
;
1070 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_stream_id
[disp_cfg_stream_location
] = context
->streams
[i
]->stream_id
;
1071 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_stream_id_valid
[disp_cfg_stream_location
] = true;
1073 if (context
->stream_status
[i
].plane_count
== 0) {
1074 disp_cfg_plane_location
= dml_dispcfg
->num_surfaces
++;
1076 populate_dummy_dml_surface_cfg(&dml_dispcfg
->surface
, disp_cfg_plane_location
, context
->streams
[i
]);
1077 populate_dummy_dml_plane_cfg(&dml_dispcfg
->plane
, disp_cfg_plane_location
, context
->streams
[i
]);
1079 dml_dispcfg
->plane
.BlendingAndTiming
[disp_cfg_plane_location
] = disp_cfg_stream_location
;
1081 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_plane_id_valid
[disp_cfg_plane_location
] = true;
1083 for (j
= 0; j
< context
->stream_status
[i
].plane_count
; j
++) {
1084 disp_cfg_plane_location
= map_plane_to_dml_display_cfg(dml2
,
1085 context
->stream_status
[i
].plane_states
[j
], context
, dml_dispcfg
, context
->streams
[i
]->stream_id
, j
);
1087 if (disp_cfg_plane_location
< 0)
1088 disp_cfg_plane_location
= dml_dispcfg
->num_surfaces
++;
1090 ASSERT(disp_cfg_plane_location
>= 0 && disp_cfg_plane_location
<= __DML2_WRAPPER_MAX_STREAMS_PLANES__
);
1092 populate_dml_surface_cfg_from_plane_state(dml2
->v20
.dml_core_ctx
.project
, &dml_dispcfg
->surface
, disp_cfg_plane_location
, context
->stream_status
[i
].plane_states
[j
]);
1093 populate_dml_plane_cfg_from_plane_state(&dml_dispcfg
->plane
, disp_cfg_plane_location
, context
->stream_status
[i
].plane_states
[j
], context
);
1095 if (context
->streams
[i
]->mall_stream_config
.type
== SUBVP_MAIN
) {
1096 dml_dispcfg
->plane
.UseMALLForPStateChange
[disp_cfg_plane_location
] = dml_use_mall_pstate_change_sub_viewport
;
1097 dml_dispcfg
->plane
.UseMALLForStaticScreen
[disp_cfg_plane_location
] = dml_use_mall_static_screen_optimize
;
1098 } else if (context
->streams
[i
]->mall_stream_config
.type
== SUBVP_PHANTOM
) {
1099 dml_dispcfg
->plane
.UseMALLForPStateChange
[disp_cfg_plane_location
] = dml_use_mall_pstate_change_phantom_pipe
;
1100 dml_dispcfg
->plane
.UseMALLForStaticScreen
[disp_cfg_plane_location
] = dml_use_mall_static_screen_disable
;
1101 dml2
->v20
.dml_core_ctx
.policy
.ImmediateFlipRequirement
[disp_cfg_plane_location
] = dml_immediate_flip_not_required
;
1103 dml_dispcfg
->plane
.UseMALLForPStateChange
[disp_cfg_plane_location
] = dml_use_mall_pstate_change_disable
;
1104 dml_dispcfg
->plane
.UseMALLForStaticScreen
[disp_cfg_plane_location
] = dml_use_mall_static_screen_optimize
;
1107 dml_dispcfg
->plane
.BlendingAndTiming
[disp_cfg_plane_location
] = disp_cfg_stream_location
;
1109 if (get_plane_id(dml2
, context
, context
->stream_status
[i
].plane_states
[j
], context
->streams
[i
]->stream_id
, j
,
1110 &dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_plane_id
[disp_cfg_plane_location
]))
1111 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_plane_id_valid
[disp_cfg_plane_location
] = true;
1114 populate_dml_timing_cfg_from_stream_state(&dml_dispcfg
->timing
, disp_cfg_plane_location
, context
->streams
[i
]);
1115 populate_dml_output_cfg_from_stream_state(&dml_dispcfg
->output
, disp_cfg_plane_location
, context
->streams
[i
], &context
->res_ctx
.pipe_ctx
[i
]);
1116 switch (context
->streams
[i
]->debug
.force_odm_combine_segments
) {
1118 dml2
->v20
.dml_core_ctx
.policy
.ODMUse
[disp_cfg_plane_location
] = dml_odm_use_policy_combine_2to1
;
1121 dml2
->v20
.dml_core_ctx
.policy
.ODMUse
[disp_cfg_plane_location
] = dml_odm_use_policy_combine_4to1
;
1127 if (context
->streams
[i
]->mall_stream_config
.type
== SUBVP_MAIN
)
1128 dml_dispcfg
->plane
.UseMALLForPStateChange
[disp_cfg_plane_location
] = dml_use_mall_pstate_change_sub_viewport
;
1129 else if (context
->streams
[i
]->mall_stream_config
.type
== SUBVP_PHANTOM
)
1130 dml_dispcfg
->plane
.UseMALLForPStateChange
[disp_cfg_plane_location
] = dml_use_mall_pstate_change_phantom_pipe
;
1132 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_stream_id
[disp_cfg_plane_location
] = context
->streams
[i
]->stream_id
;
1133 dml2
->v20
.scratch
.dml_to_dc_pipe_mapping
.disp_cfg_to_stream_id_valid
[disp_cfg_plane_location
] = true;
1135 dml_dispcfg
->num_timings
++;
1141 if (!dml2
->config
.use_native_pstate_optimization
)
1142 apply_legacy_svp_drr_settings(dml2
, context
, dml_dispcfg
);
1145 void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st
*rq_regs
,
1146 struct _vcs_dpi_dml_display_dlg_regs_st
*disp_dlg_regs
,
1147 struct _vcs_dpi_dml_display_ttu_regs_st
*disp_ttu_regs
,
1148 struct pipe_ctx
*out
)
1150 memset(&out
->rq_regs
, 0, sizeof(out
->rq_regs
));
1151 out
->rq_regs
.rq_regs_l
.chunk_size
= rq_regs
->rq_regs_l
.chunk_size
;
1152 out
->rq_regs
.rq_regs_l
.min_chunk_size
= rq_regs
->rq_regs_l
.min_chunk_size
;
1153 out
->rq_regs
.rq_regs_l
.meta_chunk_size
= rq_regs
->rq_regs_l
.meta_chunk_size
;
1154 out
->rq_regs
.rq_regs_l
.min_meta_chunk_size
= rq_regs
->rq_regs_l
.min_meta_chunk_size
;
1155 out
->rq_regs
.rq_regs_l
.dpte_group_size
= rq_regs
->rq_regs_l
.dpte_group_size
;
1156 out
->rq_regs
.rq_regs_l
.mpte_group_size
= rq_regs
->rq_regs_l
.mpte_group_size
;
1157 out
->rq_regs
.rq_regs_l
.swath_height
= rq_regs
->rq_regs_l
.swath_height
;
1158 out
->rq_regs
.rq_regs_l
.pte_row_height_linear
= rq_regs
->rq_regs_l
.pte_row_height_linear
;
1160 out
->rq_regs
.rq_regs_c
.chunk_size
= rq_regs
->rq_regs_c
.chunk_size
;
1161 out
->rq_regs
.rq_regs_c
.min_chunk_size
= rq_regs
->rq_regs_c
.min_chunk_size
;
1162 out
->rq_regs
.rq_regs_c
.meta_chunk_size
= rq_regs
->rq_regs_c
.meta_chunk_size
;
1163 out
->rq_regs
.rq_regs_c
.min_meta_chunk_size
= rq_regs
->rq_regs_c
.min_meta_chunk_size
;
1164 out
->rq_regs
.rq_regs_c
.dpte_group_size
= rq_regs
->rq_regs_c
.dpte_group_size
;
1165 out
->rq_regs
.rq_regs_c
.mpte_group_size
= rq_regs
->rq_regs_c
.mpte_group_size
;
1166 out
->rq_regs
.rq_regs_c
.swath_height
= rq_regs
->rq_regs_c
.swath_height
;
1167 out
->rq_regs
.rq_regs_c
.pte_row_height_linear
= rq_regs
->rq_regs_c
.pte_row_height_linear
;
1169 out
->rq_regs
.drq_expansion_mode
= rq_regs
->drq_expansion_mode
;
1170 out
->rq_regs
.prq_expansion_mode
= rq_regs
->prq_expansion_mode
;
1171 out
->rq_regs
.mrq_expansion_mode
= rq_regs
->mrq_expansion_mode
;
1172 out
->rq_regs
.crq_expansion_mode
= rq_regs
->crq_expansion_mode
;
1173 out
->rq_regs
.plane1_base_address
= rq_regs
->plane1_base_address
;
1175 memset(&out
->dlg_regs
, 0, sizeof(out
->dlg_regs
));
1176 out
->dlg_regs
.refcyc_h_blank_end
= disp_dlg_regs
->refcyc_h_blank_end
;
1177 out
->dlg_regs
.dlg_vblank_end
= disp_dlg_regs
->dlg_vblank_end
;
1178 out
->dlg_regs
.min_dst_y_next_start
= disp_dlg_regs
->min_dst_y_next_start
;
1179 out
->dlg_regs
.refcyc_per_htotal
= disp_dlg_regs
->refcyc_per_htotal
;
1180 out
->dlg_regs
.refcyc_x_after_scaler
= disp_dlg_regs
->refcyc_x_after_scaler
;
1181 out
->dlg_regs
.dst_y_after_scaler
= disp_dlg_regs
->dst_y_after_scaler
;
1182 out
->dlg_regs
.dst_y_prefetch
= disp_dlg_regs
->dst_y_prefetch
;
1183 out
->dlg_regs
.dst_y_per_vm_vblank
= disp_dlg_regs
->dst_y_per_vm_vblank
;
1184 out
->dlg_regs
.dst_y_per_row_vblank
= disp_dlg_regs
->dst_y_per_row_vblank
;
1185 out
->dlg_regs
.dst_y_per_vm_flip
= disp_dlg_regs
->dst_y_per_vm_flip
;
1186 out
->dlg_regs
.dst_y_per_row_flip
= disp_dlg_regs
->dst_y_per_row_flip
;
1187 out
->dlg_regs
.ref_freq_to_pix_freq
= disp_dlg_regs
->ref_freq_to_pix_freq
;
1188 out
->dlg_regs
.vratio_prefetch
= disp_dlg_regs
->vratio_prefetch
;
1189 out
->dlg_regs
.vratio_prefetch_c
= disp_dlg_regs
->vratio_prefetch_c
;
1190 out
->dlg_regs
.refcyc_per_pte_group_vblank_l
= disp_dlg_regs
->refcyc_per_pte_group_vblank_l
;
1191 out
->dlg_regs
.refcyc_per_pte_group_vblank_c
= disp_dlg_regs
->refcyc_per_pte_group_vblank_c
;
1192 out
->dlg_regs
.refcyc_per_meta_chunk_vblank_l
= disp_dlg_regs
->refcyc_per_meta_chunk_vblank_l
;
1193 out
->dlg_regs
.refcyc_per_meta_chunk_vblank_c
= disp_dlg_regs
->refcyc_per_meta_chunk_vblank_c
;
1194 out
->dlg_regs
.refcyc_per_pte_group_flip_l
= disp_dlg_regs
->refcyc_per_pte_group_flip_l
;
1195 out
->dlg_regs
.refcyc_per_pte_group_flip_c
= disp_dlg_regs
->refcyc_per_pte_group_flip_c
;
1196 out
->dlg_regs
.refcyc_per_meta_chunk_flip_l
= disp_dlg_regs
->refcyc_per_meta_chunk_flip_l
;
1197 out
->dlg_regs
.refcyc_per_meta_chunk_flip_c
= disp_dlg_regs
->refcyc_per_meta_chunk_flip_c
;
1198 out
->dlg_regs
.dst_y_per_pte_row_nom_l
= disp_dlg_regs
->dst_y_per_pte_row_nom_l
;
1199 out
->dlg_regs
.dst_y_per_pte_row_nom_c
= disp_dlg_regs
->dst_y_per_pte_row_nom_c
;
1200 out
->dlg_regs
.refcyc_per_pte_group_nom_l
= disp_dlg_regs
->refcyc_per_pte_group_nom_l
;
1201 out
->dlg_regs
.refcyc_per_pte_group_nom_c
= disp_dlg_regs
->refcyc_per_pte_group_nom_c
;
1202 out
->dlg_regs
.dst_y_per_meta_row_nom_l
= disp_dlg_regs
->dst_y_per_meta_row_nom_l
;
1203 out
->dlg_regs
.dst_y_per_meta_row_nom_c
= disp_dlg_regs
->dst_y_per_meta_row_nom_c
;
1204 out
->dlg_regs
.refcyc_per_meta_chunk_nom_l
= disp_dlg_regs
->refcyc_per_meta_chunk_nom_l
;
1205 out
->dlg_regs
.refcyc_per_meta_chunk_nom_c
= disp_dlg_regs
->refcyc_per_meta_chunk_nom_c
;
1206 out
->dlg_regs
.refcyc_per_line_delivery_pre_l
= disp_dlg_regs
->refcyc_per_line_delivery_pre_l
;
1207 out
->dlg_regs
.refcyc_per_line_delivery_pre_c
= disp_dlg_regs
->refcyc_per_line_delivery_pre_c
;
1208 out
->dlg_regs
.refcyc_per_line_delivery_l
= disp_dlg_regs
->refcyc_per_line_delivery_l
;
1209 out
->dlg_regs
.refcyc_per_line_delivery_c
= disp_dlg_regs
->refcyc_per_line_delivery_c
;
1210 out
->dlg_regs
.refcyc_per_vm_group_vblank
= disp_dlg_regs
->refcyc_per_vm_group_vblank
;
1211 out
->dlg_regs
.refcyc_per_vm_group_flip
= disp_dlg_regs
->refcyc_per_vm_group_flip
;
1212 out
->dlg_regs
.refcyc_per_vm_req_vblank
= disp_dlg_regs
->refcyc_per_vm_req_vblank
;
1213 out
->dlg_regs
.refcyc_per_vm_req_flip
= disp_dlg_regs
->refcyc_per_vm_req_flip
;
1214 out
->dlg_regs
.dst_y_offset_cur0
= disp_dlg_regs
->dst_y_offset_cur0
;
1215 out
->dlg_regs
.chunk_hdl_adjust_cur0
= disp_dlg_regs
->chunk_hdl_adjust_cur0
;
1216 out
->dlg_regs
.dst_y_offset_cur1
= disp_dlg_regs
->dst_y_offset_cur1
;
1217 out
->dlg_regs
.chunk_hdl_adjust_cur1
= disp_dlg_regs
->chunk_hdl_adjust_cur1
;
1218 out
->dlg_regs
.vready_after_vcount0
= disp_dlg_regs
->vready_after_vcount0
;
1219 out
->dlg_regs
.dst_y_delta_drq_limit
= disp_dlg_regs
->dst_y_delta_drq_limit
;
1220 out
->dlg_regs
.refcyc_per_vm_dmdata
= disp_dlg_regs
->refcyc_per_vm_dmdata
;
1221 out
->dlg_regs
.dmdata_dl_delta
= disp_dlg_regs
->dmdata_dl_delta
;
1223 memset(&out
->ttu_regs
, 0, sizeof(out
->ttu_regs
));
1224 out
->ttu_regs
.qos_level_low_wm
= disp_ttu_regs
->qos_level_low_wm
;
1225 out
->ttu_regs
.qos_level_high_wm
= disp_ttu_regs
->qos_level_high_wm
;
1226 out
->ttu_regs
.min_ttu_vblank
= disp_ttu_regs
->min_ttu_vblank
;
1227 out
->ttu_regs
.qos_level_flip
= disp_ttu_regs
->qos_level_flip
;
1228 out
->ttu_regs
.refcyc_per_req_delivery_l
= disp_ttu_regs
->refcyc_per_req_delivery_l
;
1229 out
->ttu_regs
.refcyc_per_req_delivery_c
= disp_ttu_regs
->refcyc_per_req_delivery_c
;
1230 out
->ttu_regs
.refcyc_per_req_delivery_cur0
= disp_ttu_regs
->refcyc_per_req_delivery_cur0
;
1231 out
->ttu_regs
.refcyc_per_req_delivery_cur1
= disp_ttu_regs
->refcyc_per_req_delivery_cur1
;
1232 out
->ttu_regs
.refcyc_per_req_delivery_pre_l
= disp_ttu_regs
->refcyc_per_req_delivery_pre_l
;
1233 out
->ttu_regs
.refcyc_per_req_delivery_pre_c
= disp_ttu_regs
->refcyc_per_req_delivery_pre_c
;
1234 out
->ttu_regs
.refcyc_per_req_delivery_pre_cur0
= disp_ttu_regs
->refcyc_per_req_delivery_pre_cur0
;
1235 out
->ttu_regs
.refcyc_per_req_delivery_pre_cur1
= disp_ttu_regs
->refcyc_per_req_delivery_pre_cur1
;
1236 out
->ttu_regs
.qos_level_fixed_l
= disp_ttu_regs
->qos_level_fixed_l
;
1237 out
->ttu_regs
.qos_level_fixed_c
= disp_ttu_regs
->qos_level_fixed_c
;
1238 out
->ttu_regs
.qos_level_fixed_cur0
= disp_ttu_regs
->qos_level_fixed_cur0
;
1239 out
->ttu_regs
.qos_level_fixed_cur1
= disp_ttu_regs
->qos_level_fixed_cur1
;
1240 out
->ttu_regs
.qos_ramp_disable_l
= disp_ttu_regs
->qos_ramp_disable_l
;
1241 out
->ttu_regs
.qos_ramp_disable_c
= disp_ttu_regs
->qos_ramp_disable_c
;
1242 out
->ttu_regs
.qos_ramp_disable_cur0
= disp_ttu_regs
->qos_ramp_disable_cur0
;
1243 out
->ttu_regs
.qos_ramp_disable_cur1
= disp_ttu_regs
->qos_ramp_disable_cur1
;