drivers/gpu/drm/amd/display/dc/link/link_detection.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* FILE POLICY AND INTENDED USAGE:
  27  * This file manages link detection states and receiver states by using various
  28  * link protocols. It also provides helper functions to interpret certain
  29  * capabilities or status based on the states it manages or retrieve them
  30  * directly from connected receivers.
  31  */
  32
  33 #include "link_dpms.h"
  34 #include "link_detection.h"
  35 #include "link_hwss.h"
  36 #include "protocols/link_edp_panel_control.h"
  37 #include "protocols/link_ddc.h"
  38 #include "protocols/link_hpd.h"
  39 #include "protocols/link_dpcd.h"
  40 #include "protocols/link_dp_capability.h"
  41 #include "protocols/link_dp_dpia.h"
  42 #include "protocols/link_dp_phy.h"
  43 #include "protocols/link_dp_training.h"
  44 #include "accessories/link_dp_trace.h"
  45
  46 #include "link_enc_cfg.h"
  47 #include "dm_helpers.h"
  48 #include "clk_mgr.h"
  49
  50 #define DC_LOGGER \
  51         link->ctx->logger
  52 #define DC_LOGGER_INIT(logger)
  53
  54 #define LINK_INFO(...) \
  55         DC_LOG_HW_HOTPLUG(  \
  56                 __VA_ARGS__)
  57 /*
  58  * Some receivers fail to train on first try and are good
  59  * on subsequent tries. 2 retries should be plenty. If we
  60  * don't have a successful training then we don't expect to
  61  * ever get one.
  62  */
  63 #define LINK_TRAINING_MAX_VERIFY_RETRY 2
  64
  65 static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u";
  66
  67 static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
  68
  69 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
  70 {
  71         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
  72
  73         switch (sink_signal) {
  74         case SIGNAL_TYPE_DVI_SINGLE_LINK:
  75         case SIGNAL_TYPE_DVI_DUAL_LINK:
  76         case SIGNAL_TYPE_HDMI_TYPE_A:
  77         case SIGNAL_TYPE_LVDS:
  78         case SIGNAL_TYPE_RGB:
  79                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
  80                 break;
  81
  82         case SIGNAL_TYPE_DISPLAY_PORT:
  83         case SIGNAL_TYPE_EDP:
  84                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
  85                 break;
  86
  87         case SIGNAL_TYPE_DISPLAY_PORT_MST:
  88                 /* MST does not use I2COverAux, but there is the
  89                  * SPECIAL use case for "immediate dwnstrm device
  90                  * access" (EPR#370830).
  91                  */
  92                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
  93                 break;
  94
  95         default:
  96                 break;
  97         }
  98
  99         return transaction_type;
 100 }
 101
 102 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 103                                               struct graphics_object_id downstream)
 104 {
 105         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 106                 switch (downstream.id) {
 107                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 108                         switch (encoder.id) {
 109                         case ENCODER_ID_INTERNAL_DAC1:
 110                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 111                         case ENCODER_ID_INTERNAL_DAC2:
 112                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 113                                 return SIGNAL_TYPE_RGB;
 114                         default:
 115                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 116                         }
 117                 break;
 118                 case CONNECTOR_ID_DUAL_LINK_DVII:
 119                 {
 120                         switch (encoder.id) {
 121                         case ENCODER_ID_INTERNAL_DAC1:
 122                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 123                         case ENCODER_ID_INTERNAL_DAC2:
 124                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 125                                 return SIGNAL_TYPE_RGB;
 126                         default:
 127                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 128                         }
 129                 }
 130                 break;
 131                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 132                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 133                 case CONNECTOR_ID_DUAL_LINK_DVID:
 134                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 135                 case CONNECTOR_ID_VGA:
 136                         return SIGNAL_TYPE_RGB;
 137                 case CONNECTOR_ID_HDMI_TYPE_A:
 138                         return SIGNAL_TYPE_HDMI_TYPE_A;
 139                 case CONNECTOR_ID_LVDS:
 140                         return SIGNAL_TYPE_LVDS;
 141                 case CONNECTOR_ID_DISPLAY_PORT:
 142                 case CONNECTOR_ID_USBC:
 143                         return SIGNAL_TYPE_DISPLAY_PORT;
 144                 case CONNECTOR_ID_EDP:
 145                         return SIGNAL_TYPE_EDP;
 146                 default:
 147                         return SIGNAL_TYPE_NONE;
 148                 }
 149         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 150                 switch (downstream.id) {
 151                 case ENCODER_ID_EXTERNAL_NUTMEG:
 152                 case ENCODER_ID_EXTERNAL_TRAVIS:
 153                         return SIGNAL_TYPE_DISPLAY_PORT;
 154                 default:
 155                         return SIGNAL_TYPE_NONE;
 156                 }
 157         }
 158
 159         return SIGNAL_TYPE_NONE;
 160 }
 161
 162 /*
 163  * @brief
 164  * Detect output sink type
 165  */
 166 static enum signal_type link_detect_sink_signal_type(struct dc_link *link,
 167                                          enum dc_detect_reason reason)
 168 {
 169         enum signal_type result;
 170         struct graphics_object_id enc_id;
 171
 172         if (link->is_dig_mapping_flexible)
 173                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 174         else
 175                 enc_id = link->link_enc->id;
 176         result = get_basic_signal_type(enc_id, link->link_id);
 177
 178         /* Use basic signal type for link without physical connector. */
 179         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 180                 return result;
 181
 182         /* Internal digital encoder will detect only dongles
 183          * that require digital signal
 184          */
 185
 186         /* Detection mechanism is different
 187          * for different native connectors.
 188          * LVDS connector supports only LVDS signal;
 189          * PCIE is a bus slot, the actual connector needs to be detected first;
 190          * eDP connector supports only eDP signal;
 191          * HDMI should check straps for audio
 192          */
 193
 194         /* PCIE detects the actual connector on add-on board */
 195         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 196                 /* ZAZTODO implement PCIE add-on card detection */
 197         }
 198
 199         switch (link->link_id.id) {
 200         case CONNECTOR_ID_HDMI_TYPE_A: {
 201                 /* check audio support:
 202                  * if native HDMI is not supported, switch to DVI
 203                  */
 204                 struct audio_support *aud_support =
 205                                         &link->dc->res_pool->audio_support;
 206
 207                 if (!aud_support->hdmi_audio_native)
 208                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 209                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 210         }
 211         break;
 212         case CONNECTOR_ID_DISPLAY_PORT:
 213         case CONNECTOR_ID_USBC: {
 214                 /* DP HPD short pulse. Passive DP dongle will not
 215                  * have short pulse
 216                  */
 217                 if (reason != DETECT_REASON_HPDRX) {
 218                         /* Check whether DP signal detected: if not -
 219                          * we assume signal is DVI; it could be corrected
 220                          * to HDMI after dongle detection
 221                          */
 222                         if (!dm_helpers_is_dp_sink_present(link))
 223                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 224                 }
 225         }
 226         break;
 227         default:
 228         break;
 229         }
 230
 231         return result;
 232 }
 233
 234 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 235                                                                  struct audio_support *audio_support)
 236 {
 237         enum signal_type signal = SIGNAL_TYPE_NONE;
 238
 239         switch (dongle_type) {
 240         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 241                 if (audio_support->hdmi_audio_on_dongle)
 242                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 243                 else
 244                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 245                 break;
 246         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 247                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 248                 break;
 249         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 250                 if (audio_support->hdmi_audio_native)
 251                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 252                 else
 253                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 254                 break;
 255         default:
 256                 signal = SIGNAL_TYPE_NONE;
 257                 break;
 258         }
 259
 260         return signal;
 261 }
 262
 263 static void read_scdc_caps(struct ddc_service *ddc_service,
 264                 struct dc_sink *sink)
 265 {
 266         uint8_t slave_address = HDMI_SCDC_ADDRESS;
 267         uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI;
 268
 269         link_query_ddc_data(ddc_service, slave_address, &offset,
 270                         sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte,
 271                         sizeof(sink->scdc_caps.manufacturer_OUI.byte));
 272
 273         offset = HDMI_SCDC_DEVICE_ID;
 274
 275         link_query_ddc_data(ddc_service, slave_address, &offset,
 276                         sizeof(offset), &(sink->scdc_caps.device_id.byte),
 277                         sizeof(sink->scdc_caps.device_id.byte));
 278 }
 279
 280 static bool i2c_read(
 281         struct ddc_service *ddc,
 282         uint32_t address,
 283         uint8_t *buffer,
 284         uint32_t len)
 285 {
 286         uint8_t offs_data = 0;
 287         struct i2c_payload payloads[2] = {
 288                 {
 289                 .write = true,
 290                 .address = address,
 291                 .length = 1,
 292                 .data = &offs_data },
 293                 {
 294                 .write = false,
 295                 .address = address,
 296                 .length = len,
 297                 .data = buffer } };
 298
 299         struct i2c_command command = {
 300                 .payloads = payloads,
 301                 .number_of_payloads = 2,
 302                 .engine = DDC_I2C_COMMAND_ENGINE,
 303                 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
 304
 305         return dm_helpers_submit_i2c(
 306                         ddc->ctx,
 307                         ddc->link,
 308                         &command);
 309 }
 310
 311 enum {
 312         DP_SINK_CAP_SIZE =
 313                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
 314 };
 315
 316 static void query_dp_dual_mode_adaptor(
 317         struct ddc_service *ddc,
 318         struct display_sink_capability *sink_cap)
 319 {
 320         uint8_t i;
 321         bool is_valid_hdmi_signature;
 322         enum display_dongle_type *dongle = &sink_cap->dongle_type;
 323         uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
 324         bool is_type2_dongle = false;
 325         int retry_count = 2;
 326         struct dp_hdmi_dongle_signature_data *dongle_signature;
 327         struct dc_link *link = ddc->link;
 328
 329         /* Assume we have no valid DP passive dongle connected */
 330         *dongle = DISPLAY_DONGLE_NONE;
 331         sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
 332
 333         /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
 334         if (!i2c_read(
 335                 ddc,
 336                 DP_HDMI_DONGLE_ADDRESS,
 337                 type2_dongle_buf,
 338                 sizeof(type2_dongle_buf))) {
 339                 /* Passive HDMI dongles can sometimes fail here without retrying*/
 340                 while (retry_count > 0) {
 341                         if (i2c_read(ddc,
 342                                 DP_HDMI_DONGLE_ADDRESS,
 343                                 type2_dongle_buf,
 344                                 sizeof(type2_dongle_buf)))
 345                                 break;
 346                         retry_count--;
 347                 }
 348                 if (retry_count == 0) {
 349                         *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
 350                         sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
 351
 352                         CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
 353                                         "DP-DVI passive dongle %dMhz: ",
 354                                         DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
 355                         return;
 356                 }
 357         }
 358
 359         /* Check if Type 2 dongle.*/
 360         if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
 361                 is_type2_dongle = true;
 362
 363         dongle_signature =
 364                 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
 365
 366         is_valid_hdmi_signature = true;
 367
 368         /* Check EOT */
 369         if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
 370                 is_valid_hdmi_signature = false;
 371         }
 372
 373         /* Check signature */
 374         for (i = 0; i < sizeof(dongle_signature->id); ++i) {
 375                 /* If its not the right signature,
 376                  * skip mismatch in subversion byte.*/
 377                 if (dongle_signature->id[i] !=
 378                         dp_hdmi_dongle_signature_str[i] && i != 3) {
 379
 380                         if (is_type2_dongle) {
 381                                 is_valid_hdmi_signature = false;
 382                                 break;
 383                         }
 384
 385                 }
 386         }
 387
 388         if (is_type2_dongle) {
 389                 uint32_t max_tmds_clk =
 390                         type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
 391
 392                 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
 393
 394                 if (0 == max_tmds_clk ||
 395                                 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
 396                                 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
 397                         *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
 398
 399                         CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 400                                         sizeof(type2_dongle_buf),
 401                                         "DP-DVI passive dongle %dMhz: ",
 402                                         DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
 403                 } else {
 404                         if (is_valid_hdmi_signature == true) {
 405                                 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
 406
 407                                 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 408                                                 sizeof(type2_dongle_buf),
 409                                                 "Type 2 DP-HDMI passive dongle %dMhz: ",
 410                                                 max_tmds_clk);
 411                         } else {
 412                                 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
 413
 414                                 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 415                                                 sizeof(type2_dongle_buf),
 416                                                 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
 417                                                 max_tmds_clk);
 418
 419                         }
 420
 421                         /* Multiply by 1000 to convert to kHz. */
 422                         sink_cap->max_hdmi_pixel_clock =
 423                                 max_tmds_clk * 1000;
 424                 }
 425                 sink_cap->is_dongle_type_one = false;
 426
 427         } else {
 428                 if (is_valid_hdmi_signature == true) {
 429                         *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
 430
 431                         CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 432                                         sizeof(type2_dongle_buf),
 433                                         "Type 1 DP-HDMI passive dongle %dMhz: ",
 434                                         sink_cap->max_hdmi_pixel_clock / 1000);
 435                 } else {
 436                         *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
 437
 438                         CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 439                                         sizeof(type2_dongle_buf),
 440                                         "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
 441                                         sink_cap->max_hdmi_pixel_clock / 1000);
 442                 }
 443                 sink_cap->is_dongle_type_one = true;
 444         }
 445
 446         return;
 447 }
 448
 449 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 450                                                     struct display_sink_capability *sink_cap,
 451                                                     struct audio_support *audio_support)
 452 {
 453         query_dp_dual_mode_adaptor(ddc, sink_cap);
 454
 455         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 456                                                         audio_support);
 457 }
 458
 459 static void link_disconnect_sink(struct dc_link *link)
 460 {
 461         if (link->local_sink) {
 462                 dc_sink_release(link->local_sink);
 463                 link->local_sink = NULL;
 464         }
 465
 466         link->dpcd_sink_count = 0;
 467         //link->dpcd_caps.dpcd_rev.raw = 0;
 468 }
 469
 470 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 471 {
 472         dc_sink_release(link->local_sink);
 473         link->local_sink = prev_sink;
 474 }
 475
 476 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 477 {
 478         struct hdcp_protection_message msg22;
 479         struct hdcp_protection_message msg14;
 480
 481         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 482         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 483         memset(link->hdcp_caps.rx_caps.raw, 0,
 484                 sizeof(link->hdcp_caps.rx_caps.raw));
 485
 486         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 487                         link->ddc->transaction_type ==
 488                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 489                         link->connector_signal == SIGNAL_TYPE_EDP) {
 490                 msg22.data = link->hdcp_caps.rx_caps.raw;
 491                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 492                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 493         } else {
 494                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 495                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 496                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 497         }
 498         msg22.version = HDCP_VERSION_22;
 499         msg22.link = HDCP_LINK_PRIMARY;
 500         msg22.max_retries = 5;
 501         dc_process_hdcp_msg(signal, link, &msg22);
 502
 503         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 504                 msg14.data = &link->hdcp_caps.bcaps.raw;
 505                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 506                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 507                 msg14.version = HDCP_VERSION_14;
 508                 msg14.link = HDCP_LINK_PRIMARY;
 509                 msg14.max_retries = 5;
 510
 511                 dc_process_hdcp_msg(signal, link, &msg14);
 512         }
 513
 514 }
 515 static void read_current_link_settings_on_detect(struct dc_link *link)
 516 {
 517         union lane_count_set lane_count_set = {0};
 518         uint8_t link_bw_set;
 519         uint8_t link_rate_set;
 520         uint32_t read_dpcd_retry_cnt = 10;
 521         enum dc_status status = DC_ERROR_UNEXPECTED;
 522         int i;
 523         union max_down_spread max_down_spread = {0};
 524
 525         // Read DPCD 00101h to find out the number of lanes currently set
 526         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 527                 status = core_link_read_dpcd(link,
 528                                              DP_LANE_COUNT_SET,
 529                                              &lane_count_set.raw,
 530                                              sizeof(lane_count_set));
 531                 /* First DPCD read after VDD ON can fail if the particular board
 532                  * does not have HPD pin wired correctly. So if DPCD read fails,
 533                  * which it should never happen, retry a few times. Target worst
 534                  * case scenario of 80 ms.
 535                  */
 536                 if (status == DC_OK) {
 537                         link->cur_link_settings.lane_count =
 538                                         lane_count_set.bits.LANE_COUNT_SET;
 539                         break;
 540                 }
 541
 542                 msleep(8);
 543         }
 544
 545         // Read DPCD 00100h to find if standard link rates are set
 546         core_link_read_dpcd(link, DP_LINK_BW_SET,
 547                             &link_bw_set, sizeof(link_bw_set));
 548
 549         if (link_bw_set == 0) {
 550                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 551                         /* If standard link rates are not being used,
 552                          * Read DPCD 00115h to find the edp link rate set used
 553                          */
 554                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 555                                             &link_rate_set, sizeof(link_rate_set));
 556
 557                         // edp_supported_link_rates_count = 0 for DP
 558                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 559                                 link->cur_link_settings.link_rate =
 560                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 561                                 link->cur_link_settings.link_rate_set = link_rate_set;
 562                                 link->cur_link_settings.use_link_rate_set = true;
 563                         }
 564                 } else {
 565                         // Link Rate not found. Seamless boot may not work.
 566                         ASSERT(false);
 567                 }
 568         } else {
 569                 link->cur_link_settings.link_rate = link_bw_set;
 570                 link->cur_link_settings.use_link_rate_set = false;
 571         }
 572         // Read DPCD 00003h to find the max down spread.
 573         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 574                             &max_down_spread.raw, sizeof(max_down_spread));
 575         link->cur_link_settings.link_spread =
 576                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 577                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 578 }
 579
 580 static bool detect_dp(struct dc_link *link,
 581                       struct display_sink_capability *sink_caps,
 582                       enum dc_detect_reason reason)
 583 {
 584         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 585
 586         sink_caps->signal = link_detect_sink_signal_type(link, reason);
 587         sink_caps->transaction_type =
 588                 get_ddc_transaction_type(sink_caps->signal);
 589
 590         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 591                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 592                 if (!detect_dp_sink_caps(link))
 593                         return false;
 594
 595                 if (is_dp_branch_device(link))
 596                         /* DP SST branch */
 597                         link->type = dc_connection_sst_branch;
 598         } else {
 599                 if (link->dc->debug.disable_dp_plus_plus_wa &&
 600                                 link->link_enc->features.flags.bits.IS_UHBR20_CAPABLE)
 601                         return false;
 602
 603                 /* DP passive dongles */
 604                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 605                                                                 sink_caps,
 606                                                                 audio_support);
 607                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 608                 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
 609                 link->dpcd_caps.dpcd_rev.raw = 0;
 610         }
 611
 612         return true;
 613 }
 614
 615 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 616 {
 617         if (old_edid->length != new_edid->length)
 618                 return false;
 619
 620         if (new_edid->length == 0)
 621                 return false;
 622
 623         return (memcmp(old_edid->raw_edid,
 624                        new_edid->raw_edid, new_edid->length) == 0);
 625 }
 626
 627 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 628 {
 629
 630         /**
 631          * something is terribly wrong if time out is > 200ms. (5Hz)
 632          * 500 microseconds * 400 tries us 200 ms
 633          **/
 634         unsigned int sleep_time_in_microseconds = 500;
 635         unsigned int tries_allowed = 400;
 636         bool is_in_alt_mode;
 637         unsigned long long enter_timestamp;
 638         unsigned long long finish_timestamp;
 639         unsigned long long time_taken_in_ns;
 640         int tries_taken;
 641
 642         DC_LOGGER_INIT(link->ctx->logger);
 643
 644         /**
 645          * this function will only exist if we are on dcn21 (is_in_alt_mode is a
 646          *  function pointer, so checking to see if it is equal to 0 is the same
 647          *  as checking to see if it is null
 648          **/
 649         if (!link->link_enc->funcs->is_in_alt_mode)
 650                 return true;
 651
 652         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 653         DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 654
 655         if (is_in_alt_mode)
 656                 return true;
 657
 658         enter_timestamp = dm_get_timestamp(link->ctx);
 659
 660         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 661                 udelay(sleep_time_in_microseconds);
 662                 /* ask the link if alt mode is enabled, if so return ok */
 663                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 664                         finish_timestamp = dm_get_timestamp(link->ctx);
 665                         time_taken_in_ns =
 666                                 dm_get_elapse_time_in_ns(link->ctx,
 667                                                          finish_timestamp,
 668                                                          enter_timestamp);
 669                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 670                                        div_u64(time_taken_in_ns, 1000000));
 671                         return true;
 672                 }
 673         }
 674         finish_timestamp = dm_get_timestamp(link->ctx);
 675         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 676                                                     enter_timestamp);
 677         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 678                         div_u64(time_taken_in_ns, 1000000));
 679         return false;
 680 }
 681
 682 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 683 {
 684         /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
 685          * reports DSC support.
 686          */
 687         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 688                         link->type == dc_connection_mst_branch &&
 689                         link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 690                         link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
 691                         link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 692                         !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
 693                 link->wa_flags.dpia_mst_dsc_always_on = true;
 694 }
 695
 696 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 697 {
 698         /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
 699         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 700                 link->wa_flags.dpia_mst_dsc_always_on = false;
 701 }
 702
 703 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
 704 {
 705         DC_LOGGER_INIT(link->ctx->logger);
 706
 707         LINK_INFO("link=%d, mst branch is now Connected\n",
 708                   link->link_index);
 709
 710         link->type = dc_connection_mst_branch;
 711         apply_dpia_mst_dsc_always_on_wa(link);
 712
 713         dm_helpers_dp_update_branch_info(link->ctx, link);
 714         if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
 715                         link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
 716                 link_disconnect_sink(link);
 717         } else {
 718                 link->type = dc_connection_sst_branch;
 719         }
 720
 721         return link->type == dc_connection_mst_branch;
 722 }
 723
 724 bool link_reset_cur_dp_mst_topology(struct dc_link *link)
 725 {
 726         DC_LOGGER_INIT(link->ctx->logger);
 727
 728         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 729                   link->link_index);
 730
 731         revert_dpia_mst_dsc_always_on_wa(link);
 732         return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 733 }
 734
 735 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
 736                 enum dc_detect_reason reason)
 737 {
 738         int i;
 739         bool can_apply_seamless_boot = false;
 740
 741         for (i = 0; i < dc->current_state->stream_count; i++) {
 742                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
 743                         can_apply_seamless_boot = true;
 744                         break;
 745                 }
 746         }
 747
 748         return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
 749 }
 750
 751 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 752 {
 753         dc_z10_restore(dc);
 754         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
 755 }
 756
 757 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 758 {
 759         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 760 }
 761
 762 static void verify_link_capability_destructive(struct dc_link *link,
 763                 struct dc_sink *sink,
 764                 enum dc_detect_reason reason)
 765 {
 766         bool should_prepare_phy_clocks =
 767                         should_prepare_phy_clocks_for_link_verification(link->dc, reason);
 768
 769         if (should_prepare_phy_clocks)
 770                 prepare_phy_clocks_for_destructive_link_verification(link->dc);
 771
 772         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 773                 struct dc_link_settings known_limit_link_setting =
 774                                 dp_get_max_link_cap(link);
 775                 link_set_all_streams_dpms_off_for_link(link);
 776                 dp_verify_link_cap_with_retries(
 777                                 link, &known_limit_link_setting,
 778                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 779         } else {
 780                 ASSERT(0);
 781         }
 782
 783         if (should_prepare_phy_clocks)
 784                 restore_phy_clocks_for_destructive_link_verification(link->dc);
 785 }
 786
 787 static void verify_link_capability_non_destructive(struct dc_link *link)
 788 {
 789         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 790                 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
 791                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 792                         /* TODO - should we check link encoder's max link caps here?
 793                          * How do we know which link encoder to check from?
 794                          */
 795                         link->verified_link_cap = link->reported_link_cap;
 796                 else
 797                         link->verified_link_cap = dp_get_max_link_cap(link);
 798         }
 799 }
 800
 801 static bool should_verify_link_capability_destructively(struct dc_link *link,
 802                 enum dc_detect_reason reason)
 803 {
 804         bool destrictive = false;
 805         struct dc_link_settings max_link_cap;
 806         bool is_link_enc_unavailable = link->link_enc &&
 807                         link->dc->res_pool->funcs->link_encs_assign &&
 808                         !link_enc_cfg_is_link_enc_avail(
 809                                         link->ctx->dc,
 810                                         link->link_enc->preferred_engine,
 811                                         link);
 812
 813         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 814                 max_link_cap = dp_get_max_link_cap(link);
 815                 destrictive = true;
 816
 817                 if (link->dc->debug.skip_detection_link_training ||
 818                                 dc_is_embedded_signal(link->local_sink->sink_signal) ||
 819                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
 820                         destrictive = false;
 821                 } else if (link_dp_get_encoding_format(&max_link_cap) ==
 822                                 DP_8b_10b_ENCODING) {
 823                         if (link->dpcd_caps.is_mst_capable ||
 824                                         is_link_enc_unavailable) {
 825                                 destrictive = false;
 826                         }
 827                 }
 828         }
 829
 830         return destrictive;
 831 }
 832
 833 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
 834                 enum dc_detect_reason reason)
 835 {
 836         if (should_verify_link_capability_destructively(link, reason))
 837                 verify_link_capability_destructive(link, sink, reason);
 838         else
 839                 verify_link_capability_non_destructive(link);
 840 }
 841
 842 /*
 843  * detect_link_and_local_sink() - Detect if a sink is attached to a given link
 844  *
 845  * link->local_sink is created or destroyed as needed.
 846  *
 847  * This does not create remote sinks.
 848  */
 849 static bool detect_link_and_local_sink(struct dc_link *link,
 850                                   enum dc_detect_reason reason)
 851 {
 852         struct dc_sink_init_data sink_init_data = { 0 };
 853         struct display_sink_capability sink_caps = { 0 };
 854         uint32_t i;
 855         bool converter_disable_audio = false;
 856         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 857         bool same_edid = false;
 858         enum dc_edid_status edid_status;
 859         struct dc_context *dc_ctx = link->ctx;
 860         struct dc *dc = dc_ctx->dc;
 861         struct dc_sink *sink = NULL;
 862         struct dc_sink *prev_sink = NULL;
 863         struct dpcd_caps prev_dpcd_caps;
 864         enum dc_connection_type new_connection_type = dc_connection_none;
 865         enum dc_connection_type pre_connection_type = link->type;
 866         const uint32_t post_oui_delay = 30; // 30ms
 867
 868         DC_LOGGER_INIT(link->ctx->logger);
 869
 870         if (dc_is_virtual_signal(link->connector_signal))
 871                 return false;
 872
 873         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
 874                 link->connector_signal == SIGNAL_TYPE_EDP) &&
 875                 (!link->dc->config.allow_edp_hotplug_detection)) &&
 876                 link->local_sink) {
 877                 // need to re-write OUI and brightness in resume case
 878                 if (link->connector_signal == SIGNAL_TYPE_EDP &&
 879                         (link->dpcd_sink_ext_caps.bits.oled == 1)) {
 880                         dpcd_set_source_specific_data(link);
 881                         msleep(post_oui_delay);
 882                         set_cached_brightness_aux(link);
 883                 }
 884
 885                 return true;
 886         }
 887
 888         if (!link_detect_connection_type(link, &new_connection_type)) {
 889                 BREAK_TO_DEBUGGER();
 890                 return false;
 891         }
 892
 893         prev_sink = link->local_sink;
 894         if (prev_sink) {
 895                 dc_sink_retain(prev_sink);
 896                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 897         }
 898
 899         link_disconnect_sink(link);
 900         if (new_connection_type != dc_connection_none) {
 901                 link->type = new_connection_type;
 902                 link->link_state_valid = false;
 903
 904                 /* From Disconnected-to-Connected. */
 905                 switch (link->connector_signal) {
 906                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 907                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 908                         if (aud_support->hdmi_audio_native)
 909                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 910                         else
 911                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 912                         break;
 913                 }
 914
 915                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 916                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 917                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 918                         break;
 919                 }
 920
 921                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 922                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 923                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 924                         break;
 925                 }
 926
 927                 case SIGNAL_TYPE_LVDS: {
 928                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 929                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 930                         break;
 931                 }
 932
 933                 case SIGNAL_TYPE_EDP: {
 934                         detect_edp_sink_caps(link);
 935                         read_current_link_settings_on_detect(link);
 936
 937                         /* Disable power sequence on MIPI panel + converter
 938                          */
 939                         if (dc->config.enable_mipi_converter_optimization &&
 940                                 dc_ctx->dce_version == DCN_VERSION_3_01 &&
 941                                 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
 942                                 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
 943                                         sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
 944                                 dc->config.edp_no_power_sequencing = true;
 945
 946                                 if (!link->dpcd_caps.set_power_state_capable_edp)
 947                                         link->wa_flags.dp_keep_receiver_powered = true;
 948                         }
 949
 950                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 951                         sink_caps.signal = SIGNAL_TYPE_EDP;
 952                         break;
 953                 }
 954
 955                 case SIGNAL_TYPE_DISPLAY_PORT: {
 956
 957                         /* wa HPD high coming too early*/
 958                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 959                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 960
 961                                 /* if alt mode times out, return false */
 962                                 if (!wait_for_entering_dp_alt_mode(link))
 963                                         return false;
 964                         }
 965
 966                         if (!detect_dp(link, &sink_caps, reason)) {
 967                                 link->type = pre_connection_type;
 968
 969                                 if (prev_sink)
 970                                         dc_sink_release(prev_sink);
 971                                 return false;
 972                         }
 973
 974                         /* Active SST downstream branch device unplug*/
 975                         if (link->type == dc_connection_sst_branch &&
 976                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 977                                 if (prev_sink)
 978                                         /* Downstream unplug */
 979                                         dc_sink_release(prev_sink);
 980                                 return true;
 981                         }
 982
 983                         /* disable audio for non DP to HDMI active sst converter */
 984                         if (link->type == dc_connection_sst_branch &&
 985                                         is_dp_active_dongle(link) &&
 986                                         (link->dpcd_caps.dongle_type !=
 987                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
 988                                 converter_disable_audio = true;
 989
 990                         /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
 991                         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 992                                         link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
 993                                 link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
 994                         break;
 995                 }
 996
 997                 default:
 998                         DC_ERROR("Invalid connector type! signal:%d\n",
 999                                  link->connector_signal);
1000                         if (prev_sink)
1001                                 dc_sink_release(prev_sink);
1002                         return false;
1003                 } /* switch() */
1004
1005                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1006                         link->dpcd_sink_count =
1007                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1008                 else
1009                         link->dpcd_sink_count = 1;
1010
1011                 set_ddc_transaction_type(link->ddc,
1012                                                      sink_caps.transaction_type);
1013
1014                 link->aux_mode =
1015                         link_is_in_aux_transaction_mode(link->ddc);
1016
1017                 sink_init_data.link = link;
1018                 sink_init_data.sink_signal = sink_caps.signal;
1019
1020                 sink = dc_sink_create(&sink_init_data);
1021                 if (!sink) {
1022                         DC_ERROR("Failed to create sink!\n");
1023                         if (prev_sink)
1024                                 dc_sink_release(prev_sink);
1025                         return false;
1026                 }
1027
1028                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1029                 sink->converter_disable_audio = converter_disable_audio;
1030
1031                 /* dc_sink_create returns a new reference */
1032                 link->local_sink = sink;
1033
1034                 edid_status = dm_helpers_read_local_edid(link->ctx,
1035                                                          link, sink);
1036
1037                 switch (edid_status) {
1038                 case EDID_BAD_CHECKSUM:
1039                         DC_LOG_ERROR("EDID checksum invalid.\n");
1040                         break;
1041                 case EDID_PARTIAL_VALID:
1042                         DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1043                         break;
1044                 case EDID_NO_RESPONSE:
1045                         DC_LOG_ERROR("No EDID read.\n");
1046                         /*
1047                          * Abort detection for non-DP connectors if we have
1048                          * no EDID
1049                          *
1050                          * DP needs to report as connected if HDP is high
1051                          * even if we have no EDID in order to go to
1052                          * fail-safe mode
1053                          */
1054                         if (dc_is_hdmi_signal(link->connector_signal) ||
1055                             dc_is_dvi_signal(link->connector_signal)) {
1056                                 if (prev_sink)
1057                                         dc_sink_release(prev_sink);
1058
1059                                 return false;
1060                         }
1061
1062                         if (link->type == dc_connection_sst_branch &&
1063                                         link->dpcd_caps.dongle_type ==
1064                                                 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1065                                         reason == DETECT_REASON_HPDRX) {
1066                                 /* Abort detection for DP-VGA adapters when EDID
1067                                  * can't be read and detection reason is VGA-side
1068                                  * hotplug
1069                                  */
1070                                 if (prev_sink)
1071                                         dc_sink_release(prev_sink);
1072                                 link_disconnect_sink(link);
1073
1074                                 return true;
1075                         }
1076
1077                         break;
1078                 default:
1079                         break;
1080                 }
1081
1082                 // Check if edid is the same
1083                 if ((prev_sink) &&
1084                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1085                         same_edid = is_same_edid(&prev_sink->dc_edid,
1086                                                  &sink->dc_edid);
1087
1088                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1089                         link->ctx->dc->debug.hdmi20_disable = true;
1090
1091                 if (dc_is_hdmi_signal(link->connector_signal))
1092                         read_scdc_caps(link->ddc, link->local_sink);
1093
1094                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1095                     sink_caps.transaction_type ==
1096                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1097                         /*
1098                          * TODO debug why certain monitors don't like
1099                          *  two link trainings
1100                          */
1101                         query_hdcp_capability(sink->sink_signal, link);
1102                 } else {
1103                         // If edid is the same, then discard new sink and revert back to original sink
1104                         if (same_edid) {
1105                                 link_disconnect_remap(prev_sink, link);
1106                                 sink = prev_sink;
1107                                 prev_sink = NULL;
1108                         }
1109                         query_hdcp_capability(sink->sink_signal, link);
1110                 }
1111
1112                 /* HDMI-DVI Dongle */
1113                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1114                     !sink->edid_caps.edid_hdmi)
1115                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1116
1117                 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1118                         dp_trace_init(link);
1119
1120                 /* Connectivity log: detection */
1121                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1122                         CONN_DATA_DETECT(link,
1123                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1124                                          DC_EDID_BLOCK_SIZE,
1125                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1126                 }
1127
1128                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1129                         "manufacturer_id = %X, "
1130                         "product_id = %X, "
1131                         "serial_number = %X, "
1132                         "manufacture_week = %d, "
1133                         "manufacture_year = %d, "
1134                         "display_name = %s, "
1135                         "speaker_flag = %d, "
1136                         "audio_mode_count = %d\n",
1137                         __func__,
1138                         sink->edid_caps.manufacturer_id,
1139                         sink->edid_caps.product_id,
1140                         sink->edid_caps.serial_number,
1141                         sink->edid_caps.manufacture_week,
1142                         sink->edid_caps.manufacture_year,
1143                         sink->edid_caps.display_name,
1144                         sink->edid_caps.speaker_flags,
1145                         sink->edid_caps.audio_mode_count);
1146
1147                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1148                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1149                                 "format_code = %d, "
1150                                 "channel_count = %d, "
1151                                 "sample_rate = %d, "
1152                                 "sample_size = %d\n",
1153                                 __func__,
1154                                 i,
1155                                 sink->edid_caps.audio_modes[i].format_code,
1156                                 sink->edid_caps.audio_modes[i].channel_count,
1157                                 sink->edid_caps.audio_modes[i].sample_rate,
1158                                 sink->edid_caps.audio_modes[i].sample_size);
1159                 }
1160
1161                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1162                         // Init dc_panel_config by HW config
1163                         if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)
1164                                 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);
1165                         // Pickup base DM settings
1166                         dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
1167                         // Override dc_panel_config if system has specific settings
1168                         dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
1169
1170                         //sink only can use supported link rate table, we are foreced to enable it
1171                         if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
1172                                 link->panel_config.ilr.optimize_edp_link_rate = true;
1173                         if (edp_is_ilr_optimization_enabled(link))
1174                                 link->reported_link_cap.link_rate = get_max_link_rate_from_ilr_table(link);
1175                 }
1176
1177         } else {
1178                 /* From Connected-to-Disconnected. */
1179                 link->type = dc_connection_none;
1180                 sink_caps.signal = SIGNAL_TYPE_NONE;
1181                 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps));
1182                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1183                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1184                  *  the dongle is still there and limits the number of modes we can emulate.
1185                  *  Clear dongle_max_pix_clk on disconnect to fix this
1186                  */
1187                 link->dongle_max_pix_clk = 0;
1188
1189                 dc_link_clear_dprx_states(link);
1190                 dp_trace_reset(link);
1191         }
1192
1193         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1194                   link->link_index, sink,
1195                   (sink_caps.signal ==
1196                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1197                   prev_sink, same_edid);
1198
1199         if (prev_sink)
1200                 dc_sink_release(prev_sink);
1201
1202         return true;
1203 }
1204
1205 /*
1206  * link_detect_connection_type() - Determine if there is a sink connected
1207  *
1208  * @type: Returned connection type
1209  * Does not detect downstream devices, such as MST sinks
1210  * or display connected through active dongles
1211  */
1212 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type)
1213 {
1214         uint32_t is_hpd_high = 0;
1215
1216         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
1217                 *type = dc_connection_single;
1218                 return true;
1219         }
1220
1221         if (link->connector_signal == SIGNAL_TYPE_EDP) {
1222                 /*in case it is not on*/
1223                 if (!link->dc->config.edp_no_power_sequencing)
1224                         link->dc->hwss.edp_power_control(link, true);
1225                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1226         }
1227
1228         /* Link may not have physical HPD pin. */
1229         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
1230                 if (link->is_hpd_pending || !dpia_query_hpd_status(link))
1231                         *type = dc_connection_none;
1232                 else
1233                         *type = dc_connection_single;
1234
1235                 return true;
1236         }
1237
1238
1239         if (!query_hpd_status(link, &is_hpd_high))
1240                 goto hpd_gpio_failure;
1241
1242         if (is_hpd_high) {
1243                 *type = dc_connection_single;
1244                 /* TODO: need to do the actual detection */
1245         } else {
1246                 *type = dc_connection_none;
1247                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1248                         /* eDP is not connected, power down it */
1249                         if (!link->dc->config.edp_no_power_sequencing)
1250                                 link->dc->hwss.edp_power_control(link, false);
1251                 }
1252         }
1253
1254         return true;
1255
1256 hpd_gpio_failure:
1257         return false;
1258 }
1259
1260 bool link_detect(struct dc_link *link, enum dc_detect_reason reason)
1261 {
1262         bool is_local_sink_detect_success;
1263         bool is_delegated_to_mst_top_mgr = false;
1264         enum dc_connection_type pre_link_type = link->type;
1265
1266         DC_LOGGER_INIT(link->ctx->logger);
1267
1268         is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1269
1270         if (is_local_sink_detect_success && link->local_sink)
1271                 verify_link_capability(link, link->local_sink, reason);
1272
1273         DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__,
1274                                 link->link_index, is_local_sink_detect_success, pre_link_type, link->type);
1275
1276         if (is_local_sink_detect_success && link->local_sink &&
1277                         dc_is_dp_signal(link->local_sink->sink_signal) &&
1278                         link->dpcd_caps.is_mst_capable)
1279                 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1280
1281         if (is_local_sink_detect_success &&
1282                         pre_link_type == dc_connection_mst_branch &&
1283                         link->type != dc_connection_mst_branch)
1284                 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link);
1285
1286         return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1287 }
1288
1289 void link_clear_dprx_states(struct dc_link *link)
1290 {
1291         memset(&link->dprx_states, 0, sizeof(link->dprx_states));
1292 }
1293
1294 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal)
1295 {
1296         bool ret = false;
1297
1298         switch (signal) {
1299         case SIGNAL_TYPE_DISPLAY_PORT:
1300         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1301                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
1302                 break;
1303         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1304         case SIGNAL_TYPE_DVI_DUAL_LINK:
1305         case SIGNAL_TYPE_HDMI_TYPE_A:
1306         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
1307          * we can poll for bksv but some displays have an issue with this. Since its so rare
1308          * for a display to not be 1.4 capable, this assumtion is ok
1309          */
1310                 ret = true;
1311                 break;
1312         default:
1313                 break;
1314         }
1315         return ret;
1316 }
1317
1318 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal)
1319 {
1320         bool ret = false;
1321
1322         switch (signal) {
1323         case SIGNAL_TYPE_DISPLAY_PORT:
1324         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1325                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
1326                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
1327                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
1328                 break;
1329         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1330         case SIGNAL_TYPE_DVI_DUAL_LINK:
1331         case SIGNAL_TYPE_HDMI_TYPE_A:
1332                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
1333                 break;
1334         default:
1335                 break;
1336         }
1337
1338         return ret;
1339 }
1340
1341 const struct dc_link_status *link_get_status(const struct dc_link *link)
1342 {
1343         return &link->link_status;
1344 }
1345
1346
1347 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
1348 {
1349         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1350                 BREAK_TO_DEBUGGER();
1351                 return false;
1352         }
1353
1354         dc_sink_retain(sink);
1355
1356         dc_link->remote_sinks[dc_link->sink_count] = sink;
1357         dc_link->sink_count++;
1358
1359         return true;
1360 }
1361
1362 struct dc_sink *link_add_remote_sink(
1363                 struct dc_link *link,
1364                 const uint8_t *edid,
1365                 int len,
1366                 struct dc_sink_init_data *init_data)
1367 {
1368         struct dc_sink *dc_sink;
1369         enum dc_edid_status edid_status;
1370
1371         if (len > DC_MAX_EDID_BUFFER_SIZE) {
1372                 dm_error("Max EDID buffer size breached!\n");
1373                 return NULL;
1374         }
1375
1376         if (!init_data) {
1377                 BREAK_TO_DEBUGGER();
1378                 return NULL;
1379         }
1380
1381         if (!init_data->link) {
1382                 BREAK_TO_DEBUGGER();
1383                 return NULL;
1384         }
1385
1386         dc_sink = dc_sink_create(init_data);
1387
1388         if (!dc_sink)
1389                 return NULL;
1390
1391         memmove(dc_sink->dc_edid.raw_edid, edid, len);
1392         dc_sink->dc_edid.length = len;
1393
1394         if (!link_add_remote_sink_helper(
1395                         link,
1396                         dc_sink))
1397                 goto fail_add_sink;
1398
1399         edid_status = dm_helpers_parse_edid_caps(
1400                         link,
1401                         &dc_sink->dc_edid,
1402                         &dc_sink->edid_caps);
1403
1404         /*
1405          * Treat device as no EDID device if EDID
1406          * parsing fails
1407          */
1408         if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) {
1409                 dc_sink->dc_edid.length = 0;
1410                 dm_error("Bad EDID, status%d!\n", edid_status);
1411         }
1412
1413         return dc_sink;
1414
1415 fail_add_sink:
1416         dc_sink_release(dc_sink);
1417         return NULL;
1418 }
1419
1420 void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
1421 {
1422         int i;
1423
1424         if (!link->sink_count) {
1425                 BREAK_TO_DEBUGGER();
1426                 return;
1427         }
1428
1429         for (i = 0; i < link->sink_count; i++) {
1430                 if (link->remote_sinks[i] == sink) {
1431                         dc_sink_release(sink);
1432                         link->remote_sinks[i] = NULL;
1433
1434                         /* shrink array to remove empty place */
1435                         while (i < link->sink_count - 1) {
1436                                 link->remote_sinks[i] = link->remote_sinks[i+1];
1437                                 i++;
1438                         }
1439                         link->remote_sinks[i] = NULL;
1440                         link->sink_count--;
1441                         return;
1442                 }
1443         }
1444 }