drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/errno.h>
  25 #include "hwmgr.h"
  26 #include "hardwaremanager.h"
  27 #include "power_state.h"
  28
  29
  30 #define TEMP_RANGE_MIN (0)
  31 #define TEMP_RANGE_MAX (80 * 1000)
  32
  33 #define PHM_FUNC_CHECK(hw) \
  34         do {                                                    \
  35                 if ((hw) == NULL || (hw)->hwmgr_func == NULL)   \
  36                         return -EINVAL;                         \
  37         } while (0)
  38
  39 int phm_setup_asic(struct pp_hwmgr *hwmgr)
  40 {
  41         PHM_FUNC_CHECK(hwmgr);
  42
  43         if (NULL != hwmgr->hwmgr_func->asic_setup)
  44                 return hwmgr->hwmgr_func->asic_setup(hwmgr);
  45
  46         return 0;
  47 }
  48
  49 int phm_power_down_asic(struct pp_hwmgr *hwmgr)
  50 {
  51         PHM_FUNC_CHECK(hwmgr);
  52
  53         if (NULL != hwmgr->hwmgr_func->power_off_asic)
  54                 return hwmgr->hwmgr_func->power_off_asic(hwmgr);
  55
  56         return 0;
  57 }
  58
  59 int phm_set_power_state(struct pp_hwmgr *hwmgr,
  60                     const struct pp_hw_power_state *pcurrent_state,
  61                     const struct pp_hw_power_state *pnew_power_state)
  62 {
  63         struct phm_set_power_state_input states;
  64
  65         PHM_FUNC_CHECK(hwmgr);
  66
  67         states.pcurrent_state = pcurrent_state;
  68         states.pnew_state = pnew_power_state;
  69
  70         if (NULL != hwmgr->hwmgr_func->power_state_set)
  71                 return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
  72
  73         return 0;
  74 }
  75
  76 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
  77 {
  78         struct amdgpu_device *adev = NULL;
  79         int ret = -EINVAL;;
  80         PHM_FUNC_CHECK(hwmgr);
  81         adev = hwmgr->adev;
  82
  83         /* Skip for suspend/resume case */
  84         if (smum_is_dpm_running(hwmgr) && !amdgpu_passthrough(adev)
  85                 && adev->in_suspend) {
  86                 pr_info("dpm has been enabled\n");
  87                 return 0;
  88         }
  89
  90         if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
  91                 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
  92
  93         return ret;
  94 }
  95
  96 int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
  97 {
  98         int ret = -EINVAL;
  99
 100         PHM_FUNC_CHECK(hwmgr);
 101
 102         if (!smum_is_dpm_running(hwmgr)) {
 103                 pr_info("dpm has been disabled\n");
 104                 return 0;
 105         }
 106
 107         if (hwmgr->hwmgr_func->dynamic_state_management_disable)
 108                 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
 109
 110         return ret;
 111 }
 112
 113 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
 114 {
 115         int ret = 0;
 116
 117         PHM_FUNC_CHECK(hwmgr);
 118
 119         if (hwmgr->hwmgr_func->force_dpm_level != NULL)
 120                 ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
 121
 122         return ret;
 123 }
 124
 125 int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 126                                    struct pp_power_state *adjusted_ps,
 127                              const struct pp_power_state *current_ps)
 128 {
 129         PHM_FUNC_CHECK(hwmgr);
 130
 131         if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
 132                 return hwmgr->hwmgr_func->apply_state_adjust_rules(
 133                                                                         hwmgr,
 134                                                                  adjusted_ps,
 135                                                                  current_ps);
 136         return 0;
 137 }
 138
 139 int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr)
 140 {
 141         PHM_FUNC_CHECK(hwmgr);
 142
 143         if (hwmgr->hwmgr_func->apply_clocks_adjust_rules != NULL)
 144                 return hwmgr->hwmgr_func->apply_clocks_adjust_rules(hwmgr);
 145         return 0;
 146 }
 147
 148 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
 149 {
 150         PHM_FUNC_CHECK(hwmgr);
 151
 152         if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
 153                 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
 154         return 0;
 155 }
 156
 157 int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 158 {
 159         PHM_FUNC_CHECK(hwmgr);
 160
 161         if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
 162                 return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
 163
 164         return 0;
 165 }
 166
 167 int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 168 {
 169         PHM_FUNC_CHECK(hwmgr);
 170
 171         if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
 172                 return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
 173
 174         return 0;
 175 }
 176
 177 int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr)
 178 {
 179         PHM_FUNC_CHECK(hwmgr);
 180
 181         if (NULL != hwmgr->hwmgr_func->pre_display_config_changed)
 182                 hwmgr->hwmgr_func->pre_display_config_changed(hwmgr);
 183
 184         return 0;
 185
 186 }
 187
 188 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
 189 {
 190         PHM_FUNC_CHECK(hwmgr);
 191
 192         if (NULL != hwmgr->hwmgr_func->display_config_changed)
 193                 hwmgr->hwmgr_func->display_config_changed(hwmgr);
 194
 195         return 0;
 196 }
 197
 198 int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 199 {
 200         PHM_FUNC_CHECK(hwmgr);
 201
 202         if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
 203                         hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
 204
 205         return 0;
 206 }
 207
 208 int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 209 {
 210         PHM_FUNC_CHECK(hwmgr);
 211
 212         if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
 213                 return -EINVAL;
 214
 215         return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
 216 }
 217
 218 int phm_register_irq_handlers(struct pp_hwmgr *hwmgr)
 219 {
 220         PHM_FUNC_CHECK(hwmgr);
 221
 222         if (hwmgr->hwmgr_func->register_irq_handlers != NULL)
 223                 return hwmgr->hwmgr_func->register_irq_handlers(hwmgr);
 224
 225         return 0;
 226 }
 227
 228 /**
 229 * Initializes the thermal controller subsystem.
 230 *
 231 * @param    pHwMgr  the address of the powerplay hardware manager.
 232 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
 233 */
 234 int phm_start_thermal_controller(struct pp_hwmgr *hwmgr)
 235 {
 236         int ret = 0;
 237         struct PP_TemperatureRange range = {TEMP_RANGE_MIN, TEMP_RANGE_MAX};
 238         struct amdgpu_device *adev = hwmgr->adev;
 239
 240         if (hwmgr->hwmgr_func->get_thermal_temperature_range)
 241                 hwmgr->hwmgr_func->get_thermal_temperature_range(
 242                                 hwmgr, &range);
 243
 244         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 245                         PHM_PlatformCaps_ThermalController)
 246                         && hwmgr->hwmgr_func->start_thermal_controller != NULL)
 247                 ret = hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
 248
 249         adev->pm.dpm.thermal.min_temp = range.min;
 250         adev->pm.dpm.thermal.max_temp = range.max;
 251
 252         return ret;
 253 }
 254
 255
 256 bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
 257 {
 258         PHM_FUNC_CHECK(hwmgr);
 259
 260         if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
 261                 return false;
 262
 263         return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
 264 }
 265
 266
 267 int phm_check_states_equal(struct pp_hwmgr *hwmgr,
 268                                  const struct pp_hw_power_state *pstate1,
 269                                  const struct pp_hw_power_state *pstate2,
 270                                  bool *equal)
 271 {
 272         PHM_FUNC_CHECK(hwmgr);
 273
 274         if (hwmgr->hwmgr_func->check_states_equal == NULL)
 275                 return -EINVAL;
 276
 277         return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
 278 }
 279
 280 int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 281                     const struct amd_pp_display_configuration *display_config)
 282 {
 283         int index = 0;
 284         int number_of_active_display = 0;
 285
 286         PHM_FUNC_CHECK(hwmgr);
 287
 288         if (display_config == NULL)
 289                 return -EINVAL;
 290
 291         if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
 292                 hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
 293
 294         for (index = 0; index < display_config->num_path_including_non_display; index++) {
 295                 if (display_config->displays[index].controller_id != 0)
 296                         number_of_active_display++;
 297         }
 298
 299         if (NULL != hwmgr->hwmgr_func->set_active_display_count)
 300                 hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display);
 301
 302         if (hwmgr->hwmgr_func->store_cc6_data == NULL)
 303                 return -EINVAL;
 304
 305         /* TODO: pass other display configuration in the future */
 306
 307         if (hwmgr->hwmgr_func->store_cc6_data)
 308                 hwmgr->hwmgr_func->store_cc6_data(hwmgr,
 309                                 display_config->cpu_pstate_separation_time,
 310                                 display_config->cpu_cc6_disable,
 311                                 display_config->cpu_pstate_disable,
 312                                 display_config->nb_pstate_switch_disable);
 313
 314         return 0;
 315 }
 316
 317 int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
 318                 struct amd_pp_simple_clock_info *info)
 319 {
 320         PHM_FUNC_CHECK(hwmgr);
 321
 322         if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
 323                 return -EINVAL;
 324         return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
 325 }
 326
 327 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 328 {
 329         PHM_FUNC_CHECK(hwmgr);
 330
 331         if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
 332                 return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
 333
 334         return 0;
 335 }
 336
 337
 338 int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
 339                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
 340                                 PHM_PerformanceLevel *level)
 341 {
 342         PHM_FUNC_CHECK(hwmgr);
 343         if (hwmgr->hwmgr_func->get_performance_level == NULL)
 344                 return -EINVAL;
 345
 346         return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
 347
 348
 349 }
 350
 351
 352 /**
 353 * Gets Clock Info.
 354 *
 355 * @param    pHwMgr  the address of the powerplay hardware manager.
 356 * @param    pPowerState the address of the Power State structure.
 357 * @param    pClockInfo the address of PP_ClockInfo structure where the result will be returned.
 358 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
 359 */
 360 int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
 361                         PHM_PerformanceLevelDesignation designation)
 362 {
 363         int result;
 364         PHM_PerformanceLevel performance_level = {0};
 365
 366         PHM_FUNC_CHECK(hwmgr);
 367
 368         PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
 369         PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
 370
 371         result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
 372
 373         PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
 374
 375
 376         pclock_info->min_mem_clk = performance_level.memory_clock;
 377         pclock_info->min_eng_clk = performance_level.coreClock;
 378         pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
 379
 380
 381         result = phm_get_performance_level(hwmgr, state, designation,
 382                                         (hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
 383
 384         PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
 385
 386         pclock_info->max_mem_clk = performance_level.memory_clock;
 387         pclock_info->max_eng_clk = performance_level.coreClock;
 388         pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
 389
 390         return 0;
 391 }
 392
 393 int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
 394 {
 395         PHM_FUNC_CHECK(hwmgr);
 396
 397         if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
 398                 return -EINVAL;
 399
 400         return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
 401
 402 }
 403
 404 int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
 405 {
 406         PHM_FUNC_CHECK(hwmgr);
 407
 408         if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
 409                 return -EINVAL;
 410
 411         return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
 412
 413 }
 414
 415 int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
 416                 enum amd_pp_clock_type type,
 417                 struct pp_clock_levels_with_latency *clocks)
 418 {
 419         PHM_FUNC_CHECK(hwmgr);
 420
 421         if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL)
 422                 return -EINVAL;
 423
 424         return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks);
 425
 426 }
 427
 428 int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 429                 enum amd_pp_clock_type type,
 430                 struct pp_clock_levels_with_voltage *clocks)
 431 {
 432         PHM_FUNC_CHECK(hwmgr);
 433
 434         if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL)
 435                 return -EINVAL;
 436
 437         return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks);
 438
 439 }
 440
 441 int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
 442                                         void *clock_ranges)
 443 {
 444         PHM_FUNC_CHECK(hwmgr);
 445
 446         if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges)
 447                 return -EINVAL;
 448
 449         return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
 450                                                                 clock_ranges);
 451 }
 452
 453 int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
 454                 struct pp_display_clock_request *clock)
 455 {
 456         PHM_FUNC_CHECK(hwmgr);
 457
 458         if (!hwmgr->hwmgr_func->display_clock_voltage_request)
 459                 return -EINVAL;
 460
 461         return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);
 462 }
 463
 464 int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
 465 {
 466         PHM_FUNC_CHECK(hwmgr);
 467
 468         if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
 469                 return -EINVAL;
 470
 471         return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
 472 }
 473
 474 int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr)
 475 {
 476         PHM_FUNC_CHECK(hwmgr);
 477
 478         if (hwmgr->hwmgr_func->disable_smc_firmware_ctf == NULL)
 479                 return -EINVAL;
 480
 481         return hwmgr->hwmgr_func->disable_smc_firmware_ctf(hwmgr);
 482 }