2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
30 #include "amd_powerplay.h"
31 #include "hardwaremanager.h"
32 #include "ppatomfwctrl.h"
33 #include "atomfirmware.h"
34 #include "cgs_common.h"
35 #include "vega10_powertune.h"
37 #include "smu9_driver_if.h"
38 #include "vega10_inc.h"
39 #include "soc15_common.h"
40 #include "pppcielanes.h"
41 #include "vega10_hwmgr.h"
42 #include "vega10_smumgr.h"
43 #include "vega10_processpptables.h"
44 #include "vega10_pptable.h"
45 #include "vega10_thermal.h"
47 #include "amd_pcie_helpers.h"
48 #include "ppinterrupt.h"
49 #include "pp_overdriver.h"
50 #include "pp_thermal.h"
51 #include "vega10_baco.h"
53 #include "smuio/smuio_9_0_offset.h"
54 #include "smuio/smuio_9_0_sh_mask.h"
56 #define HBM_MEMORY_CHANNEL_WIDTH 128
58 static const uint32_t channel_number
[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
60 #define mmDF_CS_AON0_DramBaseAddress0 0x0044
61 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
63 //DF_CS_AON0_DramBaseAddress0
64 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
65 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
66 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
67 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
68 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
69 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
70 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
71 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
72 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
73 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
90 static const ULONG PhwVega10_Magic
= (ULONG
)(PHM_VIslands_Magic
);
92 struct vega10_power_state
*cast_phw_vega10_power_state(
93 struct pp_hw_power_state
*hw_ps
)
95 PP_ASSERT_WITH_CODE((PhwVega10_Magic
== hw_ps
->magic
),
96 "Invalid Powerstate Type!",
99 return (struct vega10_power_state
*)hw_ps
;
102 const struct vega10_power_state
*cast_const_phw_vega10_power_state(
103 const struct pp_hw_power_state
*hw_ps
)
105 PP_ASSERT_WITH_CODE((PhwVega10_Magic
== hw_ps
->magic
),
106 "Invalid Powerstate Type!",
109 return (const struct vega10_power_state
*)hw_ps
;
112 static void vega10_set_default_registry_data(struct pp_hwmgr
*hwmgr
)
114 struct vega10_hwmgr
*data
= hwmgr
->backend
;
116 data
->registry_data
.sclk_dpm_key_disabled
=
117 hwmgr
->feature_mask
& PP_SCLK_DPM_MASK
? false : true;
118 data
->registry_data
.socclk_dpm_key_disabled
=
119 hwmgr
->feature_mask
& PP_SOCCLK_DPM_MASK
? false : true;
120 data
->registry_data
.mclk_dpm_key_disabled
=
121 hwmgr
->feature_mask
& PP_MCLK_DPM_MASK
? false : true;
122 data
->registry_data
.pcie_dpm_key_disabled
=
123 hwmgr
->feature_mask
& PP_PCIE_DPM_MASK
? false : true;
125 data
->registry_data
.dcefclk_dpm_key_disabled
=
126 hwmgr
->feature_mask
& PP_DCEFCLK_DPM_MASK
? false : true;
128 if (hwmgr
->feature_mask
& PP_POWER_CONTAINMENT_MASK
) {
129 data
->registry_data
.power_containment_support
= 1;
130 data
->registry_data
.enable_pkg_pwr_tracking_feature
= 1;
131 data
->registry_data
.enable_tdc_limit_feature
= 1;
134 data
->registry_data
.clock_stretcher_support
=
135 hwmgr
->feature_mask
& PP_CLOCK_STRETCH_MASK
? true : false;
137 data
->registry_data
.ulv_support
=
138 hwmgr
->feature_mask
& PP_ULV_MASK
? true : false;
140 data
->registry_data
.sclk_deep_sleep_support
=
141 hwmgr
->feature_mask
& PP_SCLK_DEEP_SLEEP_MASK
? true : false;
143 data
->registry_data
.disable_water_mark
= 0;
145 data
->registry_data
.fan_control_support
= 1;
146 data
->registry_data
.thermal_support
= 1;
147 data
->registry_data
.fw_ctf_enabled
= 1;
149 data
->registry_data
.avfs_support
=
150 hwmgr
->feature_mask
& PP_AVFS_MASK
? true : false;
151 data
->registry_data
.led_dpm_enabled
= 1;
153 data
->registry_data
.vr0hot_enabled
= 1;
154 data
->registry_data
.vr1hot_enabled
= 1;
155 data
->registry_data
.regulator_hot_gpio_support
= 1;
157 data
->registry_data
.didt_support
= 1;
158 if (data
->registry_data
.didt_support
) {
159 data
->registry_data
.didt_mode
= 6;
160 data
->registry_data
.sq_ramping_support
= 1;
161 data
->registry_data
.db_ramping_support
= 0;
162 data
->registry_data
.td_ramping_support
= 0;
163 data
->registry_data
.tcp_ramping_support
= 0;
164 data
->registry_data
.dbr_ramping_support
= 0;
165 data
->registry_data
.edc_didt_support
= 1;
166 data
->registry_data
.gc_didt_support
= 0;
167 data
->registry_data
.psm_didt_support
= 0;
170 data
->display_voltage_mode
= PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT
;
171 data
->dcef_clk_quad_eqn_a
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
172 data
->dcef_clk_quad_eqn_b
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
173 data
->dcef_clk_quad_eqn_c
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
174 data
->disp_clk_quad_eqn_a
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
175 data
->disp_clk_quad_eqn_b
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
176 data
->disp_clk_quad_eqn_c
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
177 data
->pixel_clk_quad_eqn_a
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
178 data
->pixel_clk_quad_eqn_b
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
179 data
->pixel_clk_quad_eqn_c
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
180 data
->phy_clk_quad_eqn_a
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
181 data
->phy_clk_quad_eqn_b
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
182 data
->phy_clk_quad_eqn_c
= PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
;
184 data
->gfxclk_average_alpha
= PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT
;
185 data
->socclk_average_alpha
= PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT
;
186 data
->uclk_average_alpha
= PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT
;
187 data
->gfx_activity_average_alpha
= PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT
;
190 static int vega10_set_features_platform_caps(struct pp_hwmgr
*hwmgr
)
192 struct vega10_hwmgr
*data
= hwmgr
->backend
;
193 struct phm_ppt_v2_information
*table_info
=
194 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
195 struct amdgpu_device
*adev
= hwmgr
->adev
;
197 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
198 PHM_PlatformCaps_SclkDeepSleep
);
200 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
201 PHM_PlatformCaps_DynamicPatchPowerState
);
203 if (data
->vddci_control
== VEGA10_VOLTAGE_CONTROL_NONE
)
204 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
205 PHM_PlatformCaps_ControlVDDCI
);
207 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
208 PHM_PlatformCaps_EnableSMU7ThermalManagement
);
210 if (adev
->pg_flags
& AMD_PG_SUPPORT_UVD
)
211 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
212 PHM_PlatformCaps_UVDPowerGating
);
214 if (adev
->pg_flags
& AMD_PG_SUPPORT_VCE
)
215 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
216 PHM_PlatformCaps_VCEPowerGating
);
218 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
219 PHM_PlatformCaps_UnTabledHardwareInterface
);
221 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
222 PHM_PlatformCaps_FanSpeedInTableIsRPM
);
224 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
225 PHM_PlatformCaps_ODFuzzyFanControlSupport
);
227 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
228 PHM_PlatformCaps_DynamicPowerManagement
);
230 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
231 PHM_PlatformCaps_SMC
);
233 /* power tune caps */
234 /* assume disabled */
235 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
236 PHM_PlatformCaps_PowerContainment
);
237 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
238 PHM_PlatformCaps_DiDtSupport
);
239 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
240 PHM_PlatformCaps_SQRamping
);
241 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
242 PHM_PlatformCaps_DBRamping
);
243 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
244 PHM_PlatformCaps_TDRamping
);
245 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
246 PHM_PlatformCaps_TCPRamping
);
247 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
248 PHM_PlatformCaps_DBRRamping
);
249 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
250 PHM_PlatformCaps_DiDtEDCEnable
);
251 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
252 PHM_PlatformCaps_GCEDC
);
253 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
254 PHM_PlatformCaps_PSM
);
256 if (data
->registry_data
.didt_support
) {
257 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_DiDtSupport
);
258 if (data
->registry_data
.sq_ramping_support
)
259 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_SQRamping
);
260 if (data
->registry_data
.db_ramping_support
)
261 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_DBRamping
);
262 if (data
->registry_data
.td_ramping_support
)
263 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_TDRamping
);
264 if (data
->registry_data
.tcp_ramping_support
)
265 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_TCPRamping
);
266 if (data
->registry_data
.dbr_ramping_support
)
267 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_DBRRamping
);
268 if (data
->registry_data
.edc_didt_support
)
269 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_DiDtEDCEnable
);
270 if (data
->registry_data
.gc_didt_support
)
271 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_GCEDC
);
272 if (data
->registry_data
.psm_didt_support
)
273 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_PSM
);
276 if (data
->registry_data
.power_containment_support
)
277 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
278 PHM_PlatformCaps_PowerContainment
);
279 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
280 PHM_PlatformCaps_CAC
);
282 if (table_info
->tdp_table
->usClockStretchAmount
&&
283 data
->registry_data
.clock_stretcher_support
)
284 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
285 PHM_PlatformCaps_ClockStretcher
);
287 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
288 PHM_PlatformCaps_RegulatorHot
);
289 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
290 PHM_PlatformCaps_AutomaticDCTransition
);
292 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
293 PHM_PlatformCaps_UVDDPM
);
294 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
295 PHM_PlatformCaps_VCEDPM
);
300 static int vega10_odn_initial_default_setting(struct pp_hwmgr
*hwmgr
)
302 struct vega10_hwmgr
*data
= hwmgr
->backend
;
303 struct phm_ppt_v2_information
*table_info
=
304 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
305 struct vega10_odn_dpm_table
*odn_table
= &(data
->odn_dpm_table
);
306 struct vega10_odn_vddc_lookup_table
*od_lookup_table
;
307 struct phm_ppt_v1_voltage_lookup_table
*vddc_lookup_table
;
308 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
[3];
309 struct phm_ppt_v1_clock_voltage_dependency_table
*od_table
[3];
310 struct pp_atomfwctrl_avfs_parameters avfs_params
= {0};
314 result
= pp_atomfwctrl_get_avfs_information(hwmgr
, &avfs_params
);
316 data
->odn_dpm_table
.max_vddc
= avfs_params
.ulMaxVddc
;
317 data
->odn_dpm_table
.min_vddc
= avfs_params
.ulMinVddc
;
320 od_lookup_table
= &odn_table
->vddc_lookup_table
;
321 vddc_lookup_table
= table_info
->vddc_lookup_table
;
323 for (i
= 0; i
< vddc_lookup_table
->count
; i
++)
324 od_lookup_table
->entries
[i
].us_vdd
= vddc_lookup_table
->entries
[i
].us_vdd
;
326 od_lookup_table
->count
= vddc_lookup_table
->count
;
328 dep_table
[0] = table_info
->vdd_dep_on_sclk
;
329 dep_table
[1] = table_info
->vdd_dep_on_mclk
;
330 dep_table
[2] = table_info
->vdd_dep_on_socclk
;
331 od_table
[0] = (struct phm_ppt_v1_clock_voltage_dependency_table
*)&odn_table
->vdd_dep_on_sclk
;
332 od_table
[1] = (struct phm_ppt_v1_clock_voltage_dependency_table
*)&odn_table
->vdd_dep_on_mclk
;
333 od_table
[2] = (struct phm_ppt_v1_clock_voltage_dependency_table
*)&odn_table
->vdd_dep_on_socclk
;
335 for (i
= 0; i
< 3; i
++)
336 smu_get_voltage_dependency_table_ppt_v1(dep_table
[i
], od_table
[i
]);
338 if (odn_table
->max_vddc
== 0 || odn_table
->max_vddc
> 2000)
339 odn_table
->max_vddc
= dep_table
[0]->entries
[dep_table
[0]->count
- 1].vddc
;
340 if (odn_table
->min_vddc
== 0 || odn_table
->min_vddc
> 2000)
341 odn_table
->min_vddc
= dep_table
[0]->entries
[0].vddc
;
343 i
= od_table
[2]->count
- 1;
344 od_table
[2]->entries
[i
].clk
= hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
> od_table
[2]->entries
[i
].clk
?
345 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
:
346 od_table
[2]->entries
[i
].clk
;
347 od_table
[2]->entries
[i
].vddc
= odn_table
->max_vddc
> od_table
[2]->entries
[i
].vddc
?
348 odn_table
->max_vddc
:
349 od_table
[2]->entries
[i
].vddc
;
354 static void vega10_init_dpm_defaults(struct pp_hwmgr
*hwmgr
)
356 struct vega10_hwmgr
*data
= hwmgr
->backend
;
358 uint32_t sub_vendor_id
, hw_revision
;
359 struct amdgpu_device
*adev
= hwmgr
->adev
;
361 vega10_initialize_power_tune_defaults(hwmgr
);
363 for (i
= 0; i
< GNLD_FEATURES_MAX
; i
++) {
364 data
->smu_features
[i
].smu_feature_id
= 0xffff;
365 data
->smu_features
[i
].smu_feature_bitmap
= 1 << i
;
366 data
->smu_features
[i
].enabled
= false;
367 data
->smu_features
[i
].supported
= false;
370 data
->smu_features
[GNLD_DPM_PREFETCHER
].smu_feature_id
=
371 FEATURE_DPM_PREFETCHER_BIT
;
372 data
->smu_features
[GNLD_DPM_GFXCLK
].smu_feature_id
=
373 FEATURE_DPM_GFXCLK_BIT
;
374 data
->smu_features
[GNLD_DPM_UCLK
].smu_feature_id
=
375 FEATURE_DPM_UCLK_BIT
;
376 data
->smu_features
[GNLD_DPM_SOCCLK
].smu_feature_id
=
377 FEATURE_DPM_SOCCLK_BIT
;
378 data
->smu_features
[GNLD_DPM_UVD
].smu_feature_id
=
380 data
->smu_features
[GNLD_DPM_VCE
].smu_feature_id
=
382 data
->smu_features
[GNLD_DPM_MP0CLK
].smu_feature_id
=
383 FEATURE_DPM_MP0CLK_BIT
;
384 data
->smu_features
[GNLD_DPM_LINK
].smu_feature_id
=
385 FEATURE_DPM_LINK_BIT
;
386 data
->smu_features
[GNLD_DPM_DCEFCLK
].smu_feature_id
=
387 FEATURE_DPM_DCEFCLK_BIT
;
388 data
->smu_features
[GNLD_ULV
].smu_feature_id
=
390 data
->smu_features
[GNLD_AVFS
].smu_feature_id
=
392 data
->smu_features
[GNLD_DS_GFXCLK
].smu_feature_id
=
393 FEATURE_DS_GFXCLK_BIT
;
394 data
->smu_features
[GNLD_DS_SOCCLK
].smu_feature_id
=
395 FEATURE_DS_SOCCLK_BIT
;
396 data
->smu_features
[GNLD_DS_LCLK
].smu_feature_id
=
398 data
->smu_features
[GNLD_PPT
].smu_feature_id
=
400 data
->smu_features
[GNLD_TDC
].smu_feature_id
=
402 data
->smu_features
[GNLD_THERMAL
].smu_feature_id
=
404 data
->smu_features
[GNLD_GFX_PER_CU_CG
].smu_feature_id
=
405 FEATURE_GFX_PER_CU_CG_BIT
;
406 data
->smu_features
[GNLD_RM
].smu_feature_id
=
408 data
->smu_features
[GNLD_DS_DCEFCLK
].smu_feature_id
=
409 FEATURE_DS_DCEFCLK_BIT
;
410 data
->smu_features
[GNLD_ACDC
].smu_feature_id
=
412 data
->smu_features
[GNLD_VR0HOT
].smu_feature_id
=
414 data
->smu_features
[GNLD_VR1HOT
].smu_feature_id
=
416 data
->smu_features
[GNLD_FW_CTF
].smu_feature_id
=
418 data
->smu_features
[GNLD_LED_DISPLAY
].smu_feature_id
=
419 FEATURE_LED_DISPLAY_BIT
;
420 data
->smu_features
[GNLD_FAN_CONTROL
].smu_feature_id
=
421 FEATURE_FAN_CONTROL_BIT
;
422 data
->smu_features
[GNLD_ACG
].smu_feature_id
= FEATURE_ACG_BIT
;
423 data
->smu_features
[GNLD_DIDT
].smu_feature_id
= FEATURE_GFX_EDC_BIT
;
424 data
->smu_features
[GNLD_PCC_LIMIT
].smu_feature_id
= FEATURE_PCC_LIMIT_CONTROL_BIT
;
426 if (!data
->registry_data
.prefetcher_dpm_key_disabled
)
427 data
->smu_features
[GNLD_DPM_PREFETCHER
].supported
= true;
429 if (!data
->registry_data
.sclk_dpm_key_disabled
)
430 data
->smu_features
[GNLD_DPM_GFXCLK
].supported
= true;
432 if (!data
->registry_data
.mclk_dpm_key_disabled
)
433 data
->smu_features
[GNLD_DPM_UCLK
].supported
= true;
435 if (!data
->registry_data
.socclk_dpm_key_disabled
)
436 data
->smu_features
[GNLD_DPM_SOCCLK
].supported
= true;
438 if (PP_CAP(PHM_PlatformCaps_UVDDPM
))
439 data
->smu_features
[GNLD_DPM_UVD
].supported
= true;
441 if (PP_CAP(PHM_PlatformCaps_VCEDPM
))
442 data
->smu_features
[GNLD_DPM_VCE
].supported
= true;
444 if (!data
->registry_data
.pcie_dpm_key_disabled
)
445 data
->smu_features
[GNLD_DPM_LINK
].supported
= true;
447 if (!data
->registry_data
.dcefclk_dpm_key_disabled
)
448 data
->smu_features
[GNLD_DPM_DCEFCLK
].supported
= true;
450 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep
) &&
451 data
->registry_data
.sclk_deep_sleep_support
) {
452 data
->smu_features
[GNLD_DS_GFXCLK
].supported
= true;
453 data
->smu_features
[GNLD_DS_SOCCLK
].supported
= true;
454 data
->smu_features
[GNLD_DS_LCLK
].supported
= true;
455 data
->smu_features
[GNLD_DS_DCEFCLK
].supported
= true;
458 if (data
->registry_data
.enable_pkg_pwr_tracking_feature
)
459 data
->smu_features
[GNLD_PPT
].supported
= true;
461 if (data
->registry_data
.enable_tdc_limit_feature
)
462 data
->smu_features
[GNLD_TDC
].supported
= true;
464 if (data
->registry_data
.thermal_support
)
465 data
->smu_features
[GNLD_THERMAL
].supported
= true;
467 if (data
->registry_data
.fan_control_support
)
468 data
->smu_features
[GNLD_FAN_CONTROL
].supported
= true;
470 if (data
->registry_data
.fw_ctf_enabled
)
471 data
->smu_features
[GNLD_FW_CTF
].supported
= true;
473 if (data
->registry_data
.avfs_support
)
474 data
->smu_features
[GNLD_AVFS
].supported
= true;
476 if (data
->registry_data
.led_dpm_enabled
)
477 data
->smu_features
[GNLD_LED_DISPLAY
].supported
= true;
479 if (data
->registry_data
.vr1hot_enabled
)
480 data
->smu_features
[GNLD_VR1HOT
].supported
= true;
482 if (data
->registry_data
.vr0hot_enabled
)
483 data
->smu_features
[GNLD_VR0HOT
].supported
= true;
485 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_GetSmuVersion
);
486 hwmgr
->smu_version
= smum_get_argument(hwmgr
);
487 /* ACG firmware has major version 5 */
488 if ((hwmgr
->smu_version
& 0xff000000) == 0x5000000)
489 data
->smu_features
[GNLD_ACG
].supported
= true;
490 if (data
->registry_data
.didt_support
)
491 data
->smu_features
[GNLD_DIDT
].supported
= true;
493 hw_revision
= adev
->pdev
->revision
;
494 sub_vendor_id
= adev
->pdev
->subsystem_vendor
;
496 if ((hwmgr
->chip_id
== 0x6862 ||
497 hwmgr
->chip_id
== 0x6861 ||
498 hwmgr
->chip_id
== 0x6868) &&
499 (hw_revision
== 0) &&
500 (sub_vendor_id
!= 0x1002))
501 data
->smu_features
[GNLD_PCC_LIMIT
].supported
= true;
504 #ifdef PPLIB_VEGA10_EVV_SUPPORT
505 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr
*hwmgr
,
506 phm_ppt_v1_voltage_lookup_table
*lookup_table
,
507 uint16_t virtual_voltage_id
, int32_t *socclk
)
511 struct phm_ppt_v2_information
*table_info
=
512 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
514 PP_ASSERT_WITH_CODE(lookup_table
->count
!= 0,
515 "Lookup table is empty",
518 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
519 for (entry_id
= 0; entry_id
< table_info
->vdd_dep_on_sclk
->count
; entry_id
++) {
520 voltage_id
= table_info
->vdd_dep_on_socclk
->entries
[entry_id
].vddInd
;
521 if (lookup_table
->entries
[voltage_id
].us_vdd
== virtual_voltage_id
)
525 PP_ASSERT_WITH_CODE(entry_id
< table_info
->vdd_dep_on_socclk
->count
,
526 "Can't find requested voltage id in vdd_dep_on_socclk table!",
529 *socclk
= table_info
->vdd_dep_on_socclk
->entries
[entry_id
].clk
;
534 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
536 * Get Leakage VDDC based on leakage ID.
538 * @param hwmgr the address of the powerplay hardware manager.
541 static int vega10_get_evv_voltages(struct pp_hwmgr
*hwmgr
)
543 struct vega10_hwmgr
*data
= hwmgr
->backend
;
548 struct phm_ppt_v2_information
*table_info
=
549 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
550 struct phm_ppt_v1_clock_voltage_dependency_table
*socclk_table
=
551 table_info
->vdd_dep_on_socclk
;
554 for (i
= 0; i
< VEGA10_MAX_LEAKAGE_COUNT
; i
++) {
555 vv_id
= ATOM_VIRTUAL_VOLTAGE_ID0
+ i
;
557 if (!vega10_get_socclk_for_voltage_evv(hwmgr
,
558 table_info
->vddc_lookup_table
, vv_id
, &sclk
)) {
559 if (PP_CAP(PHM_PlatformCaps_ClockStretcher
)) {
560 for (j
= 1; j
< socclk_table
->count
; j
++) {
561 if (socclk_table
->entries
[j
].clk
== sclk
&&
562 socclk_table
->entries
[j
].cks_enable
== 0) {
569 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr
,
570 VOLTAGE_TYPE_VDDC
, sclk
, vv_id
, &vddc
),
571 "Error retrieving EVV voltage value!",
575 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
576 PP_ASSERT_WITH_CODE((vddc
< 2000 && vddc
!= 0),
577 "Invalid VDDC value", result
= -EINVAL
;);
579 /* the voltage should not be zero nor equal to leakage ID */
580 if (vddc
!= 0 && vddc
!= vv_id
) {
581 data
->vddc_leakage
.actual_voltage
[data
->vddc_leakage
.count
] = (uint16_t)(vddc
/100);
582 data
->vddc_leakage
.leakage_id
[data
->vddc_leakage
.count
] = vv_id
;
583 data
->vddc_leakage
.count
++;
592 * Change virtual leakage voltage to actual value.
594 * @param hwmgr the address of the powerplay hardware manager.
595 * @param pointer to changing voltage
596 * @param pointer to leakage table
598 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr
*hwmgr
,
599 uint16_t *voltage
, struct vega10_leakage_voltage
*leakage_table
)
603 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
604 for (index
= 0; index
< leakage_table
->count
; index
++) {
605 /* if this voltage matches a leakage voltage ID */
606 /* patch with actual leakage voltage */
607 if (leakage_table
->leakage_id
[index
] == *voltage
) {
608 *voltage
= leakage_table
->actual_voltage
[index
];
613 if (*voltage
> ATOM_VIRTUAL_VOLTAGE_ID0
)
614 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
618 * Patch voltage lookup table by EVV leakages.
620 * @param hwmgr the address of the powerplay hardware manager.
621 * @param pointer to voltage lookup table
622 * @param pointer to leakage table
625 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr
*hwmgr
,
626 phm_ppt_v1_voltage_lookup_table
*lookup_table
,
627 struct vega10_leakage_voltage
*leakage_table
)
631 for (i
= 0; i
< lookup_table
->count
; i
++)
632 vega10_patch_with_vdd_leakage(hwmgr
,
633 &lookup_table
->entries
[i
].us_vdd
, leakage_table
);
638 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
639 struct pp_hwmgr
*hwmgr
, struct vega10_leakage_voltage
*leakage_table
,
642 vega10_patch_with_vdd_leakage(hwmgr
, (uint16_t *)vddc
, leakage_table
);
648 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
649 struct pp_hwmgr
*hwmgr
)
651 uint8_t entry_id
, voltage_id
;
653 struct phm_ppt_v2_information
*table_info
=
654 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
655 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
656 table_info
->mm_dep_table
;
657 struct phm_ppt_v1_clock_voltage_dependency_table
*mclk_table
=
658 table_info
->vdd_dep_on_mclk
;
660 for (i
= 0; i
< 6; i
++) {
661 struct phm_ppt_v1_clock_voltage_dependency_table
*vdt
;
663 case 0: vdt
= table_info
->vdd_dep_on_socclk
; break;
664 case 1: vdt
= table_info
->vdd_dep_on_sclk
; break;
665 case 2: vdt
= table_info
->vdd_dep_on_dcefclk
; break;
666 case 3: vdt
= table_info
->vdd_dep_on_pixclk
; break;
667 case 4: vdt
= table_info
->vdd_dep_on_dispclk
; break;
668 case 5: vdt
= table_info
->vdd_dep_on_phyclk
; break;
671 for (entry_id
= 0; entry_id
< vdt
->count
; entry_id
++) {
672 voltage_id
= vdt
->entries
[entry_id
].vddInd
;
673 vdt
->entries
[entry_id
].vddc
=
674 table_info
->vddc_lookup_table
->entries
[voltage_id
].us_vdd
;
678 for (entry_id
= 0; entry_id
< mm_table
->count
; ++entry_id
) {
679 voltage_id
= mm_table
->entries
[entry_id
].vddcInd
;
680 mm_table
->entries
[entry_id
].vddc
=
681 table_info
->vddc_lookup_table
->entries
[voltage_id
].us_vdd
;
684 for (entry_id
= 0; entry_id
< mclk_table
->count
; ++entry_id
) {
685 voltage_id
= mclk_table
->entries
[entry_id
].vddInd
;
686 mclk_table
->entries
[entry_id
].vddc
=
687 table_info
->vddc_lookup_table
->entries
[voltage_id
].us_vdd
;
688 voltage_id
= mclk_table
->entries
[entry_id
].vddciInd
;
689 mclk_table
->entries
[entry_id
].vddci
=
690 table_info
->vddci_lookup_table
->entries
[voltage_id
].us_vdd
;
691 voltage_id
= mclk_table
->entries
[entry_id
].mvddInd
;
692 mclk_table
->entries
[entry_id
].mvdd
=
693 table_info
->vddmem_lookup_table
->entries
[voltage_id
].us_vdd
;
701 static int vega10_sort_lookup_table(struct pp_hwmgr
*hwmgr
,
702 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
)
704 uint32_t table_size
, i
, j
;
705 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record
;
707 PP_ASSERT_WITH_CODE(lookup_table
&& lookup_table
->count
,
708 "Lookup table is empty", return -EINVAL
);
710 table_size
= lookup_table
->count
;
712 /* Sorting voltages */
713 for (i
= 0; i
< table_size
- 1; i
++) {
714 for (j
= i
+ 1; j
> 0; j
--) {
715 if (lookup_table
->entries
[j
].us_vdd
<
716 lookup_table
->entries
[j
- 1].us_vdd
) {
717 tmp_voltage_lookup_record
= lookup_table
->entries
[j
- 1];
718 lookup_table
->entries
[j
- 1] = lookup_table
->entries
[j
];
719 lookup_table
->entries
[j
] = tmp_voltage_lookup_record
;
727 static int vega10_complete_dependency_tables(struct pp_hwmgr
*hwmgr
)
731 struct phm_ppt_v2_information
*table_info
=
732 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
733 #ifdef PPLIB_VEGA10_EVV_SUPPORT
734 struct vega10_hwmgr
*data
= hwmgr
->backend
;
736 tmp_result
= vega10_patch_lookup_table_with_leakage(hwmgr
,
737 table_info
->vddc_lookup_table
, &(data
->vddc_leakage
));
741 tmp_result
= vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr
,
742 &(data
->vddc_leakage
), &table_info
->max_clock_voltage_on_dc
.vddc
);
747 tmp_result
= vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr
);
751 tmp_result
= vega10_sort_lookup_table(hwmgr
, table_info
->vddc_lookup_table
);
758 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr
*hwmgr
)
760 struct phm_ppt_v2_information
*table_info
=
761 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
762 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_sclk_vdd_table
=
763 table_info
->vdd_dep_on_socclk
;
764 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_mclk_vdd_table
=
765 table_info
->vdd_dep_on_mclk
;
767 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
,
768 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL
);
769 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
->count
>= 1,
770 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL
);
772 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
,
773 "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL
);
774 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
->count
>= 1,
775 "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL
);
777 table_info
->max_clock_voltage_on_ac
.sclk
=
778 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].clk
;
779 table_info
->max_clock_voltage_on_ac
.mclk
=
780 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].clk
;
781 table_info
->max_clock_voltage_on_ac
.vddc
=
782 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].vddc
;
783 table_info
->max_clock_voltage_on_ac
.vddci
=
784 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].vddci
;
786 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.sclk
=
787 table_info
->max_clock_voltage_on_ac
.sclk
;
788 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.mclk
=
789 table_info
->max_clock_voltage_on_ac
.mclk
;
790 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddc
=
791 table_info
->max_clock_voltage_on_ac
.vddc
;
792 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddci
=
793 table_info
->max_clock_voltage_on_ac
.vddci
;
798 static int vega10_hwmgr_backend_fini(struct pp_hwmgr
*hwmgr
)
800 kfree(hwmgr
->dyn_state
.vddc_dep_on_dal_pwrl
);
801 hwmgr
->dyn_state
.vddc_dep_on_dal_pwrl
= NULL
;
803 kfree(hwmgr
->backend
);
804 hwmgr
->backend
= NULL
;
809 static int vega10_hwmgr_backend_init(struct pp_hwmgr
*hwmgr
)
812 struct vega10_hwmgr
*data
;
813 uint32_t config_telemetry
= 0;
814 struct pp_atomfwctrl_voltage_table vol_table
;
815 struct amdgpu_device
*adev
= hwmgr
->adev
;
817 data
= kzalloc(sizeof(struct vega10_hwmgr
), GFP_KERNEL
);
821 hwmgr
->backend
= data
;
823 hwmgr
->workload_mask
= 1 << hwmgr
->workload_prority
[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT
];
824 hwmgr
->power_profile_mode
= PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT
;
825 hwmgr
->default_power_profile_mode
= PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT
;
827 vega10_set_default_registry_data(hwmgr
);
828 data
->disable_dpm_mask
= 0xff;
830 /* need to set voltage control types before EVV patching */
831 data
->vddc_control
= VEGA10_VOLTAGE_CONTROL_NONE
;
832 data
->mvdd_control
= VEGA10_VOLTAGE_CONTROL_NONE
;
833 data
->vddci_control
= VEGA10_VOLTAGE_CONTROL_NONE
;
836 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr
,
837 VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_SVID2
)) {
838 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr
,
839 VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_SVID2
,
841 config_telemetry
= ((vol_table
.telemetry_slope
<< 8) & 0xff00) |
842 (vol_table
.telemetry_offset
& 0xff);
843 data
->vddc_control
= VEGA10_VOLTAGE_CONTROL_BY_SVID2
;
846 kfree(hwmgr
->backend
);
847 hwmgr
->backend
= NULL
;
848 PP_ASSERT_WITH_CODE(false,
849 "VDDCR_SOC is not SVID2!",
854 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr
,
855 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_SVID2
)) {
856 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr
,
857 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_SVID2
,
860 ((vol_table
.telemetry_slope
<< 24) & 0xff000000) |
861 ((vol_table
.telemetry_offset
<< 16) & 0xff0000);
862 data
->mvdd_control
= VEGA10_VOLTAGE_CONTROL_BY_SVID2
;
867 if (PP_CAP(PHM_PlatformCaps_ControlVDDCI
)) {
868 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr
,
869 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
))
870 data
->vddci_control
= VEGA10_VOLTAGE_CONTROL_BY_GPIO
;
873 data
->config_telemetry
= config_telemetry
;
875 vega10_set_features_platform_caps(hwmgr
);
877 vega10_init_dpm_defaults(hwmgr
);
879 #ifdef PPLIB_VEGA10_EVV_SUPPORT
880 /* Get leakage voltage based on leakage ID. */
881 PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr
),
882 "Get EVV Voltage Failed. Abort Driver loading!",
886 /* Patch our voltage dependency table with actual leakage voltage
887 * We need to perform leakage translation before it's used by other functions
889 vega10_complete_dependency_tables(hwmgr
);
891 /* Parse pptable data read from VBIOS */
892 vega10_set_private_data_based_on_pptable(hwmgr
);
894 data
->is_tlu_enabled
= false;
896 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
=
897 VEGA10_MAX_HARDWARE_POWERLEVELS
;
898 hwmgr
->platform_descriptor
.hardwarePerformanceLevels
= 2;
899 hwmgr
->platform_descriptor
.minimumClocksReductionPercentage
= 50;
901 hwmgr
->platform_descriptor
.vbiosInterruptId
= 0x20000400; /* IRQ_SOURCE1_SW_INT */
902 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
903 hwmgr
->platform_descriptor
.clockStep
.engineClock
= 500;
904 hwmgr
->platform_descriptor
.clockStep
.memoryClock
= 500;
906 data
->total_active_cus
= adev
->gfx
.cu_info
.number
;
907 /* Setup default Overdrive Fan control settings */
908 data
->odn_fan_table
.target_fan_speed
=
909 hwmgr
->thermal_controller
.advanceFanControlParameters
.usMaxFanRPM
;
910 data
->odn_fan_table
.target_temperature
=
911 hwmgr
->thermal_controller
.
912 advanceFanControlParameters
.ucTargetTemperature
;
913 data
->odn_fan_table
.min_performance_clock
=
914 hwmgr
->thermal_controller
.advanceFanControlParameters
.
915 ulMinFanSCLKAcousticLimit
;
916 data
->odn_fan_table
.min_fan_limit
=
917 hwmgr
->thermal_controller
.
918 advanceFanControlParameters
.usFanPWMMinLimit
*
919 hwmgr
->thermal_controller
.fanInfo
.ulMaxRPM
/ 100;
921 data
->mem_channels
= (RREG32_SOC15(DF
, 0, mmDF_CS_AON0_DramBaseAddress0
) &
922 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK
) >>
923 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT
;
924 PP_ASSERT_WITH_CODE(data
->mem_channels
< ARRAY_SIZE(channel_number
),
925 "Mem Channel Index Exceeded maximum!",
931 static int vega10_init_sclk_threshold(struct pp_hwmgr
*hwmgr
)
933 struct vega10_hwmgr
*data
= hwmgr
->backend
;
935 data
->low_sclk_interrupt_threshold
= 0;
940 static int vega10_setup_dpm_led_config(struct pp_hwmgr
*hwmgr
)
942 struct vega10_hwmgr
*data
= hwmgr
->backend
;
943 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
945 struct pp_atomfwctrl_voltage_table table
;
951 ret
= pp_atomfwctrl_get_voltage_table_v4(hwmgr
, VOLTAGE_TYPE_LEDDPM
,
952 VOLTAGE_OBJ_GPIO_LUT
, &table
);
955 tmp
= table
.mask_low
;
956 for (i
= 0, j
= 0; i
< 32; i
++) {
958 mask
|= (uint32_t)(i
<< (8 * j
));
966 pp_table
->LedPin0
= (uint8_t)(mask
& 0xff);
967 pp_table
->LedPin1
= (uint8_t)((mask
>> 8) & 0xff);
968 pp_table
->LedPin2
= (uint8_t)((mask
>> 16) & 0xff);
972 static int vega10_setup_asic_task(struct pp_hwmgr
*hwmgr
)
974 PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr
),
975 "Failed to init sclk threshold!",
978 PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr
),
979 "Failed to set up led dpm config!",
982 smum_send_msg_to_smc_with_parameter(hwmgr
, PPSMC_MSG_NumOfDisplays
, 0);
988 * Remove repeated voltage values and create table with unique values.
990 * @param hwmgr the address of the powerplay hardware manager.
991 * @param vol_table the pointer to changing voltage table
992 * @return 0 in success
995 static int vega10_trim_voltage_table(struct pp_hwmgr
*hwmgr
,
996 struct pp_atomfwctrl_voltage_table
*vol_table
)
1001 struct pp_atomfwctrl_voltage_table
*table
;
1003 PP_ASSERT_WITH_CODE(vol_table
,
1004 "Voltage Table empty.", return -EINVAL
);
1005 table
= kzalloc(sizeof(struct pp_atomfwctrl_voltage_table
),
1011 table
->mask_low
= vol_table
->mask_low
;
1012 table
->phase_delay
= vol_table
->phase_delay
;
1014 for (i
= 0; i
< vol_table
->count
; i
++) {
1015 vvalue
= vol_table
->entries
[i
].value
;
1018 for (j
= 0; j
< table
->count
; j
++) {
1019 if (vvalue
== table
->entries
[j
].value
) {
1026 table
->entries
[table
->count
].value
= vvalue
;
1027 table
->entries
[table
->count
].smio_low
=
1028 vol_table
->entries
[i
].smio_low
;
1033 memcpy(vol_table
, table
, sizeof(struct pp_atomfwctrl_voltage_table
));
1039 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr
*hwmgr
,
1040 phm_ppt_v1_clock_voltage_dependency_table
*dep_table
,
1041 struct pp_atomfwctrl_voltage_table
*vol_table
)
1045 PP_ASSERT_WITH_CODE(dep_table
->count
,
1046 "Voltage Dependency Table empty.",
1049 vol_table
->mask_low
= 0;
1050 vol_table
->phase_delay
= 0;
1051 vol_table
->count
= dep_table
->count
;
1053 for (i
= 0; i
< vol_table
->count
; i
++) {
1054 vol_table
->entries
[i
].value
= dep_table
->entries
[i
].mvdd
;
1055 vol_table
->entries
[i
].smio_low
= 0;
1058 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr
,
1060 "Failed to trim MVDD Table!",
1066 static int vega10_get_vddci_voltage_table(struct pp_hwmgr
*hwmgr
,
1067 phm_ppt_v1_clock_voltage_dependency_table
*dep_table
,
1068 struct pp_atomfwctrl_voltage_table
*vol_table
)
1072 PP_ASSERT_WITH_CODE(dep_table
->count
,
1073 "Voltage Dependency Table empty.",
1076 vol_table
->mask_low
= 0;
1077 vol_table
->phase_delay
= 0;
1078 vol_table
->count
= dep_table
->count
;
1080 for (i
= 0; i
< dep_table
->count
; i
++) {
1081 vol_table
->entries
[i
].value
= dep_table
->entries
[i
].vddci
;
1082 vol_table
->entries
[i
].smio_low
= 0;
1085 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr
, vol_table
),
1086 "Failed to trim VDDCI table.",
1092 static int vega10_get_vdd_voltage_table(struct pp_hwmgr
*hwmgr
,
1093 phm_ppt_v1_clock_voltage_dependency_table
*dep_table
,
1094 struct pp_atomfwctrl_voltage_table
*vol_table
)
1098 PP_ASSERT_WITH_CODE(dep_table
->count
,
1099 "Voltage Dependency Table empty.",
1102 vol_table
->mask_low
= 0;
1103 vol_table
->phase_delay
= 0;
1104 vol_table
->count
= dep_table
->count
;
1106 for (i
= 0; i
< vol_table
->count
; i
++) {
1107 vol_table
->entries
[i
].value
= dep_table
->entries
[i
].vddc
;
1108 vol_table
->entries
[i
].smio_low
= 0;
1114 /* ---- Voltage Tables ----
1115 * If the voltage table would be bigger than
1116 * what will fit into the state table on
1117 * the SMC keep only the higher entries.
1119 static void vega10_trim_voltage_table_to_fit_state_table(
1120 struct pp_hwmgr
*hwmgr
,
1121 uint32_t max_vol_steps
,
1122 struct pp_atomfwctrl_voltage_table
*vol_table
)
1124 unsigned int i
, diff
;
1126 if (vol_table
->count
<= max_vol_steps
)
1129 diff
= vol_table
->count
- max_vol_steps
;
1131 for (i
= 0; i
< max_vol_steps
; i
++)
1132 vol_table
->entries
[i
] = vol_table
->entries
[i
+ diff
];
1134 vol_table
->count
= max_vol_steps
;
1138 * Create Voltage Tables.
1140 * @param hwmgr the address of the powerplay hardware manager.
1143 static int vega10_construct_voltage_tables(struct pp_hwmgr
*hwmgr
)
1145 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1146 struct phm_ppt_v2_information
*table_info
=
1147 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
1150 if (data
->mvdd_control
== VEGA10_VOLTAGE_CONTROL_BY_SVID2
||
1151 data
->mvdd_control
== VEGA10_VOLTAGE_CONTROL_NONE
) {
1152 result
= vega10_get_mvdd_voltage_table(hwmgr
,
1153 table_info
->vdd_dep_on_mclk
,
1154 &(data
->mvdd_voltage_table
));
1155 PP_ASSERT_WITH_CODE(!result
,
1156 "Failed to retrieve MVDDC table!",
1160 if (data
->vddci_control
== VEGA10_VOLTAGE_CONTROL_NONE
) {
1161 result
= vega10_get_vddci_voltage_table(hwmgr
,
1162 table_info
->vdd_dep_on_mclk
,
1163 &(data
->vddci_voltage_table
));
1164 PP_ASSERT_WITH_CODE(!result
,
1165 "Failed to retrieve VDDCI_MEM table!",
1169 if (data
->vddc_control
== VEGA10_VOLTAGE_CONTROL_BY_SVID2
||
1170 data
->vddc_control
== VEGA10_VOLTAGE_CONTROL_NONE
) {
1171 result
= vega10_get_vdd_voltage_table(hwmgr
,
1172 table_info
->vdd_dep_on_sclk
,
1173 &(data
->vddc_voltage_table
));
1174 PP_ASSERT_WITH_CODE(!result
,
1175 "Failed to retrieve VDDCR_SOC table!",
1179 PP_ASSERT_WITH_CODE(data
->vddc_voltage_table
.count
<= 16,
1180 "Too many voltage values for VDDC. Trimming to fit state table.",
1181 vega10_trim_voltage_table_to_fit_state_table(hwmgr
,
1182 16, &(data
->vddc_voltage_table
)));
1184 PP_ASSERT_WITH_CODE(data
->vddci_voltage_table
.count
<= 16,
1185 "Too many voltage values for VDDCI. Trimming to fit state table.",
1186 vega10_trim_voltage_table_to_fit_state_table(hwmgr
,
1187 16, &(data
->vddci_voltage_table
)));
1189 PP_ASSERT_WITH_CODE(data
->mvdd_voltage_table
.count
<= 16,
1190 "Too many voltage values for MVDD. Trimming to fit state table.",
1191 vega10_trim_voltage_table_to_fit_state_table(hwmgr
,
1192 16, &(data
->mvdd_voltage_table
)));
1199 * @fn vega10_init_dpm_state
1200 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1202 * @param dpm_state - the address of the DPM Table to initiailize.
1205 static void vega10_init_dpm_state(struct vega10_dpm_state
*dpm_state
)
1207 dpm_state
->soft_min_level
= 0xff;
1208 dpm_state
->soft_max_level
= 0xff;
1209 dpm_state
->hard_min_level
= 0xff;
1210 dpm_state
->hard_max_level
= 0xff;
1213 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr
*hwmgr
,
1214 struct vega10_single_dpm_table
*dpm_table
,
1215 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
)
1219 dpm_table
->count
= 0;
1221 for (i
= 0; i
< dep_table
->count
; i
++) {
1222 if (i
== 0 || dpm_table
->dpm_levels
[dpm_table
->count
- 1].value
<=
1223 dep_table
->entries
[i
].clk
) {
1224 dpm_table
->dpm_levels
[dpm_table
->count
].value
=
1225 dep_table
->entries
[i
].clk
;
1226 dpm_table
->dpm_levels
[dpm_table
->count
].enabled
= true;
1231 static int vega10_setup_default_pcie_table(struct pp_hwmgr
*hwmgr
)
1233 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1234 struct vega10_pcie_table
*pcie_table
= &(data
->dpm_table
.pcie_table
);
1235 struct phm_ppt_v2_information
*table_info
=
1236 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
1237 struct phm_ppt_v1_pcie_table
*bios_pcie_table
=
1238 table_info
->pcie_table
;
1241 PP_ASSERT_WITH_CODE(bios_pcie_table
->count
,
1242 "Incorrect number of PCIE States from VBIOS!",
1245 for (i
= 0; i
< NUM_LINK_LEVELS
; i
++) {
1246 if (data
->registry_data
.pcieSpeedOverride
)
1247 pcie_table
->pcie_gen
[i
] =
1248 data
->registry_data
.pcieSpeedOverride
;
1250 pcie_table
->pcie_gen
[i
] =
1251 bios_pcie_table
->entries
[i
].gen_speed
;
1253 if (data
->registry_data
.pcieLaneOverride
)
1254 pcie_table
->pcie_lane
[i
] = (uint8_t)encode_pcie_lane_width(
1255 data
->registry_data
.pcieLaneOverride
);
1257 pcie_table
->pcie_lane
[i
] = (uint8_t)encode_pcie_lane_width(
1258 bios_pcie_table
->entries
[i
].lane_width
);
1259 if (data
->registry_data
.pcieClockOverride
)
1260 pcie_table
->lclk
[i
] =
1261 data
->registry_data
.pcieClockOverride
;
1263 pcie_table
->lclk
[i
] =
1264 bios_pcie_table
->entries
[i
].pcie_sclk
;
1267 pcie_table
->count
= NUM_LINK_LEVELS
;
1273 * This function is to initialize all DPM state tables
1274 * for SMU based on the dependency table.
1275 * Dynamic state patching function will then trim these
1276 * state tables to the allowed range based
1277 * on the power policy or external client requests,
1278 * such as UVD request, etc.
1280 static int vega10_setup_default_dpm_tables(struct pp_hwmgr
*hwmgr
)
1282 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1283 struct phm_ppt_v2_information
*table_info
=
1284 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
1285 struct vega10_single_dpm_table
*dpm_table
;
1288 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_soc_table
=
1289 table_info
->vdd_dep_on_socclk
;
1290 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_gfx_table
=
1291 table_info
->vdd_dep_on_sclk
;
1292 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
=
1293 table_info
->vdd_dep_on_mclk
;
1294 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*dep_mm_table
=
1295 table_info
->mm_dep_table
;
1296 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_dcef_table
=
1297 table_info
->vdd_dep_on_dcefclk
;
1298 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_pix_table
=
1299 table_info
->vdd_dep_on_pixclk
;
1300 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_disp_table
=
1301 table_info
->vdd_dep_on_dispclk
;
1302 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_phy_table
=
1303 table_info
->vdd_dep_on_phyclk
;
1305 PP_ASSERT_WITH_CODE(dep_soc_table
,
1306 "SOCCLK dependency table is missing. This table is mandatory",
1308 PP_ASSERT_WITH_CODE(dep_soc_table
->count
>= 1,
1309 "SOCCLK dependency table is empty. This table is mandatory",
1312 PP_ASSERT_WITH_CODE(dep_gfx_table
,
1313 "GFXCLK dependency table is missing. This table is mandatory",
1315 PP_ASSERT_WITH_CODE(dep_gfx_table
->count
>= 1,
1316 "GFXCLK dependency table is empty. This table is mandatory",
1319 PP_ASSERT_WITH_CODE(dep_mclk_table
,
1320 "MCLK dependency table is missing. This table is mandatory",
1322 PP_ASSERT_WITH_CODE(dep_mclk_table
->count
>= 1,
1323 "MCLK dependency table has to have is missing. This table is mandatory",
1326 /* Initialize Sclk DPM table based on allow Sclk values */
1327 dpm_table
= &(data
->dpm_table
.soc_table
);
1328 vega10_setup_default_single_dpm_table(hwmgr
,
1332 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1334 dpm_table
= &(data
->dpm_table
.gfx_table
);
1335 vega10_setup_default_single_dpm_table(hwmgr
,
1338 if (hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
== 0)
1339 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
=
1340 dpm_table
->dpm_levels
[dpm_table
->count
-1].value
;
1341 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1343 /* Initialize Mclk DPM table based on allow Mclk values */
1344 data
->dpm_table
.mem_table
.count
= 0;
1345 dpm_table
= &(data
->dpm_table
.mem_table
);
1346 vega10_setup_default_single_dpm_table(hwmgr
,
1349 if (hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
== 0)
1350 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
=
1351 dpm_table
->dpm_levels
[dpm_table
->count
-1].value
;
1352 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1354 data
->dpm_table
.eclk_table
.count
= 0;
1355 dpm_table
= &(data
->dpm_table
.eclk_table
);
1356 for (i
= 0; i
< dep_mm_table
->count
; i
++) {
1357 if (i
== 0 || dpm_table
->dpm_levels
1358 [dpm_table
->count
- 1].value
<=
1359 dep_mm_table
->entries
[i
].eclk
) {
1360 dpm_table
->dpm_levels
[dpm_table
->count
].value
=
1361 dep_mm_table
->entries
[i
].eclk
;
1362 dpm_table
->dpm_levels
[dpm_table
->count
].enabled
=
1363 (i
== 0) ? true : false;
1367 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1369 data
->dpm_table
.vclk_table
.count
= 0;
1370 data
->dpm_table
.dclk_table
.count
= 0;
1371 dpm_table
= &(data
->dpm_table
.vclk_table
);
1372 for (i
= 0; i
< dep_mm_table
->count
; i
++) {
1373 if (i
== 0 || dpm_table
->dpm_levels
1374 [dpm_table
->count
- 1].value
<=
1375 dep_mm_table
->entries
[i
].vclk
) {
1376 dpm_table
->dpm_levels
[dpm_table
->count
].value
=
1377 dep_mm_table
->entries
[i
].vclk
;
1378 dpm_table
->dpm_levels
[dpm_table
->count
].enabled
=
1379 (i
== 0) ? true : false;
1383 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1385 dpm_table
= &(data
->dpm_table
.dclk_table
);
1386 for (i
= 0; i
< dep_mm_table
->count
; i
++) {
1387 if (i
== 0 || dpm_table
->dpm_levels
1388 [dpm_table
->count
- 1].value
<=
1389 dep_mm_table
->entries
[i
].dclk
) {
1390 dpm_table
->dpm_levels
[dpm_table
->count
].value
=
1391 dep_mm_table
->entries
[i
].dclk
;
1392 dpm_table
->dpm_levels
[dpm_table
->count
].enabled
=
1393 (i
== 0) ? true : false;
1397 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1399 /* Assume there is no headless Vega10 for now */
1400 dpm_table
= &(data
->dpm_table
.dcef_table
);
1401 vega10_setup_default_single_dpm_table(hwmgr
,
1405 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1407 dpm_table
= &(data
->dpm_table
.pixel_table
);
1408 vega10_setup_default_single_dpm_table(hwmgr
,
1412 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1414 dpm_table
= &(data
->dpm_table
.display_table
);
1415 vega10_setup_default_single_dpm_table(hwmgr
,
1419 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1421 dpm_table
= &(data
->dpm_table
.phy_table
);
1422 vega10_setup_default_single_dpm_table(hwmgr
,
1426 vega10_init_dpm_state(&(dpm_table
->dpm_state
));
1428 vega10_setup_default_pcie_table(hwmgr
);
1430 /* save a copy of the default DPM table */
1431 memcpy(&(data
->golden_dpm_table
), &(data
->dpm_table
),
1432 sizeof(struct vega10_dpm_table
));
1438 * @fn vega10_populate_ulv_state
1439 * @brief Function to provide parameters for Utral Low Voltage state to SMC.
1441 * @param hwmgr - the address of the hardware manager.
1444 static int vega10_populate_ulv_state(struct pp_hwmgr
*hwmgr
)
1446 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1447 struct phm_ppt_v2_information
*table_info
=
1448 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
1450 data
->smc_state_table
.pp_table
.UlvOffsetVid
=
1451 (uint8_t)table_info
->us_ulv_voltage_offset
;
1453 data
->smc_state_table
.pp_table
.UlvSmnclkDid
=
1454 (uint8_t)(table_info
->us_ulv_smnclk_did
);
1455 data
->smc_state_table
.pp_table
.UlvMp1clkDid
=
1456 (uint8_t)(table_info
->us_ulv_mp1clk_did
);
1457 data
->smc_state_table
.pp_table
.UlvGfxclkBypass
=
1458 (uint8_t)(table_info
->us_ulv_gfxclk_bypass
);
1459 data
->smc_state_table
.pp_table
.UlvPhaseSheddingPsi0
=
1460 (uint8_t)(data
->vddc_voltage_table
.psi0_enable
);
1461 data
->smc_state_table
.pp_table
.UlvPhaseSheddingPsi1
=
1462 (uint8_t)(data
->vddc_voltage_table
.psi1_enable
);
1467 static int vega10_populate_single_lclk_level(struct pp_hwmgr
*hwmgr
,
1468 uint32_t lclock
, uint8_t *curr_lclk_did
)
1470 struct pp_atomfwctrl_clock_dividers_soc15 dividers
;
1472 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1474 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
1476 "Failed to get LCLK clock settings from VBIOS!",
1479 *curr_lclk_did
= dividers
.ulDid
;
1484 static int vega10_populate_smc_link_levels(struct pp_hwmgr
*hwmgr
)
1487 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1488 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
1489 struct vega10_pcie_table
*pcie_table
=
1490 &(data
->dpm_table
.pcie_table
);
1493 for (i
= 0; i
< pcie_table
->count
; i
++) {
1494 pp_table
->PcieGenSpeed
[i
] = pcie_table
->pcie_gen
[i
];
1495 pp_table
->PcieLaneCount
[i
] = pcie_table
->pcie_lane
[i
];
1497 result
= vega10_populate_single_lclk_level(hwmgr
,
1498 pcie_table
->lclk
[i
], &(pp_table
->LclkDid
[i
]));
1500 pr_info("Populate LClock Level %d Failed!\n", i
);
1506 while (i
< NUM_LINK_LEVELS
) {
1507 pp_table
->PcieGenSpeed
[i
] = pcie_table
->pcie_gen
[j
];
1508 pp_table
->PcieLaneCount
[i
] = pcie_table
->pcie_lane
[j
];
1510 result
= vega10_populate_single_lclk_level(hwmgr
,
1511 pcie_table
->lclk
[j
], &(pp_table
->LclkDid
[i
]));
1513 pr_info("Populate LClock Level %d Failed!\n", i
);
1523 * Populates single SMC GFXSCLK structure using the provided engine clock
1525 * @param hwmgr the address of the hardware manager
1526 * @param gfx_clock the GFX clock to use to populate the structure.
1527 * @param current_gfxclk_level location in PPTable for the SMC GFXCLK structure.
1530 static int vega10_populate_single_gfx_level(struct pp_hwmgr
*hwmgr
,
1531 uint32_t gfx_clock
, PllSetting_t
*current_gfxclk_level
,
1534 struct phm_ppt_v2_information
*table_info
=
1535 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
1536 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_on_sclk
;
1537 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1538 struct pp_atomfwctrl_clock_dividers_soc15 dividers
;
1539 uint32_t gfx_max_clock
=
1540 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
;
1543 if (hwmgr
->od_enabled
)
1544 dep_on_sclk
= (struct phm_ppt_v1_clock_voltage_dependency_table
*)
1545 &(data
->odn_dpm_table
.vdd_dep_on_sclk
);
1547 dep_on_sclk
= table_info
->vdd_dep_on_sclk
;
1549 PP_ASSERT_WITH_CODE(dep_on_sclk
,
1550 "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1553 if (data
->need_update_dpm_table
& DPMTABLE_OD_UPDATE_SCLK
)
1554 gfx_clock
= gfx_clock
> gfx_max_clock
? gfx_max_clock
: gfx_clock
;
1556 for (i
= 0; i
< dep_on_sclk
->count
; i
++) {
1557 if (dep_on_sclk
->entries
[i
].clk
== gfx_clock
)
1560 PP_ASSERT_WITH_CODE(dep_on_sclk
->count
> i
,
1561 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1565 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr
,
1566 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK
,
1567 gfx_clock
, ÷rs
),
1568 "Failed to get GFX Clock settings from VBIOS!",
1571 /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1572 current_gfxclk_level
->FbMult
=
1573 cpu_to_le32(dividers
.ulPll_fb_mult
);
1574 /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1575 current_gfxclk_level
->SsOn
= dividers
.ucPll_ss_enable
;
1576 current_gfxclk_level
->SsFbMult
=
1577 cpu_to_le32(dividers
.ulPll_ss_fbsmult
);
1578 current_gfxclk_level
->SsSlewFrac
=
1579 cpu_to_le16(dividers
.usPll_ss_slew_frac
);
1580 current_gfxclk_level
->Did
= (uint8_t)(dividers
.ulDid
);
1582 *acg_freq
= gfx_clock
/ 100; /* 100 Khz to Mhz conversion */
1588 * @brief Populates single SMC SOCCLK structure using the provided clock.
1590 * @param hwmgr - the address of the hardware manager.
1591 * @param soc_clock - the SOC clock to use to populate the structure.
1592 * @param current_socclk_level - location in PPTable for the SMC SOCCLK structure.
1593 * @return 0 on success..
1595 static int vega10_populate_single_soc_level(struct pp_hwmgr
*hwmgr
,
1596 uint32_t soc_clock
, uint8_t *current_soc_did
,
1597 uint8_t *current_vol_index
)
1599 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1600 struct phm_ppt_v2_information
*table_info
=
1601 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
1602 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_on_soc
;
1603 struct pp_atomfwctrl_clock_dividers_soc15 dividers
;
1606 if (hwmgr
->od_enabled
) {
1607 dep_on_soc
= (struct phm_ppt_v1_clock_voltage_dependency_table
*)
1608 &data
->odn_dpm_table
.vdd_dep_on_socclk
;
1609 for (i
= 0; i
< dep_on_soc
->count
; i
++) {
1610 if (dep_on_soc
->entries
[i
].clk
>= soc_clock
)
1614 dep_on_soc
= table_info
->vdd_dep_on_socclk
;
1615 for (i
= 0; i
< dep_on_soc
->count
; i
++) {
1616 if (dep_on_soc
->entries
[i
].clk
== soc_clock
)
1621 PP_ASSERT_WITH_CODE(dep_on_soc
->count
> i
,
1622 "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1625 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr
,
1626 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
1627 soc_clock
, ÷rs
),
1628 "Failed to get SOC Clock settings from VBIOS!",
1631 *current_soc_did
= (uint8_t)dividers
.ulDid
;
1632 *current_vol_index
= (uint8_t)(dep_on_soc
->entries
[i
].vddInd
);
1637 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1639 * @param hwmgr the address of the hardware manager
1641 static int vega10_populate_all_graphic_levels(struct pp_hwmgr
*hwmgr
)
1643 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1644 struct phm_ppt_v2_information
*table_info
=
1645 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
1646 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
1647 struct vega10_single_dpm_table
*dpm_table
= &(data
->dpm_table
.gfx_table
);
1651 for (i
= 0; i
< dpm_table
->count
; i
++) {
1652 result
= vega10_populate_single_gfx_level(hwmgr
,
1653 dpm_table
->dpm_levels
[i
].value
,
1654 &(pp_table
->GfxclkLevel
[i
]),
1655 &(pp_table
->AcgFreqTable
[i
]));
1661 while (i
< NUM_GFXCLK_DPM_LEVELS
) {
1662 result
= vega10_populate_single_gfx_level(hwmgr
,
1663 dpm_table
->dpm_levels
[j
].value
,
1664 &(pp_table
->GfxclkLevel
[i
]),
1665 &(pp_table
->AcgFreqTable
[i
]));
1671 pp_table
->GfxclkSlewRate
=
1672 cpu_to_le16(table_info
->us_gfxclk_slew_rate
);
1674 dpm_table
= &(data
->dpm_table
.soc_table
);
1675 for (i
= 0; i
< dpm_table
->count
; i
++) {
1676 result
= vega10_populate_single_soc_level(hwmgr
,
1677 dpm_table
->dpm_levels
[i
].value
,
1678 &(pp_table
->SocclkDid
[i
]),
1679 &(pp_table
->SocDpmVoltageIndex
[i
]));
1685 while (i
< NUM_SOCCLK_DPM_LEVELS
) {
1686 result
= vega10_populate_single_soc_level(hwmgr
,
1687 dpm_table
->dpm_levels
[j
].value
,
1688 &(pp_table
->SocclkDid
[i
]),
1689 &(pp_table
->SocDpmVoltageIndex
[i
]));
1698 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr
*hwmgr
)
1700 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1701 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
1702 struct phm_ppt_v2_information
*table_info
= hwmgr
->pptable
;
1703 struct phm_ppt_v1_voltage_lookup_table
*vddc_lookup_table
;
1705 uint8_t soc_vid
= 0;
1706 uint32_t i
, max_vddc_level
;
1708 if (hwmgr
->od_enabled
)
1709 vddc_lookup_table
= (struct phm_ppt_v1_voltage_lookup_table
*)&data
->odn_dpm_table
.vddc_lookup_table
;
1711 vddc_lookup_table
= table_info
->vddc_lookup_table
;
1713 max_vddc_level
= vddc_lookup_table
->count
;
1714 for (i
= 0; i
< max_vddc_level
; i
++) {
1715 soc_vid
= (uint8_t)convert_to_vid(vddc_lookup_table
->entries
[i
].us_vdd
);
1716 pp_table
->SocVid
[i
] = soc_vid
;
1718 while (i
< MAX_REGULAR_DPM_NUMBER
) {
1719 pp_table
->SocVid
[i
] = soc_vid
;
1725 * @brief Populates single SMC GFXCLK structure using the provided clock.
1727 * @param hwmgr - the address of the hardware manager.
1728 * @param mem_clock - the memory clock to use to populate the structure.
1729 * @return 0 on success..
1731 static int vega10_populate_single_memory_level(struct pp_hwmgr
*hwmgr
,
1732 uint32_t mem_clock
, uint8_t *current_mem_vid
,
1733 PllSetting_t
*current_memclk_level
, uint8_t *current_mem_soc_vind
)
1735 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1736 struct phm_ppt_v2_information
*table_info
=
1737 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
1738 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_on_mclk
;
1739 struct pp_atomfwctrl_clock_dividers_soc15 dividers
;
1740 uint32_t mem_max_clock
=
1741 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
;
1744 if (hwmgr
->od_enabled
)
1745 dep_on_mclk
= (struct phm_ppt_v1_clock_voltage_dependency_table
*)
1746 &data
->odn_dpm_table
.vdd_dep_on_mclk
;
1748 dep_on_mclk
= table_info
->vdd_dep_on_mclk
;
1750 PP_ASSERT_WITH_CODE(dep_on_mclk
,
1751 "Invalid SOC_VDD-UCLK Dependency Table!",
1754 if (data
->need_update_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
) {
1755 mem_clock
= mem_clock
> mem_max_clock
? mem_max_clock
: mem_clock
;
1757 for (i
= 0; i
< dep_on_mclk
->count
; i
++) {
1758 if (dep_on_mclk
->entries
[i
].clk
== mem_clock
)
1761 PP_ASSERT_WITH_CODE(dep_on_mclk
->count
> i
,
1762 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1766 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1767 hwmgr
, COMPUTE_GPUCLK_INPUT_FLAG_UCLK
, mem_clock
, ÷rs
),
1768 "Failed to get UCLK settings from VBIOS!",
1772 (uint8_t)(convert_to_vid(dep_on_mclk
->entries
[i
].mvdd
));
1773 *current_mem_soc_vind
=
1774 (uint8_t)(dep_on_mclk
->entries
[i
].vddInd
);
1775 current_memclk_level
->FbMult
= cpu_to_le32(dividers
.ulPll_fb_mult
);
1776 current_memclk_level
->Did
= (uint8_t)(dividers
.ulDid
);
1778 PP_ASSERT_WITH_CODE(current_memclk_level
->Did
>= 1,
1779 "Invalid Divider ID!",
1786 * @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
1788 * @param pHwMgr - the address of the hardware manager.
1789 * @return PP_Result_OK on success.
1791 static int vega10_populate_all_memory_levels(struct pp_hwmgr
*hwmgr
)
1793 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1794 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
1795 struct vega10_single_dpm_table
*dpm_table
=
1796 &(data
->dpm_table
.mem_table
);
1800 for (i
= 0; i
< dpm_table
->count
; i
++) {
1801 result
= vega10_populate_single_memory_level(hwmgr
,
1802 dpm_table
->dpm_levels
[i
].value
,
1803 &(pp_table
->MemVid
[i
]),
1804 &(pp_table
->UclkLevel
[i
]),
1805 &(pp_table
->MemSocVoltageIndex
[i
]));
1811 while (i
< NUM_UCLK_DPM_LEVELS
) {
1812 result
= vega10_populate_single_memory_level(hwmgr
,
1813 dpm_table
->dpm_levels
[j
].value
,
1814 &(pp_table
->MemVid
[i
]),
1815 &(pp_table
->UclkLevel
[i
]),
1816 &(pp_table
->MemSocVoltageIndex
[i
]));
1822 pp_table
->NumMemoryChannels
= (uint16_t)(data
->mem_channels
);
1823 pp_table
->MemoryChannelWidth
=
1824 (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH
*
1825 channel_number
[data
->mem_channels
]);
1827 pp_table
->LowestUclkReservedForUlv
=
1828 (uint8_t)(data
->lowest_uclk_reserved_for_ulv
);
1833 static int vega10_populate_single_display_type(struct pp_hwmgr
*hwmgr
,
1834 DSPCLK_e disp_clock
)
1836 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1837 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
1838 struct phm_ppt_v2_information
*table_info
=
1839 (struct phm_ppt_v2_information
*)
1841 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
;
1843 uint16_t clk
= 0, vddc
= 0;
1846 switch (disp_clock
) {
1847 case DSPCLK_DCEFCLK
:
1848 dep_table
= table_info
->vdd_dep_on_dcefclk
;
1850 case DSPCLK_DISPCLK
:
1851 dep_table
= table_info
->vdd_dep_on_dispclk
;
1854 dep_table
= table_info
->vdd_dep_on_pixclk
;
1857 dep_table
= table_info
->vdd_dep_on_phyclk
;
1863 PP_ASSERT_WITH_CODE(dep_table
->count
<= NUM_DSPCLK_LEVELS
,
1864 "Number Of Entries Exceeded maximum!",
1867 for (i
= 0; i
< dep_table
->count
; i
++) {
1868 clk
= (uint16_t)(dep_table
->entries
[i
].clk
/ 100);
1869 vddc
= table_info
->vddc_lookup_table
->
1870 entries
[dep_table
->entries
[i
].vddInd
].us_vdd
;
1871 vid
= (uint8_t)convert_to_vid(vddc
);
1872 pp_table
->DisplayClockTable
[disp_clock
][i
].Freq
=
1874 pp_table
->DisplayClockTable
[disp_clock
][i
].Vid
=
1878 while (i
< NUM_DSPCLK_LEVELS
) {
1879 pp_table
->DisplayClockTable
[disp_clock
][i
].Freq
=
1881 pp_table
->DisplayClockTable
[disp_clock
][i
].Vid
=
1889 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr
*hwmgr
)
1893 for (i
= 0; i
< DSPCLK_COUNT
; i
++) {
1894 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr
, i
),
1895 "Failed to populate Clock in DisplayClockTable!",
1902 static int vega10_populate_single_eclock_level(struct pp_hwmgr
*hwmgr
,
1903 uint32_t eclock
, uint8_t *current_eclk_did
,
1904 uint8_t *current_soc_vol
)
1906 struct phm_ppt_v2_information
*table_info
=
1907 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
1908 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*dep_table
=
1909 table_info
->mm_dep_table
;
1910 struct pp_atomfwctrl_clock_dividers_soc15 dividers
;
1913 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr
,
1914 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
1916 "Failed to get ECLK clock settings from VBIOS!",
1919 *current_eclk_did
= (uint8_t)dividers
.ulDid
;
1921 for (i
= 0; i
< dep_table
->count
; i
++) {
1922 if (dep_table
->entries
[i
].eclk
== eclock
)
1923 *current_soc_vol
= dep_table
->entries
[i
].vddcInd
;
1929 static int vega10_populate_smc_vce_levels(struct pp_hwmgr
*hwmgr
)
1931 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1932 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
1933 struct vega10_single_dpm_table
*dpm_table
= &(data
->dpm_table
.eclk_table
);
1934 int result
= -EINVAL
;
1937 for (i
= 0; i
< dpm_table
->count
; i
++) {
1938 result
= vega10_populate_single_eclock_level(hwmgr
,
1939 dpm_table
->dpm_levels
[i
].value
,
1940 &(pp_table
->EclkDid
[i
]),
1941 &(pp_table
->VceDpmVoltageIndex
[i
]));
1947 while (i
< NUM_VCE_DPM_LEVELS
) {
1948 result
= vega10_populate_single_eclock_level(hwmgr
,
1949 dpm_table
->dpm_levels
[j
].value
,
1950 &(pp_table
->EclkDid
[i
]),
1951 &(pp_table
->VceDpmVoltageIndex
[i
]));
1960 static int vega10_populate_single_vclock_level(struct pp_hwmgr
*hwmgr
,
1961 uint32_t vclock
, uint8_t *current_vclk_did
)
1963 struct pp_atomfwctrl_clock_dividers_soc15 dividers
;
1965 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr
,
1966 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
1968 "Failed to get VCLK clock settings from VBIOS!",
1971 *current_vclk_did
= (uint8_t)dividers
.ulDid
;
1976 static int vega10_populate_single_dclock_level(struct pp_hwmgr
*hwmgr
,
1977 uint32_t dclock
, uint8_t *current_dclk_did
)
1979 struct pp_atomfwctrl_clock_dividers_soc15 dividers
;
1981 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr
,
1982 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
1984 "Failed to get DCLK clock settings from VBIOS!",
1987 *current_dclk_did
= (uint8_t)dividers
.ulDid
;
1992 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr
*hwmgr
)
1994 struct vega10_hwmgr
*data
= hwmgr
->backend
;
1995 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
1996 struct vega10_single_dpm_table
*vclk_dpm_table
=
1997 &(data
->dpm_table
.vclk_table
);
1998 struct vega10_single_dpm_table
*dclk_dpm_table
=
1999 &(data
->dpm_table
.dclk_table
);
2000 struct phm_ppt_v2_information
*table_info
=
2001 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
2002 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*dep_table
=
2003 table_info
->mm_dep_table
;
2004 int result
= -EINVAL
;
2007 for (i
= 0; i
< vclk_dpm_table
->count
; i
++) {
2008 result
= vega10_populate_single_vclock_level(hwmgr
,
2009 vclk_dpm_table
->dpm_levels
[i
].value
,
2010 &(pp_table
->VclkDid
[i
]));
2016 while (i
< NUM_UVD_DPM_LEVELS
) {
2017 result
= vega10_populate_single_vclock_level(hwmgr
,
2018 vclk_dpm_table
->dpm_levels
[j
].value
,
2019 &(pp_table
->VclkDid
[i
]));
2025 for (i
= 0; i
< dclk_dpm_table
->count
; i
++) {
2026 result
= vega10_populate_single_dclock_level(hwmgr
,
2027 dclk_dpm_table
->dpm_levels
[i
].value
,
2028 &(pp_table
->DclkDid
[i
]));
2034 while (i
< NUM_UVD_DPM_LEVELS
) {
2035 result
= vega10_populate_single_dclock_level(hwmgr
,
2036 dclk_dpm_table
->dpm_levels
[j
].value
,
2037 &(pp_table
->DclkDid
[i
]));
2043 for (i
= 0; i
< dep_table
->count
; i
++) {
2044 if (dep_table
->entries
[i
].vclk
==
2045 vclk_dpm_table
->dpm_levels
[i
].value
&&
2046 dep_table
->entries
[i
].dclk
==
2047 dclk_dpm_table
->dpm_levels
[i
].value
)
2048 pp_table
->UvdDpmVoltageIndex
[i
] =
2049 dep_table
->entries
[i
].vddcInd
;
2055 while (i
< NUM_UVD_DPM_LEVELS
) {
2056 pp_table
->UvdDpmVoltageIndex
[i
] = dep_table
->entries
[j
].vddcInd
;
2063 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr
*hwmgr
)
2065 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2066 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
2067 struct phm_ppt_v2_information
*table_info
=
2068 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
2069 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
=
2070 table_info
->vdd_dep_on_sclk
;
2073 for (i
= 0; i
< dep_table
->count
; i
++) {
2074 pp_table
->CksEnable
[i
] = dep_table
->entries
[i
].cks_enable
;
2075 pp_table
->CksVidOffset
[i
] = (uint8_t)(dep_table
->entries
[i
].cks_voffset
2076 * VOLTAGE_VID_OFFSET_SCALE2
/ VOLTAGE_VID_OFFSET_SCALE1
);
2082 static int vega10_populate_avfs_parameters(struct pp_hwmgr
*hwmgr
)
2084 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2085 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
2086 struct phm_ppt_v2_information
*table_info
=
2087 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
2088 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
=
2089 table_info
->vdd_dep_on_sclk
;
2090 struct pp_atomfwctrl_avfs_parameters avfs_params
= {0};
2094 pp_table
->MinVoltageVid
= (uint8_t)0xff;
2095 pp_table
->MaxVoltageVid
= (uint8_t)0;
2097 if (data
->smu_features
[GNLD_AVFS
].supported
) {
2098 result
= pp_atomfwctrl_get_avfs_information(hwmgr
, &avfs_params
);
2100 pp_table
->MinVoltageVid
= (uint8_t)
2101 convert_to_vid((uint16_t)(avfs_params
.ulMinVddc
));
2102 pp_table
->MaxVoltageVid
= (uint8_t)
2103 convert_to_vid((uint16_t)(avfs_params
.ulMaxVddc
));
2105 pp_table
->AConstant
[0] = cpu_to_le32(avfs_params
.ulMeanNsigmaAcontant0
);
2106 pp_table
->AConstant
[1] = cpu_to_le32(avfs_params
.ulMeanNsigmaAcontant1
);
2107 pp_table
->AConstant
[2] = cpu_to_le32(avfs_params
.ulMeanNsigmaAcontant2
);
2108 pp_table
->DC_tol_sigma
= cpu_to_le16(avfs_params
.usMeanNsigmaDcTolSigma
);
2109 pp_table
->Platform_mean
= cpu_to_le16(avfs_params
.usMeanNsigmaPlatformMean
);
2110 pp_table
->Platform_sigma
= cpu_to_le16(avfs_params
.usMeanNsigmaDcTolSigma
);
2111 pp_table
->PSM_Age_CompFactor
= cpu_to_le16(avfs_params
.usPsmAgeComfactor
);
2113 pp_table
->BtcGbVdroopTableCksOff
.a0
=
2114 cpu_to_le32(avfs_params
.ulGbVdroopTableCksoffA0
);
2115 pp_table
->BtcGbVdroopTableCksOff
.a0_shift
= 20;
2116 pp_table
->BtcGbVdroopTableCksOff
.a1
=
2117 cpu_to_le32(avfs_params
.ulGbVdroopTableCksoffA1
);
2118 pp_table
->BtcGbVdroopTableCksOff
.a1_shift
= 20;
2119 pp_table
->BtcGbVdroopTableCksOff
.a2
=
2120 cpu_to_le32(avfs_params
.ulGbVdroopTableCksoffA2
);
2121 pp_table
->BtcGbVdroopTableCksOff
.a2_shift
= 20;
2123 pp_table
->OverrideBtcGbCksOn
= avfs_params
.ucEnableGbVdroopTableCkson
;
2124 pp_table
->BtcGbVdroopTableCksOn
.a0
=
2125 cpu_to_le32(avfs_params
.ulGbVdroopTableCksonA0
);
2126 pp_table
->BtcGbVdroopTableCksOn
.a0_shift
= 20;
2127 pp_table
->BtcGbVdroopTableCksOn
.a1
=
2128 cpu_to_le32(avfs_params
.ulGbVdroopTableCksonA1
);
2129 pp_table
->BtcGbVdroopTableCksOn
.a1_shift
= 20;
2130 pp_table
->BtcGbVdroopTableCksOn
.a2
=
2131 cpu_to_le32(avfs_params
.ulGbVdroopTableCksonA2
);
2132 pp_table
->BtcGbVdroopTableCksOn
.a2_shift
= 20;
2134 pp_table
->AvfsGbCksOn
.m1
=
2135 cpu_to_le32(avfs_params
.ulGbFuseTableCksonM1
);
2136 pp_table
->AvfsGbCksOn
.m2
=
2137 cpu_to_le32(avfs_params
.ulGbFuseTableCksonM2
);
2138 pp_table
->AvfsGbCksOn
.b
=
2139 cpu_to_le32(avfs_params
.ulGbFuseTableCksonB
);
2140 pp_table
->AvfsGbCksOn
.m1_shift
= 24;
2141 pp_table
->AvfsGbCksOn
.m2_shift
= 12;
2142 pp_table
->AvfsGbCksOn
.b_shift
= 0;
2144 pp_table
->OverrideAvfsGbCksOn
=
2145 avfs_params
.ucEnableGbFuseTableCkson
;
2146 pp_table
->AvfsGbCksOff
.m1
=
2147 cpu_to_le32(avfs_params
.ulGbFuseTableCksoffM1
);
2148 pp_table
->AvfsGbCksOff
.m2
=
2149 cpu_to_le32(avfs_params
.ulGbFuseTableCksoffM2
);
2150 pp_table
->AvfsGbCksOff
.b
=
2151 cpu_to_le32(avfs_params
.ulGbFuseTableCksoffB
);
2152 pp_table
->AvfsGbCksOff
.m1_shift
= 24;
2153 pp_table
->AvfsGbCksOff
.m2_shift
= 12;
2154 pp_table
->AvfsGbCksOff
.b_shift
= 0;
2156 for (i
= 0; i
< dep_table
->count
; i
++)
2157 pp_table
->StaticVoltageOffsetVid
[i
] =
2158 convert_to_vid((uint8_t)(dep_table
->entries
[i
].sclk_offset
));
2160 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
!=
2161 data
->disp_clk_quad_eqn_a
) &&
2162 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
!=
2163 data
->disp_clk_quad_eqn_b
)) {
2164 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DISPCLK
].m1
=
2165 (int32_t)data
->disp_clk_quad_eqn_a
;
2166 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DISPCLK
].m2
=
2167 (int32_t)data
->disp_clk_quad_eqn_b
;
2168 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DISPCLK
].b
=
2169 (int32_t)data
->disp_clk_quad_eqn_c
;
2171 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DISPCLK
].m1
=
2172 (int32_t)avfs_params
.ulDispclk2GfxclkM1
;
2173 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DISPCLK
].m2
=
2174 (int32_t)avfs_params
.ulDispclk2GfxclkM2
;
2175 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DISPCLK
].b
=
2176 (int32_t)avfs_params
.ulDispclk2GfxclkB
;
2179 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DISPCLK
].m1_shift
= 24;
2180 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DISPCLK
].m2_shift
= 12;
2181 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DISPCLK
].b_shift
= 12;
2183 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
!=
2184 data
->dcef_clk_quad_eqn_a
) &&
2185 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
!=
2186 data
->dcef_clk_quad_eqn_b
)) {
2187 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DCEFCLK
].m1
=
2188 (int32_t)data
->dcef_clk_quad_eqn_a
;
2189 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DCEFCLK
].m2
=
2190 (int32_t)data
->dcef_clk_quad_eqn_b
;
2191 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DCEFCLK
].b
=
2192 (int32_t)data
->dcef_clk_quad_eqn_c
;
2194 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DCEFCLK
].m1
=
2195 (int32_t)avfs_params
.ulDcefclk2GfxclkM1
;
2196 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DCEFCLK
].m2
=
2197 (int32_t)avfs_params
.ulDcefclk2GfxclkM2
;
2198 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DCEFCLK
].b
=
2199 (int32_t)avfs_params
.ulDcefclk2GfxclkB
;
2202 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DCEFCLK
].m1_shift
= 24;
2203 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DCEFCLK
].m2_shift
= 12;
2204 pp_table
->DisplayClock2Gfxclk
[DSPCLK_DCEFCLK
].b_shift
= 12;
2206 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
!=
2207 data
->pixel_clk_quad_eqn_a
) &&
2208 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
!=
2209 data
->pixel_clk_quad_eqn_b
)) {
2210 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PIXCLK
].m1
=
2211 (int32_t)data
->pixel_clk_quad_eqn_a
;
2212 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PIXCLK
].m2
=
2213 (int32_t)data
->pixel_clk_quad_eqn_b
;
2214 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PIXCLK
].b
=
2215 (int32_t)data
->pixel_clk_quad_eqn_c
;
2217 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PIXCLK
].m1
=
2218 (int32_t)avfs_params
.ulPixelclk2GfxclkM1
;
2219 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PIXCLK
].m2
=
2220 (int32_t)avfs_params
.ulPixelclk2GfxclkM2
;
2221 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PIXCLK
].b
=
2222 (int32_t)avfs_params
.ulPixelclk2GfxclkB
;
2225 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PIXCLK
].m1_shift
= 24;
2226 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PIXCLK
].m2_shift
= 12;
2227 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PIXCLK
].b_shift
= 12;
2228 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
!=
2229 data
->phy_clk_quad_eqn_a
) &&
2230 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
!=
2231 data
->phy_clk_quad_eqn_b
)) {
2232 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PHYCLK
].m1
=
2233 (int32_t)data
->phy_clk_quad_eqn_a
;
2234 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PHYCLK
].m2
=
2235 (int32_t)data
->phy_clk_quad_eqn_b
;
2236 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PHYCLK
].b
=
2237 (int32_t)data
->phy_clk_quad_eqn_c
;
2239 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PHYCLK
].m1
=
2240 (int32_t)avfs_params
.ulPhyclk2GfxclkM1
;
2241 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PHYCLK
].m2
=
2242 (int32_t)avfs_params
.ulPhyclk2GfxclkM2
;
2243 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PHYCLK
].b
=
2244 (int32_t)avfs_params
.ulPhyclk2GfxclkB
;
2247 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PHYCLK
].m1_shift
= 24;
2248 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PHYCLK
].m2_shift
= 12;
2249 pp_table
->DisplayClock2Gfxclk
[DSPCLK_PHYCLK
].b_shift
= 12;
2251 pp_table
->AcgBtcGbVdroopTable
.a0
= avfs_params
.ulAcgGbVdroopTableA0
;
2252 pp_table
->AcgBtcGbVdroopTable
.a0_shift
= 20;
2253 pp_table
->AcgBtcGbVdroopTable
.a1
= avfs_params
.ulAcgGbVdroopTableA1
;
2254 pp_table
->AcgBtcGbVdroopTable
.a1_shift
= 20;
2255 pp_table
->AcgBtcGbVdroopTable
.a2
= avfs_params
.ulAcgGbVdroopTableA2
;
2256 pp_table
->AcgBtcGbVdroopTable
.a2_shift
= 20;
2258 pp_table
->AcgAvfsGb
.m1
= avfs_params
.ulAcgGbFuseTableM1
;
2259 pp_table
->AcgAvfsGb
.m2
= avfs_params
.ulAcgGbFuseTableM2
;
2260 pp_table
->AcgAvfsGb
.b
= avfs_params
.ulAcgGbFuseTableB
;
2261 pp_table
->AcgAvfsGb
.m1_shift
= 0;
2262 pp_table
->AcgAvfsGb
.m2_shift
= 0;
2263 pp_table
->AcgAvfsGb
.b_shift
= 0;
2266 data
->smu_features
[GNLD_AVFS
].supported
= false;
2273 static int vega10_acg_enable(struct pp_hwmgr
*hwmgr
)
2275 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2276 uint32_t agc_btc_response
;
2278 if (data
->smu_features
[GNLD_ACG
].supported
) {
2279 if (0 == vega10_enable_smc_features(hwmgr
, true,
2280 data
->smu_features
[GNLD_DPM_PREFETCHER
].smu_feature_bitmap
))
2281 data
->smu_features
[GNLD_DPM_PREFETCHER
].enabled
= true;
2283 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_InitializeAcg
);
2285 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_RunAcgBtc
);
2286 agc_btc_response
= smum_get_argument(hwmgr
);
2288 if (1 == agc_btc_response
) {
2289 if (1 == data
->acg_loop_state
)
2290 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_RunAcgInClosedLoop
);
2291 else if (2 == data
->acg_loop_state
)
2292 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_RunAcgInOpenLoop
);
2293 if (0 == vega10_enable_smc_features(hwmgr
, true,
2294 data
->smu_features
[GNLD_ACG
].smu_feature_bitmap
))
2295 data
->smu_features
[GNLD_ACG
].enabled
= true;
2297 pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2298 data
->smu_features
[GNLD_ACG
].enabled
= false;
2305 static int vega10_acg_disable(struct pp_hwmgr
*hwmgr
)
2307 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2309 if (data
->smu_features
[GNLD_ACG
].supported
&&
2310 data
->smu_features
[GNLD_ACG
].enabled
)
2311 if (!vega10_enable_smc_features(hwmgr
, false,
2312 data
->smu_features
[GNLD_ACG
].smu_feature_bitmap
))
2313 data
->smu_features
[GNLD_ACG
].enabled
= false;
2318 static int vega10_populate_gpio_parameters(struct pp_hwmgr
*hwmgr
)
2320 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2321 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
2322 struct pp_atomfwctrl_gpio_parameters gpio_params
= {0};
2325 result
= pp_atomfwctrl_get_gpio_information(hwmgr
, &gpio_params
);
2327 if (PP_CAP(PHM_PlatformCaps_RegulatorHot
) &&
2328 data
->registry_data
.regulator_hot_gpio_support
) {
2329 pp_table
->VR0HotGpio
= gpio_params
.ucVR0HotGpio
;
2330 pp_table
->VR0HotPolarity
= gpio_params
.ucVR0HotPolarity
;
2331 pp_table
->VR1HotGpio
= gpio_params
.ucVR1HotGpio
;
2332 pp_table
->VR1HotPolarity
= gpio_params
.ucVR1HotPolarity
;
2334 pp_table
->VR0HotGpio
= 0;
2335 pp_table
->VR0HotPolarity
= 0;
2336 pp_table
->VR1HotGpio
= 0;
2337 pp_table
->VR1HotPolarity
= 0;
2340 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition
) &&
2341 data
->registry_data
.ac_dc_switch_gpio_support
) {
2342 pp_table
->AcDcGpio
= gpio_params
.ucAcDcGpio
;
2343 pp_table
->AcDcPolarity
= gpio_params
.ucAcDcPolarity
;
2345 pp_table
->AcDcGpio
= 0;
2346 pp_table
->AcDcPolarity
= 0;
2353 static int vega10_avfs_enable(struct pp_hwmgr
*hwmgr
, bool enable
)
2355 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2357 if (data
->smu_features
[GNLD_AVFS
].supported
) {
2359 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2361 data
->smu_features
[GNLD_AVFS
].smu_feature_bitmap
),
2362 "[avfs_control] Attempt to Enable AVFS feature Failed!",
2364 data
->smu_features
[GNLD_AVFS
].enabled
= true;
2366 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2368 data
->smu_features
[GNLD_AVFS
].smu_feature_bitmap
),
2369 "[avfs_control] Attempt to Disable AVFS feature Failed!",
2371 data
->smu_features
[GNLD_AVFS
].enabled
= false;
2378 static int vega10_update_avfs(struct pp_hwmgr
*hwmgr
)
2380 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2382 if (data
->need_update_dpm_table
& DPMTABLE_OD_UPDATE_VDDC
) {
2383 vega10_avfs_enable(hwmgr
, false);
2384 } else if (data
->need_update_dpm_table
) {
2385 vega10_avfs_enable(hwmgr
, false);
2386 vega10_avfs_enable(hwmgr
, true);
2388 vega10_avfs_enable(hwmgr
, true);
2394 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr
*hwmgr
)
2398 uint64_t serial_number
= 0;
2399 uint32_t top32
, bottom32
;
2400 struct phm_fuses_default fuse
;
2402 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2403 AvfsFuseOverride_t
*avfs_fuse_table
= &(data
->smc_state_table
.avfs_fuse_override_table
);
2405 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_ReadSerialNumTop32
);
2406 top32
= smum_get_argument(hwmgr
);
2408 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_ReadSerialNumBottom32
);
2409 bottom32
= smum_get_argument(hwmgr
);
2411 serial_number
= ((uint64_t)bottom32
<< 32) | top32
;
2413 if (pp_override_get_default_fuse_value(serial_number
, &fuse
) == 0) {
2414 avfs_fuse_table
->VFT0_b
= fuse
.VFT0_b
;
2415 avfs_fuse_table
->VFT0_m1
= fuse
.VFT0_m1
;
2416 avfs_fuse_table
->VFT0_m2
= fuse
.VFT0_m2
;
2417 avfs_fuse_table
->VFT1_b
= fuse
.VFT1_b
;
2418 avfs_fuse_table
->VFT1_m1
= fuse
.VFT1_m1
;
2419 avfs_fuse_table
->VFT1_m2
= fuse
.VFT1_m2
;
2420 avfs_fuse_table
->VFT2_b
= fuse
.VFT2_b
;
2421 avfs_fuse_table
->VFT2_m1
= fuse
.VFT2_m1
;
2422 avfs_fuse_table
->VFT2_m2
= fuse
.VFT2_m2
;
2423 result
= smum_smc_table_manager(hwmgr
, (uint8_t *)avfs_fuse_table
,
2424 AVFSFUSETABLE
, false);
2425 PP_ASSERT_WITH_CODE(!result
,
2426 "Failed to upload FuseOVerride!",
2433 static void vega10_check_dpm_table_updated(struct pp_hwmgr
*hwmgr
)
2435 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2436 struct vega10_odn_dpm_table
*odn_table
= &(data
->odn_dpm_table
);
2437 struct phm_ppt_v2_information
*table_info
= hwmgr
->pptable
;
2438 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
;
2439 struct phm_ppt_v1_clock_voltage_dependency_table
*odn_dep_table
;
2442 dep_table
= table_info
->vdd_dep_on_mclk
;
2443 odn_dep_table
= (struct phm_ppt_v1_clock_voltage_dependency_table
*)&(odn_table
->vdd_dep_on_mclk
);
2445 for (i
= 0; i
< dep_table
->count
; i
++) {
2446 if (dep_table
->entries
[i
].vddc
!= odn_dep_table
->entries
[i
].vddc
) {
2447 data
->need_update_dpm_table
|= DPMTABLE_OD_UPDATE_VDDC
| DPMTABLE_OD_UPDATE_MCLK
;
2452 dep_table
= table_info
->vdd_dep_on_sclk
;
2453 odn_dep_table
= (struct phm_ppt_v1_clock_voltage_dependency_table
*)&(odn_table
->vdd_dep_on_sclk
);
2454 for (i
= 0; i
< dep_table
->count
; i
++) {
2455 if (dep_table
->entries
[i
].vddc
!= odn_dep_table
->entries
[i
].vddc
) {
2456 data
->need_update_dpm_table
|= DPMTABLE_OD_UPDATE_VDDC
| DPMTABLE_OD_UPDATE_SCLK
;
2461 if (data
->need_update_dpm_table
& DPMTABLE_OD_UPDATE_VDDC
) {
2462 data
->need_update_dpm_table
&= ~DPMTABLE_OD_UPDATE_VDDC
;
2463 data
->need_update_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
| DPMTABLE_OD_UPDATE_MCLK
;
2468 * Initializes the SMC table and uploads it
2470 * @param hwmgr the address of the powerplay hardware manager.
2471 * @param pInput the pointer to input data (PowerState)
2474 static int vega10_init_smc_table(struct pp_hwmgr
*hwmgr
)
2477 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2478 struct phm_ppt_v2_information
*table_info
=
2479 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
2480 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
2481 struct pp_atomfwctrl_voltage_table voltage_table
;
2482 struct pp_atomfwctrl_bios_boot_up_values boot_up_values
;
2483 struct vega10_odn_dpm_table
*odn_table
= &(data
->odn_dpm_table
);
2485 result
= vega10_setup_default_dpm_tables(hwmgr
);
2486 PP_ASSERT_WITH_CODE(!result
,
2487 "Failed to setup default DPM tables!",
2490 /* initialize ODN table */
2491 if (hwmgr
->od_enabled
) {
2492 if (odn_table
->max_vddc
) {
2493 data
->need_update_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
| DPMTABLE_OD_UPDATE_MCLK
;
2494 vega10_check_dpm_table_updated(hwmgr
);
2496 vega10_odn_initial_default_setting(hwmgr
);
2500 pp_atomfwctrl_get_voltage_table_v4(hwmgr
, VOLTAGE_TYPE_VDDC
,
2501 VOLTAGE_OBJ_SVID2
, &voltage_table
);
2502 pp_table
->MaxVidStep
= voltage_table
.max_vid_step
;
2504 pp_table
->GfxDpmVoltageMode
=
2505 (uint8_t)(table_info
->uc_gfx_dpm_voltage_mode
);
2506 pp_table
->SocDpmVoltageMode
=
2507 (uint8_t)(table_info
->uc_soc_dpm_voltage_mode
);
2508 pp_table
->UclkDpmVoltageMode
=
2509 (uint8_t)(table_info
->uc_uclk_dpm_voltage_mode
);
2510 pp_table
->UvdDpmVoltageMode
=
2511 (uint8_t)(table_info
->uc_uvd_dpm_voltage_mode
);
2512 pp_table
->VceDpmVoltageMode
=
2513 (uint8_t)(table_info
->uc_vce_dpm_voltage_mode
);
2514 pp_table
->Mp0DpmVoltageMode
=
2515 (uint8_t)(table_info
->uc_mp0_dpm_voltage_mode
);
2517 pp_table
->DisplayDpmVoltageMode
=
2518 (uint8_t)(table_info
->uc_dcef_dpm_voltage_mode
);
2520 data
->vddc_voltage_table
.psi0_enable
= voltage_table
.psi0_enable
;
2521 data
->vddc_voltage_table
.psi1_enable
= voltage_table
.psi1_enable
;
2523 if (data
->registry_data
.ulv_support
&&
2524 table_info
->us_ulv_voltage_offset
) {
2525 result
= vega10_populate_ulv_state(hwmgr
);
2526 PP_ASSERT_WITH_CODE(!result
,
2527 "Failed to initialize ULV state!",
2531 result
= vega10_populate_smc_link_levels(hwmgr
);
2532 PP_ASSERT_WITH_CODE(!result
,
2533 "Failed to initialize Link Level!",
2536 result
= vega10_populate_all_graphic_levels(hwmgr
);
2537 PP_ASSERT_WITH_CODE(!result
,
2538 "Failed to initialize Graphics Level!",
2541 result
= vega10_populate_all_memory_levels(hwmgr
);
2542 PP_ASSERT_WITH_CODE(!result
,
2543 "Failed to initialize Memory Level!",
2546 vega10_populate_vddc_soc_levels(hwmgr
);
2548 result
= vega10_populate_all_display_clock_levels(hwmgr
);
2549 PP_ASSERT_WITH_CODE(!result
,
2550 "Failed to initialize Display Level!",
2553 result
= vega10_populate_smc_vce_levels(hwmgr
);
2554 PP_ASSERT_WITH_CODE(!result
,
2555 "Failed to initialize VCE Level!",
2558 result
= vega10_populate_smc_uvd_levels(hwmgr
);
2559 PP_ASSERT_WITH_CODE(!result
,
2560 "Failed to initialize UVD Level!",
2563 if (data
->registry_data
.clock_stretcher_support
) {
2564 result
= vega10_populate_clock_stretcher_table(hwmgr
);
2565 PP_ASSERT_WITH_CODE(!result
,
2566 "Failed to populate Clock Stretcher Table!",
2570 result
= pp_atomfwctrl_get_vbios_bootup_values(hwmgr
, &boot_up_values
);
2572 data
->vbios_boot_state
.vddc
= boot_up_values
.usVddc
;
2573 data
->vbios_boot_state
.vddci
= boot_up_values
.usVddci
;
2574 data
->vbios_boot_state
.mvddc
= boot_up_values
.usMvddc
;
2575 data
->vbios_boot_state
.gfx_clock
= boot_up_values
.ulGfxClk
;
2576 data
->vbios_boot_state
.mem_clock
= boot_up_values
.ulUClk
;
2577 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr
,
2578 SMU9_SYSPLL0_SOCCLK_ID
, &boot_up_values
.ulSocClk
);
2580 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr
,
2581 SMU9_SYSPLL0_DCEFCLK_ID
, &boot_up_values
.ulDCEFClk
);
2583 data
->vbios_boot_state
.soc_clock
= boot_up_values
.ulSocClk
;
2584 data
->vbios_boot_state
.dcef_clock
= boot_up_values
.ulDCEFClk
;
2585 if (0 != boot_up_values
.usVddc
) {
2586 smum_send_msg_to_smc_with_parameter(hwmgr
,
2587 PPSMC_MSG_SetFloorSocVoltage
,
2588 (boot_up_values
.usVddc
* 4));
2589 data
->vbios_boot_state
.bsoc_vddc_lock
= true;
2591 data
->vbios_boot_state
.bsoc_vddc_lock
= false;
2593 smum_send_msg_to_smc_with_parameter(hwmgr
,
2594 PPSMC_MSG_SetMinDeepSleepDcefclk
,
2595 (uint32_t)(data
->vbios_boot_state
.dcef_clock
/ 100));
2598 result
= vega10_populate_avfs_parameters(hwmgr
);
2599 PP_ASSERT_WITH_CODE(!result
,
2600 "Failed to initialize AVFS Parameters!",
2603 result
= vega10_populate_gpio_parameters(hwmgr
);
2604 PP_ASSERT_WITH_CODE(!result
,
2605 "Failed to initialize GPIO Parameters!",
2608 pp_table
->GfxclkAverageAlpha
= (uint8_t)
2609 (data
->gfxclk_average_alpha
);
2610 pp_table
->SocclkAverageAlpha
= (uint8_t)
2611 (data
->socclk_average_alpha
);
2612 pp_table
->UclkAverageAlpha
= (uint8_t)
2613 (data
->uclk_average_alpha
);
2614 pp_table
->GfxActivityAverageAlpha
= (uint8_t)
2615 (data
->gfx_activity_average_alpha
);
2617 vega10_populate_and_upload_avfs_fuse_override(hwmgr
);
2619 result
= smum_smc_table_manager(hwmgr
, (uint8_t *)pp_table
, PPTABLE
, false);
2621 PP_ASSERT_WITH_CODE(!result
,
2622 "Failed to upload PPtable!", return result
);
2624 result
= vega10_avfs_enable(hwmgr
, true);
2625 PP_ASSERT_WITH_CODE(!result
, "Attempt to enable AVFS feature Failed!",
2627 vega10_acg_enable(hwmgr
);
2632 static int vega10_enable_thermal_protection(struct pp_hwmgr
*hwmgr
)
2634 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2636 if (data
->smu_features
[GNLD_THERMAL
].supported
) {
2637 if (data
->smu_features
[GNLD_THERMAL
].enabled
)
2638 pr_info("THERMAL Feature Already enabled!");
2640 PP_ASSERT_WITH_CODE(
2641 !vega10_enable_smc_features(hwmgr
,
2643 data
->smu_features
[GNLD_THERMAL
].smu_feature_bitmap
),
2644 "Enable THERMAL Feature Failed!",
2646 data
->smu_features
[GNLD_THERMAL
].enabled
= true;
2652 static int vega10_disable_thermal_protection(struct pp_hwmgr
*hwmgr
)
2654 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2656 if (data
->smu_features
[GNLD_THERMAL
].supported
) {
2657 if (!data
->smu_features
[GNLD_THERMAL
].enabled
)
2658 pr_info("THERMAL Feature Already disabled!");
2660 PP_ASSERT_WITH_CODE(
2661 !vega10_enable_smc_features(hwmgr
,
2663 data
->smu_features
[GNLD_THERMAL
].smu_feature_bitmap
),
2664 "disable THERMAL Feature Failed!",
2666 data
->smu_features
[GNLD_THERMAL
].enabled
= false;
2672 static int vega10_enable_vrhot_feature(struct pp_hwmgr
*hwmgr
)
2674 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2676 if (PP_CAP(PHM_PlatformCaps_RegulatorHot
)) {
2677 if (data
->smu_features
[GNLD_VR0HOT
].supported
) {
2678 PP_ASSERT_WITH_CODE(
2679 !vega10_enable_smc_features(hwmgr
,
2681 data
->smu_features
[GNLD_VR0HOT
].smu_feature_bitmap
),
2682 "Attempt to Enable VR0 Hot feature Failed!",
2684 data
->smu_features
[GNLD_VR0HOT
].enabled
= true;
2686 if (data
->smu_features
[GNLD_VR1HOT
].supported
) {
2687 PP_ASSERT_WITH_CODE(
2688 !vega10_enable_smc_features(hwmgr
,
2690 data
->smu_features
[GNLD_VR1HOT
].smu_feature_bitmap
),
2691 "Attempt to Enable VR0 Hot feature Failed!",
2693 data
->smu_features
[GNLD_VR1HOT
].enabled
= true;
2700 static int vega10_enable_ulv(struct pp_hwmgr
*hwmgr
)
2702 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2704 if (data
->registry_data
.ulv_support
) {
2705 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2706 true, data
->smu_features
[GNLD_ULV
].smu_feature_bitmap
),
2707 "Enable ULV Feature Failed!",
2709 data
->smu_features
[GNLD_ULV
].enabled
= true;
2715 static int vega10_disable_ulv(struct pp_hwmgr
*hwmgr
)
2717 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2719 if (data
->registry_data
.ulv_support
) {
2720 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2721 false, data
->smu_features
[GNLD_ULV
].smu_feature_bitmap
),
2722 "disable ULV Feature Failed!",
2724 data
->smu_features
[GNLD_ULV
].enabled
= false;
2730 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr
*hwmgr
)
2732 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2734 if (data
->smu_features
[GNLD_DS_GFXCLK
].supported
) {
2735 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2736 true, data
->smu_features
[GNLD_DS_GFXCLK
].smu_feature_bitmap
),
2737 "Attempt to Enable DS_GFXCLK Feature Failed!",
2739 data
->smu_features
[GNLD_DS_GFXCLK
].enabled
= true;
2742 if (data
->smu_features
[GNLD_DS_SOCCLK
].supported
) {
2743 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2744 true, data
->smu_features
[GNLD_DS_SOCCLK
].smu_feature_bitmap
),
2745 "Attempt to Enable DS_SOCCLK Feature Failed!",
2747 data
->smu_features
[GNLD_DS_SOCCLK
].enabled
= true;
2750 if (data
->smu_features
[GNLD_DS_LCLK
].supported
) {
2751 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2752 true, data
->smu_features
[GNLD_DS_LCLK
].smu_feature_bitmap
),
2753 "Attempt to Enable DS_LCLK Feature Failed!",
2755 data
->smu_features
[GNLD_DS_LCLK
].enabled
= true;
2758 if (data
->smu_features
[GNLD_DS_DCEFCLK
].supported
) {
2759 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2760 true, data
->smu_features
[GNLD_DS_DCEFCLK
].smu_feature_bitmap
),
2761 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2763 data
->smu_features
[GNLD_DS_DCEFCLK
].enabled
= true;
2769 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr
*hwmgr
)
2771 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2773 if (data
->smu_features
[GNLD_DS_GFXCLK
].supported
) {
2774 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2775 false, data
->smu_features
[GNLD_DS_GFXCLK
].smu_feature_bitmap
),
2776 "Attempt to disable DS_GFXCLK Feature Failed!",
2778 data
->smu_features
[GNLD_DS_GFXCLK
].enabled
= false;
2781 if (data
->smu_features
[GNLD_DS_SOCCLK
].supported
) {
2782 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2783 false, data
->smu_features
[GNLD_DS_SOCCLK
].smu_feature_bitmap
),
2784 "Attempt to disable DS_ Feature Failed!",
2786 data
->smu_features
[GNLD_DS_SOCCLK
].enabled
= false;
2789 if (data
->smu_features
[GNLD_DS_LCLK
].supported
) {
2790 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2791 false, data
->smu_features
[GNLD_DS_LCLK
].smu_feature_bitmap
),
2792 "Attempt to disable DS_LCLK Feature Failed!",
2794 data
->smu_features
[GNLD_DS_LCLK
].enabled
= false;
2797 if (data
->smu_features
[GNLD_DS_DCEFCLK
].supported
) {
2798 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2799 false, data
->smu_features
[GNLD_DS_DCEFCLK
].smu_feature_bitmap
),
2800 "Attempt to disable DS_DCEFCLK Feature Failed!",
2802 data
->smu_features
[GNLD_DS_DCEFCLK
].enabled
= false;
2808 static int vega10_stop_dpm(struct pp_hwmgr
*hwmgr
, uint32_t bitmap
)
2810 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2811 uint32_t i
, feature_mask
= 0;
2814 if(data
->smu_features
[GNLD_LED_DISPLAY
].supported
== true){
2815 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2816 false, data
->smu_features
[GNLD_LED_DISPLAY
].smu_feature_bitmap
),
2817 "Attempt to disable LED DPM feature failed!", return -EINVAL
);
2818 data
->smu_features
[GNLD_LED_DISPLAY
].enabled
= false;
2821 for (i
= 0; i
< GNLD_DPM_MAX
; i
++) {
2822 if (data
->smu_features
[i
].smu_feature_bitmap
& bitmap
) {
2823 if (data
->smu_features
[i
].supported
) {
2824 if (data
->smu_features
[i
].enabled
) {
2825 feature_mask
|= data
->smu_features
[i
].
2827 data
->smu_features
[i
].enabled
= false;
2833 vega10_enable_smc_features(hwmgr
, false, feature_mask
);
2839 * @brief Tell SMC to enabled the supported DPMs.
2841 * @param hwmgr - the address of the powerplay hardware manager.
2842 * @Param bitmap - bitmap for the features to enabled.
2843 * @return 0 on at least one DPM is successfully enabled.
2845 static int vega10_start_dpm(struct pp_hwmgr
*hwmgr
, uint32_t bitmap
)
2847 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2848 uint32_t i
, feature_mask
= 0;
2850 for (i
= 0; i
< GNLD_DPM_MAX
; i
++) {
2851 if (data
->smu_features
[i
].smu_feature_bitmap
& bitmap
) {
2852 if (data
->smu_features
[i
].supported
) {
2853 if (!data
->smu_features
[i
].enabled
) {
2854 feature_mask
|= data
->smu_features
[i
].
2856 data
->smu_features
[i
].enabled
= true;
2862 if (vega10_enable_smc_features(hwmgr
,
2863 true, feature_mask
)) {
2864 for (i
= 0; i
< GNLD_DPM_MAX
; i
++) {
2865 if (data
->smu_features
[i
].smu_feature_bitmap
&
2867 data
->smu_features
[i
].enabled
= false;
2871 if(data
->smu_features
[GNLD_LED_DISPLAY
].supported
== true){
2872 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2873 true, data
->smu_features
[GNLD_LED_DISPLAY
].smu_feature_bitmap
),
2874 "Attempt to Enable LED DPM feature Failed!", return -EINVAL
);
2875 data
->smu_features
[GNLD_LED_DISPLAY
].enabled
= true;
2878 if (data
->vbios_boot_state
.bsoc_vddc_lock
) {
2879 smum_send_msg_to_smc_with_parameter(hwmgr
,
2880 PPSMC_MSG_SetFloorSocVoltage
, 0);
2881 data
->vbios_boot_state
.bsoc_vddc_lock
= false;
2884 if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition
)) {
2885 if (data
->smu_features
[GNLD_ACDC
].supported
) {
2886 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2887 true, data
->smu_features
[GNLD_ACDC
].smu_feature_bitmap
),
2888 "Attempt to Enable DS_GFXCLK Feature Failed!",
2890 data
->smu_features
[GNLD_ACDC
].enabled
= true;
2897 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr
*hwmgr
, bool enable
)
2899 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2901 if (data
->smu_features
[GNLD_PCC_LIMIT
].supported
) {
2902 if (enable
== data
->smu_features
[GNLD_PCC_LIMIT
].enabled
)
2903 pr_info("GNLD_PCC_LIMIT has been %s \n", enable
? "enabled" : "disabled");
2904 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
2905 enable
, data
->smu_features
[GNLD_PCC_LIMIT
].smu_feature_bitmap
),
2906 "Attempt to Enable PCC Limit feature Failed!",
2908 data
->smu_features
[GNLD_PCC_LIMIT
].enabled
= enable
;
2914 static int vega10_enable_dpm_tasks(struct pp_hwmgr
*hwmgr
)
2916 struct vega10_hwmgr
*data
= hwmgr
->backend
;
2917 int tmp_result
, result
= 0;
2919 vega10_enable_disable_PCC_limit_feature(hwmgr
, true);
2921 smum_send_msg_to_smc_with_parameter(hwmgr
,
2922 PPSMC_MSG_ConfigureTelemetry
, data
->config_telemetry
);
2924 tmp_result
= vega10_construct_voltage_tables(hwmgr
);
2925 PP_ASSERT_WITH_CODE(!tmp_result
,
2926 "Failed to construct voltage tables!",
2927 result
= tmp_result
);
2929 tmp_result
= vega10_init_smc_table(hwmgr
);
2930 PP_ASSERT_WITH_CODE(!tmp_result
,
2931 "Failed to initialize SMC table!",
2932 result
= tmp_result
);
2934 if (PP_CAP(PHM_PlatformCaps_ThermalController
)) {
2935 tmp_result
= vega10_enable_thermal_protection(hwmgr
);
2936 PP_ASSERT_WITH_CODE(!tmp_result
,
2937 "Failed to enable thermal protection!",
2938 result
= tmp_result
);
2941 tmp_result
= vega10_enable_vrhot_feature(hwmgr
);
2942 PP_ASSERT_WITH_CODE(!tmp_result
,
2943 "Failed to enable VR hot feature!",
2944 result
= tmp_result
);
2946 tmp_result
= vega10_enable_deep_sleep_master_switch(hwmgr
);
2947 PP_ASSERT_WITH_CODE(!tmp_result
,
2948 "Failed to enable deep sleep master switch!",
2949 result
= tmp_result
);
2951 tmp_result
= vega10_start_dpm(hwmgr
, SMC_DPM_FEATURES
);
2952 PP_ASSERT_WITH_CODE(!tmp_result
,
2953 "Failed to start DPM!", result
= tmp_result
);
2955 /* enable didt, do not abort if failed didt */
2956 tmp_result
= vega10_enable_didt_config(hwmgr
);
2957 PP_ASSERT(!tmp_result
,
2958 "Failed to enable didt config!");
2960 tmp_result
= vega10_enable_power_containment(hwmgr
);
2961 PP_ASSERT_WITH_CODE(!tmp_result
,
2962 "Failed to enable power containment!",
2963 result
= tmp_result
);
2965 tmp_result
= vega10_power_control_set_level(hwmgr
);
2966 PP_ASSERT_WITH_CODE(!tmp_result
,
2967 "Failed to power control set level!",
2968 result
= tmp_result
);
2970 tmp_result
= vega10_enable_ulv(hwmgr
);
2971 PP_ASSERT_WITH_CODE(!tmp_result
,
2972 "Failed to enable ULV!",
2973 result
= tmp_result
);
2978 static int vega10_get_power_state_size(struct pp_hwmgr
*hwmgr
)
2980 return sizeof(struct vega10_power_state
);
2983 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr
*hwmgr
,
2984 void *state
, struct pp_power_state
*power_state
,
2985 void *pp_table
, uint32_t classification_flag
)
2987 ATOM_Vega10_GFXCLK_Dependency_Record_V2
*patom_record_V2
;
2988 struct vega10_power_state
*vega10_power_state
=
2989 cast_phw_vega10_power_state(&(power_state
->hardware
));
2990 struct vega10_performance_level
*performance_level
;
2991 ATOM_Vega10_State
*state_entry
= (ATOM_Vega10_State
*)state
;
2992 ATOM_Vega10_POWERPLAYTABLE
*powerplay_table
=
2993 (ATOM_Vega10_POWERPLAYTABLE
*)pp_table
;
2994 ATOM_Vega10_SOCCLK_Dependency_Table
*socclk_dep_table
=
2995 (ATOM_Vega10_SOCCLK_Dependency_Table
*)
2996 (((unsigned long)powerplay_table
) +
2997 le16_to_cpu(powerplay_table
->usSocclkDependencyTableOffset
));
2998 ATOM_Vega10_GFXCLK_Dependency_Table
*gfxclk_dep_table
=
2999 (ATOM_Vega10_GFXCLK_Dependency_Table
*)
3000 (((unsigned long)powerplay_table
) +
3001 le16_to_cpu(powerplay_table
->usGfxclkDependencyTableOffset
));
3002 ATOM_Vega10_MCLK_Dependency_Table
*mclk_dep_table
=
3003 (ATOM_Vega10_MCLK_Dependency_Table
*)
3004 (((unsigned long)powerplay_table
) +
3005 le16_to_cpu(powerplay_table
->usMclkDependencyTableOffset
));
3008 /* The following fields are not initialized here:
3009 * id orderedList allStatesList
3011 power_state
->classification
.ui_label
=
3012 (le16_to_cpu(state_entry
->usClassification
) &
3013 ATOM_PPLIB_CLASSIFICATION_UI_MASK
) >>
3014 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT
;
3015 power_state
->classification
.flags
= classification_flag
;
3016 /* NOTE: There is a classification2 flag in BIOS
3017 * that is not being used right now
3019 power_state
->classification
.temporary_state
= false;
3020 power_state
->classification
.to_be_deleted
= false;
3022 power_state
->validation
.disallowOnDC
=
3023 ((le32_to_cpu(state_entry
->ulCapsAndSettings
) &
3024 ATOM_Vega10_DISALLOW_ON_DC
) != 0);
3026 power_state
->display
.disableFrameModulation
= false;
3027 power_state
->display
.limitRefreshrate
= false;
3028 power_state
->display
.enableVariBright
=
3029 ((le32_to_cpu(state_entry
->ulCapsAndSettings
) &
3030 ATOM_Vega10_ENABLE_VARIBRIGHT
) != 0);
3032 power_state
->validation
.supportedPowerLevels
= 0;
3033 power_state
->uvd_clocks
.VCLK
= 0;
3034 power_state
->uvd_clocks
.DCLK
= 0;
3035 power_state
->temperatures
.min
= 0;
3036 power_state
->temperatures
.max
= 0;
3038 performance_level
= &(vega10_power_state
->performance_levels
3039 [vega10_power_state
->performance_level_count
++]);
3041 PP_ASSERT_WITH_CODE(
3042 (vega10_power_state
->performance_level_count
<
3043 NUM_GFXCLK_DPM_LEVELS
),
3044 "Performance levels exceeds SMC limit!",
3047 PP_ASSERT_WITH_CODE(
3048 (vega10_power_state
->performance_level_count
<=
3049 hwmgr
->platform_descriptor
.
3050 hardwareActivityPerformanceLevels
),
3051 "Performance levels exceeds Driver limit!",
3054 /* Performance levels are arranged from low to high. */
3055 performance_level
->soc_clock
= socclk_dep_table
->entries
3056 [state_entry
->ucSocClockIndexLow
].ulClk
;
3057 performance_level
->gfx_clock
= gfxclk_dep_table
->entries
3058 [state_entry
->ucGfxClockIndexLow
].ulClk
;
3059 performance_level
->mem_clock
= mclk_dep_table
->entries
3060 [state_entry
->ucMemClockIndexLow
].ulMemClk
;
3062 performance_level
= &(vega10_power_state
->performance_levels
3063 [vega10_power_state
->performance_level_count
++]);
3064 performance_level
->soc_clock
= socclk_dep_table
->entries
3065 [state_entry
->ucSocClockIndexHigh
].ulClk
;
3066 if (gfxclk_dep_table
->ucRevId
== 0) {
3067 performance_level
->gfx_clock
= gfxclk_dep_table
->entries
3068 [state_entry
->ucGfxClockIndexHigh
].ulClk
;
3069 } else if (gfxclk_dep_table
->ucRevId
== 1) {
3070 patom_record_V2
= (ATOM_Vega10_GFXCLK_Dependency_Record_V2
*)gfxclk_dep_table
->entries
;
3071 performance_level
->gfx_clock
= patom_record_V2
[state_entry
->ucGfxClockIndexHigh
].ulClk
;
3074 performance_level
->mem_clock
= mclk_dep_table
->entries
3075 [state_entry
->ucMemClockIndexHigh
].ulMemClk
;
3079 static int vega10_get_pp_table_entry(struct pp_hwmgr
*hwmgr
,
3080 unsigned long entry_index
, struct pp_power_state
*state
)
3083 struct vega10_power_state
*ps
;
3085 state
->hardware
.magic
= PhwVega10_Magic
;
3087 ps
= cast_phw_vega10_power_state(&state
->hardware
);
3089 result
= vega10_get_powerplay_table_entry(hwmgr
, entry_index
, state
,
3090 vega10_get_pp_table_entry_callback_func
);
3093 * This is the earliest time we have all the dependency table
3094 * and the VBIOS boot state
3096 /* set DC compatible flag if this state supports DC */
3097 if (!state
->validation
.disallowOnDC
)
3098 ps
->dc_compatible
= true;
3100 ps
->uvd_clks
.vclk
= state
->uvd_clocks
.VCLK
;
3101 ps
->uvd_clks
.dclk
= state
->uvd_clocks
.DCLK
;
3106 static int vega10_patch_boot_state(struct pp_hwmgr
*hwmgr
,
3107 struct pp_hw_power_state
*hw_ps
)
3112 static int vega10_apply_state_adjust_rules(struct pp_hwmgr
*hwmgr
,
3113 struct pp_power_state
*request_ps
,
3114 const struct pp_power_state
*current_ps
)
3116 struct amdgpu_device
*adev
= hwmgr
->adev
;
3117 struct vega10_power_state
*vega10_ps
=
3118 cast_phw_vega10_power_state(&request_ps
->hardware
);
3121 struct PP_Clocks minimum_clocks
= {0};
3122 bool disable_mclk_switching
;
3123 bool disable_mclk_switching_for_frame_lock
;
3124 bool disable_mclk_switching_for_vr
;
3125 bool force_mclk_high
;
3126 const struct phm_clock_and_voltage_limits
*max_limits
;
3128 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3129 struct phm_ppt_v2_information
*table_info
=
3130 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
3132 uint32_t stable_pstate_sclk_dpm_percentage
;
3133 uint32_t stable_pstate_sclk
= 0, stable_pstate_mclk
= 0;
3136 data
->battery_state
= (PP_StateUILabel_Battery
==
3137 request_ps
->classification
.ui_label
);
3139 if (vega10_ps
->performance_level_count
!= 2)
3140 pr_info("VI should always have 2 performance levels");
3142 max_limits
= adev
->pm
.ac_power
?
3143 &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
) :
3144 &(hwmgr
->dyn_state
.max_clock_voltage_on_dc
);
3146 /* Cap clock DPM tables at DC MAX if it is in DC. */
3147 if (!adev
->pm
.ac_power
) {
3148 for (i
= 0; i
< vega10_ps
->performance_level_count
; i
++) {
3149 if (vega10_ps
->performance_levels
[i
].mem_clock
>
3151 vega10_ps
->performance_levels
[i
].mem_clock
=
3153 if (vega10_ps
->performance_levels
[i
].gfx_clock
>
3155 vega10_ps
->performance_levels
[i
].gfx_clock
=
3160 /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3161 minimum_clocks
.engineClock
= hwmgr
->display_config
->min_core_set_clock
;
3162 minimum_clocks
.memoryClock
= hwmgr
->display_config
->min_mem_set_clock
;
3164 if (PP_CAP(PHM_PlatformCaps_StablePState
)) {
3165 stable_pstate_sclk_dpm_percentage
=
3166 data
->registry_data
.stable_pstate_sclk_dpm_percentage
;
3167 PP_ASSERT_WITH_CODE(
3168 data
->registry_data
.stable_pstate_sclk_dpm_percentage
>= 1 &&
3169 data
->registry_data
.stable_pstate_sclk_dpm_percentage
<= 100,
3170 "percent sclk value must range from 1% to 100%, setting default value",
3171 stable_pstate_sclk_dpm_percentage
= 75);
3173 max_limits
= &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
);
3174 stable_pstate_sclk
= (max_limits
->sclk
*
3175 stable_pstate_sclk_dpm_percentage
) / 100;
3177 for (count
= table_info
->vdd_dep_on_sclk
->count
- 1;
3178 count
>= 0; count
--) {
3179 if (stable_pstate_sclk
>=
3180 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
) {
3181 stable_pstate_sclk
=
3182 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
;
3188 stable_pstate_sclk
= table_info
->vdd_dep_on_sclk
->entries
[0].clk
;
3190 stable_pstate_mclk
= max_limits
->mclk
;
3192 minimum_clocks
.engineClock
= stable_pstate_sclk
;
3193 minimum_clocks
.memoryClock
= stable_pstate_mclk
;
3196 disable_mclk_switching_for_frame_lock
=
3197 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock
);
3198 disable_mclk_switching_for_vr
=
3199 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR
);
3200 force_mclk_high
= PP_CAP(PHM_PlatformCaps_ForceMclkHigh
);
3202 if (hwmgr
->display_config
->num_display
== 0)
3203 disable_mclk_switching
= false;
3205 disable_mclk_switching
= (hwmgr
->display_config
->num_display
> 1) ||
3206 disable_mclk_switching_for_frame_lock
||
3207 disable_mclk_switching_for_vr
||
3210 sclk
= vega10_ps
->performance_levels
[0].gfx_clock
;
3211 mclk
= vega10_ps
->performance_levels
[0].mem_clock
;
3213 if (sclk
< minimum_clocks
.engineClock
)
3214 sclk
= (minimum_clocks
.engineClock
> max_limits
->sclk
) ?
3215 max_limits
->sclk
: minimum_clocks
.engineClock
;
3217 if (mclk
< minimum_clocks
.memoryClock
)
3218 mclk
= (minimum_clocks
.memoryClock
> max_limits
->mclk
) ?
3219 max_limits
->mclk
: minimum_clocks
.memoryClock
;
3221 vega10_ps
->performance_levels
[0].gfx_clock
= sclk
;
3222 vega10_ps
->performance_levels
[0].mem_clock
= mclk
;
3224 if (vega10_ps
->performance_levels
[1].gfx_clock
<
3225 vega10_ps
->performance_levels
[0].gfx_clock
)
3226 vega10_ps
->performance_levels
[0].gfx_clock
=
3227 vega10_ps
->performance_levels
[1].gfx_clock
;
3229 if (disable_mclk_switching
) {
3230 /* Set Mclk the max of level 0 and level 1 */
3231 if (mclk
< vega10_ps
->performance_levels
[1].mem_clock
)
3232 mclk
= vega10_ps
->performance_levels
[1].mem_clock
;
3234 /* Find the lowest MCLK frequency that is within
3235 * the tolerable latency defined in DAL
3237 latency
= hwmgr
->display_config
->dce_tolerable_mclk_in_active_latency
;
3238 for (i
= 0; i
< data
->mclk_latency_table
.count
; i
++) {
3239 if ((data
->mclk_latency_table
.entries
[i
].latency
<= latency
) &&
3240 (data
->mclk_latency_table
.entries
[i
].frequency
>=
3241 vega10_ps
->performance_levels
[0].mem_clock
) &&
3242 (data
->mclk_latency_table
.entries
[i
].frequency
<=
3243 vega10_ps
->performance_levels
[1].mem_clock
))
3244 mclk
= data
->mclk_latency_table
.entries
[i
].frequency
;
3246 vega10_ps
->performance_levels
[0].mem_clock
= mclk
;
3248 if (vega10_ps
->performance_levels
[1].mem_clock
<
3249 vega10_ps
->performance_levels
[0].mem_clock
)
3250 vega10_ps
->performance_levels
[0].mem_clock
=
3251 vega10_ps
->performance_levels
[1].mem_clock
;
3254 if (PP_CAP(PHM_PlatformCaps_StablePState
)) {
3255 for (i
= 0; i
< vega10_ps
->performance_level_count
; i
++) {
3256 vega10_ps
->performance_levels
[i
].gfx_clock
= stable_pstate_sclk
;
3257 vega10_ps
->performance_levels
[i
].mem_clock
= stable_pstate_mclk
;
3264 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr
*hwmgr
, const void *input
)
3266 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3267 const struct phm_set_power_state_input
*states
=
3268 (const struct phm_set_power_state_input
*)input
;
3269 const struct vega10_power_state
*vega10_ps
=
3270 cast_const_phw_vega10_power_state(states
->pnew_state
);
3271 struct vega10_single_dpm_table
*sclk_table
= &(data
->dpm_table
.gfx_table
);
3272 uint32_t sclk
= vega10_ps
->performance_levels
3273 [vega10_ps
->performance_level_count
- 1].gfx_clock
;
3274 struct vega10_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mem_table
);
3275 uint32_t mclk
= vega10_ps
->performance_levels
3276 [vega10_ps
->performance_level_count
- 1].mem_clock
;
3279 for (i
= 0; i
< sclk_table
->count
; i
++) {
3280 if (sclk
== sclk_table
->dpm_levels
[i
].value
)
3284 if (i
>= sclk_table
->count
) {
3285 if (sclk
> sclk_table
->dpm_levels
[i
-1].value
) {
3286 data
->need_update_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
;
3287 sclk_table
->dpm_levels
[i
-1].value
= sclk
;
3291 for (i
= 0; i
< mclk_table
->count
; i
++) {
3292 if (mclk
== mclk_table
->dpm_levels
[i
].value
)
3296 if (i
>= mclk_table
->count
) {
3297 if (mclk
> mclk_table
->dpm_levels
[i
-1].value
) {
3298 data
->need_update_dpm_table
|= DPMTABLE_OD_UPDATE_MCLK
;
3299 mclk_table
->dpm_levels
[i
-1].value
= mclk
;
3303 if (data
->display_timing
.num_existing_displays
!= hwmgr
->display_config
->num_display
)
3304 data
->need_update_dpm_table
|= DPMTABLE_UPDATE_MCLK
;
3309 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3310 struct pp_hwmgr
*hwmgr
, const void *input
)
3313 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3314 struct vega10_dpm_table
*dpm_table
= &data
->dpm_table
;
3315 struct vega10_odn_dpm_table
*odn_table
= &data
->odn_dpm_table
;
3316 struct vega10_odn_clock_voltage_dependency_table
*odn_clk_table
= &odn_table
->vdd_dep_on_sclk
;
3319 if (!data
->need_update_dpm_table
)
3322 if (hwmgr
->od_enabled
&& data
->need_update_dpm_table
& DPMTABLE_OD_UPDATE_SCLK
) {
3323 for (count
= 0; count
< dpm_table
->gfx_table
.count
; count
++)
3324 dpm_table
->gfx_table
.dpm_levels
[count
].value
= odn_clk_table
->entries
[count
].clk
;
3327 odn_clk_table
= &odn_table
->vdd_dep_on_mclk
;
3328 if (hwmgr
->od_enabled
&& data
->need_update_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
) {
3329 for (count
= 0; count
< dpm_table
->mem_table
.count
; count
++)
3330 dpm_table
->mem_table
.dpm_levels
[count
].value
= odn_clk_table
->entries
[count
].clk
;
3333 if (data
->need_update_dpm_table
&
3334 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
+ DPMTABLE_UPDATE_SOCCLK
)) {
3335 result
= vega10_populate_all_graphic_levels(hwmgr
);
3336 PP_ASSERT_WITH_CODE((0 == result
),
3337 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3341 if (data
->need_update_dpm_table
&
3342 (DPMTABLE_OD_UPDATE_MCLK
+ DPMTABLE_UPDATE_MCLK
)) {
3343 result
= vega10_populate_all_memory_levels(hwmgr
);
3344 PP_ASSERT_WITH_CODE((0 == result
),
3345 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3349 vega10_populate_vddc_soc_levels(hwmgr
);
3354 static int vega10_trim_single_dpm_states(struct pp_hwmgr
*hwmgr
,
3355 struct vega10_single_dpm_table
*dpm_table
,
3356 uint32_t low_limit
, uint32_t high_limit
)
3360 for (i
= 0; i
< dpm_table
->count
; i
++) {
3361 if ((dpm_table
->dpm_levels
[i
].value
< low_limit
) ||
3362 (dpm_table
->dpm_levels
[i
].value
> high_limit
))
3363 dpm_table
->dpm_levels
[i
].enabled
= false;
3365 dpm_table
->dpm_levels
[i
].enabled
= true;
3370 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr
*hwmgr
,
3371 struct vega10_single_dpm_table
*dpm_table
,
3372 uint32_t low_limit
, uint32_t high_limit
,
3373 uint32_t disable_dpm_mask
)
3377 for (i
= 0; i
< dpm_table
->count
; i
++) {
3378 if ((dpm_table
->dpm_levels
[i
].value
< low_limit
) ||
3379 (dpm_table
->dpm_levels
[i
].value
> high_limit
))
3380 dpm_table
->dpm_levels
[i
].enabled
= false;
3381 else if (!((1 << i
) & disable_dpm_mask
))
3382 dpm_table
->dpm_levels
[i
].enabled
= false;
3384 dpm_table
->dpm_levels
[i
].enabled
= true;
3389 static int vega10_trim_dpm_states(struct pp_hwmgr
*hwmgr
,
3390 const struct vega10_power_state
*vega10_ps
)
3392 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3393 uint32_t high_limit_count
;
3395 PP_ASSERT_WITH_CODE((vega10_ps
->performance_level_count
>= 1),
3396 "power state did not have any performance level",
3399 high_limit_count
= (vega10_ps
->performance_level_count
== 1) ? 0 : 1;
3401 vega10_trim_single_dpm_states(hwmgr
,
3402 &(data
->dpm_table
.soc_table
),
3403 vega10_ps
->performance_levels
[0].soc_clock
,
3404 vega10_ps
->performance_levels
[high_limit_count
].soc_clock
);
3406 vega10_trim_single_dpm_states_with_mask(hwmgr
,
3407 &(data
->dpm_table
.gfx_table
),
3408 vega10_ps
->performance_levels
[0].gfx_clock
,
3409 vega10_ps
->performance_levels
[high_limit_count
].gfx_clock
,
3410 data
->disable_dpm_mask
);
3412 vega10_trim_single_dpm_states(hwmgr
,
3413 &(data
->dpm_table
.mem_table
),
3414 vega10_ps
->performance_levels
[0].mem_clock
,
3415 vega10_ps
->performance_levels
[high_limit_count
].mem_clock
);
3420 static uint32_t vega10_find_lowest_dpm_level(
3421 struct vega10_single_dpm_table
*table
)
3425 for (i
= 0; i
< table
->count
; i
++) {
3426 if (table
->dpm_levels
[i
].enabled
)
3433 static uint32_t vega10_find_highest_dpm_level(
3434 struct vega10_single_dpm_table
*table
)
3438 if (table
->count
<= MAX_REGULAR_DPM_NUMBER
) {
3439 for (i
= table
->count
; i
> 0; i
--) {
3440 if (table
->dpm_levels
[i
- 1].enabled
)
3444 pr_info("DPM Table Has Too Many Entries!");
3445 return MAX_REGULAR_DPM_NUMBER
- 1;
3451 static void vega10_apply_dal_minimum_voltage_request(
3452 struct pp_hwmgr
*hwmgr
)
3457 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr
*hwmgr
)
3459 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_table_on_mclk
;
3460 struct phm_ppt_v2_information
*table_info
=
3461 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
3463 vdd_dep_table_on_mclk
= table_info
->vdd_dep_on_mclk
;
3465 return vdd_dep_table_on_mclk
->entries
[NUM_UCLK_DPM_LEVELS
- 1].vddInd
+ 1;
3468 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr
*hwmgr
)
3470 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3471 uint32_t socclk_idx
;
3473 vega10_apply_dal_minimum_voltage_request(hwmgr
);
3475 if (!data
->registry_data
.sclk_dpm_key_disabled
) {
3476 if (data
->smc_state_table
.gfx_boot_level
!=
3477 data
->dpm_table
.gfx_table
.dpm_state
.soft_min_level
) {
3478 smum_send_msg_to_smc_with_parameter(hwmgr
,
3479 PPSMC_MSG_SetSoftMinGfxclkByIndex
,
3480 data
->smc_state_table
.gfx_boot_level
);
3481 data
->dpm_table
.gfx_table
.dpm_state
.soft_min_level
=
3482 data
->smc_state_table
.gfx_boot_level
;
3486 if (!data
->registry_data
.mclk_dpm_key_disabled
) {
3487 if (data
->smc_state_table
.mem_boot_level
!=
3488 data
->dpm_table
.mem_table
.dpm_state
.soft_min_level
) {
3489 if (data
->smc_state_table
.mem_boot_level
== NUM_UCLK_DPM_LEVELS
- 1) {
3490 socclk_idx
= vega10_get_soc_index_for_max_uclk(hwmgr
);
3491 smum_send_msg_to_smc_with_parameter(hwmgr
,
3492 PPSMC_MSG_SetSoftMinSocclkByIndex
,
3495 smum_send_msg_to_smc_with_parameter(hwmgr
,
3496 PPSMC_MSG_SetSoftMinUclkByIndex
,
3497 data
->smc_state_table
.mem_boot_level
);
3499 data
->dpm_table
.mem_table
.dpm_state
.soft_min_level
=
3500 data
->smc_state_table
.mem_boot_level
;
3504 if (!data
->registry_data
.socclk_dpm_key_disabled
) {
3505 if (data
->smc_state_table
.soc_boot_level
!=
3506 data
->dpm_table
.soc_table
.dpm_state
.soft_min_level
) {
3507 smum_send_msg_to_smc_with_parameter(hwmgr
,
3508 PPSMC_MSG_SetSoftMinSocclkByIndex
,
3509 data
->smc_state_table
.soc_boot_level
);
3510 data
->dpm_table
.soc_table
.dpm_state
.soft_min_level
=
3511 data
->smc_state_table
.soc_boot_level
;
3518 static int vega10_upload_dpm_max_level(struct pp_hwmgr
*hwmgr
)
3520 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3522 vega10_apply_dal_minimum_voltage_request(hwmgr
);
3524 if (!data
->registry_data
.sclk_dpm_key_disabled
) {
3525 if (data
->smc_state_table
.gfx_max_level
!=
3526 data
->dpm_table
.gfx_table
.dpm_state
.soft_max_level
) {
3527 smum_send_msg_to_smc_with_parameter(hwmgr
,
3528 PPSMC_MSG_SetSoftMaxGfxclkByIndex
,
3529 data
->smc_state_table
.gfx_max_level
);
3530 data
->dpm_table
.gfx_table
.dpm_state
.soft_max_level
=
3531 data
->smc_state_table
.gfx_max_level
;
3535 if (!data
->registry_data
.mclk_dpm_key_disabled
) {
3536 if (data
->smc_state_table
.mem_max_level
!=
3537 data
->dpm_table
.mem_table
.dpm_state
.soft_max_level
) {
3538 smum_send_msg_to_smc_with_parameter(hwmgr
,
3539 PPSMC_MSG_SetSoftMaxUclkByIndex
,
3540 data
->smc_state_table
.mem_max_level
);
3541 data
->dpm_table
.mem_table
.dpm_state
.soft_max_level
=
3542 data
->smc_state_table
.mem_max_level
;
3546 if (!data
->registry_data
.socclk_dpm_key_disabled
) {
3547 if (data
->smc_state_table
.soc_max_level
!=
3548 data
->dpm_table
.soc_table
.dpm_state
.soft_max_level
) {
3549 smum_send_msg_to_smc_with_parameter(hwmgr
,
3550 PPSMC_MSG_SetSoftMaxSocclkByIndex
,
3551 data
->smc_state_table
.soc_max_level
);
3552 data
->dpm_table
.soc_table
.dpm_state
.soft_max_level
=
3553 data
->smc_state_table
.soc_max_level
;
3560 static int vega10_generate_dpm_level_enable_mask(
3561 struct pp_hwmgr
*hwmgr
, const void *input
)
3563 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3564 const struct phm_set_power_state_input
*states
=
3565 (const struct phm_set_power_state_input
*)input
;
3566 const struct vega10_power_state
*vega10_ps
=
3567 cast_const_phw_vega10_power_state(states
->pnew_state
);
3570 PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr
, vega10_ps
),
3571 "Attempt to Trim DPM States Failed!",
3574 data
->smc_state_table
.gfx_boot_level
=
3575 vega10_find_lowest_dpm_level(&(data
->dpm_table
.gfx_table
));
3576 data
->smc_state_table
.gfx_max_level
=
3577 vega10_find_highest_dpm_level(&(data
->dpm_table
.gfx_table
));
3578 data
->smc_state_table
.mem_boot_level
=
3579 vega10_find_lowest_dpm_level(&(data
->dpm_table
.mem_table
));
3580 data
->smc_state_table
.mem_max_level
=
3581 vega10_find_highest_dpm_level(&(data
->dpm_table
.mem_table
));
3583 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr
),
3584 "Attempt to upload DPM Bootup Levels Failed!",
3586 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr
),
3587 "Attempt to upload DPM Max Levels Failed!",
3589 for(i
= data
->smc_state_table
.gfx_boot_level
; i
< data
->smc_state_table
.gfx_max_level
; i
++)
3590 data
->dpm_table
.gfx_table
.dpm_levels
[i
].enabled
= true;
3593 for(i
= data
->smc_state_table
.mem_boot_level
; i
< data
->smc_state_table
.mem_max_level
; i
++)
3594 data
->dpm_table
.mem_table
.dpm_levels
[i
].enabled
= true;
3599 int vega10_enable_disable_vce_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
3601 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3603 if (data
->smu_features
[GNLD_DPM_VCE
].supported
) {
3604 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
3606 data
->smu_features
[GNLD_DPM_VCE
].smu_feature_bitmap
),
3607 "Attempt to Enable/Disable DPM VCE Failed!",
3609 data
->smu_features
[GNLD_DPM_VCE
].enabled
= enable
;
3615 static int vega10_update_sclk_threshold(struct pp_hwmgr
*hwmgr
)
3617 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3618 uint32_t low_sclk_interrupt_threshold
= 0;
3620 if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification
) &&
3621 (data
->low_sclk_interrupt_threshold
!= 0)) {
3622 low_sclk_interrupt_threshold
=
3623 data
->low_sclk_interrupt_threshold
;
3625 data
->smc_state_table
.pp_table
.LowGfxclkInterruptThreshold
=
3626 cpu_to_le32(low_sclk_interrupt_threshold
);
3628 /* This message will also enable SmcToHost Interrupt */
3629 smum_send_msg_to_smc_with_parameter(hwmgr
,
3630 PPSMC_MSG_SetLowGfxclkInterruptThreshold
,
3631 (uint32_t)low_sclk_interrupt_threshold
);
3637 static int vega10_set_power_state_tasks(struct pp_hwmgr
*hwmgr
,
3640 int tmp_result
, result
= 0;
3641 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3642 PPTable_t
*pp_table
= &(data
->smc_state_table
.pp_table
);
3644 tmp_result
= vega10_find_dpm_states_clocks_in_dpm_table(hwmgr
, input
);
3645 PP_ASSERT_WITH_CODE(!tmp_result
,
3646 "Failed to find DPM states clocks in DPM table!",
3647 result
= tmp_result
);
3649 tmp_result
= vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr
, input
);
3650 PP_ASSERT_WITH_CODE(!tmp_result
,
3651 "Failed to populate and upload SCLK MCLK DPM levels!",
3652 result
= tmp_result
);
3654 tmp_result
= vega10_generate_dpm_level_enable_mask(hwmgr
, input
);
3655 PP_ASSERT_WITH_CODE(!tmp_result
,
3656 "Failed to generate DPM level enabled mask!",
3657 result
= tmp_result
);
3659 tmp_result
= vega10_update_sclk_threshold(hwmgr
);
3660 PP_ASSERT_WITH_CODE(!tmp_result
,
3661 "Failed to update SCLK threshold!",
3662 result
= tmp_result
);
3664 result
= smum_smc_table_manager(hwmgr
, (uint8_t *)pp_table
, PPTABLE
, false);
3665 PP_ASSERT_WITH_CODE(!result
,
3666 "Failed to upload PPtable!", return result
);
3668 vega10_update_avfs(hwmgr
);
3670 data
->need_update_dpm_table
&= DPMTABLE_OD_UPDATE_VDDC
;
3675 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr
*hwmgr
, bool low
)
3677 struct pp_power_state
*ps
;
3678 struct vega10_power_state
*vega10_ps
;
3683 ps
= hwmgr
->request_ps
;
3688 vega10_ps
= cast_phw_vega10_power_state(&ps
->hardware
);
3691 return vega10_ps
->performance_levels
[0].gfx_clock
;
3693 return vega10_ps
->performance_levels
3694 [vega10_ps
->performance_level_count
- 1].gfx_clock
;
3697 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr
*hwmgr
, bool low
)
3699 struct pp_power_state
*ps
;
3700 struct vega10_power_state
*vega10_ps
;
3705 ps
= hwmgr
->request_ps
;
3710 vega10_ps
= cast_phw_vega10_power_state(&ps
->hardware
);
3713 return vega10_ps
->performance_levels
[0].mem_clock
;
3715 return vega10_ps
->performance_levels
3716 [vega10_ps
->performance_level_count
-1].mem_clock
;
3719 static int vega10_get_gpu_power(struct pp_hwmgr
*hwmgr
,
3727 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_GetCurrPkgPwr
);
3728 value
= smum_get_argument(hwmgr
);
3730 /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3731 *query
= value
<< 8;
3736 static int vega10_read_sensor(struct pp_hwmgr
*hwmgr
, int idx
,
3737 void *value
, int *size
)
3739 struct amdgpu_device
*adev
= hwmgr
->adev
;
3740 uint32_t sclk_mhz
, mclk_idx
, activity_percent
= 0;
3741 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3742 struct vega10_dpm_table
*dpm_table
= &data
->dpm_table
;
3747 case AMDGPU_PP_SENSOR_GFX_SCLK
:
3748 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_GetAverageGfxclkActualFrequency
);
3749 sclk_mhz
= smum_get_argument(hwmgr
);
3750 *((uint32_t *)value
) = sclk_mhz
* 100;
3752 case AMDGPU_PP_SENSOR_GFX_MCLK
:
3753 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_GetCurrentUclkIndex
);
3754 mclk_idx
= smum_get_argument(hwmgr
);
3755 if (mclk_idx
< dpm_table
->mem_table
.count
) {
3756 *((uint32_t *)value
) = dpm_table
->mem_table
.dpm_levels
[mclk_idx
].value
;
3762 case AMDGPU_PP_SENSOR_GPU_LOAD
:
3763 smum_send_msg_to_smc_with_parameter(hwmgr
, PPSMC_MSG_GetAverageGfxActivity
, 0);
3764 activity_percent
= smum_get_argument(hwmgr
);
3765 *((uint32_t *)value
) = activity_percent
> 100 ? 100 : activity_percent
;
3768 case AMDGPU_PP_SENSOR_GPU_TEMP
:
3769 *((uint32_t *)value
) = vega10_thermal_get_temperature(hwmgr
);
3772 case AMDGPU_PP_SENSOR_UVD_POWER
:
3773 *((uint32_t *)value
) = data
->uvd_power_gated
? 0 : 1;
3776 case AMDGPU_PP_SENSOR_VCE_POWER
:
3777 *((uint32_t *)value
) = data
->vce_power_gated
? 0 : 1;
3780 case AMDGPU_PP_SENSOR_GPU_POWER
:
3781 ret
= vega10_get_gpu_power(hwmgr
, (uint32_t *)value
);
3783 case AMDGPU_PP_SENSOR_VDDGFX
:
3784 val_vid
= (RREG32_SOC15(SMUIO
, 0, mmSMUSVI0_PLANE0_CURRENTVID
) &
3785 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK
) >>
3786 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT
;
3787 *((uint32_t *)value
) = (uint32_t)convert_to_vddc((uint8_t)val_vid
);
3789 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK
:
3790 ret
= vega10_get_enabled_smc_features(hwmgr
, (uint64_t *)value
);
3802 static void vega10_notify_smc_display_change(struct pp_hwmgr
*hwmgr
,
3805 smum_send_msg_to_smc_with_parameter(hwmgr
,
3806 PPSMC_MSG_SetUclkFastSwitch
,
3810 int vega10_display_clock_voltage_request(struct pp_hwmgr
*hwmgr
,
3811 struct pp_display_clock_request
*clock_req
)
3814 enum amd_pp_clock_type clk_type
= clock_req
->clock_type
;
3815 uint32_t clk_freq
= clock_req
->clock_freq_in_khz
/ 1000;
3816 DSPCLK_e clk_select
= 0;
3817 uint32_t clk_request
= 0;
3820 case amd_pp_dcef_clock
:
3821 clk_select
= DSPCLK_DCEFCLK
;
3823 case amd_pp_disp_clock
:
3824 clk_select
= DSPCLK_DISPCLK
;
3826 case amd_pp_pixel_clock
:
3827 clk_select
= DSPCLK_PIXCLK
;
3829 case amd_pp_phy_clock
:
3830 clk_select
= DSPCLK_PHYCLK
;
3833 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
3839 clk_request
= (clk_freq
<< 16) | clk_select
;
3840 smum_send_msg_to_smc_with_parameter(hwmgr
,
3841 PPSMC_MSG_RequestDisplayClockByFreq
,
3848 static uint8_t vega10_get_uclk_index(struct pp_hwmgr
*hwmgr
,
3849 struct phm_ppt_v1_clock_voltage_dependency_table
*mclk_table
,
3855 if (mclk_table
== NULL
|| mclk_table
->count
== 0)
3858 count
= (uint8_t)(mclk_table
->count
);
3860 for(i
= 0; i
< count
; i
++) {
3861 if(mclk_table
->entries
[i
].clk
>= frequency
)
3868 static int vega10_notify_smc_display_config_after_ps_adjustment(
3869 struct pp_hwmgr
*hwmgr
)
3871 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3872 struct vega10_single_dpm_table
*dpm_table
=
3873 &data
->dpm_table
.dcef_table
;
3874 struct phm_ppt_v2_information
*table_info
=
3875 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
3876 struct phm_ppt_v1_clock_voltage_dependency_table
*mclk_table
= table_info
->vdd_dep_on_mclk
;
3878 struct PP_Clocks min_clocks
= {0};
3880 struct pp_display_clock_request clock_req
;
3882 if ((hwmgr
->display_config
->num_display
> 1) &&
3883 !hwmgr
->display_config
->multi_monitor_in_sync
&&
3884 !hwmgr
->display_config
->nb_pstate_switch_disable
)
3885 vega10_notify_smc_display_change(hwmgr
, false);
3887 vega10_notify_smc_display_change(hwmgr
, true);
3889 min_clocks
.dcefClock
= hwmgr
->display_config
->min_dcef_set_clk
;
3890 min_clocks
.dcefClockInSR
= hwmgr
->display_config
->min_dcef_deep_sleep_set_clk
;
3891 min_clocks
.memoryClock
= hwmgr
->display_config
->min_mem_set_clock
;
3893 for (i
= 0; i
< dpm_table
->count
; i
++) {
3894 if (dpm_table
->dpm_levels
[i
].value
== min_clocks
.dcefClock
)
3898 if (i
< dpm_table
->count
) {
3899 clock_req
.clock_type
= amd_pp_dcef_clock
;
3900 clock_req
.clock_freq_in_khz
= dpm_table
->dpm_levels
[i
].value
* 10;
3901 if (!vega10_display_clock_voltage_request(hwmgr
, &clock_req
)) {
3902 smum_send_msg_to_smc_with_parameter(
3903 hwmgr
, PPSMC_MSG_SetMinDeepSleepDcefclk
,
3904 min_clocks
.dcefClockInSR
/ 100);
3906 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
3909 pr_debug("Cannot find requested DCEFCLK!");
3912 if (min_clocks
.memoryClock
!= 0) {
3913 idx
= vega10_get_uclk_index(hwmgr
, mclk_table
, min_clocks
.memoryClock
);
3914 smum_send_msg_to_smc_with_parameter(hwmgr
, PPSMC_MSG_SetSoftMinUclkByIndex
, idx
);
3915 data
->dpm_table
.mem_table
.dpm_state
.soft_min_level
= idx
;
3921 static int vega10_force_dpm_highest(struct pp_hwmgr
*hwmgr
)
3923 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3925 data
->smc_state_table
.gfx_boot_level
=
3926 data
->smc_state_table
.gfx_max_level
=
3927 vega10_find_highest_dpm_level(&(data
->dpm_table
.gfx_table
));
3928 data
->smc_state_table
.mem_boot_level
=
3929 data
->smc_state_table
.mem_max_level
=
3930 vega10_find_highest_dpm_level(&(data
->dpm_table
.mem_table
));
3932 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr
),
3933 "Failed to upload boot level to highest!",
3936 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr
),
3937 "Failed to upload dpm max level to highest!",
3943 static int vega10_force_dpm_lowest(struct pp_hwmgr
*hwmgr
)
3945 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3947 data
->smc_state_table
.gfx_boot_level
=
3948 data
->smc_state_table
.gfx_max_level
=
3949 vega10_find_lowest_dpm_level(&(data
->dpm_table
.gfx_table
));
3950 data
->smc_state_table
.mem_boot_level
=
3951 data
->smc_state_table
.mem_max_level
=
3952 vega10_find_lowest_dpm_level(&(data
->dpm_table
.mem_table
));
3954 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr
),
3955 "Failed to upload boot level to highest!",
3958 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr
),
3959 "Failed to upload dpm max level to highest!",
3966 static int vega10_unforce_dpm_levels(struct pp_hwmgr
*hwmgr
)
3968 struct vega10_hwmgr
*data
= hwmgr
->backend
;
3970 data
->smc_state_table
.gfx_boot_level
=
3971 vega10_find_lowest_dpm_level(&(data
->dpm_table
.gfx_table
));
3972 data
->smc_state_table
.gfx_max_level
=
3973 vega10_find_highest_dpm_level(&(data
->dpm_table
.gfx_table
));
3974 data
->smc_state_table
.mem_boot_level
=
3975 vega10_find_lowest_dpm_level(&(data
->dpm_table
.mem_table
));
3976 data
->smc_state_table
.mem_max_level
=
3977 vega10_find_highest_dpm_level(&(data
->dpm_table
.mem_table
));
3979 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr
),
3980 "Failed to upload DPM Bootup Levels!",
3983 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr
),
3984 "Failed to upload DPM Max Levels!",
3989 static int vega10_get_profiling_clk_mask(struct pp_hwmgr
*hwmgr
, enum amd_dpm_forced_level level
,
3990 uint32_t *sclk_mask
, uint32_t *mclk_mask
, uint32_t *soc_mask
)
3992 struct phm_ppt_v2_information
*table_info
=
3993 (struct phm_ppt_v2_information
*)(hwmgr
->pptable
);
3995 if (table_info
->vdd_dep_on_sclk
->count
> VEGA10_UMD_PSTATE_GFXCLK_LEVEL
&&
3996 table_info
->vdd_dep_on_socclk
->count
> VEGA10_UMD_PSTATE_SOCCLK_LEVEL
&&
3997 table_info
->vdd_dep_on_mclk
->count
> VEGA10_UMD_PSTATE_MCLK_LEVEL
) {
3998 *sclk_mask
= VEGA10_UMD_PSTATE_GFXCLK_LEVEL
;
3999 *soc_mask
= VEGA10_UMD_PSTATE_SOCCLK_LEVEL
;
4000 *mclk_mask
= VEGA10_UMD_PSTATE_MCLK_LEVEL
;
4001 hwmgr
->pstate_sclk
= table_info
->vdd_dep_on_sclk
->entries
[VEGA10_UMD_PSTATE_GFXCLK_LEVEL
].clk
;
4002 hwmgr
->pstate_mclk
= table_info
->vdd_dep_on_mclk
->entries
[VEGA10_UMD_PSTATE_MCLK_LEVEL
].clk
;
4005 if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
) {
4007 } else if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
) {
4009 } else if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
) {
4010 *sclk_mask
= table_info
->vdd_dep_on_sclk
->count
- 1;
4011 *soc_mask
= table_info
->vdd_dep_on_socclk
->count
- 1;
4012 *mclk_mask
= table_info
->vdd_dep_on_mclk
->count
- 1;
4017 static void vega10_set_fan_control_mode(struct pp_hwmgr
*hwmgr
, uint32_t mode
)
4020 case AMD_FAN_CTRL_NONE
:
4021 vega10_fan_ctrl_set_fan_speed_percent(hwmgr
, 100);
4023 case AMD_FAN_CTRL_MANUAL
:
4024 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl
))
4025 vega10_fan_ctrl_stop_smc_fan_control(hwmgr
);
4027 case AMD_FAN_CTRL_AUTO
:
4028 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl
))
4029 vega10_fan_ctrl_start_smc_fan_control(hwmgr
);
4036 static int vega10_force_clock_level(struct pp_hwmgr
*hwmgr
,
4037 enum pp_clock_type type
, uint32_t mask
)
4039 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4043 data
->smc_state_table
.gfx_boot_level
= mask
? (ffs(mask
) - 1) : 0;
4044 data
->smc_state_table
.gfx_max_level
= mask
? (fls(mask
) - 1) : 0;
4046 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr
),
4047 "Failed to upload boot level to lowest!",
4050 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr
),
4051 "Failed to upload dpm max level to highest!",
4056 data
->smc_state_table
.mem_boot_level
= mask
? (ffs(mask
) - 1) : 0;
4057 data
->smc_state_table
.mem_max_level
= mask
? (fls(mask
) - 1) : 0;
4059 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr
),
4060 "Failed to upload boot level to lowest!",
4063 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr
),
4064 "Failed to upload dpm max level to highest!",
4070 data
->smc_state_table
.soc_boot_level
= mask
? (ffs(mask
) - 1) : 0;
4071 data
->smc_state_table
.soc_max_level
= mask
? (fls(mask
) - 1) : 0;
4073 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr
),
4074 "Failed to upload boot level to lowest!",
4077 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr
),
4078 "Failed to upload dpm max level to highest!",
4084 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
4095 static int vega10_dpm_force_dpm_level(struct pp_hwmgr
*hwmgr
,
4096 enum amd_dpm_forced_level level
)
4099 uint32_t sclk_mask
= 0;
4100 uint32_t mclk_mask
= 0;
4101 uint32_t soc_mask
= 0;
4103 if (hwmgr
->pstate_sclk
== 0)
4104 vega10_get_profiling_clk_mask(hwmgr
, level
, &sclk_mask
, &mclk_mask
, &soc_mask
);
4107 case AMD_DPM_FORCED_LEVEL_HIGH
:
4108 ret
= vega10_force_dpm_highest(hwmgr
);
4110 case AMD_DPM_FORCED_LEVEL_LOW
:
4111 ret
= vega10_force_dpm_lowest(hwmgr
);
4113 case AMD_DPM_FORCED_LEVEL_AUTO
:
4114 ret
= vega10_unforce_dpm_levels(hwmgr
);
4116 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
:
4117 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
:
4118 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
:
4119 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
:
4120 ret
= vega10_get_profiling_clk_mask(hwmgr
, level
, &sclk_mask
, &mclk_mask
, &soc_mask
);
4123 vega10_force_clock_level(hwmgr
, PP_SCLK
, 1<<sclk_mask
);
4124 vega10_force_clock_level(hwmgr
, PP_MCLK
, 1<<mclk_mask
);
4126 case AMD_DPM_FORCED_LEVEL_MANUAL
:
4127 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
:
4133 if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
&& hwmgr
->dpm_level
!= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
)
4134 vega10_set_fan_control_mode(hwmgr
, AMD_FAN_CTRL_NONE
);
4135 else if (level
!= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
&& hwmgr
->dpm_level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
)
4136 vega10_set_fan_control_mode(hwmgr
, AMD_FAN_CTRL_AUTO
);
4142 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr
*hwmgr
)
4144 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4146 if (data
->smu_features
[GNLD_FAN_CONTROL
].enabled
== false)
4147 return AMD_FAN_CTRL_MANUAL
;
4149 return AMD_FAN_CTRL_AUTO
;
4152 static int vega10_get_dal_power_level(struct pp_hwmgr
*hwmgr
,
4153 struct amd_pp_simple_clock_info
*info
)
4155 struct phm_ppt_v2_information
*table_info
=
4156 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
4157 struct phm_clock_and_voltage_limits
*max_limits
=
4158 &table_info
->max_clock_voltage_on_ac
;
4160 info
->engine_max_clock
= max_limits
->sclk
;
4161 info
->memory_max_clock
= max_limits
->mclk
;
4166 static void vega10_get_sclks(struct pp_hwmgr
*hwmgr
,
4167 struct pp_clock_levels_with_latency
*clocks
)
4169 struct phm_ppt_v2_information
*table_info
=
4170 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
4171 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
=
4172 table_info
->vdd_dep_on_sclk
;
4175 clocks
->num_levels
= 0;
4176 for (i
= 0; i
< dep_table
->count
; i
++) {
4177 if (dep_table
->entries
[i
].clk
) {
4178 clocks
->data
[clocks
->num_levels
].clocks_in_khz
=
4179 dep_table
->entries
[i
].clk
* 10;
4180 clocks
->num_levels
++;
4186 static void vega10_get_memclocks(struct pp_hwmgr
*hwmgr
,
4187 struct pp_clock_levels_with_latency
*clocks
)
4189 struct phm_ppt_v2_information
*table_info
=
4190 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
4191 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
=
4192 table_info
->vdd_dep_on_mclk
;
4193 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4197 for (i
= 0; i
< dep_table
->count
; i
++) {
4198 if (dep_table
->entries
[i
].clk
) {
4200 clocks
->data
[j
].clocks_in_khz
=
4201 dep_table
->entries
[i
].clk
* 10;
4202 data
->mclk_latency_table
.entries
[j
].frequency
=
4203 dep_table
->entries
[i
].clk
;
4204 clocks
->data
[j
].latency_in_us
=
4205 data
->mclk_latency_table
.entries
[j
].latency
= 25;
4209 clocks
->num_levels
= data
->mclk_latency_table
.count
= j
;
4212 static void vega10_get_dcefclocks(struct pp_hwmgr
*hwmgr
,
4213 struct pp_clock_levels_with_latency
*clocks
)
4215 struct phm_ppt_v2_information
*table_info
=
4216 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
4217 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
=
4218 table_info
->vdd_dep_on_dcefclk
;
4221 for (i
= 0; i
< dep_table
->count
; i
++) {
4222 clocks
->data
[i
].clocks_in_khz
= dep_table
->entries
[i
].clk
* 10;
4223 clocks
->data
[i
].latency_in_us
= 0;
4224 clocks
->num_levels
++;
4228 static void vega10_get_socclocks(struct pp_hwmgr
*hwmgr
,
4229 struct pp_clock_levels_with_latency
*clocks
)
4231 struct phm_ppt_v2_information
*table_info
=
4232 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
4233 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
=
4234 table_info
->vdd_dep_on_socclk
;
4237 for (i
= 0; i
< dep_table
->count
; i
++) {
4238 clocks
->data
[i
].clocks_in_khz
= dep_table
->entries
[i
].clk
* 10;
4239 clocks
->data
[i
].latency_in_us
= 0;
4240 clocks
->num_levels
++;
4244 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr
*hwmgr
,
4245 enum amd_pp_clock_type type
,
4246 struct pp_clock_levels_with_latency
*clocks
)
4249 case amd_pp_sys_clock
:
4250 vega10_get_sclks(hwmgr
, clocks
);
4252 case amd_pp_mem_clock
:
4253 vega10_get_memclocks(hwmgr
, clocks
);
4255 case amd_pp_dcef_clock
:
4256 vega10_get_dcefclocks(hwmgr
, clocks
);
4258 case amd_pp_soc_clock
:
4259 vega10_get_socclocks(hwmgr
, clocks
);
4268 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr
*hwmgr
,
4269 enum amd_pp_clock_type type
,
4270 struct pp_clock_levels_with_voltage
*clocks
)
4272 struct phm_ppt_v2_information
*table_info
=
4273 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
4274 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
;
4278 case amd_pp_mem_clock
:
4279 dep_table
= table_info
->vdd_dep_on_mclk
;
4281 case amd_pp_dcef_clock
:
4282 dep_table
= table_info
->vdd_dep_on_dcefclk
;
4284 case amd_pp_disp_clock
:
4285 dep_table
= table_info
->vdd_dep_on_dispclk
;
4287 case amd_pp_pixel_clock
:
4288 dep_table
= table_info
->vdd_dep_on_pixclk
;
4290 case amd_pp_phy_clock
:
4291 dep_table
= table_info
->vdd_dep_on_phyclk
;
4297 for (i
= 0; i
< dep_table
->count
; i
++) {
4298 clocks
->data
[i
].clocks_in_khz
= dep_table
->entries
[i
].clk
* 10;
4299 clocks
->data
[i
].voltage_in_mv
= (uint32_t)(table_info
->vddc_lookup_table
->
4300 entries
[dep_table
->entries
[i
].vddInd
].us_vdd
);
4301 clocks
->num_levels
++;
4304 if (i
< dep_table
->count
)
4310 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr
*hwmgr
,
4313 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4314 struct dm_pp_wm_sets_with_clock_ranges_soc15
*wm_with_clock_ranges
= clock_range
;
4315 Watermarks_t
*table
= &(data
->smc_state_table
.water_marks_table
);
4318 if (!data
->registry_data
.disable_water_mark
) {
4319 smu_set_watermarks_for_clocks_ranges(table
, wm_with_clock_ranges
);
4320 data
->water_marks_bitmap
= WaterMarksExist
;
4326 static int vega10_get_ppfeature_status(struct pp_hwmgr
*hwmgr
, char *buf
)
4328 static const char *ppfeature_name
[] = {
4359 static const char *output_title
[] = {
4363 uint64_t features_enabled
;
4368 ret
= vega10_get_enabled_smc_features(hwmgr
, &features_enabled
);
4369 PP_ASSERT_WITH_CODE(!ret
,
4370 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
4373 size
+= sprintf(buf
+ size
, "Current ppfeatures: 0x%016llx\n", features_enabled
);
4374 size
+= sprintf(buf
+ size
, "%-19s %-22s %s\n",
4378 for (i
= 0; i
< GNLD_FEATURES_MAX
; i
++) {
4379 size
+= sprintf(buf
+ size
, "%-19s 0x%016llx %6s\n",
4382 (features_enabled
& (1ULL << i
)) ? "Y" : "N");
4388 static int vega10_set_ppfeature_status(struct pp_hwmgr
*hwmgr
, uint64_t new_ppfeature_masks
)
4390 uint64_t features_enabled
;
4391 uint64_t features_to_enable
;
4392 uint64_t features_to_disable
;
4395 if (new_ppfeature_masks
>= (1ULL << GNLD_FEATURES_MAX
))
4398 ret
= vega10_get_enabled_smc_features(hwmgr
, &features_enabled
);
4402 features_to_disable
=
4403 (features_enabled
^ new_ppfeature_masks
) & features_enabled
;
4404 features_to_enable
=
4405 (features_enabled
^ new_ppfeature_masks
) ^ features_to_disable
;
4407 pr_debug("features_to_disable 0x%llx\n", features_to_disable
);
4408 pr_debug("features_to_enable 0x%llx\n", features_to_enable
);
4410 if (features_to_disable
) {
4411 ret
= vega10_enable_smc_features(hwmgr
, false, features_to_disable
);
4416 if (features_to_enable
) {
4417 ret
= vega10_enable_smc_features(hwmgr
, true, features_to_enable
);
4425 static int vega10_print_clock_levels(struct pp_hwmgr
*hwmgr
,
4426 enum pp_clock_type type
, char *buf
)
4428 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4429 struct vega10_single_dpm_table
*sclk_table
= &(data
->dpm_table
.gfx_table
);
4430 struct vega10_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mem_table
);
4431 struct vega10_single_dpm_table
*soc_table
= &(data
->dpm_table
.soc_table
);
4432 struct vega10_single_dpm_table
*dcef_table
= &(data
->dpm_table
.dcef_table
);
4433 struct vega10_pcie_table
*pcie_table
= &(data
->dpm_table
.pcie_table
);
4434 struct vega10_odn_clock_voltage_dependency_table
*podn_vdd_dep
= NULL
;
4436 int i
, now
, size
= 0;
4440 if (data
->registry_data
.sclk_dpm_key_disabled
)
4443 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_GetCurrentGfxclkIndex
);
4444 now
= smum_get_argument(hwmgr
);
4446 for (i
= 0; i
< sclk_table
->count
; i
++)
4447 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
4448 i
, sclk_table
->dpm_levels
[i
].value
/ 100,
4449 (i
== now
) ? "*" : "");
4452 if (data
->registry_data
.mclk_dpm_key_disabled
)
4455 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_GetCurrentUclkIndex
);
4456 now
= smum_get_argument(hwmgr
);
4458 for (i
= 0; i
< mclk_table
->count
; i
++)
4459 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
4460 i
, mclk_table
->dpm_levels
[i
].value
/ 100,
4461 (i
== now
) ? "*" : "");
4464 if (data
->registry_data
.socclk_dpm_key_disabled
)
4467 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_GetCurrentSocclkIndex
);
4468 now
= smum_get_argument(hwmgr
);
4470 for (i
= 0; i
< soc_table
->count
; i
++)
4471 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
4472 i
, soc_table
->dpm_levels
[i
].value
/ 100,
4473 (i
== now
) ? "*" : "");
4476 if (data
->registry_data
.dcefclk_dpm_key_disabled
)
4479 smum_send_msg_to_smc_with_parameter(hwmgr
,
4480 PPSMC_MSG_GetClockFreqMHz
, CLK_DCEFCLK
);
4481 now
= smum_get_argument(hwmgr
);
4483 for (i
= 0; i
< dcef_table
->count
; i
++)
4484 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
4485 i
, dcef_table
->dpm_levels
[i
].value
/ 100,
4486 (dcef_table
->dpm_levels
[i
].value
/ 100 == now
) ?
4490 smum_send_msg_to_smc(hwmgr
, PPSMC_MSG_GetCurrentLinkIndex
);
4491 now
= smum_get_argument(hwmgr
);
4493 for (i
= 0; i
< pcie_table
->count
; i
++)
4494 size
+= sprintf(buf
+ size
, "%d: %s %s\n", i
,
4495 (pcie_table
->pcie_gen
[i
] == 0) ? "2.5GT/s, x1" :
4496 (pcie_table
->pcie_gen
[i
] == 1) ? "5.0GT/s, x16" :
4497 (pcie_table
->pcie_gen
[i
] == 2) ? "8.0GT/s, x16" : "",
4498 (i
== now
) ? "*" : "");
4501 if (hwmgr
->od_enabled
) {
4502 size
= sprintf(buf
, "%s:\n", "OD_SCLK");
4503 podn_vdd_dep
= &data
->odn_dpm_table
.vdd_dep_on_sclk
;
4504 for (i
= 0; i
< podn_vdd_dep
->count
; i
++)
4505 size
+= sprintf(buf
+ size
, "%d: %10uMhz %10umV\n",
4506 i
, podn_vdd_dep
->entries
[i
].clk
/ 100,
4507 podn_vdd_dep
->entries
[i
].vddc
);
4511 if (hwmgr
->od_enabled
) {
4512 size
= sprintf(buf
, "%s:\n", "OD_MCLK");
4513 podn_vdd_dep
= &data
->odn_dpm_table
.vdd_dep_on_mclk
;
4514 for (i
= 0; i
< podn_vdd_dep
->count
; i
++)
4515 size
+= sprintf(buf
+ size
, "%d: %10uMhz %10umV\n",
4516 i
, podn_vdd_dep
->entries
[i
].clk
/100,
4517 podn_vdd_dep
->entries
[i
].vddc
);
4521 if (hwmgr
->od_enabled
) {
4522 size
= sprintf(buf
, "%s:\n", "OD_RANGE");
4523 size
+= sprintf(buf
+ size
, "SCLK: %7uMHz %10uMHz\n",
4524 data
->golden_dpm_table
.gfx_table
.dpm_levels
[0].value
/100,
4525 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
/100);
4526 size
+= sprintf(buf
+ size
, "MCLK: %7uMHz %10uMHz\n",
4527 data
->golden_dpm_table
.mem_table
.dpm_levels
[0].value
/100,
4528 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
/100);
4529 size
+= sprintf(buf
+ size
, "VDDC: %7umV %11umV\n",
4530 data
->odn_dpm_table
.min_vddc
,
4531 data
->odn_dpm_table
.max_vddc
);
4540 static int vega10_display_configuration_changed_task(struct pp_hwmgr
*hwmgr
)
4542 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4543 Watermarks_t
*wm_table
= &(data
->smc_state_table
.water_marks_table
);
4546 if ((data
->water_marks_bitmap
& WaterMarksExist
) &&
4547 !(data
->water_marks_bitmap
& WaterMarksLoaded
)) {
4548 result
= smum_smc_table_manager(hwmgr
, (uint8_t *)wm_table
, WMTABLE
, false);
4549 PP_ASSERT_WITH_CODE(result
, "Failed to update WMTABLE!", return EINVAL
);
4550 data
->water_marks_bitmap
|= WaterMarksLoaded
;
4553 if (data
->water_marks_bitmap
& WaterMarksLoaded
) {
4554 smum_send_msg_to_smc_with_parameter(hwmgr
,
4555 PPSMC_MSG_NumOfDisplays
, hwmgr
->display_config
->num_display
);
4561 int vega10_enable_disable_uvd_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4563 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4565 if (data
->smu_features
[GNLD_DPM_UVD
].supported
) {
4566 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr
,
4568 data
->smu_features
[GNLD_DPM_UVD
].smu_feature_bitmap
),
4569 "Attempt to Enable/Disable DPM UVD Failed!",
4571 data
->smu_features
[GNLD_DPM_UVD
].enabled
= enable
;
4576 static void vega10_power_gate_vce(struct pp_hwmgr
*hwmgr
, bool bgate
)
4578 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4580 data
->vce_power_gated
= bgate
;
4581 vega10_enable_disable_vce_dpm(hwmgr
, !bgate
);
4584 static void vega10_power_gate_uvd(struct pp_hwmgr
*hwmgr
, bool bgate
)
4586 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4588 data
->uvd_power_gated
= bgate
;
4589 vega10_enable_disable_uvd_dpm(hwmgr
, !bgate
);
4592 static inline bool vega10_are_power_levels_equal(
4593 const struct vega10_performance_level
*pl1
,
4594 const struct vega10_performance_level
*pl2
)
4596 return ((pl1
->soc_clock
== pl2
->soc_clock
) &&
4597 (pl1
->gfx_clock
== pl2
->gfx_clock
) &&
4598 (pl1
->mem_clock
== pl2
->mem_clock
));
4601 static int vega10_check_states_equal(struct pp_hwmgr
*hwmgr
,
4602 const struct pp_hw_power_state
*pstate1
,
4603 const struct pp_hw_power_state
*pstate2
, bool *equal
)
4605 const struct vega10_power_state
*psa
;
4606 const struct vega10_power_state
*psb
;
4609 if (pstate1
== NULL
|| pstate2
== NULL
|| equal
== NULL
)
4612 psa
= cast_const_phw_vega10_power_state(pstate1
);
4613 psb
= cast_const_phw_vega10_power_state(pstate2
);
4614 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4615 if (psa
->performance_level_count
!= psb
->performance_level_count
) {
4620 for (i
= 0; i
< psa
->performance_level_count
; i
++) {
4621 if (!vega10_are_power_levels_equal(&(psa
->performance_levels
[i
]), &(psb
->performance_levels
[i
]))) {
4622 /* If we have found even one performance level pair that is different the states are different. */
4628 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4629 *equal
= ((psa
->uvd_clks
.vclk
== psb
->uvd_clks
.vclk
) && (psa
->uvd_clks
.dclk
== psb
->uvd_clks
.dclk
));
4630 *equal
&= ((psa
->vce_clks
.evclk
== psb
->vce_clks
.evclk
) && (psa
->vce_clks
.ecclk
== psb
->vce_clks
.ecclk
));
4631 *equal
&= (psa
->sclk_threshold
== psb
->sclk_threshold
);
4637 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr
*hwmgr
)
4639 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4640 bool is_update_required
= false;
4642 if (data
->display_timing
.num_existing_displays
!= hwmgr
->display_config
->num_display
)
4643 is_update_required
= true;
4645 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep
)) {
4646 if (data
->display_timing
.min_clock_in_sr
!= hwmgr
->display_config
->min_core_set_clock_in_sr
)
4647 is_update_required
= true;
4650 return is_update_required
;
4653 static int vega10_disable_dpm_tasks(struct pp_hwmgr
*hwmgr
)
4655 int tmp_result
, result
= 0;
4657 if (PP_CAP(PHM_PlatformCaps_ThermalController
))
4658 vega10_disable_thermal_protection(hwmgr
);
4660 tmp_result
= vega10_disable_power_containment(hwmgr
);
4661 PP_ASSERT_WITH_CODE((tmp_result
== 0),
4662 "Failed to disable power containment!", result
= tmp_result
);
4664 tmp_result
= vega10_disable_didt_config(hwmgr
);
4665 PP_ASSERT_WITH_CODE((tmp_result
== 0),
4666 "Failed to disable didt config!", result
= tmp_result
);
4668 tmp_result
= vega10_avfs_enable(hwmgr
, false);
4669 PP_ASSERT_WITH_CODE((tmp_result
== 0),
4670 "Failed to disable AVFS!", result
= tmp_result
);
4672 tmp_result
= vega10_stop_dpm(hwmgr
, SMC_DPM_FEATURES
);
4673 PP_ASSERT_WITH_CODE((tmp_result
== 0),
4674 "Failed to stop DPM!", result
= tmp_result
);
4676 tmp_result
= vega10_disable_deep_sleep_master_switch(hwmgr
);
4677 PP_ASSERT_WITH_CODE((tmp_result
== 0),
4678 "Failed to disable deep sleep!", result
= tmp_result
);
4680 tmp_result
= vega10_disable_ulv(hwmgr
);
4681 PP_ASSERT_WITH_CODE((tmp_result
== 0),
4682 "Failed to disable ulv!", result
= tmp_result
);
4684 tmp_result
= vega10_acg_disable(hwmgr
);
4685 PP_ASSERT_WITH_CODE((tmp_result
== 0),
4686 "Failed to disable acg!", result
= tmp_result
);
4688 vega10_enable_disable_PCC_limit_feature(hwmgr
, false);
4692 static int vega10_power_off_asic(struct pp_hwmgr
*hwmgr
)
4694 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4697 result
= vega10_disable_dpm_tasks(hwmgr
);
4698 PP_ASSERT_WITH_CODE((0 == result
),
4699 "[disable_dpm_tasks] Failed to disable DPM!",
4701 data
->water_marks_bitmap
&= ~(WaterMarksLoaded
);
4706 static int vega10_get_sclk_od(struct pp_hwmgr
*hwmgr
)
4708 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4709 struct vega10_single_dpm_table
*sclk_table
= &(data
->dpm_table
.gfx_table
);
4710 struct vega10_single_dpm_table
*golden_sclk_table
=
4711 &(data
->golden_dpm_table
.gfx_table
);
4712 int value
= sclk_table
->dpm_levels
[sclk_table
->count
- 1].value
;
4713 int golden_value
= golden_sclk_table
->dpm_levels
4714 [golden_sclk_table
->count
- 1].value
;
4716 value
-= golden_value
;
4717 value
= DIV_ROUND_UP(value
* 100, golden_value
);
4722 static int vega10_set_sclk_od(struct pp_hwmgr
*hwmgr
, uint32_t value
)
4724 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4725 struct vega10_single_dpm_table
*golden_sclk_table
=
4726 &(data
->golden_dpm_table
.gfx_table
);
4727 struct pp_power_state
*ps
;
4728 struct vega10_power_state
*vega10_ps
;
4730 ps
= hwmgr
->request_ps
;
4735 vega10_ps
= cast_phw_vega10_power_state(&ps
->hardware
);
4737 vega10_ps
->performance_levels
4738 [vega10_ps
->performance_level_count
- 1].gfx_clock
=
4739 golden_sclk_table
->dpm_levels
4740 [golden_sclk_table
->count
- 1].value
*
4742 golden_sclk_table
->dpm_levels
4743 [golden_sclk_table
->count
- 1].value
;
4745 if (vega10_ps
->performance_levels
4746 [vega10_ps
->performance_level_count
- 1].gfx_clock
>
4747 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
) {
4748 vega10_ps
->performance_levels
4749 [vega10_ps
->performance_level_count
- 1].gfx_clock
=
4750 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
;
4751 pr_warn("max sclk supported by vbios is %d\n",
4752 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
);
4757 static int vega10_get_mclk_od(struct pp_hwmgr
*hwmgr
)
4759 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4760 struct vega10_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mem_table
);
4761 struct vega10_single_dpm_table
*golden_mclk_table
=
4762 &(data
->golden_dpm_table
.mem_table
);
4763 int value
= mclk_table
->dpm_levels
[mclk_table
->count
- 1].value
;
4764 int golden_value
= golden_mclk_table
->dpm_levels
4765 [golden_mclk_table
->count
- 1].value
;
4767 value
-= golden_value
;
4768 value
= DIV_ROUND_UP(value
* 100, golden_value
);
4773 static int vega10_set_mclk_od(struct pp_hwmgr
*hwmgr
, uint32_t value
)
4775 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4776 struct vega10_single_dpm_table
*golden_mclk_table
=
4777 &(data
->golden_dpm_table
.mem_table
);
4778 struct pp_power_state
*ps
;
4779 struct vega10_power_state
*vega10_ps
;
4781 ps
= hwmgr
->request_ps
;
4786 vega10_ps
= cast_phw_vega10_power_state(&ps
->hardware
);
4788 vega10_ps
->performance_levels
4789 [vega10_ps
->performance_level_count
- 1].mem_clock
=
4790 golden_mclk_table
->dpm_levels
4791 [golden_mclk_table
->count
- 1].value
*
4793 golden_mclk_table
->dpm_levels
4794 [golden_mclk_table
->count
- 1].value
;
4796 if (vega10_ps
->performance_levels
4797 [vega10_ps
->performance_level_count
- 1].mem_clock
>
4798 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
) {
4799 vega10_ps
->performance_levels
4800 [vega10_ps
->performance_level_count
- 1].mem_clock
=
4801 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
;
4802 pr_warn("max mclk supported by vbios is %d\n",
4803 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
);
4809 static int vega10_notify_cac_buffer_info(struct pp_hwmgr
*hwmgr
,
4810 uint32_t virtual_addr_low
,
4811 uint32_t virtual_addr_hi
,
4812 uint32_t mc_addr_low
,
4813 uint32_t mc_addr_hi
,
4816 smum_send_msg_to_smc_with_parameter(hwmgr
,
4817 PPSMC_MSG_SetSystemVirtualDramAddrHigh
,
4819 smum_send_msg_to_smc_with_parameter(hwmgr
,
4820 PPSMC_MSG_SetSystemVirtualDramAddrLow
,
4822 smum_send_msg_to_smc_with_parameter(hwmgr
,
4823 PPSMC_MSG_DramLogSetDramAddrHigh
,
4826 smum_send_msg_to_smc_with_parameter(hwmgr
,
4827 PPSMC_MSG_DramLogSetDramAddrLow
,
4830 smum_send_msg_to_smc_with_parameter(hwmgr
,
4831 PPSMC_MSG_DramLogSetDramSize
,
4836 static int vega10_get_thermal_temperature_range(struct pp_hwmgr
*hwmgr
,
4837 struct PP_TemperatureRange
*thermal_data
)
4839 struct phm_ppt_v2_information
*table_info
=
4840 (struct phm_ppt_v2_information
*)hwmgr
->pptable
;
4842 memcpy(thermal_data
, &SMU7ThermalWithDelayPolicy
[0], sizeof(struct PP_TemperatureRange
));
4844 thermal_data
->max
= table_info
->tdp_table
->usSoftwareShutdownTemp
*
4845 PP_TEMPERATURE_UNITS_PER_CENTIGRADES
;
4850 static int vega10_get_power_profile_mode(struct pp_hwmgr
*hwmgr
, char *buf
)
4852 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4853 uint32_t i
, size
= 0;
4854 static const uint8_t profile_mode_setting
[6][4] = {{70, 60, 0, 0,},
4861 static const char *profile_name
[7] = {"BOOTUP_DEFAULT",
4868 static const char *title
[6] = {"NUM",
4873 "MIN_ACTIVE_LEVEL"};
4878 size
+= sprintf(buf
+ size
, "%s %16s %s %s %s %s\n",title
[0],
4879 title
[1], title
[2], title
[3], title
[4], title
[5]);
4881 for (i
= 0; i
< PP_SMC_POWER_PROFILE_CUSTOM
; i
++)
4882 size
+= sprintf(buf
+ size
, "%3d %14s%s: %14d %3d %10d %14d\n",
4883 i
, profile_name
[i
], (i
== hwmgr
->power_profile_mode
) ? "*" : " ",
4884 profile_mode_setting
[i
][0], profile_mode_setting
[i
][1],
4885 profile_mode_setting
[i
][2], profile_mode_setting
[i
][3]);
4886 size
+= sprintf(buf
+ size
, "%3d %14s%s: %14d %3d %10d %14d\n", i
,
4887 profile_name
[i
], (i
== hwmgr
->power_profile_mode
) ? "*" : " ",
4888 data
->custom_profile_mode
[0], data
->custom_profile_mode
[1],
4889 data
->custom_profile_mode
[2], data
->custom_profile_mode
[3]);
4893 static int vega10_set_power_profile_mode(struct pp_hwmgr
*hwmgr
, long *input
, uint32_t size
)
4895 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4896 uint8_t busy_set_point
;
4898 uint8_t use_rlc_busy
;
4899 uint8_t min_active_level
;
4901 hwmgr
->power_profile_mode
= input
[size
];
4903 smum_send_msg_to_smc_with_parameter(hwmgr
, PPSMC_MSG_SetWorkloadMask
,
4904 1<<hwmgr
->power_profile_mode
);
4906 if (hwmgr
->power_profile_mode
== PP_SMC_POWER_PROFILE_CUSTOM
) {
4907 if (size
== 0 || size
> 4)
4910 data
->custom_profile_mode
[0] = busy_set_point
= input
[0];
4911 data
->custom_profile_mode
[1] = FPS
= input
[1];
4912 data
->custom_profile_mode
[2] = use_rlc_busy
= input
[2];
4913 data
->custom_profile_mode
[3] = min_active_level
= input
[3];
4914 smum_send_msg_to_smc_with_parameter(hwmgr
,
4915 PPSMC_MSG_SetCustomGfxDpmParameters
,
4916 busy_set_point
| FPS
<<8 |
4917 use_rlc_busy
<< 16 | min_active_level
<<24);
4924 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr
*hwmgr
,
4925 enum PP_OD_DPM_TABLE_COMMAND type
,
4929 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4930 struct vega10_odn_dpm_table
*odn_table
= &(data
->odn_dpm_table
);
4931 struct vega10_single_dpm_table
*golden_table
;
4933 if (voltage
< odn_table
->min_vddc
|| voltage
> odn_table
->max_vddc
) {
4934 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table
->min_vddc
, odn_table
->max_vddc
);
4938 if (type
== PP_OD_EDIT_SCLK_VDDC_TABLE
) {
4939 golden_table
= &(data
->golden_dpm_table
.gfx_table
);
4940 if (golden_table
->dpm_levels
[0].value
> clk
||
4941 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
< clk
) {
4942 pr_info("OD engine clock is out of range [%d - %d] MHz\n",
4943 golden_table
->dpm_levels
[0].value
/100,
4944 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
/100);
4947 } else if (type
== PP_OD_EDIT_MCLK_VDDC_TABLE
) {
4948 golden_table
= &(data
->golden_dpm_table
.mem_table
);
4949 if (golden_table
->dpm_levels
[0].value
> clk
||
4950 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
< clk
) {
4951 pr_info("OD memory clock is out of range [%d - %d] MHz\n",
4952 golden_table
->dpm_levels
[0].value
/100,
4953 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
/100);
4963 static void vega10_odn_update_soc_table(struct pp_hwmgr
*hwmgr
,
4964 enum PP_OD_DPM_TABLE_COMMAND type
)
4966 struct vega10_hwmgr
*data
= hwmgr
->backend
;
4967 struct phm_ppt_v2_information
*table_info
= hwmgr
->pptable
;
4968 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
= table_info
->vdd_dep_on_socclk
;
4969 struct vega10_single_dpm_table
*dpm_table
= &data
->golden_dpm_table
.soc_table
;
4971 struct vega10_odn_clock_voltage_dependency_table
*podn_vdd_dep_on_socclk
=
4972 &data
->odn_dpm_table
.vdd_dep_on_socclk
;
4973 struct vega10_odn_vddc_lookup_table
*od_vddc_lookup_table
= &data
->odn_dpm_table
.vddc_lookup_table
;
4975 struct vega10_odn_clock_voltage_dependency_table
*podn_vdd_dep
;
4978 if (type
== PP_OD_EDIT_SCLK_VDDC_TABLE
) {
4979 podn_vdd_dep
= &data
->odn_dpm_table
.vdd_dep_on_sclk
;
4980 for (i
= 0; i
< podn_vdd_dep
->count
- 1; i
++)
4981 od_vddc_lookup_table
->entries
[i
].us_vdd
= podn_vdd_dep
->entries
[i
].vddc
;
4982 if (od_vddc_lookup_table
->entries
[i
].us_vdd
< podn_vdd_dep
->entries
[i
].vddc
)
4983 od_vddc_lookup_table
->entries
[i
].us_vdd
= podn_vdd_dep
->entries
[i
].vddc
;
4984 } else if (type
== PP_OD_EDIT_MCLK_VDDC_TABLE
) {
4985 podn_vdd_dep
= &data
->odn_dpm_table
.vdd_dep_on_mclk
;
4986 for (i
= 0; i
< dpm_table
->count
; i
++) {
4987 for (j
= 0; j
< od_vddc_lookup_table
->count
; j
++) {
4988 if (od_vddc_lookup_table
->entries
[j
].us_vdd
>
4989 podn_vdd_dep
->entries
[i
].vddc
)
4992 if (j
== od_vddc_lookup_table
->count
) {
4993 od_vddc_lookup_table
->entries
[j
-1].us_vdd
=
4994 podn_vdd_dep
->entries
[i
].vddc
;
4995 data
->need_update_dpm_table
|= DPMTABLE_OD_UPDATE_VDDC
;
4997 podn_vdd_dep
->entries
[i
].vddInd
= j
;
4999 dpm_table
= &data
->dpm_table
.soc_table
;
5000 for (i
= 0; i
< dep_table
->count
; i
++) {
5001 if (dep_table
->entries
[i
].vddInd
== podn_vdd_dep
->entries
[dep_table
->count
-1].vddInd
&&
5002 dep_table
->entries
[i
].clk
< podn_vdd_dep
->entries
[dep_table
->count
-1].clk
) {
5003 data
->need_update_dpm_table
|= DPMTABLE_UPDATE_SOCCLK
;
5004 podn_vdd_dep_on_socclk
->entries
[i
].clk
= podn_vdd_dep
->entries
[dep_table
->count
-1].clk
;
5005 dpm_table
->dpm_levels
[i
].value
= podn_vdd_dep_on_socclk
->entries
[i
].clk
;
5008 if (podn_vdd_dep_on_socclk
->entries
[podn_vdd_dep_on_socclk
->count
- 1].clk
<
5009 podn_vdd_dep
->entries
[dep_table
->count
-1].clk
) {
5010 data
->need_update_dpm_table
|= DPMTABLE_UPDATE_SOCCLK
;
5011 podn_vdd_dep_on_socclk
->entries
[podn_vdd_dep_on_socclk
->count
- 1].clk
= podn_vdd_dep
->entries
[dep_table
->count
-1].clk
;
5012 dpm_table
->dpm_levels
[podn_vdd_dep_on_socclk
->count
- 1].value
= podn_vdd_dep
->entries
[dep_table
->count
-1].clk
;
5014 if (podn_vdd_dep_on_socclk
->entries
[podn_vdd_dep_on_socclk
->count
- 1].vddInd
<
5015 podn_vdd_dep
->entries
[dep_table
->count
-1].vddInd
) {
5016 data
->need_update_dpm_table
|= DPMTABLE_UPDATE_SOCCLK
;
5017 podn_vdd_dep_on_socclk
->entries
[podn_vdd_dep_on_socclk
->count
- 1].vddInd
= podn_vdd_dep
->entries
[dep_table
->count
-1].vddInd
;
5022 static int vega10_odn_edit_dpm_table(struct pp_hwmgr
*hwmgr
,
5023 enum PP_OD_DPM_TABLE_COMMAND type
,
5024 long *input
, uint32_t size
)
5026 struct vega10_hwmgr
*data
= hwmgr
->backend
;
5027 struct vega10_odn_clock_voltage_dependency_table
*podn_vdd_dep_table
;
5028 struct vega10_single_dpm_table
*dpm_table
;
5032 uint32_t input_level
;
5035 PP_ASSERT_WITH_CODE(input
, "NULL user input for clock and voltage",
5038 if (!hwmgr
->od_enabled
) {
5039 pr_info("OverDrive feature not enabled\n");
5043 if (PP_OD_EDIT_SCLK_VDDC_TABLE
== type
) {
5044 dpm_table
= &data
->dpm_table
.gfx_table
;
5045 podn_vdd_dep_table
= &data
->odn_dpm_table
.vdd_dep_on_sclk
;
5046 data
->need_update_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
;
5047 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE
== type
) {
5048 dpm_table
= &data
->dpm_table
.mem_table
;
5049 podn_vdd_dep_table
= &data
->odn_dpm_table
.vdd_dep_on_mclk
;
5050 data
->need_update_dpm_table
|= DPMTABLE_OD_UPDATE_MCLK
;
5051 } else if (PP_OD_RESTORE_DEFAULT_TABLE
== type
) {
5052 memcpy(&(data
->dpm_table
), &(data
->golden_dpm_table
), sizeof(struct vega10_dpm_table
));
5053 vega10_odn_initial_default_setting(hwmgr
);
5055 } else if (PP_OD_COMMIT_DPM_TABLE
== type
) {
5056 vega10_check_dpm_table_updated(hwmgr
);
5062 for (i
= 0; i
< size
; i
+= 3) {
5063 if (i
+ 3 > size
|| input
[i
] >= podn_vdd_dep_table
->count
) {
5064 pr_info("invalid clock voltage input\n");
5067 input_level
= input
[i
];
5068 input_clk
= input
[i
+1] * 100;
5069 input_vol
= input
[i
+2];
5071 if (vega10_check_clk_voltage_valid(hwmgr
, type
, input_clk
, input_vol
)) {
5072 dpm_table
->dpm_levels
[input_level
].value
= input_clk
;
5073 podn_vdd_dep_table
->entries
[input_level
].clk
= input_clk
;
5074 podn_vdd_dep_table
->entries
[input_level
].vddc
= input_vol
;
5079 vega10_odn_update_soc_table(hwmgr
, type
);
5083 static int vega10_get_performance_level(struct pp_hwmgr
*hwmgr
, const struct pp_hw_power_state
*state
,
5084 PHM_PerformanceLevelDesignation designation
, uint32_t index
,
5085 PHM_PerformanceLevel
*level
)
5087 const struct vega10_power_state
*ps
;
5088 struct vega10_hwmgr
*data
;
5091 if (level
== NULL
|| hwmgr
== NULL
|| state
== NULL
)
5094 data
= hwmgr
->backend
;
5095 ps
= cast_const_phw_vega10_power_state(state
);
5097 i
= index
> ps
->performance_level_count
- 1 ?
5098 ps
->performance_level_count
- 1 : index
;
5100 level
->coreClock
= ps
->performance_levels
[i
].gfx_clock
;
5101 level
->memory_clock
= ps
->performance_levels
[i
].mem_clock
;
5106 static const struct pp_hwmgr_func vega10_hwmgr_funcs
= {
5107 .backend_init
= vega10_hwmgr_backend_init
,
5108 .backend_fini
= vega10_hwmgr_backend_fini
,
5109 .asic_setup
= vega10_setup_asic_task
,
5110 .dynamic_state_management_enable
= vega10_enable_dpm_tasks
,
5111 .dynamic_state_management_disable
= vega10_disable_dpm_tasks
,
5112 .get_num_of_pp_table_entries
=
5113 vega10_get_number_of_powerplay_table_entries
,
5114 .get_power_state_size
= vega10_get_power_state_size
,
5115 .get_pp_table_entry
= vega10_get_pp_table_entry
,
5116 .patch_boot_state
= vega10_patch_boot_state
,
5117 .apply_state_adjust_rules
= vega10_apply_state_adjust_rules
,
5118 .power_state_set
= vega10_set_power_state_tasks
,
5119 .get_sclk
= vega10_dpm_get_sclk
,
5120 .get_mclk
= vega10_dpm_get_mclk
,
5121 .notify_smc_display_config_after_ps_adjustment
=
5122 vega10_notify_smc_display_config_after_ps_adjustment
,
5123 .force_dpm_level
= vega10_dpm_force_dpm_level
,
5124 .stop_thermal_controller
= vega10_thermal_stop_thermal_controller
,
5125 .get_fan_speed_info
= vega10_fan_ctrl_get_fan_speed_info
,
5126 .get_fan_speed_percent
= vega10_fan_ctrl_get_fan_speed_percent
,
5127 .set_fan_speed_percent
= vega10_fan_ctrl_set_fan_speed_percent
,
5128 .reset_fan_speed_to_default
=
5129 vega10_fan_ctrl_reset_fan_speed_to_default
,
5130 .get_fan_speed_rpm
= vega10_fan_ctrl_get_fan_speed_rpm
,
5131 .set_fan_speed_rpm
= vega10_fan_ctrl_set_fan_speed_rpm
,
5132 .uninitialize_thermal_controller
=
5133 vega10_thermal_ctrl_uninitialize_thermal_controller
,
5134 .set_fan_control_mode
= vega10_set_fan_control_mode
,
5135 .get_fan_control_mode
= vega10_get_fan_control_mode
,
5136 .read_sensor
= vega10_read_sensor
,
5137 .get_dal_power_level
= vega10_get_dal_power_level
,
5138 .get_clock_by_type_with_latency
= vega10_get_clock_by_type_with_latency
,
5139 .get_clock_by_type_with_voltage
= vega10_get_clock_by_type_with_voltage
,
5140 .set_watermarks_for_clocks_ranges
= vega10_set_watermarks_for_clocks_ranges
,
5141 .display_clock_voltage_request
= vega10_display_clock_voltage_request
,
5142 .force_clock_level
= vega10_force_clock_level
,
5143 .print_clock_levels
= vega10_print_clock_levels
,
5144 .display_config_changed
= vega10_display_configuration_changed_task
,
5145 .powergate_uvd
= vega10_power_gate_uvd
,
5146 .powergate_vce
= vega10_power_gate_vce
,
5147 .check_states_equal
= vega10_check_states_equal
,
5148 .check_smc_update_required_for_display_configuration
=
5149 vega10_check_smc_update_required_for_display_configuration
,
5150 .power_off_asic
= vega10_power_off_asic
,
5151 .disable_smc_firmware_ctf
= vega10_thermal_disable_alert
,
5152 .get_sclk_od
= vega10_get_sclk_od
,
5153 .set_sclk_od
= vega10_set_sclk_od
,
5154 .get_mclk_od
= vega10_get_mclk_od
,
5155 .set_mclk_od
= vega10_set_mclk_od
,
5156 .avfs_control
= vega10_avfs_enable
,
5157 .notify_cac_buffer_info
= vega10_notify_cac_buffer_info
,
5158 .get_thermal_temperature_range
= vega10_get_thermal_temperature_range
,
5159 .register_irq_handlers
= smu9_register_irq_handlers
,
5160 .start_thermal_controller
= vega10_start_thermal_controller
,
5161 .get_power_profile_mode
= vega10_get_power_profile_mode
,
5162 .set_power_profile_mode
= vega10_set_power_profile_mode
,
5163 .set_power_limit
= vega10_set_power_limit
,
5164 .odn_edit_dpm_table
= vega10_odn_edit_dpm_table
,
5165 .get_performance_level
= vega10_get_performance_level
,
5166 .get_asic_baco_capability
= vega10_baco_get_capability
,
5167 .get_asic_baco_state
= vega10_baco_get_state
,
5168 .set_asic_baco_state
= vega10_baco_set_state
,
5169 .enable_mgpu_fan_boost
= vega10_enable_mgpu_fan_boost
,
5170 .get_ppfeature_status
= vega10_get_ppfeature_status
,
5171 .set_ppfeature_status
= vega10_set_ppfeature_status
,
5174 int vega10_hwmgr_init(struct pp_hwmgr
*hwmgr
)
5176 hwmgr
->hwmgr_func
= &vega10_hwmgr_funcs
;
5177 hwmgr
->pptable_func
= &vega10_pptable_funcs
;