drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
   4  * Author: James.Qian.Wang <james.qian.wang@arm.com>
   5  *
   6  */
   7 #include "malidp_io.h"
   8 #include "komeda_dev.h"
   9
  10 static int d71_enum_resources(struct komeda_dev *mdev)
  11 {
  12         /* TODO add enum resources */
  13         return -1;
  14 }
  15
  16 #define __HW_ID(__group, __format) \
  17         ((((__group) & 0x7) << 3) | ((__format) & 0x7))
  18
  19 #define RICH            KOMEDA_FMT_RICH_LAYER
  20 #define SIMPLE          KOMEDA_FMT_SIMPLE_LAYER
  21 #define RICH_SIMPLE     (KOMEDA_FMT_RICH_LAYER | KOMEDA_FMT_SIMPLE_LAYER)
  22 #define RICH_WB         (KOMEDA_FMT_RICH_LAYER | KOMEDA_FMT_WB_LAYER)
  23 #define RICH_SIMPLE_WB  (RICH_SIMPLE | KOMEDA_FMT_WB_LAYER)
  24
  25 #define Rot_0           DRM_MODE_ROTATE_0
  26 #define Flip_H_V        (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | Rot_0)
  27 #define Rot_ALL_H_V     (DRM_MODE_ROTATE_MASK | Flip_H_V)
  28
  29 #define LYT_NM          BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16)
  30 #define LYT_WB          BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8)
  31 #define LYT_NM_WB       (LYT_NM | LYT_WB)
  32
  33 #define AFB_TH          AFBC(_TILED | _SPARSE)
  34 #define AFB_TH_SC_YTR   AFBC(_TILED | _SC | _SPARSE | _YTR)
  35 #define AFB_TH_SC_YTR_BS AFBC(_TILED | _SC | _SPARSE | _YTR | _SPLIT)
  36
  37 static struct komeda_format_caps d71_format_caps_table[] = {
  38         /*   HW_ID    |        fourcc        | tile_sz |   layer_types |   rots    | afbc_layouts | afbc_features */
  39         /* ABGR_2101010*/
  40         {__HW_ID(0, 0), DRM_FORMAT_ARGB2101010, 1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  41         {__HW_ID(0, 1), DRM_FORMAT_ABGR2101010, 1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  42         {__HW_ID(0, 1), DRM_FORMAT_ABGR2101010, 1,      RICH_SIMPLE,    Rot_ALL_H_V,    LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
  43         {__HW_ID(0, 2), DRM_FORMAT_RGBA1010102, 1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  44         {__HW_ID(0, 3), DRM_FORMAT_BGRA1010102, 1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  45         /* ABGR_8888*/
  46         {__HW_ID(1, 0), DRM_FORMAT_ARGB8888,    1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  47         {__HW_ID(1, 1), DRM_FORMAT_ABGR8888,    1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  48         {__HW_ID(1, 1), DRM_FORMAT_ABGR8888,    1,      RICH_SIMPLE,    Rot_ALL_H_V,    LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
  49         {__HW_ID(1, 2), DRM_FORMAT_RGBA8888,    1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  50         {__HW_ID(1, 3), DRM_FORMAT_BGRA8888,    1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  51         /* XBGB_8888 */
  52         {__HW_ID(2, 0), DRM_FORMAT_XRGB8888,    1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  53         {__HW_ID(2, 1), DRM_FORMAT_XBGR8888,    1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  54         {__HW_ID(2, 2), DRM_FORMAT_RGBX8888,    1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  55         {__HW_ID(2, 3), DRM_FORMAT_BGRX8888,    1,      RICH_SIMPLE_WB, Flip_H_V,               0, 0},
  56         /* BGR_888 */ /* none-afbc RGB888 doesn't support rotation and flip */
  57         {__HW_ID(3, 0), DRM_FORMAT_RGB888,      1,      RICH_SIMPLE_WB, Rot_0,                  0, 0},
  58         {__HW_ID(3, 1), DRM_FORMAT_BGR888,      1,      RICH_SIMPLE_WB, Rot_0,                  0, 0},
  59         {__HW_ID(3, 1), DRM_FORMAT_BGR888,      1,      RICH_SIMPLE,    Rot_ALL_H_V,    LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
  60         /* BGR 16bpp */
  61         {__HW_ID(4, 0), DRM_FORMAT_RGBA5551,    1,      RICH_SIMPLE,    Flip_H_V,               0, 0},
  62         {__HW_ID(4, 1), DRM_FORMAT_ABGR1555,    1,      RICH_SIMPLE,    Flip_H_V,               0, 0},
  63         {__HW_ID(4, 1), DRM_FORMAT_ABGR1555,    1,      RICH_SIMPLE,    Rot_ALL_H_V,    LYT_NM_WB, AFB_TH_SC_YTR}, /* afbc */
  64         {__HW_ID(4, 2), DRM_FORMAT_RGB565,      1,      RICH_SIMPLE,    Flip_H_V,               0, 0},
  65         {__HW_ID(4, 3), DRM_FORMAT_BGR565,      1,      RICH_SIMPLE,    Flip_H_V,               0, 0},
  66         {__HW_ID(4, 3), DRM_FORMAT_BGR565,      1,      RICH_SIMPLE,    Rot_ALL_H_V,    LYT_NM_WB, AFB_TH_SC_YTR}, /* afbc */
  67         {__HW_ID(4, 4), DRM_FORMAT_R8,          1,      SIMPLE,         Rot_0,                  0, 0},
  68         /* YUV 444/422/420 8bit  */
  69         {__HW_ID(5, 0), 0 /*XYUV8888*/,         1,      0,              0,                      0, 0},
  70         /* XYUV unsupported*/
  71         {__HW_ID(5, 1), DRM_FORMAT_YUYV,        1,      RICH,           Rot_ALL_H_V,    LYT_NM, AFB_TH}, /* afbc */
  72         {__HW_ID(5, 2), DRM_FORMAT_YUYV,        1,      RICH,           Flip_H_V,               0, 0},
  73         {__HW_ID(5, 3), DRM_FORMAT_UYVY,        1,      RICH,           Flip_H_V,               0, 0},
  74         {__HW_ID(5, 4), 0, /*X0L0 */            2,              0,                      0, 0}, /* Y0L0 unsupported */
  75         {__HW_ID(5, 6), DRM_FORMAT_NV12,        1,      RICH,           Flip_H_V,               0, 0},
  76         {__HW_ID(5, 6), 0/*DRM_FORMAT_YUV420_8BIT*/,    1,      RICH,   Rot_ALL_H_V,    LYT_NM, AFB_TH}, /* afbc */
  77         {__HW_ID(5, 7), DRM_FORMAT_YUV420,      1,      RICH,           Flip_H_V,               0, 0},
  78         /* YUV 10bit*/
  79         {__HW_ID(6, 0), 0,/*XVYU2101010*/       1,      0,              0,                      0, 0},/* VYV30 unsupported */
  80         {__HW_ID(6, 6), 0/*DRM_FORMAT_X0L2*/,   2,      RICH,           Flip_H_V,               0, 0},
  81         {__HW_ID(6, 7), 0/*DRM_FORMAT_P010*/,   1,      RICH,           Flip_H_V,               0, 0},
  82         {__HW_ID(6, 7), 0/*DRM_FORMAT_YUV420_10BIT*/, 1,        RICH,   Rot_ALL_H_V,    LYT_NM, AFB_TH},
  83 };
  84
  85 static void d71_init_fmt_tbl(struct komeda_dev *mdev)
  86 {
  87         struct komeda_format_caps_table *table = &mdev->fmt_tbl;
  88
  89         table->format_caps = d71_format_caps_table;
  90         table->n_formats = ARRAY_SIZE(d71_format_caps_table);
  91 }
  92
  93 static struct komeda_dev_funcs d71_chip_funcs = {
  94         .init_format_table = d71_init_fmt_tbl,
  95         .enum_resources = d71_enum_resources,
  96         .cleanup        = NULL,
  97 };
  98
  99 #define GLB_ARCH_ID             0x000
 100 #define GLB_CORE_ID             0x004
 101 #define GLB_CORE_INFO           0x008
 102
 103 struct komeda_dev_funcs *
 104 d71_identify(u32 __iomem *reg_base, struct komeda_chip_info *chip)
 105 {
 106         chip->arch_id   = malidp_read32(reg_base, GLB_ARCH_ID);
 107         chip->core_id   = malidp_read32(reg_base, GLB_CORE_ID);
 108         chip->core_info = malidp_read32(reg_base, GLB_CORE_INFO);
 109
 110         return &d71_chip_funcs;
 111 }