1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/hdmi.h>
13 #include <linux/i2c.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/regmap.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/spinlock.h>
23 #include <media/cec-notifier.h>
25 #include <uapi/linux/media-bus-format.h>
26 #include <uapi/linux/videodev2.h>
28 #include <drm/bridge/dw_hdmi.h>
29 #include <drm/display/drm_hdmi_helper.h>
30 #include <drm/display/drm_scdc_helper.h>
31 #include <drm/drm_atomic.h>
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_bridge.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_of.h>
36 #include <drm/drm_print.h>
37 #include <drm/drm_probe_helper.h>
39 #include "dw-hdmi-audio.h"
40 #include "dw-hdmi-cec.h"
43 #define DDC_CI_ADDR 0x37
44 #define DDC_SEGMENT_ADDR 0x30
46 #define HDMI_EDID_LEN 512
48 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
49 #define SCDC_MIN_SOURCE_VERSION 0x1
51 #define HDMI14_MAX_TMDSCLK 340000000
53 static const u16 csc_coeff_default
[3][4] = {
54 { 0x2000, 0x0000, 0x0000, 0x0000 },
55 { 0x0000, 0x2000, 0x0000, 0x0000 },
56 { 0x0000, 0x0000, 0x2000, 0x0000 }
59 static const u16 csc_coeff_rgb_out_eitu601
[3][4] = {
60 { 0x2000, 0x6926, 0x74fd, 0x010e },
61 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
62 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
65 static const u16 csc_coeff_rgb_out_eitu709
[3][4] = {
66 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
67 { 0x2000, 0x3264, 0x0000, 0x7e6d },
68 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
71 static const u16 csc_coeff_rgb_in_eitu601
[3][4] = {
72 { 0x2591, 0x1322, 0x074b, 0x0000 },
73 { 0x6535, 0x2000, 0x7acc, 0x0200 },
74 { 0x6acd, 0x7534, 0x2000, 0x0200 }
77 static const u16 csc_coeff_rgb_in_eitu709
[3][4] = {
78 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
79 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
80 { 0x6756, 0x78ab, 0x2000, 0x0200 }
83 static const u16 csc_coeff_rgb_full_to_rgb_limited
[3][4] = {
84 { 0x1b7c, 0x0000, 0x0000, 0x0020 },
85 { 0x0000, 0x1b7c, 0x0000, 0x0020 },
86 { 0x0000, 0x0000, 0x1b7c, 0x0020 }
90 bool mdataenablepolarity
;
92 unsigned int mpixelclock
;
93 unsigned int mpixelrepetitioninput
;
94 unsigned int mpixelrepetitionoutput
;
95 unsigned int mtmdsclock
;
98 struct hdmi_data_info
{
99 unsigned int enc_in_bus_format
;
100 unsigned int enc_out_bus_format
;
101 unsigned int enc_in_encoding
;
102 unsigned int enc_out_encoding
;
103 unsigned int pix_repet_factor
;
104 unsigned int hdcp_enable
;
105 struct hdmi_vmode video_mode
;
106 bool rgb_limited_range
;
110 struct i2c_adapter adap
;
112 struct mutex lock
; /* used to serialize data transfers */
113 struct completion cmp
;
121 struct dw_hdmi_phy_data
{
122 enum dw_hdmi_phy_type type
;
126 int (*configure
)(struct dw_hdmi
*hdmi
,
127 const struct dw_hdmi_plat_data
*pdata
,
128 unsigned long mpixelclock
);
132 struct drm_connector connector
;
133 struct drm_bridge bridge
;
134 struct drm_bridge
*next_bridge
;
136 unsigned int version
;
138 struct platform_device
*audio
;
139 struct platform_device
*cec
;
141 struct clk
*isfr_clk
;
142 struct clk
*iahb_clk
;
144 struct dw_hdmi_i2c
*i2c
;
146 struct hdmi_data_info hdmi_data
;
147 const struct dw_hdmi_plat_data
*plat_data
;
151 u8 edid
[HDMI_EDID_LEN
];
154 const struct dw_hdmi_phy_ops
*ops
;
160 struct drm_display_mode previous_mode
;
162 struct i2c_adapter
*ddc
;
167 struct pinctrl
*pinctrl
;
168 struct pinctrl_state
*default_state
;
169 struct pinctrl_state
*unwedge_state
;
171 struct mutex mutex
; /* for state below and previous_mode */
172 enum drm_connector_force force
; /* mutex-protected force state */
173 struct drm_connector
*curr_conn
;/* current connector (only valid when !disabled) */
174 bool disabled
; /* DRM has disabled our bridge */
175 bool bridge_is_on
; /* indicates the bridge is on */
176 bool rxsense
; /* rxsense state */
177 u8 phy_mask
; /* desired phy int mask settings */
178 u8 mc_clkdis
; /* clock disable register */
180 spinlock_t audio_lock
;
181 struct mutex audio_mutex
;
182 unsigned int sample_non_pcm
;
183 unsigned int sample_width
;
184 unsigned int sample_rate
;
185 unsigned int channels
;
186 unsigned int audio_cts
;
187 unsigned int audio_n
;
190 unsigned int reg_shift
;
192 void (*enable_audio
)(struct dw_hdmi
*hdmi
);
193 void (*disable_audio
)(struct dw_hdmi
*hdmi
);
195 struct mutex cec_notifier_mutex
;
196 struct cec_notifier
*cec_notifier
;
198 hdmi_codec_plugged_cb plugged_cb
;
199 struct device
*codec_dev
;
200 enum drm_connector_status last_connector_result
;
203 #define HDMI_IH_PHY_STAT0_RX_SENSE \
204 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
205 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
207 #define HDMI_PHY_RX_SENSE \
208 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
209 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
211 static inline void hdmi_writeb(struct dw_hdmi
*hdmi
, u8 val
, int offset
)
213 regmap_write(hdmi
->regm
, offset
<< hdmi
->reg_shift
, val
);
216 static inline u8
hdmi_readb(struct dw_hdmi
*hdmi
, int offset
)
218 unsigned int val
= 0;
220 regmap_read(hdmi
->regm
, offset
<< hdmi
->reg_shift
, &val
);
225 static void handle_plugged_change(struct dw_hdmi
*hdmi
, bool plugged
)
227 if (hdmi
->plugged_cb
&& hdmi
->codec_dev
)
228 hdmi
->plugged_cb(hdmi
->codec_dev
, plugged
);
231 int dw_hdmi_set_plugged_cb(struct dw_hdmi
*hdmi
, hdmi_codec_plugged_cb fn
,
232 struct device
*codec_dev
)
236 mutex_lock(&hdmi
->mutex
);
237 hdmi
->plugged_cb
= fn
;
238 hdmi
->codec_dev
= codec_dev
;
239 plugged
= hdmi
->last_connector_result
== connector_status_connected
;
240 handle_plugged_change(hdmi
, plugged
);
241 mutex_unlock(&hdmi
->mutex
);
245 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb
);
247 static void hdmi_modb(struct dw_hdmi
*hdmi
, u8 data
, u8 mask
, unsigned reg
)
249 regmap_update_bits(hdmi
->regm
, reg
<< hdmi
->reg_shift
, mask
, data
);
252 static void hdmi_mask_writeb(struct dw_hdmi
*hdmi
, u8 data
, unsigned int reg
,
255 hdmi_modb(hdmi
, data
<< shift
, mask
, reg
);
258 static void dw_hdmi_i2c_init(struct dw_hdmi
*hdmi
)
260 hdmi_writeb(hdmi
, HDMI_PHY_I2CM_INT_ADDR_DONE_POL
,
261 HDMI_PHY_I2CM_INT_ADDR
);
263 hdmi_writeb(hdmi
, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL
|
264 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL
,
265 HDMI_PHY_I2CM_CTLINT_ADDR
);
268 hdmi_writeb(hdmi
, 0x00, HDMI_I2CM_SOFTRSTZ
);
270 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
271 hdmi_writeb(hdmi
, 0x00, HDMI_I2CM_DIV
);
273 /* Set done, not acknowledged and arbitration interrupt polarities */
274 hdmi_writeb(hdmi
, HDMI_I2CM_INT_DONE_POL
, HDMI_I2CM_INT
);
275 hdmi_writeb(hdmi
, HDMI_I2CM_CTLINT_NAC_POL
| HDMI_I2CM_CTLINT_ARB_POL
,
278 /* Clear DONE and ERROR interrupts */
279 hdmi_writeb(hdmi
, HDMI_IH_I2CM_STAT0_ERROR
| HDMI_IH_I2CM_STAT0_DONE
,
282 /* Mute DONE and ERROR interrupts */
283 hdmi_writeb(hdmi
, HDMI_IH_I2CM_STAT0_ERROR
| HDMI_IH_I2CM_STAT0_DONE
,
284 HDMI_IH_MUTE_I2CM_STAT0
);
287 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi
*hdmi
)
289 /* If no unwedge state then give up */
290 if (!hdmi
->unwedge_state
)
293 dev_info(hdmi
->dev
, "Attempting to unwedge stuck i2c bus\n");
296 * This is a huge hack to workaround a problem where the dw_hdmi i2c
297 * bus could sometimes get wedged. Once wedged there doesn't appear
298 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
299 * other than pulsing the SDA line.
301 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
303 * 1. Remux the pin as a GPIO output, driven low.
304 * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
305 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
307 * At the moment of remuxing, the line will still be low due to its
308 * recent stint as an output, but then it will be pulled high by the
309 * (presumed) external pullup. dw_hdmi seems to see this as a rising
310 * edge and that seems to get it out of its jam.
312 * This wedging was only ever seen on one TV, and only on one of
313 * its HDMI ports. It happened when the TV was powered on while the
314 * device was plugged in. A scope trace shows the TV bringing both SDA
315 * and SCL low, then bringing them both back up at roughly the same
316 * time. Presumably this confuses dw_hdmi because it saw activity but
317 * no real STOP (maybe it thinks there's another master on the bus?).
318 * Giving it a clean rising edge of SDA while SCL is already high
319 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
322 * Note that after coming back alive, transfers seem to immediately
323 * resume, so if we unwedge due to a timeout we should wait a little
324 * longer for our transfer to finish, since it might have just started
327 pinctrl_select_state(hdmi
->pinctrl
, hdmi
->unwedge_state
);
329 pinctrl_select_state(hdmi
->pinctrl
, hdmi
->default_state
);
334 static int dw_hdmi_i2c_wait(struct dw_hdmi
*hdmi
)
336 struct dw_hdmi_i2c
*i2c
= hdmi
->i2c
;
339 stat
= wait_for_completion_timeout(&i2c
->cmp
, HZ
/ 10);
341 /* If we can't unwedge, return timeout */
342 if (!dw_hdmi_i2c_unwedge(hdmi
))
345 /* We tried to unwedge; give it another chance */
346 stat
= wait_for_completion_timeout(&i2c
->cmp
, HZ
/ 10);
351 /* Check for error condition on the bus */
352 if (i2c
->stat
& HDMI_IH_I2CM_STAT0_ERROR
)
358 static int dw_hdmi_i2c_read(struct dw_hdmi
*hdmi
,
359 unsigned char *buf
, unsigned int length
)
361 struct dw_hdmi_i2c
*i2c
= hdmi
->i2c
;
364 if (!i2c
->is_regaddr
) {
365 dev_dbg(hdmi
->dev
, "set read register address to 0\n");
366 i2c
->slave_reg
= 0x00;
367 i2c
->is_regaddr
= true;
371 reinit_completion(&i2c
->cmp
);
373 hdmi_writeb(hdmi
, i2c
->slave_reg
++, HDMI_I2CM_ADDRESS
);
375 hdmi_writeb(hdmi
, HDMI_I2CM_OPERATION_READ_EXT
,
376 HDMI_I2CM_OPERATION
);
378 hdmi_writeb(hdmi
, HDMI_I2CM_OPERATION_READ
,
379 HDMI_I2CM_OPERATION
);
381 ret
= dw_hdmi_i2c_wait(hdmi
);
385 *buf
++ = hdmi_readb(hdmi
, HDMI_I2CM_DATAI
);
387 i2c
->is_segment
= false;
392 static int dw_hdmi_i2c_write(struct dw_hdmi
*hdmi
,
393 unsigned char *buf
, unsigned int length
)
395 struct dw_hdmi_i2c
*i2c
= hdmi
->i2c
;
398 if (!i2c
->is_regaddr
) {
399 /* Use the first write byte as register address */
400 i2c
->slave_reg
= buf
[0];
403 i2c
->is_regaddr
= true;
407 reinit_completion(&i2c
->cmp
);
409 hdmi_writeb(hdmi
, *buf
++, HDMI_I2CM_DATAO
);
410 hdmi_writeb(hdmi
, i2c
->slave_reg
++, HDMI_I2CM_ADDRESS
);
411 hdmi_writeb(hdmi
, HDMI_I2CM_OPERATION_WRITE
,
412 HDMI_I2CM_OPERATION
);
414 ret
= dw_hdmi_i2c_wait(hdmi
);
422 static int dw_hdmi_i2c_xfer(struct i2c_adapter
*adap
,
423 struct i2c_msg
*msgs
, int num
)
425 struct dw_hdmi
*hdmi
= i2c_get_adapdata(adap
);
426 struct dw_hdmi_i2c
*i2c
= hdmi
->i2c
;
427 u8 addr
= msgs
[0].addr
;
430 if (addr
== DDC_CI_ADDR
)
432 * The internal I2C controller does not support the multi-byte
433 * read and write operations needed for DDC/CI.
434 * TOFIX: Blacklist the DDC/CI address until we filter out
435 * unsupported I2C operations.
439 dev_dbg(hdmi
->dev
, "xfer: num: %d, addr: %#x\n", num
, addr
);
441 for (i
= 0; i
< num
; i
++) {
442 if (msgs
[i
].len
== 0) {
444 "unsupported transfer %d/%d, no data\n",
450 mutex_lock(&i2c
->lock
);
452 /* Unmute DONE and ERROR interrupts */
453 hdmi_writeb(hdmi
, 0x00, HDMI_IH_MUTE_I2CM_STAT0
);
455 /* Set slave device address taken from the first I2C message */
456 hdmi_writeb(hdmi
, addr
, HDMI_I2CM_SLAVE
);
458 /* Set slave device register address on transfer */
459 i2c
->is_regaddr
= false;
461 /* Set segment pointer for I2C extended read mode operation */
462 i2c
->is_segment
= false;
464 for (i
= 0; i
< num
; i
++) {
465 dev_dbg(hdmi
->dev
, "xfer: num: %d/%d, len: %d, flags: %#x\n",
466 i
+ 1, num
, msgs
[i
].len
, msgs
[i
].flags
);
467 if (msgs
[i
].addr
== DDC_SEGMENT_ADDR
&& msgs
[i
].len
== 1) {
468 i2c
->is_segment
= true;
469 hdmi_writeb(hdmi
, DDC_SEGMENT_ADDR
, HDMI_I2CM_SEGADDR
);
470 hdmi_writeb(hdmi
, *msgs
[i
].buf
, HDMI_I2CM_SEGPTR
);
472 if (msgs
[i
].flags
& I2C_M_RD
)
473 ret
= dw_hdmi_i2c_read(hdmi
, msgs
[i
].buf
,
476 ret
= dw_hdmi_i2c_write(hdmi
, msgs
[i
].buf
,
486 /* Mute DONE and ERROR interrupts */
487 hdmi_writeb(hdmi
, HDMI_IH_I2CM_STAT0_ERROR
| HDMI_IH_I2CM_STAT0_DONE
,
488 HDMI_IH_MUTE_I2CM_STAT0
);
490 mutex_unlock(&i2c
->lock
);
495 static u32
dw_hdmi_i2c_func(struct i2c_adapter
*adapter
)
497 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
500 static const struct i2c_algorithm dw_hdmi_algorithm
= {
501 .master_xfer
= dw_hdmi_i2c_xfer
,
502 .functionality
= dw_hdmi_i2c_func
,
505 static struct i2c_adapter
*dw_hdmi_i2c_adapter(struct dw_hdmi
*hdmi
)
507 struct i2c_adapter
*adap
;
508 struct dw_hdmi_i2c
*i2c
;
511 i2c
= devm_kzalloc(hdmi
->dev
, sizeof(*i2c
), GFP_KERNEL
);
513 return ERR_PTR(-ENOMEM
);
515 mutex_init(&i2c
->lock
);
516 init_completion(&i2c
->cmp
);
519 adap
->owner
= THIS_MODULE
;
520 adap
->dev
.parent
= hdmi
->dev
;
521 adap
->algo
= &dw_hdmi_algorithm
;
522 strscpy(adap
->name
, "DesignWare HDMI", sizeof(adap
->name
));
523 i2c_set_adapdata(adap
, hdmi
);
525 ret
= i2c_add_adapter(adap
);
527 dev_warn(hdmi
->dev
, "cannot add %s I2C adapter\n", adap
->name
);
528 devm_kfree(hdmi
->dev
, i2c
);
534 dev_info(hdmi
->dev
, "registered %s I2C bus driver\n", adap
->name
);
539 static void hdmi_set_cts_n(struct dw_hdmi
*hdmi
, unsigned int cts
,
542 /* Must be set/cleared first */
543 hdmi_modb(hdmi
, 0, HDMI_AUD_CTS3_CTS_MANUAL
, HDMI_AUD_CTS3
);
545 /* nshift factor = 0 */
546 hdmi_modb(hdmi
, 0, HDMI_AUD_CTS3_N_SHIFT_MASK
, HDMI_AUD_CTS3
);
548 /* Use automatic CTS generation mode when CTS is not set */
550 hdmi_writeb(hdmi
, ((cts
>> 16) &
551 HDMI_AUD_CTS3_AUDCTS19_16_MASK
) |
552 HDMI_AUD_CTS3_CTS_MANUAL
,
555 hdmi_writeb(hdmi
, 0, HDMI_AUD_CTS3
);
556 hdmi_writeb(hdmi
, (cts
>> 8) & 0xff, HDMI_AUD_CTS2
);
557 hdmi_writeb(hdmi
, cts
& 0xff, HDMI_AUD_CTS1
);
559 hdmi_writeb(hdmi
, (n
>> 16) & 0x0f, HDMI_AUD_N3
);
560 hdmi_writeb(hdmi
, (n
>> 8) & 0xff, HDMI_AUD_N2
);
561 hdmi_writeb(hdmi
, n
& 0xff, HDMI_AUD_N1
);
564 static unsigned int hdmi_compute_n(unsigned int freq
, unsigned long pixel_clk
)
566 unsigned int n
= (128 * freq
) / 1000;
567 unsigned int mult
= 1;
569 while (freq
> 48000) {
576 if (pixel_clk
== 25175000)
578 else if (pixel_clk
== 27027000)
580 else if (pixel_clk
== 74176000 || pixel_clk
== 148352000)
582 else if (pixel_clk
== 297000000)
590 if (pixel_clk
== 25175000)
592 else if (pixel_clk
== 74176000)
594 else if (pixel_clk
== 148352000)
596 else if (pixel_clk
== 297000000)
604 if (pixel_clk
== 25175000)
606 else if (pixel_clk
== 27027000)
608 else if (pixel_clk
== 74176000)
610 else if (pixel_clk
== 148352000)
612 else if (pixel_clk
== 297000000)
627 * When transmitting IEC60958 linear PCM audio, these registers allow to
628 * configure the channel status information of all the channel status
629 * bits in the IEC60958 frame. For the moment this configuration is only
630 * used when the I2S audio interface, General Purpose Audio (GPA),
631 * or AHB audio DMA (AHBAUDDMA) interface is active
632 * (for S/PDIF interface this information comes from the stream).
634 void dw_hdmi_set_channel_status(struct dw_hdmi
*hdmi
,
638 * Set channel status register for frequency and word length.
639 * Use default values for other registers.
641 hdmi_writeb(hdmi
, channel_status
[3], HDMI_FC_AUDSCHNLS7
);
642 hdmi_writeb(hdmi
, channel_status
[4], HDMI_FC_AUDSCHNLS8
);
644 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status
);
646 static void hdmi_set_clk_regenerator(struct dw_hdmi
*hdmi
,
647 unsigned long pixel_clk
, unsigned int sample_rate
)
649 unsigned long ftdms
= pixel_clk
;
654 n
= hdmi_compute_n(sample_rate
, pixel_clk
);
656 config3
= hdmi_readb(hdmi
, HDMI_CONFIG3_ID
);
658 /* Compute CTS when using internal AHB audio or General Parallel audio*/
659 if ((config3
& HDMI_CONFIG3_AHBAUDDMA
) || (config3
& HDMI_CONFIG3_GPAUD
)) {
661 * Compute the CTS value from the N value. Note that CTS and N
662 * can be up to 20 bits in total, so we need 64-bit math. Also
663 * note that our TDMS clock is not fully accurate; it is
664 * accurate to kHz. This can introduce an unnecessary remainder
665 * in the calculation below, so we don't try to warn about that.
667 tmp
= (u64
)ftdms
* n
;
668 do_div(tmp
, 128 * sample_rate
);
671 dev_dbg(hdmi
->dev
, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
672 __func__
, sample_rate
,
673 ftdms
/ 1000000, (ftdms
/ 1000) % 1000,
679 spin_lock_irq(&hdmi
->audio_lock
);
681 hdmi
->audio_cts
= cts
;
682 hdmi_set_cts_n(hdmi
, cts
, hdmi
->audio_enable
? n
: 0);
683 spin_unlock_irq(&hdmi
->audio_lock
);
686 static void hdmi_init_clk_regenerator(struct dw_hdmi
*hdmi
)
688 mutex_lock(&hdmi
->audio_mutex
);
689 hdmi_set_clk_regenerator(hdmi
, 74250000, hdmi
->sample_rate
);
690 mutex_unlock(&hdmi
->audio_mutex
);
693 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi
*hdmi
)
695 mutex_lock(&hdmi
->audio_mutex
);
696 hdmi_set_clk_regenerator(hdmi
, hdmi
->hdmi_data
.video_mode
.mtmdsclock
,
698 mutex_unlock(&hdmi
->audio_mutex
);
701 void dw_hdmi_set_sample_width(struct dw_hdmi
*hdmi
, unsigned int width
)
703 mutex_lock(&hdmi
->audio_mutex
);
704 hdmi
->sample_width
= width
;
705 mutex_unlock(&hdmi
->audio_mutex
);
707 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width
);
709 void dw_hdmi_set_sample_non_pcm(struct dw_hdmi
*hdmi
, unsigned int non_pcm
)
711 mutex_lock(&hdmi
->audio_mutex
);
712 hdmi
->sample_non_pcm
= non_pcm
;
713 mutex_unlock(&hdmi
->audio_mutex
);
715 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm
);
717 void dw_hdmi_set_sample_rate(struct dw_hdmi
*hdmi
, unsigned int rate
)
719 mutex_lock(&hdmi
->audio_mutex
);
720 hdmi
->sample_rate
= rate
;
721 hdmi_set_clk_regenerator(hdmi
, hdmi
->hdmi_data
.video_mode
.mtmdsclock
,
723 mutex_unlock(&hdmi
->audio_mutex
);
725 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate
);
727 void dw_hdmi_set_channel_count(struct dw_hdmi
*hdmi
, unsigned int cnt
)
731 mutex_lock(&hdmi
->audio_mutex
);
732 hdmi
->channels
= cnt
;
735 * For >2 channel PCM audio, we need to select layout 1
736 * and set an appropriate channel map.
739 layout
= HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1
;
741 layout
= HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0
;
743 hdmi_modb(hdmi
, layout
, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK
,
746 /* Set the audio infoframes channel count */
747 hdmi_modb(hdmi
, (cnt
- 1) << HDMI_FC_AUDICONF0_CC_OFFSET
,
748 HDMI_FC_AUDICONF0_CC_MASK
, HDMI_FC_AUDICONF0
);
750 mutex_unlock(&hdmi
->audio_mutex
);
752 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count
);
754 void dw_hdmi_set_channel_allocation(struct dw_hdmi
*hdmi
, unsigned int ca
)
756 mutex_lock(&hdmi
->audio_mutex
);
758 hdmi_writeb(hdmi
, ca
, HDMI_FC_AUDICONF2
);
760 mutex_unlock(&hdmi
->audio_mutex
);
762 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation
);
764 static void hdmi_enable_audio_clk(struct dw_hdmi
*hdmi
, bool enable
)
767 hdmi
->mc_clkdis
&= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE
;
769 hdmi
->mc_clkdis
|= HDMI_MC_CLKDIS_AUDCLK_DISABLE
;
770 hdmi_writeb(hdmi
, hdmi
->mc_clkdis
, HDMI_MC_CLKDIS
);
773 static u8
*hdmi_audio_get_eld(struct dw_hdmi
*hdmi
)
775 if (!hdmi
->curr_conn
)
778 return hdmi
->curr_conn
->eld
;
781 static void dw_hdmi_gp_audio_enable(struct dw_hdmi
*hdmi
)
783 const struct dw_hdmi_plat_data
*pdata
= hdmi
->plat_data
;
784 int sample_freq
= 0x2, org_sample_freq
= 0xD;
785 int ch_mask
= BIT(hdmi
->channels
) - 1;
787 switch (hdmi
->sample_rate
) {
790 org_sample_freq
= 0x0C;
794 org_sample_freq
= 0x0F;
798 org_sample_freq
= 0x0D;
802 org_sample_freq
= 0x07;
806 org_sample_freq
= 0x05;
810 org_sample_freq
= 0x03;
814 org_sample_freq
= 0x01;
820 hdmi_set_cts_n(hdmi
, hdmi
->audio_cts
, hdmi
->audio_n
);
821 hdmi_enable_audio_clk(hdmi
, true);
823 hdmi_writeb(hdmi
, 0x1, HDMI_FC_AUDSCHNLS0
);
824 hdmi_writeb(hdmi
, hdmi
->channels
, HDMI_FC_AUDSCHNLS2
);
825 hdmi_writeb(hdmi
, 0x22, HDMI_FC_AUDSCHNLS3
);
826 hdmi_writeb(hdmi
, 0x22, HDMI_FC_AUDSCHNLS4
);
827 hdmi_writeb(hdmi
, 0x11, HDMI_FC_AUDSCHNLS5
);
828 hdmi_writeb(hdmi
, 0x11, HDMI_FC_AUDSCHNLS6
);
829 hdmi_writeb(hdmi
, (0x3 << 4) | sample_freq
, HDMI_FC_AUDSCHNLS7
);
830 hdmi_writeb(hdmi
, (org_sample_freq
<< 4) | 0xb, HDMI_FC_AUDSCHNLS8
);
832 hdmi_writeb(hdmi
, ch_mask
, HDMI_GP_CONF1
);
833 hdmi_writeb(hdmi
, 0x02, HDMI_GP_CONF2
);
834 hdmi_writeb(hdmi
, 0x01, HDMI_GP_CONF0
);
836 hdmi_modb(hdmi
, 0x3, 0x3, HDMI_FC_DATAUTO3
);
839 if (hdmi
->sample_rate
== 192000 && hdmi
->channels
== 8 &&
840 hdmi
->sample_width
== 32 && hdmi
->sample_non_pcm
)
841 hdmi_modb(hdmi
, 0x01, 0x01, HDMI_GP_CONF2
);
843 if (pdata
->enable_audio
)
844 pdata
->enable_audio(hdmi
,
848 hdmi
->sample_non_pcm
);
851 static void dw_hdmi_gp_audio_disable(struct dw_hdmi
*hdmi
)
853 const struct dw_hdmi_plat_data
*pdata
= hdmi
->plat_data
;
855 hdmi_set_cts_n(hdmi
, hdmi
->audio_cts
, 0);
857 hdmi_modb(hdmi
, 0, 0x3, HDMI_FC_DATAUTO3
);
858 if (pdata
->disable_audio
)
859 pdata
->disable_audio(hdmi
);
861 hdmi_enable_audio_clk(hdmi
, false);
864 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi
*hdmi
)
866 hdmi_set_cts_n(hdmi
, hdmi
->audio_cts
, hdmi
->audio_n
);
869 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi
*hdmi
)
871 hdmi_set_cts_n(hdmi
, hdmi
->audio_cts
, 0);
874 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi
*hdmi
)
876 hdmi_set_cts_n(hdmi
, hdmi
->audio_cts
, hdmi
->audio_n
);
877 hdmi_enable_audio_clk(hdmi
, true);
880 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi
*hdmi
)
882 hdmi_enable_audio_clk(hdmi
, false);
885 void dw_hdmi_audio_enable(struct dw_hdmi
*hdmi
)
889 spin_lock_irqsave(&hdmi
->audio_lock
, flags
);
890 hdmi
->audio_enable
= true;
891 if (hdmi
->enable_audio
)
892 hdmi
->enable_audio(hdmi
);
893 spin_unlock_irqrestore(&hdmi
->audio_lock
, flags
);
895 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable
);
897 void dw_hdmi_audio_disable(struct dw_hdmi
*hdmi
)
901 spin_lock_irqsave(&hdmi
->audio_lock
, flags
);
902 hdmi
->audio_enable
= false;
903 if (hdmi
->disable_audio
)
904 hdmi
->disable_audio(hdmi
);
905 spin_unlock_irqrestore(&hdmi
->audio_lock
, flags
);
907 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable
);
909 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format
)
911 switch (bus_format
) {
912 case MEDIA_BUS_FMT_RGB888_1X24
:
913 case MEDIA_BUS_FMT_RGB101010_1X30
:
914 case MEDIA_BUS_FMT_RGB121212_1X36
:
915 case MEDIA_BUS_FMT_RGB161616_1X48
:
923 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format
)
925 switch (bus_format
) {
926 case MEDIA_BUS_FMT_YUV8_1X24
:
927 case MEDIA_BUS_FMT_YUV10_1X30
:
928 case MEDIA_BUS_FMT_YUV12_1X36
:
929 case MEDIA_BUS_FMT_YUV16_1X48
:
937 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format
)
939 switch (bus_format
) {
940 case MEDIA_BUS_FMT_UYVY8_1X16
:
941 case MEDIA_BUS_FMT_UYVY10_1X20
:
942 case MEDIA_BUS_FMT_UYVY12_1X24
:
950 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format
)
952 switch (bus_format
) {
953 case MEDIA_BUS_FMT_UYYVYY8_0_5X24
:
954 case MEDIA_BUS_FMT_UYYVYY10_0_5X30
:
955 case MEDIA_BUS_FMT_UYYVYY12_0_5X36
:
956 case MEDIA_BUS_FMT_UYYVYY16_0_5X48
:
964 static int hdmi_bus_fmt_color_depth(unsigned int bus_format
)
966 switch (bus_format
) {
967 case MEDIA_BUS_FMT_RGB888_1X24
:
968 case MEDIA_BUS_FMT_YUV8_1X24
:
969 case MEDIA_BUS_FMT_UYVY8_1X16
:
970 case MEDIA_BUS_FMT_UYYVYY8_0_5X24
:
973 case MEDIA_BUS_FMT_RGB101010_1X30
:
974 case MEDIA_BUS_FMT_YUV10_1X30
:
975 case MEDIA_BUS_FMT_UYVY10_1X20
:
976 case MEDIA_BUS_FMT_UYYVYY10_0_5X30
:
979 case MEDIA_BUS_FMT_RGB121212_1X36
:
980 case MEDIA_BUS_FMT_YUV12_1X36
:
981 case MEDIA_BUS_FMT_UYVY12_1X24
:
982 case MEDIA_BUS_FMT_UYYVYY12_0_5X36
:
985 case MEDIA_BUS_FMT_RGB161616_1X48
:
986 case MEDIA_BUS_FMT_YUV16_1X48
:
987 case MEDIA_BUS_FMT_UYYVYY16_0_5X48
:
996 * this submodule is responsible for the video data synchronization.
997 * for example, for RGB 4:4:4 input, the data map is defined as
998 * pin{47~40} <==> R[7:0]
999 * pin{31~24} <==> G[7:0]
1000 * pin{15~8} <==> B[7:0]
1002 static void hdmi_video_sample(struct dw_hdmi
*hdmi
)
1004 int color_format
= 0;
1007 switch (hdmi
->hdmi_data
.enc_in_bus_format
) {
1008 case MEDIA_BUS_FMT_RGB888_1X24
:
1009 color_format
= 0x01;
1011 case MEDIA_BUS_FMT_RGB101010_1X30
:
1012 color_format
= 0x03;
1014 case MEDIA_BUS_FMT_RGB121212_1X36
:
1015 color_format
= 0x05;
1017 case MEDIA_BUS_FMT_RGB161616_1X48
:
1018 color_format
= 0x07;
1021 case MEDIA_BUS_FMT_YUV8_1X24
:
1022 case MEDIA_BUS_FMT_UYYVYY8_0_5X24
:
1023 color_format
= 0x09;
1025 case MEDIA_BUS_FMT_YUV10_1X30
:
1026 case MEDIA_BUS_FMT_UYYVYY10_0_5X30
:
1027 color_format
= 0x0B;
1029 case MEDIA_BUS_FMT_YUV12_1X36
:
1030 case MEDIA_BUS_FMT_UYYVYY12_0_5X36
:
1031 color_format
= 0x0D;
1033 case MEDIA_BUS_FMT_YUV16_1X48
:
1034 case MEDIA_BUS_FMT_UYYVYY16_0_5X48
:
1035 color_format
= 0x0F;
1038 case MEDIA_BUS_FMT_UYVY8_1X16
:
1039 color_format
= 0x16;
1041 case MEDIA_BUS_FMT_UYVY10_1X20
:
1042 color_format
= 0x14;
1044 case MEDIA_BUS_FMT_UYVY12_1X24
:
1045 color_format
= 0x12;
1052 val
= HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE
|
1053 ((color_format
<< HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET
) &
1054 HDMI_TX_INVID0_VIDEO_MAPPING_MASK
);
1055 hdmi_writeb(hdmi
, val
, HDMI_TX_INVID0
);
1057 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
1058 val
= HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE
|
1059 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE
|
1060 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE
;
1061 hdmi_writeb(hdmi
, val
, HDMI_TX_INSTUFFING
);
1062 hdmi_writeb(hdmi
, 0x0, HDMI_TX_GYDATA0
);
1063 hdmi_writeb(hdmi
, 0x0, HDMI_TX_GYDATA1
);
1064 hdmi_writeb(hdmi
, 0x0, HDMI_TX_RCRDATA0
);
1065 hdmi_writeb(hdmi
, 0x0, HDMI_TX_RCRDATA1
);
1066 hdmi_writeb(hdmi
, 0x0, HDMI_TX_BCBDATA0
);
1067 hdmi_writeb(hdmi
, 0x0, HDMI_TX_BCBDATA1
);
1070 static int is_color_space_conversion(struct dw_hdmi
*hdmi
)
1072 struct hdmi_data_info
*hdmi_data
= &hdmi
->hdmi_data
;
1073 bool is_input_rgb
, is_output_rgb
;
1075 is_input_rgb
= hdmi_bus_fmt_is_rgb(hdmi_data
->enc_in_bus_format
);
1076 is_output_rgb
= hdmi_bus_fmt_is_rgb(hdmi_data
->enc_out_bus_format
);
1078 return (is_input_rgb
!= is_output_rgb
) ||
1079 (is_input_rgb
&& is_output_rgb
&& hdmi_data
->rgb_limited_range
);
1082 static int is_color_space_decimation(struct dw_hdmi
*hdmi
)
1084 if (!hdmi_bus_fmt_is_yuv422(hdmi
->hdmi_data
.enc_out_bus_format
))
1087 if (hdmi_bus_fmt_is_rgb(hdmi
->hdmi_data
.enc_in_bus_format
) ||
1088 hdmi_bus_fmt_is_yuv444(hdmi
->hdmi_data
.enc_in_bus_format
))
1094 static int is_color_space_interpolation(struct dw_hdmi
*hdmi
)
1096 if (!hdmi_bus_fmt_is_yuv422(hdmi
->hdmi_data
.enc_in_bus_format
))
1099 if (hdmi_bus_fmt_is_rgb(hdmi
->hdmi_data
.enc_out_bus_format
) ||
1100 hdmi_bus_fmt_is_yuv444(hdmi
->hdmi_data
.enc_out_bus_format
))
1106 static bool is_csc_needed(struct dw_hdmi
*hdmi
)
1108 return is_color_space_conversion(hdmi
) ||
1109 is_color_space_decimation(hdmi
) ||
1110 is_color_space_interpolation(hdmi
);
1113 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi
*hdmi
)
1115 const u16 (*csc_coeff
)[3][4] = &csc_coeff_default
;
1116 bool is_input_rgb
, is_output_rgb
;
1120 is_input_rgb
= hdmi_bus_fmt_is_rgb(hdmi
->hdmi_data
.enc_in_bus_format
);
1121 is_output_rgb
= hdmi_bus_fmt_is_rgb(hdmi
->hdmi_data
.enc_out_bus_format
);
1123 if (!is_input_rgb
&& is_output_rgb
) {
1124 if (hdmi
->hdmi_data
.enc_out_encoding
== V4L2_YCBCR_ENC_601
)
1125 csc_coeff
= &csc_coeff_rgb_out_eitu601
;
1127 csc_coeff
= &csc_coeff_rgb_out_eitu709
;
1128 } else if (is_input_rgb
&& !is_output_rgb
) {
1129 if (hdmi
->hdmi_data
.enc_out_encoding
== V4L2_YCBCR_ENC_601
)
1130 csc_coeff
= &csc_coeff_rgb_in_eitu601
;
1132 csc_coeff
= &csc_coeff_rgb_in_eitu709
;
1134 } else if (is_input_rgb
&& is_output_rgb
&&
1135 hdmi
->hdmi_data
.rgb_limited_range
) {
1136 csc_coeff
= &csc_coeff_rgb_full_to_rgb_limited
;
1139 /* The CSC registers are sequential, alternating MSB then LSB */
1140 for (i
= 0; i
< ARRAY_SIZE(csc_coeff_default
[0]); i
++) {
1141 u16 coeff_a
= (*csc_coeff
)[0][i
];
1142 u16 coeff_b
= (*csc_coeff
)[1][i
];
1143 u16 coeff_c
= (*csc_coeff
)[2][i
];
1145 hdmi_writeb(hdmi
, coeff_a
& 0xff, HDMI_CSC_COEF_A1_LSB
+ i
* 2);
1146 hdmi_writeb(hdmi
, coeff_a
>> 8, HDMI_CSC_COEF_A1_MSB
+ i
* 2);
1147 hdmi_writeb(hdmi
, coeff_b
& 0xff, HDMI_CSC_COEF_B1_LSB
+ i
* 2);
1148 hdmi_writeb(hdmi
, coeff_b
>> 8, HDMI_CSC_COEF_B1_MSB
+ i
* 2);
1149 hdmi_writeb(hdmi
, coeff_c
& 0xff, HDMI_CSC_COEF_C1_LSB
+ i
* 2);
1150 hdmi_writeb(hdmi
, coeff_c
>> 8, HDMI_CSC_COEF_C1_MSB
+ i
* 2);
1153 hdmi_modb(hdmi
, csc_scale
, HDMI_CSC_SCALE_CSCSCALE_MASK
,
1157 static void hdmi_video_csc(struct dw_hdmi
*hdmi
)
1159 int color_depth
= 0;
1160 int interpolation
= HDMI_CSC_CFG_INTMODE_DISABLE
;
1163 /* YCC422 interpolation to 444 mode */
1164 if (is_color_space_interpolation(hdmi
))
1165 interpolation
= HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1
;
1166 else if (is_color_space_decimation(hdmi
))
1167 decimation
= HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3
;
1169 switch (hdmi_bus_fmt_color_depth(hdmi
->hdmi_data
.enc_out_bus_format
)) {
1171 color_depth
= HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP
;
1174 color_depth
= HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP
;
1177 color_depth
= HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP
;
1180 color_depth
= HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP
;
1187 /* Configure the CSC registers */
1188 hdmi_writeb(hdmi
, interpolation
| decimation
, HDMI_CSC_CFG
);
1189 hdmi_modb(hdmi
, color_depth
, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK
,
1192 dw_hdmi_update_csc_coeffs(hdmi
);
1196 * HDMI video packetizer is used to packetize the data.
1197 * for example, if input is YCC422 mode or repeater is used,
1198 * data should be repacked this module can be bypassed.
1200 static void hdmi_video_packetize(struct dw_hdmi
*hdmi
)
1202 unsigned int color_depth
= 0;
1203 unsigned int remap_size
= HDMI_VP_REMAP_YCC422_16bit
;
1204 unsigned int output_select
= HDMI_VP_CONF_OUTPUT_SELECTOR_PP
;
1205 struct hdmi_data_info
*hdmi_data
= &hdmi
->hdmi_data
;
1207 u8 clear_gcp_auto
= 0;
1210 if (hdmi_bus_fmt_is_rgb(hdmi
->hdmi_data
.enc_out_bus_format
) ||
1211 hdmi_bus_fmt_is_yuv444(hdmi
->hdmi_data
.enc_out_bus_format
) ||
1212 hdmi_bus_fmt_is_yuv420(hdmi
->hdmi_data
.enc_out_bus_format
)) {
1213 switch (hdmi_bus_fmt_color_depth(
1214 hdmi
->hdmi_data
.enc_out_bus_format
)) {
1217 output_select
= HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS
;
1230 output_select
= HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS
;
1232 } else if (hdmi_bus_fmt_is_yuv422(hdmi
->hdmi_data
.enc_out_bus_format
)) {
1233 switch (hdmi_bus_fmt_color_depth(
1234 hdmi
->hdmi_data
.enc_out_bus_format
)) {
1237 remap_size
= HDMI_VP_REMAP_YCC422_16bit
;
1241 remap_size
= HDMI_VP_REMAP_YCC422_20bit
;
1244 remap_size
= HDMI_VP_REMAP_YCC422_24bit
;
1250 output_select
= HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422
;
1255 /* set the packetizer registers */
1256 val
= ((color_depth
<< HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET
) &
1257 HDMI_VP_PR_CD_COLOR_DEPTH_MASK
) |
1258 ((hdmi_data
->pix_repet_factor
<<
1259 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET
) &
1260 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK
);
1261 hdmi_writeb(hdmi
, val
, HDMI_VP_PR_CD
);
1263 /* HDMI1.4b specification section 6.5.3:
1264 * Source shall only send GCPs with non-zero CD to sinks
1265 * that indicate support for Deep Color.
1266 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet).
1267 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
1269 val
= hdmi_readb(hdmi
, HDMI_FC_DATAUTO3
);
1270 if (clear_gcp_auto
== 1)
1271 val
&= ~HDMI_FC_DATAUTO3_GCP_AUTO
;
1273 val
|= HDMI_FC_DATAUTO3_GCP_AUTO
;
1274 hdmi_writeb(hdmi
, val
, HDMI_FC_DATAUTO3
);
1276 hdmi_modb(hdmi
, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE
,
1277 HDMI_VP_STUFF_PR_STUFFING_MASK
, HDMI_VP_STUFF
);
1279 /* Data from pixel repeater block */
1280 if (hdmi_data
->pix_repet_factor
> 1) {
1281 vp_conf
= HDMI_VP_CONF_PR_EN_ENABLE
|
1282 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER
;
1283 } else { /* data from packetizer block */
1284 vp_conf
= HDMI_VP_CONF_PR_EN_DISABLE
|
1285 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER
;
1288 hdmi_modb(hdmi
, vp_conf
,
1289 HDMI_VP_CONF_PR_EN_MASK
|
1290 HDMI_VP_CONF_BYPASS_SELECT_MASK
, HDMI_VP_CONF
);
1292 hdmi_modb(hdmi
, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET
,
1293 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK
, HDMI_VP_STUFF
);
1295 hdmi_writeb(hdmi
, remap_size
, HDMI_VP_REMAP
);
1297 if (output_select
== HDMI_VP_CONF_OUTPUT_SELECTOR_PP
) {
1298 vp_conf
= HDMI_VP_CONF_BYPASS_EN_DISABLE
|
1299 HDMI_VP_CONF_PP_EN_ENABLE
|
1300 HDMI_VP_CONF_YCC422_EN_DISABLE
;
1301 } else if (output_select
== HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422
) {
1302 vp_conf
= HDMI_VP_CONF_BYPASS_EN_DISABLE
|
1303 HDMI_VP_CONF_PP_EN_DISABLE
|
1304 HDMI_VP_CONF_YCC422_EN_ENABLE
;
1305 } else if (output_select
== HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS
) {
1306 vp_conf
= HDMI_VP_CONF_BYPASS_EN_ENABLE
|
1307 HDMI_VP_CONF_PP_EN_DISABLE
|
1308 HDMI_VP_CONF_YCC422_EN_DISABLE
;
1313 hdmi_modb(hdmi
, vp_conf
,
1314 HDMI_VP_CONF_BYPASS_EN_MASK
| HDMI_VP_CONF_PP_EN_ENMASK
|
1315 HDMI_VP_CONF_YCC422_EN_MASK
, HDMI_VP_CONF
);
1317 hdmi_modb(hdmi
, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE
|
1318 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE
,
1319 HDMI_VP_STUFF_PP_STUFFING_MASK
|
1320 HDMI_VP_STUFF_YCC422_STUFFING_MASK
, HDMI_VP_STUFF
);
1322 hdmi_modb(hdmi
, output_select
, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK
,
1326 /* -----------------------------------------------------------------------------
1327 * Synopsys PHY Handling
1330 static inline void hdmi_phy_test_clear(struct dw_hdmi
*hdmi
,
1333 hdmi_modb(hdmi
, bit
<< HDMI_PHY_TST0_TSTCLR_OFFSET
,
1334 HDMI_PHY_TST0_TSTCLR_MASK
, HDMI_PHY_TST0
);
1337 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi
*hdmi
, int msec
)
1341 while ((val
= hdmi_readb(hdmi
, HDMI_IH_I2CMPHY_STAT0
) & 0x3) == 0) {
1346 hdmi_writeb(hdmi
, val
, HDMI_IH_I2CMPHY_STAT0
);
1351 void dw_hdmi_phy_i2c_write(struct dw_hdmi
*hdmi
, unsigned short data
,
1354 hdmi_writeb(hdmi
, 0xFF, HDMI_IH_I2CMPHY_STAT0
);
1355 hdmi_writeb(hdmi
, addr
, HDMI_PHY_I2CM_ADDRESS_ADDR
);
1356 hdmi_writeb(hdmi
, (unsigned char)(data
>> 8),
1357 HDMI_PHY_I2CM_DATAO_1_ADDR
);
1358 hdmi_writeb(hdmi
, (unsigned char)(data
>> 0),
1359 HDMI_PHY_I2CM_DATAO_0_ADDR
);
1360 hdmi_writeb(hdmi
, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE
,
1361 HDMI_PHY_I2CM_OPERATION_ADDR
);
1362 hdmi_phy_wait_i2c_done(hdmi
, 1000);
1364 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write
);
1366 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
1367 static bool dw_hdmi_support_scdc(struct dw_hdmi
*hdmi
,
1368 const struct drm_display_info
*display
)
1370 /* Completely disable SCDC support for older controllers */
1371 if (hdmi
->version
< 0x200a)
1374 /* Disable if no DDC bus */
1378 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1379 if (!display
->hdmi
.scdc
.supported
||
1380 !display
->hdmi
.scdc
.scrambling
.supported
)
1384 * Disable if display only support low TMDS rates and scrambling
1385 * for low rates is not supported either
1387 if (!display
->hdmi
.scdc
.scrambling
.low_rates
&&
1388 display
->max_tmds_clock
<= 340000)
1395 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1396 * - The Source shall suspend transmission of the TMDS clock and data
1397 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1398 * from a 0 to a 1 or from a 1 to a 0
1399 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1400 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1401 * transmission of TMDS clock and data
1403 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1404 * helper should called right before enabling the TMDS Clock and Data in
1405 * the PHY configuration callback.
1407 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi
*hdmi
,
1408 const struct drm_display_info
*display
)
1410 unsigned long mtmdsclock
= hdmi
->hdmi_data
.video_mode
.mtmdsclock
;
1412 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1413 if (dw_hdmi_support_scdc(hdmi
, display
)) {
1414 if (mtmdsclock
> HDMI14_MAX_TMDSCLK
)
1415 drm_scdc_set_high_tmds_clock_ratio(hdmi
->curr_conn
, 1);
1417 drm_scdc_set_high_tmds_clock_ratio(hdmi
->curr_conn
, 0);
1420 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio
);
1422 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi
*hdmi
, bool enable
)
1424 hdmi_mask_writeb(hdmi
, !enable
, HDMI_PHY_CONF0
,
1425 HDMI_PHY_CONF0_PDZ_OFFSET
,
1426 HDMI_PHY_CONF0_PDZ_MASK
);
1429 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi
*hdmi
, u8 enable
)
1431 hdmi_mask_writeb(hdmi
, enable
, HDMI_PHY_CONF0
,
1432 HDMI_PHY_CONF0_ENTMDS_OFFSET
,
1433 HDMI_PHY_CONF0_ENTMDS_MASK
);
1436 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi
*hdmi
, u8 enable
)
1438 hdmi_mask_writeb(hdmi
, enable
, HDMI_PHY_CONF0
,
1439 HDMI_PHY_CONF0_SVSRET_OFFSET
,
1440 HDMI_PHY_CONF0_SVSRET_MASK
);
1443 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi
*hdmi
, u8 enable
)
1445 hdmi_mask_writeb(hdmi
, enable
, HDMI_PHY_CONF0
,
1446 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET
,
1447 HDMI_PHY_CONF0_GEN2_PDDQ_MASK
);
1449 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq
);
1451 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi
*hdmi
, u8 enable
)
1453 hdmi_mask_writeb(hdmi
, enable
, HDMI_PHY_CONF0
,
1454 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET
,
1455 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK
);
1457 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron
);
1459 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi
*hdmi
, u8 enable
)
1461 hdmi_mask_writeb(hdmi
, enable
, HDMI_PHY_CONF0
,
1462 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET
,
1463 HDMI_PHY_CONF0_SELDATAENPOL_MASK
);
1466 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi
*hdmi
, u8 enable
)
1468 hdmi_mask_writeb(hdmi
, enable
, HDMI_PHY_CONF0
,
1469 HDMI_PHY_CONF0_SELDIPIF_OFFSET
,
1470 HDMI_PHY_CONF0_SELDIPIF_MASK
);
1473 void dw_hdmi_phy_gen1_reset(struct dw_hdmi
*hdmi
)
1475 /* PHY reset. The reset signal is active low on Gen1 PHYs. */
1476 hdmi_writeb(hdmi
, 0, HDMI_MC_PHYRSTZ
);
1477 hdmi_writeb(hdmi
, HDMI_MC_PHYRSTZ_PHYRSTZ
, HDMI_MC_PHYRSTZ
);
1479 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset
);
1481 void dw_hdmi_phy_gen2_reset(struct dw_hdmi
*hdmi
)
1483 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1484 hdmi_writeb(hdmi
, HDMI_MC_PHYRSTZ_PHYRSTZ
, HDMI_MC_PHYRSTZ
);
1485 hdmi_writeb(hdmi
, 0, HDMI_MC_PHYRSTZ
);
1487 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset
);
1489 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi
*hdmi
, u8 address
)
1491 hdmi_phy_test_clear(hdmi
, 1);
1492 hdmi_writeb(hdmi
, address
, HDMI_PHY_I2CM_SLAVE_ADDR
);
1493 hdmi_phy_test_clear(hdmi
, 0);
1495 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr
);
1497 static void dw_hdmi_phy_power_off(struct dw_hdmi
*hdmi
)
1499 const struct dw_hdmi_phy_data
*phy
= hdmi
->phy
.data
;
1503 if (phy
->gen
== 1) {
1504 dw_hdmi_phy_enable_tmds(hdmi
, 0);
1505 dw_hdmi_phy_enable_powerdown(hdmi
, true);
1509 dw_hdmi_phy_gen2_txpwron(hdmi
, 0);
1512 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1513 * to low power mode.
1515 for (i
= 0; i
< 5; ++i
) {
1516 val
= hdmi_readb(hdmi
, HDMI_PHY_STAT0
);
1517 if (!(val
& HDMI_PHY_TX_PHY_LOCK
))
1520 usleep_range(1000, 2000);
1523 if (val
& HDMI_PHY_TX_PHY_LOCK
)
1524 dev_warn(hdmi
->dev
, "PHY failed to power down\n");
1526 dev_dbg(hdmi
->dev
, "PHY powered down in %u iterations\n", i
);
1528 dw_hdmi_phy_gen2_pddq(hdmi
, 1);
1531 static int dw_hdmi_phy_power_on(struct dw_hdmi
*hdmi
)
1533 const struct dw_hdmi_phy_data
*phy
= hdmi
->phy
.data
;
1537 if (phy
->gen
== 1) {
1538 dw_hdmi_phy_enable_powerdown(hdmi
, false);
1540 /* Toggle TMDS enable. */
1541 dw_hdmi_phy_enable_tmds(hdmi
, 0);
1542 dw_hdmi_phy_enable_tmds(hdmi
, 1);
1546 dw_hdmi_phy_gen2_txpwron(hdmi
, 1);
1547 dw_hdmi_phy_gen2_pddq(hdmi
, 0);
1549 /* Wait for PHY PLL lock */
1550 for (i
= 0; i
< 5; ++i
) {
1551 val
= hdmi_readb(hdmi
, HDMI_PHY_STAT0
) & HDMI_PHY_TX_PHY_LOCK
;
1555 usleep_range(1000, 2000);
1559 dev_err(hdmi
->dev
, "PHY PLL failed to lock\n");
1563 dev_dbg(hdmi
->dev
, "PHY PLL locked %u iterations\n", i
);
1568 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1569 * information the DWC MHL PHY has the same register layout and is thus also
1570 * supported by this function.
1572 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi
*hdmi
,
1573 const struct dw_hdmi_plat_data
*pdata
,
1574 unsigned long mpixelclock
)
1576 const struct dw_hdmi_mpll_config
*mpll_config
= pdata
->mpll_cfg
;
1577 const struct dw_hdmi_curr_ctrl
*curr_ctrl
= pdata
->cur_ctr
;
1578 const struct dw_hdmi_phy_config
*phy_config
= pdata
->phy_config
;
1580 /* TOFIX Will need 420 specific PHY configuration tables */
1582 /* PLL/MPLL Cfg - always match on final entry */
1583 for (; mpll_config
->mpixelclock
!= ~0UL; mpll_config
++)
1584 if (mpixelclock
<= mpll_config
->mpixelclock
)
1587 for (; curr_ctrl
->mpixelclock
!= ~0UL; curr_ctrl
++)
1588 if (mpixelclock
<= curr_ctrl
->mpixelclock
)
1591 for (; phy_config
->mpixelclock
!= ~0UL; phy_config
++)
1592 if (mpixelclock
<= phy_config
->mpixelclock
)
1595 if (mpll_config
->mpixelclock
== ~0UL ||
1596 curr_ctrl
->mpixelclock
== ~0UL ||
1597 phy_config
->mpixelclock
== ~0UL)
1600 dw_hdmi_phy_i2c_write(hdmi
, mpll_config
->res
[0].cpce
,
1601 HDMI_3D_TX_PHY_CPCE_CTRL
);
1602 dw_hdmi_phy_i2c_write(hdmi
, mpll_config
->res
[0].gmp
,
1603 HDMI_3D_TX_PHY_GMPCTRL
);
1604 dw_hdmi_phy_i2c_write(hdmi
, curr_ctrl
->curr
[0],
1605 HDMI_3D_TX_PHY_CURRCTRL
);
1607 dw_hdmi_phy_i2c_write(hdmi
, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL
);
1608 dw_hdmi_phy_i2c_write(hdmi
, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK
,
1609 HDMI_3D_TX_PHY_MSM_CTRL
);
1611 dw_hdmi_phy_i2c_write(hdmi
, phy_config
->term
, HDMI_3D_TX_PHY_TXTERM
);
1612 dw_hdmi_phy_i2c_write(hdmi
, phy_config
->sym_ctr
,
1613 HDMI_3D_TX_PHY_CKSYMTXCTRL
);
1614 dw_hdmi_phy_i2c_write(hdmi
, phy_config
->vlev_ctr
,
1615 HDMI_3D_TX_PHY_VLEVCTRL
);
1617 /* Override and disable clock termination. */
1618 dw_hdmi_phy_i2c_write(hdmi
, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE
,
1619 HDMI_3D_TX_PHY_CKCALCTRL
);
1624 static int hdmi_phy_configure(struct dw_hdmi
*hdmi
,
1625 const struct drm_display_info
*display
)
1627 const struct dw_hdmi_phy_data
*phy
= hdmi
->phy
.data
;
1628 const struct dw_hdmi_plat_data
*pdata
= hdmi
->plat_data
;
1629 unsigned long mpixelclock
= hdmi
->hdmi_data
.video_mode
.mpixelclock
;
1630 unsigned long mtmdsclock
= hdmi
->hdmi_data
.video_mode
.mtmdsclock
;
1633 dw_hdmi_phy_power_off(hdmi
);
1635 dw_hdmi_set_high_tmds_clock_ratio(hdmi
, display
);
1637 /* Leave low power consumption mode by asserting SVSRET. */
1638 if (phy
->has_svsret
)
1639 dw_hdmi_phy_enable_svsret(hdmi
, 1);
1641 dw_hdmi_phy_gen2_reset(hdmi
);
1643 hdmi_writeb(hdmi
, HDMI_MC_HEACPHY_RST_ASSERT
, HDMI_MC_HEACPHY_RST
);
1645 dw_hdmi_phy_i2c_set_addr(hdmi
, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2
);
1647 /* Write to the PHY as configured by the platform */
1648 if (pdata
->configure_phy
)
1649 ret
= pdata
->configure_phy(hdmi
, pdata
->priv_data
, mpixelclock
);
1651 ret
= phy
->configure(hdmi
, pdata
, mpixelclock
);
1653 dev_err(hdmi
->dev
, "PHY configuration failed (clock %lu)\n",
1658 /* Wait for resuming transmission of TMDS clock and data */
1659 if (mtmdsclock
> HDMI14_MAX_TMDSCLK
)
1662 return dw_hdmi_phy_power_on(hdmi
);
1665 static int dw_hdmi_phy_init(struct dw_hdmi
*hdmi
, void *data
,
1666 const struct drm_display_info
*display
,
1667 const struct drm_display_mode
*mode
)
1671 /* HDMI Phy spec says to do the phy initialization sequence twice */
1672 for (i
= 0; i
< 2; i
++) {
1673 dw_hdmi_phy_sel_data_en_pol(hdmi
, 1);
1674 dw_hdmi_phy_sel_interface_control(hdmi
, 0);
1676 ret
= hdmi_phy_configure(hdmi
, display
);
1684 static void dw_hdmi_phy_disable(struct dw_hdmi
*hdmi
, void *data
)
1686 dw_hdmi_phy_power_off(hdmi
);
1689 enum drm_connector_status
dw_hdmi_phy_read_hpd(struct dw_hdmi
*hdmi
,
1692 return hdmi_readb(hdmi
, HDMI_PHY_STAT0
) & HDMI_PHY_HPD
?
1693 connector_status_connected
: connector_status_disconnected
;
1695 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd
);
1697 void dw_hdmi_phy_update_hpd(struct dw_hdmi
*hdmi
, void *data
,
1698 bool force
, bool disabled
, bool rxsense
)
1700 u8 old_mask
= hdmi
->phy_mask
;
1702 if (force
|| disabled
|| !rxsense
)
1703 hdmi
->phy_mask
|= HDMI_PHY_RX_SENSE
;
1705 hdmi
->phy_mask
&= ~HDMI_PHY_RX_SENSE
;
1707 if (old_mask
!= hdmi
->phy_mask
)
1708 hdmi_writeb(hdmi
, hdmi
->phy_mask
, HDMI_PHY_MASK0
);
1710 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd
);
1712 void dw_hdmi_phy_setup_hpd(struct dw_hdmi
*hdmi
, void *data
)
1715 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1716 * any pending interrupt.
1718 hdmi_writeb(hdmi
, HDMI_PHY_HPD
| HDMI_PHY_RX_SENSE
, HDMI_PHY_POL0
);
1719 hdmi_writeb(hdmi
, HDMI_IH_PHY_STAT0_HPD
| HDMI_IH_PHY_STAT0_RX_SENSE
,
1722 /* Enable cable hot plug irq. */
1723 hdmi_writeb(hdmi
, hdmi
->phy_mask
, HDMI_PHY_MASK0
);
1725 /* Clear and unmute interrupts. */
1726 hdmi_writeb(hdmi
, HDMI_IH_PHY_STAT0_HPD
| HDMI_IH_PHY_STAT0_RX_SENSE
,
1728 hdmi_writeb(hdmi
, ~(HDMI_IH_PHY_STAT0_HPD
| HDMI_IH_PHY_STAT0_RX_SENSE
),
1729 HDMI_IH_MUTE_PHY_STAT0
);
1731 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd
);
1733 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops
= {
1734 .init
= dw_hdmi_phy_init
,
1735 .disable
= dw_hdmi_phy_disable
,
1736 .read_hpd
= dw_hdmi_phy_read_hpd
,
1737 .update_hpd
= dw_hdmi_phy_update_hpd
,
1738 .setup_hpd
= dw_hdmi_phy_setup_hpd
,
1741 /* -----------------------------------------------------------------------------
1745 static void hdmi_tx_hdcp_config(struct dw_hdmi
*hdmi
)
1749 if (hdmi
->hdmi_data
.video_mode
.mdataenablepolarity
)
1750 de
= HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH
;
1752 de
= HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW
;
1754 /* disable rx detect */
1755 hdmi_modb(hdmi
, HDMI_A_HDCPCFG0_RXDETECT_DISABLE
,
1756 HDMI_A_HDCPCFG0_RXDETECT_MASK
, HDMI_A_HDCPCFG0
);
1758 hdmi_modb(hdmi
, de
, HDMI_A_VIDPOLCFG_DATAENPOL_MASK
, HDMI_A_VIDPOLCFG
);
1760 hdmi_modb(hdmi
, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE
,
1761 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK
, HDMI_A_HDCPCFG1
);
1764 static void hdmi_config_AVI(struct dw_hdmi
*hdmi
,
1765 const struct drm_connector
*connector
,
1766 const struct drm_display_mode
*mode
)
1768 struct hdmi_avi_infoframe frame
;
1771 /* Initialise info frame from DRM mode */
1772 drm_hdmi_avi_infoframe_from_display_mode(&frame
, connector
, mode
);
1774 if (hdmi_bus_fmt_is_rgb(hdmi
->hdmi_data
.enc_out_bus_format
)) {
1775 drm_hdmi_avi_infoframe_quant_range(&frame
, connector
, mode
,
1776 hdmi
->hdmi_data
.rgb_limited_range
?
1777 HDMI_QUANTIZATION_RANGE_LIMITED
:
1778 HDMI_QUANTIZATION_RANGE_FULL
);
1780 frame
.quantization_range
= HDMI_QUANTIZATION_RANGE_DEFAULT
;
1781 frame
.ycc_quantization_range
=
1782 HDMI_YCC_QUANTIZATION_RANGE_LIMITED
;
1785 if (hdmi_bus_fmt_is_yuv444(hdmi
->hdmi_data
.enc_out_bus_format
))
1786 frame
.colorspace
= HDMI_COLORSPACE_YUV444
;
1787 else if (hdmi_bus_fmt_is_yuv422(hdmi
->hdmi_data
.enc_out_bus_format
))
1788 frame
.colorspace
= HDMI_COLORSPACE_YUV422
;
1789 else if (hdmi_bus_fmt_is_yuv420(hdmi
->hdmi_data
.enc_out_bus_format
))
1790 frame
.colorspace
= HDMI_COLORSPACE_YUV420
;
1792 frame
.colorspace
= HDMI_COLORSPACE_RGB
;
1794 /* Set up colorimetry */
1795 if (!hdmi_bus_fmt_is_rgb(hdmi
->hdmi_data
.enc_out_bus_format
)) {
1796 switch (hdmi
->hdmi_data
.enc_out_encoding
) {
1797 case V4L2_YCBCR_ENC_601
:
1798 if (hdmi
->hdmi_data
.enc_in_encoding
== V4L2_YCBCR_ENC_XV601
)
1799 frame
.colorimetry
= HDMI_COLORIMETRY_EXTENDED
;
1801 frame
.colorimetry
= HDMI_COLORIMETRY_ITU_601
;
1802 frame
.extended_colorimetry
=
1803 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601
;
1805 case V4L2_YCBCR_ENC_709
:
1806 if (hdmi
->hdmi_data
.enc_in_encoding
== V4L2_YCBCR_ENC_XV709
)
1807 frame
.colorimetry
= HDMI_COLORIMETRY_EXTENDED
;
1809 frame
.colorimetry
= HDMI_COLORIMETRY_ITU_709
;
1810 frame
.extended_colorimetry
=
1811 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709
;
1813 default: /* Carries no data */
1814 frame
.colorimetry
= HDMI_COLORIMETRY_ITU_601
;
1815 frame
.extended_colorimetry
=
1816 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601
;
1820 frame
.colorimetry
= HDMI_COLORIMETRY_NONE
;
1821 frame
.extended_colorimetry
=
1822 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601
;
1826 * The Designware IP uses a different byte format from standard
1827 * AVI info frames, though generally the bits are in the correct
1832 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1833 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1834 * bit 6 rather than 4.
1836 val
= (frame
.scan_mode
& 3) << 4 | (frame
.colorspace
& 3);
1837 if (frame
.active_aspect
& 15)
1838 val
|= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT
;
1839 if (frame
.top_bar
|| frame
.bottom_bar
)
1840 val
|= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR
;
1841 if (frame
.left_bar
|| frame
.right_bar
)
1842 val
|= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR
;
1843 hdmi_writeb(hdmi
, val
, HDMI_FC_AVICONF0
);
1845 /* AVI data byte 2 differences: none */
1846 val
= ((frame
.colorimetry
& 0x3) << 6) |
1847 ((frame
.picture_aspect
& 0x3) << 4) |
1848 (frame
.active_aspect
& 0xf);
1849 hdmi_writeb(hdmi
, val
, HDMI_FC_AVICONF1
);
1851 /* AVI data byte 3 differences: none */
1852 val
= ((frame
.extended_colorimetry
& 0x7) << 4) |
1853 ((frame
.quantization_range
& 0x3) << 2) |
1856 val
|= HDMI_FC_AVICONF2_IT_CONTENT_VALID
;
1857 hdmi_writeb(hdmi
, val
, HDMI_FC_AVICONF2
);
1859 /* AVI data byte 4 differences: none */
1860 val
= frame
.video_code
& 0x7f;
1861 hdmi_writeb(hdmi
, val
, HDMI_FC_AVIVID
);
1863 /* AVI Data Byte 5- set up input and output pixel repetition */
1864 val
= (((hdmi
->hdmi_data
.video_mode
.mpixelrepetitioninput
+ 1) <<
1865 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET
) &
1866 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK
) |
1867 ((hdmi
->hdmi_data
.video_mode
.mpixelrepetitionoutput
<<
1868 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET
) &
1869 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK
);
1870 hdmi_writeb(hdmi
, val
, HDMI_FC_PRCONF
);
1873 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1874 * ycc range in bits 2,3 rather than 6,7
1876 val
= ((frame
.ycc_quantization_range
& 0x3) << 2) |
1877 (frame
.content_type
& 0x3);
1878 hdmi_writeb(hdmi
, val
, HDMI_FC_AVICONF3
);
1880 /* AVI Data Bytes 6-13 */
1881 hdmi_writeb(hdmi
, frame
.top_bar
& 0xff, HDMI_FC_AVIETB0
);
1882 hdmi_writeb(hdmi
, (frame
.top_bar
>> 8) & 0xff, HDMI_FC_AVIETB1
);
1883 hdmi_writeb(hdmi
, frame
.bottom_bar
& 0xff, HDMI_FC_AVISBB0
);
1884 hdmi_writeb(hdmi
, (frame
.bottom_bar
>> 8) & 0xff, HDMI_FC_AVISBB1
);
1885 hdmi_writeb(hdmi
, frame
.left_bar
& 0xff, HDMI_FC_AVIELB0
);
1886 hdmi_writeb(hdmi
, (frame
.left_bar
>> 8) & 0xff, HDMI_FC_AVIELB1
);
1887 hdmi_writeb(hdmi
, frame
.right_bar
& 0xff, HDMI_FC_AVISRB0
);
1888 hdmi_writeb(hdmi
, (frame
.right_bar
>> 8) & 0xff, HDMI_FC_AVISRB1
);
1891 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi
*hdmi
,
1892 const struct drm_connector
*connector
,
1893 const struct drm_display_mode
*mode
)
1895 struct hdmi_vendor_infoframe frame
;
1899 err
= drm_hdmi_vendor_infoframe_from_display_mode(&frame
, connector
,
1903 * Going into that statement does not means vendor infoframe
1904 * fails. It just informed us that vendor infoframe is not
1905 * needed for the selected mode. Only 4k or stereoscopic 3D
1906 * mode requires vendor infoframe. So just simply return.
1910 err
= hdmi_vendor_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1912 dev_err(hdmi
->dev
, "Failed to pack vendor infoframe: %zd\n",
1916 hdmi_mask_writeb(hdmi
, 0, HDMI_FC_DATAUTO0
, HDMI_FC_DATAUTO0_VSD_OFFSET
,
1917 HDMI_FC_DATAUTO0_VSD_MASK
);
1919 /* Set the length of HDMI vendor specific InfoFrame payload */
1920 hdmi_writeb(hdmi
, buffer
[2], HDMI_FC_VSDSIZE
);
1922 /* Set 24bit IEEE Registration Identifier */
1923 hdmi_writeb(hdmi
, buffer
[4], HDMI_FC_VSDIEEEID0
);
1924 hdmi_writeb(hdmi
, buffer
[5], HDMI_FC_VSDIEEEID1
);
1925 hdmi_writeb(hdmi
, buffer
[6], HDMI_FC_VSDIEEEID2
);
1927 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1928 hdmi_writeb(hdmi
, buffer
[7], HDMI_FC_VSDPAYLOAD0
);
1929 hdmi_writeb(hdmi
, buffer
[8], HDMI_FC_VSDPAYLOAD1
);
1931 if (frame
.s3d_struct
>= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF
)
1932 hdmi_writeb(hdmi
, buffer
[9], HDMI_FC_VSDPAYLOAD2
);
1934 /* Packet frame interpolation */
1935 hdmi_writeb(hdmi
, 1, HDMI_FC_DATAUTO1
);
1937 /* Auto packets per frame and line spacing */
1938 hdmi_writeb(hdmi
, 0x11, HDMI_FC_DATAUTO2
);
1940 /* Configures the Frame Composer On RDRB mode */
1941 hdmi_mask_writeb(hdmi
, 1, HDMI_FC_DATAUTO0
, HDMI_FC_DATAUTO0_VSD_OFFSET
,
1942 HDMI_FC_DATAUTO0_VSD_MASK
);
1945 static void hdmi_config_drm_infoframe(struct dw_hdmi
*hdmi
,
1946 const struct drm_connector
*connector
)
1948 const struct drm_connector_state
*conn_state
= connector
->state
;
1949 struct hdmi_drm_infoframe frame
;
1954 if (!hdmi
->plat_data
->use_drm_infoframe
)
1957 hdmi_modb(hdmi
, HDMI_FC_PACKET_TX_EN_DRM_DISABLE
,
1958 HDMI_FC_PACKET_TX_EN_DRM_MASK
, HDMI_FC_PACKET_TX_EN
);
1960 err
= drm_hdmi_infoframe_set_hdr_metadata(&frame
, conn_state
);
1964 err
= hdmi_drm_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1966 dev_err(hdmi
->dev
, "Failed to pack drm infoframe: %zd\n", err
);
1970 hdmi_writeb(hdmi
, frame
.version
, HDMI_FC_DRM_HB0
);
1971 hdmi_writeb(hdmi
, frame
.length
, HDMI_FC_DRM_HB1
);
1973 for (i
= 0; i
< frame
.length
; i
++)
1974 hdmi_writeb(hdmi
, buffer
[4 + i
], HDMI_FC_DRM_PB0
+ i
);
1976 hdmi_writeb(hdmi
, 1, HDMI_FC_DRM_UP
);
1977 hdmi_modb(hdmi
, HDMI_FC_PACKET_TX_EN_DRM_ENABLE
,
1978 HDMI_FC_PACKET_TX_EN_DRM_MASK
, HDMI_FC_PACKET_TX_EN
);
1981 static void hdmi_av_composer(struct dw_hdmi
*hdmi
,
1982 const struct drm_display_info
*display
,
1983 const struct drm_display_mode
*mode
)
1986 const struct drm_hdmi_info
*hdmi_info
= &display
->hdmi
;
1987 struct hdmi_vmode
*vmode
= &hdmi
->hdmi_data
.video_mode
;
1988 int hblank
, vblank
, h_de_hs
, v_de_vs
, hsync_len
, vsync_len
;
1989 unsigned int vdisplay
, hdisplay
;
1991 vmode
->mpixelclock
= mode
->clock
* 1000;
1993 dev_dbg(hdmi
->dev
, "final pixclk = %d\n", vmode
->mpixelclock
);
1995 vmode
->mtmdsclock
= vmode
->mpixelclock
;
1997 if (!hdmi_bus_fmt_is_yuv422(hdmi
->hdmi_data
.enc_out_bus_format
)) {
1998 switch (hdmi_bus_fmt_color_depth(
1999 hdmi
->hdmi_data
.enc_out_bus_format
)) {
2001 vmode
->mtmdsclock
= vmode
->mpixelclock
* 2;
2004 vmode
->mtmdsclock
= vmode
->mpixelclock
* 3 / 2;
2007 vmode
->mtmdsclock
= vmode
->mpixelclock
* 5 / 4;
2012 if (hdmi_bus_fmt_is_yuv420(hdmi
->hdmi_data
.enc_out_bus_format
))
2013 vmode
->mtmdsclock
/= 2;
2015 dev_dbg(hdmi
->dev
, "final tmdsclock = %d\n", vmode
->mtmdsclock
);
2017 /* Set up HDMI_FC_INVIDCONF */
2018 inv_val
= (hdmi
->hdmi_data
.hdcp_enable
||
2019 (dw_hdmi_support_scdc(hdmi
, display
) &&
2020 (vmode
->mtmdsclock
> HDMI14_MAX_TMDSCLK
||
2021 hdmi_info
->scdc
.scrambling
.low_rates
)) ?
2022 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE
:
2023 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE
);
2025 inv_val
|= mode
->flags
& DRM_MODE_FLAG_PVSYNC
?
2026 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH
:
2027 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW
;
2029 inv_val
|= mode
->flags
& DRM_MODE_FLAG_PHSYNC
?
2030 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH
:
2031 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW
;
2033 inv_val
|= (vmode
->mdataenablepolarity
?
2034 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH
:
2035 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW
);
2037 if (hdmi
->vic
== 39)
2038 inv_val
|= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH
;
2040 inv_val
|= mode
->flags
& DRM_MODE_FLAG_INTERLACE
?
2041 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH
:
2042 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW
;
2044 inv_val
|= mode
->flags
& DRM_MODE_FLAG_INTERLACE
?
2045 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED
:
2046 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE
;
2048 inv_val
|= hdmi
->sink_is_hdmi
?
2049 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE
:
2050 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE
;
2052 hdmi_writeb(hdmi
, inv_val
, HDMI_FC_INVIDCONF
);
2054 hdisplay
= mode
->hdisplay
;
2055 hblank
= mode
->htotal
- mode
->hdisplay
;
2056 h_de_hs
= mode
->hsync_start
- mode
->hdisplay
;
2057 hsync_len
= mode
->hsync_end
- mode
->hsync_start
;
2060 * When we're setting a YCbCr420 mode, we need
2061 * to adjust the horizontal timing to suit.
2063 if (hdmi_bus_fmt_is_yuv420(hdmi
->hdmi_data
.enc_out_bus_format
)) {
2070 vdisplay
= mode
->vdisplay
;
2071 vblank
= mode
->vtotal
- mode
->vdisplay
;
2072 v_de_vs
= mode
->vsync_start
- mode
->vdisplay
;
2073 vsync_len
= mode
->vsync_end
- mode
->vsync_start
;
2076 * When we're setting an interlaced mode, we need
2077 * to adjust the vertical timing to suit.
2079 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
2086 /* Scrambling Control */
2087 if (dw_hdmi_support_scdc(hdmi
, display
)) {
2088 if (vmode
->mtmdsclock
> HDMI14_MAX_TMDSCLK
||
2089 hdmi_info
->scdc
.scrambling
.low_rates
) {
2091 * HDMI2.0 Specifies the following procedure:
2092 * After the Source Device has determined that
2093 * SCDC_Present is set (=1), the Source Device should
2094 * write the accurate Version of the Source Device
2095 * to the Source Version field in the SCDCS.
2096 * Source Devices compliant shall set the
2097 * Source Version = 1.
2099 drm_scdc_readb(hdmi
->ddc
, SCDC_SINK_VERSION
,
2101 drm_scdc_writeb(hdmi
->ddc
, SCDC_SOURCE_VERSION
,
2102 min_t(u8
, bytes
, SCDC_MIN_SOURCE_VERSION
));
2104 /* Enabled Scrambling in the Sink */
2105 drm_scdc_set_scrambling(hdmi
->curr_conn
, 1);
2108 * To activate the scrambler feature, you must ensure
2109 * that the quasi-static configuration bit
2110 * fc_invidconf.HDCP_keepout is set at configuration
2111 * time, before the required mc_swrstzreq.tmdsswrst_req
2112 * reset request is issued.
2114 hdmi_writeb(hdmi
, (u8
)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ
,
2116 hdmi_writeb(hdmi
, 1, HDMI_FC_SCRAMBLER_CTRL
);
2118 hdmi_writeb(hdmi
, 0, HDMI_FC_SCRAMBLER_CTRL
);
2119 hdmi_writeb(hdmi
, (u8
)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ
,
2121 drm_scdc_set_scrambling(hdmi
->curr_conn
, 0);
2125 /* Set up horizontal active pixel width */
2126 hdmi_writeb(hdmi
, hdisplay
>> 8, HDMI_FC_INHACTV1
);
2127 hdmi_writeb(hdmi
, hdisplay
, HDMI_FC_INHACTV0
);
2129 /* Set up vertical active lines */
2130 hdmi_writeb(hdmi
, vdisplay
>> 8, HDMI_FC_INVACTV1
);
2131 hdmi_writeb(hdmi
, vdisplay
, HDMI_FC_INVACTV0
);
2133 /* Set up horizontal blanking pixel region width */
2134 hdmi_writeb(hdmi
, hblank
>> 8, HDMI_FC_INHBLANK1
);
2135 hdmi_writeb(hdmi
, hblank
, HDMI_FC_INHBLANK0
);
2137 /* Set up vertical blanking pixel region width */
2138 hdmi_writeb(hdmi
, vblank
, HDMI_FC_INVBLANK
);
2140 /* Set up HSYNC active edge delay width (in pixel clks) */
2141 hdmi_writeb(hdmi
, h_de_hs
>> 8, HDMI_FC_HSYNCINDELAY1
);
2142 hdmi_writeb(hdmi
, h_de_hs
, HDMI_FC_HSYNCINDELAY0
);
2144 /* Set up VSYNC active edge delay (in lines) */
2145 hdmi_writeb(hdmi
, v_de_vs
, HDMI_FC_VSYNCINDELAY
);
2147 /* Set up HSYNC active pulse width (in pixel clks) */
2148 hdmi_writeb(hdmi
, hsync_len
>> 8, HDMI_FC_HSYNCINWIDTH1
);
2149 hdmi_writeb(hdmi
, hsync_len
, HDMI_FC_HSYNCINWIDTH0
);
2151 /* Set up VSYNC active edge delay (in lines) */
2152 hdmi_writeb(hdmi
, vsync_len
, HDMI_FC_VSYNCINWIDTH
);
2155 /* HDMI Initialization Step B.4 */
2156 static void dw_hdmi_enable_video_path(struct dw_hdmi
*hdmi
)
2158 /* control period minimum duration */
2159 hdmi_writeb(hdmi
, 12, HDMI_FC_CTRLDUR
);
2160 hdmi_writeb(hdmi
, 32, HDMI_FC_EXCTRLDUR
);
2161 hdmi_writeb(hdmi
, 1, HDMI_FC_EXCTRLSPAC
);
2163 /* Set to fill TMDS data channels */
2164 hdmi_writeb(hdmi
, 0x0B, HDMI_FC_CH0PREAM
);
2165 hdmi_writeb(hdmi
, 0x16, HDMI_FC_CH1PREAM
);
2166 hdmi_writeb(hdmi
, 0x21, HDMI_FC_CH2PREAM
);
2168 /* Enable pixel clock and tmds data path */
2169 hdmi
->mc_clkdis
|= HDMI_MC_CLKDIS_HDCPCLK_DISABLE
|
2170 HDMI_MC_CLKDIS_CSCCLK_DISABLE
|
2171 HDMI_MC_CLKDIS_AUDCLK_DISABLE
|
2172 HDMI_MC_CLKDIS_PREPCLK_DISABLE
|
2173 HDMI_MC_CLKDIS_TMDSCLK_DISABLE
;
2174 hdmi
->mc_clkdis
&= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE
;
2175 hdmi_writeb(hdmi
, hdmi
->mc_clkdis
, HDMI_MC_CLKDIS
);
2177 hdmi
->mc_clkdis
&= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE
;
2178 hdmi_writeb(hdmi
, hdmi
->mc_clkdis
, HDMI_MC_CLKDIS
);
2180 /* Enable csc path */
2181 if (is_csc_needed(hdmi
)) {
2182 hdmi
->mc_clkdis
&= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE
;
2183 hdmi_writeb(hdmi
, hdmi
->mc_clkdis
, HDMI_MC_CLKDIS
);
2185 hdmi_writeb(hdmi
, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH
,
2188 hdmi
->mc_clkdis
|= HDMI_MC_CLKDIS_CSCCLK_DISABLE
;
2189 hdmi_writeb(hdmi
, hdmi
->mc_clkdis
, HDMI_MC_CLKDIS
);
2191 hdmi_writeb(hdmi
, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS
,
2196 /* Workaround to clear the overflow condition */
2197 static void dw_hdmi_clear_overflow(struct dw_hdmi
*hdmi
)
2204 * Under some circumstances the Frame Composer arithmetic unit can miss
2205 * an FC register write due to being busy processing the previous one.
2206 * The issue can be worked around by issuing a TMDS software reset and
2207 * then write one of the FC registers several times.
2209 * The number of iterations matters and depends on the HDMI TX revision
2210 * (and possibly on the platform).
2211 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others.
2212 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a),
2213 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a)
2214 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround
2215 * with a single iteration.
2218 switch (hdmi
->version
) {
2227 /* TMDS software reset */
2228 hdmi_writeb(hdmi
, (u8
)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ
, HDMI_MC_SWRSTZ
);
2230 val
= hdmi_readb(hdmi
, HDMI_FC_INVIDCONF
);
2231 for (i
= 0; i
< count
; i
++)
2232 hdmi_writeb(hdmi
, val
, HDMI_FC_INVIDCONF
);
2235 static void hdmi_disable_overflow_interrupts(struct dw_hdmi
*hdmi
)
2237 hdmi_writeb(hdmi
, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK
,
2238 HDMI_IH_MUTE_FC_STAT2
);
2241 static int dw_hdmi_setup(struct dw_hdmi
*hdmi
,
2242 const struct drm_connector
*connector
,
2243 const struct drm_display_mode
*mode
)
2247 hdmi_disable_overflow_interrupts(hdmi
);
2249 hdmi
->vic
= drm_match_cea_mode(mode
);
2252 dev_dbg(hdmi
->dev
, "Non-CEA mode used in HDMI\n");
2254 dev_dbg(hdmi
->dev
, "CEA mode used vic=%d\n", hdmi
->vic
);
2257 if ((hdmi
->vic
== 6) || (hdmi
->vic
== 7) ||
2258 (hdmi
->vic
== 21) || (hdmi
->vic
== 22) ||
2259 (hdmi
->vic
== 2) || (hdmi
->vic
== 3) ||
2260 (hdmi
->vic
== 17) || (hdmi
->vic
== 18))
2261 hdmi
->hdmi_data
.enc_out_encoding
= V4L2_YCBCR_ENC_601
;
2263 hdmi
->hdmi_data
.enc_out_encoding
= V4L2_YCBCR_ENC_709
;
2265 hdmi
->hdmi_data
.video_mode
.mpixelrepetitionoutput
= 0;
2266 hdmi
->hdmi_data
.video_mode
.mpixelrepetitioninput
= 0;
2268 if (hdmi
->hdmi_data
.enc_in_bus_format
== MEDIA_BUS_FMT_FIXED
)
2269 hdmi
->hdmi_data
.enc_in_bus_format
= MEDIA_BUS_FMT_RGB888_1X24
;
2271 /* TOFIX: Get input encoding from plat data or fallback to none */
2272 if (hdmi
->plat_data
->input_bus_encoding
)
2273 hdmi
->hdmi_data
.enc_in_encoding
=
2274 hdmi
->plat_data
->input_bus_encoding
;
2276 hdmi
->hdmi_data
.enc_in_encoding
= V4L2_YCBCR_ENC_DEFAULT
;
2278 if (hdmi
->hdmi_data
.enc_out_bus_format
== MEDIA_BUS_FMT_FIXED
)
2279 hdmi
->hdmi_data
.enc_out_bus_format
= MEDIA_BUS_FMT_RGB888_1X24
;
2281 hdmi
->hdmi_data
.rgb_limited_range
= hdmi
->sink_is_hdmi
&&
2282 drm_default_rgb_quant_range(mode
) ==
2283 HDMI_QUANTIZATION_RANGE_LIMITED
;
2285 hdmi
->hdmi_data
.pix_repet_factor
= 0;
2286 hdmi
->hdmi_data
.hdcp_enable
= 0;
2287 hdmi
->hdmi_data
.video_mode
.mdataenablepolarity
= true;
2289 /* HDMI Initialization Step B.1 */
2290 hdmi_av_composer(hdmi
, &connector
->display_info
, mode
);
2292 /* HDMI Initializateion Step B.2 */
2293 ret
= hdmi
->phy
.ops
->init(hdmi
, hdmi
->phy
.data
,
2294 &connector
->display_info
,
2295 &hdmi
->previous_mode
);
2298 hdmi
->phy
.enabled
= true;
2300 /* HDMI Initialization Step B.3 */
2301 dw_hdmi_enable_video_path(hdmi
);
2303 if (hdmi
->sink_has_audio
) {
2304 dev_dbg(hdmi
->dev
, "sink has audio support\n");
2306 /* HDMI Initialization Step E - Configure audio */
2307 hdmi_clk_regenerator_update_pixel_clock(hdmi
);
2308 hdmi_enable_audio_clk(hdmi
, hdmi
->audio_enable
);
2311 /* not for DVI mode */
2312 if (hdmi
->sink_is_hdmi
) {
2313 dev_dbg(hdmi
->dev
, "%s HDMI mode\n", __func__
);
2315 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2316 hdmi_config_AVI(hdmi
, connector
, mode
);
2317 hdmi_config_vendor_specific_infoframe(hdmi
, connector
, mode
);
2318 hdmi_config_drm_infoframe(hdmi
, connector
);
2320 dev_dbg(hdmi
->dev
, "%s DVI mode\n", __func__
);
2323 hdmi_video_packetize(hdmi
);
2324 hdmi_video_csc(hdmi
);
2325 hdmi_video_sample(hdmi
);
2326 hdmi_tx_hdcp_config(hdmi
);
2328 dw_hdmi_clear_overflow(hdmi
);
2333 static void initialize_hdmi_ih_mutes(struct dw_hdmi
*hdmi
)
2338 * Boot up defaults are:
2339 * HDMI_IH_MUTE = 0x03 (disabled)
2340 * HDMI_IH_MUTE_* = 0x00 (enabled)
2342 * Disable top level interrupt bits in HDMI block
2344 ih_mute
= hdmi_readb(hdmi
, HDMI_IH_MUTE
) |
2345 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT
|
2346 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT
;
2348 hdmi_writeb(hdmi
, ih_mute
, HDMI_IH_MUTE
);
2350 /* by default mask all interrupts */
2351 hdmi_writeb(hdmi
, 0xff, HDMI_VP_MASK
);
2352 hdmi_writeb(hdmi
, 0xff, HDMI_FC_MASK0
);
2353 hdmi_writeb(hdmi
, 0xff, HDMI_FC_MASK1
);
2354 hdmi_writeb(hdmi
, 0xff, HDMI_FC_MASK2
);
2355 hdmi_writeb(hdmi
, 0xff, HDMI_PHY_MASK0
);
2356 hdmi_writeb(hdmi
, 0xff, HDMI_PHY_I2CM_INT_ADDR
);
2357 hdmi_writeb(hdmi
, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR
);
2358 hdmi_writeb(hdmi
, 0xff, HDMI_AUD_INT
);
2359 hdmi_writeb(hdmi
, 0xff, HDMI_AUD_SPDIFINT
);
2360 hdmi_writeb(hdmi
, 0xff, HDMI_AUD_HBR_MASK
);
2361 hdmi_writeb(hdmi
, 0xff, HDMI_GP_MASK
);
2362 hdmi_writeb(hdmi
, 0xff, HDMI_A_APIINTMSK
);
2363 hdmi_writeb(hdmi
, 0xff, HDMI_I2CM_INT
);
2364 hdmi_writeb(hdmi
, 0xff, HDMI_I2CM_CTLINT
);
2366 /* Disable interrupts in the IH_MUTE_* registers */
2367 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_FC_STAT0
);
2368 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_FC_STAT1
);
2369 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_FC_STAT2
);
2370 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_AS_STAT0
);
2371 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_PHY_STAT0
);
2372 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_I2CM_STAT0
);
2373 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_CEC_STAT0
);
2374 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_VP_STAT0
);
2375 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0
);
2376 hdmi_writeb(hdmi
, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0
);
2378 /* Enable top level interrupt bits in HDMI block */
2379 ih_mute
&= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT
|
2380 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT
);
2381 hdmi_writeb(hdmi
, ih_mute
, HDMI_IH_MUTE
);
2384 static void dw_hdmi_poweron(struct dw_hdmi
*hdmi
)
2386 hdmi
->bridge_is_on
= true;
2389 * The curr_conn field is guaranteed to be valid here, as this function
2390 * is only be called when !hdmi->disabled.
2392 dw_hdmi_setup(hdmi
, hdmi
->curr_conn
, &hdmi
->previous_mode
);
2395 static void dw_hdmi_poweroff(struct dw_hdmi
*hdmi
)
2397 if (hdmi
->phy
.enabled
) {
2398 hdmi
->phy
.ops
->disable(hdmi
, hdmi
->phy
.data
);
2399 hdmi
->phy
.enabled
= false;
2402 hdmi
->bridge_is_on
= false;
2405 static void dw_hdmi_update_power(struct dw_hdmi
*hdmi
)
2407 int force
= hdmi
->force
;
2409 if (hdmi
->disabled
) {
2410 force
= DRM_FORCE_OFF
;
2411 } else if (force
== DRM_FORCE_UNSPECIFIED
) {
2413 force
= DRM_FORCE_ON
;
2415 force
= DRM_FORCE_OFF
;
2418 if (force
== DRM_FORCE_OFF
) {
2419 if (hdmi
->bridge_is_on
)
2420 dw_hdmi_poweroff(hdmi
);
2422 if (!hdmi
->bridge_is_on
)
2423 dw_hdmi_poweron(hdmi
);
2428 * Adjust the detection of RXSENSE according to whether we have a forced
2429 * connection mode enabled, or whether we have been disabled. There is
2430 * no point processing RXSENSE interrupts if we have a forced connection
2431 * state, or DRM has us disabled.
2433 * We also disable rxsense interrupts when we think we're disconnected
2434 * to avoid floating TDMS signals giving false rxsense interrupts.
2436 * Note: we still need to listen for HPD interrupts even when DRM has us
2437 * disabled so that we can detect a connect event.
2439 static void dw_hdmi_update_phy_mask(struct dw_hdmi
*hdmi
)
2441 if (hdmi
->phy
.ops
->update_hpd
)
2442 hdmi
->phy
.ops
->update_hpd(hdmi
, hdmi
->phy
.data
,
2443 hdmi
->force
, hdmi
->disabled
,
2447 static enum drm_connector_status
dw_hdmi_detect(struct dw_hdmi
*hdmi
)
2449 enum drm_connector_status result
;
2451 result
= hdmi
->phy
.ops
->read_hpd(hdmi
, hdmi
->phy
.data
);
2452 hdmi
->last_connector_result
= result
;
2457 static struct edid
*dw_hdmi_get_edid(struct dw_hdmi
*hdmi
,
2458 struct drm_connector
*connector
)
2465 edid
= drm_get_edid(connector
, hdmi
->ddc
);
2467 dev_dbg(hdmi
->dev
, "failed to get edid\n");
2471 dev_dbg(hdmi
->dev
, "got edid: width[%d] x height[%d]\n",
2472 edid
->width_cm
, edid
->height_cm
);
2474 hdmi
->sink_is_hdmi
= drm_detect_hdmi_monitor(edid
);
2475 hdmi
->sink_has_audio
= drm_detect_monitor_audio(edid
);
2480 /* -----------------------------------------------------------------------------
2481 * DRM Connector Operations
2484 static enum drm_connector_status
2485 dw_hdmi_connector_detect(struct drm_connector
*connector
, bool force
)
2487 struct dw_hdmi
*hdmi
= container_of(connector
, struct dw_hdmi
,
2489 return dw_hdmi_detect(hdmi
);
2492 static int dw_hdmi_connector_get_modes(struct drm_connector
*connector
)
2494 struct dw_hdmi
*hdmi
= container_of(connector
, struct dw_hdmi
,
2499 edid
= dw_hdmi_get_edid(hdmi
, connector
);
2503 drm_connector_update_edid_property(connector
, edid
);
2504 cec_notifier_set_phys_addr_from_edid(hdmi
->cec_notifier
, edid
);
2505 ret
= drm_add_edid_modes(connector
, edid
);
2511 static int dw_hdmi_connector_atomic_check(struct drm_connector
*connector
,
2512 struct drm_atomic_state
*state
)
2514 struct drm_connector_state
*old_state
=
2515 drm_atomic_get_old_connector_state(state
, connector
);
2516 struct drm_connector_state
*new_state
=
2517 drm_atomic_get_new_connector_state(state
, connector
);
2518 struct drm_crtc
*crtc
= new_state
->crtc
;
2519 struct drm_crtc_state
*crtc_state
;
2524 if (!drm_connector_atomic_hdr_metadata_equal(old_state
, new_state
)) {
2525 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
2526 if (IS_ERR(crtc_state
))
2527 return PTR_ERR(crtc_state
);
2529 crtc_state
->mode_changed
= true;
2535 static void dw_hdmi_connector_force(struct drm_connector
*connector
)
2537 struct dw_hdmi
*hdmi
= container_of(connector
, struct dw_hdmi
,
2540 mutex_lock(&hdmi
->mutex
);
2541 hdmi
->force
= connector
->force
;
2542 dw_hdmi_update_power(hdmi
);
2543 dw_hdmi_update_phy_mask(hdmi
);
2544 mutex_unlock(&hdmi
->mutex
);
2547 static const struct drm_connector_funcs dw_hdmi_connector_funcs
= {
2548 .fill_modes
= drm_helper_probe_single_connector_modes
,
2549 .detect
= dw_hdmi_connector_detect
,
2550 .destroy
= drm_connector_cleanup
,
2551 .force
= dw_hdmi_connector_force
,
2552 .reset
= drm_atomic_helper_connector_reset
,
2553 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
2554 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
2557 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs
= {
2558 .get_modes
= dw_hdmi_connector_get_modes
,
2559 .atomic_check
= dw_hdmi_connector_atomic_check
,
2562 static int dw_hdmi_connector_create(struct dw_hdmi
*hdmi
)
2564 struct drm_connector
*connector
= &hdmi
->connector
;
2565 struct cec_connector_info conn_info
;
2566 struct cec_notifier
*notifier
;
2568 if (hdmi
->version
>= 0x200a)
2569 connector
->ycbcr_420_allowed
=
2570 hdmi
->plat_data
->ycbcr_420_allowed
;
2572 connector
->ycbcr_420_allowed
= false;
2574 connector
->interlace_allowed
= 1;
2575 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2577 drm_connector_helper_add(connector
, &dw_hdmi_connector_helper_funcs
);
2579 drm_connector_init_with_ddc(hdmi
->bridge
.dev
, connector
,
2580 &dw_hdmi_connector_funcs
,
2581 DRM_MODE_CONNECTOR_HDMIA
,
2585 * drm_connector_attach_max_bpc_property() requires the
2586 * connector to have a state.
2588 drm_atomic_helper_connector_reset(connector
);
2590 drm_connector_attach_max_bpc_property(connector
, 8, 16);
2592 if (hdmi
->version
>= 0x200a && hdmi
->plat_data
->use_drm_infoframe
)
2593 drm_connector_attach_hdr_output_metadata_property(connector
);
2595 drm_connector_attach_encoder(connector
, hdmi
->bridge
.encoder
);
2597 cec_fill_conn_info_from_drm(&conn_info
, connector
);
2599 notifier
= cec_notifier_conn_register(hdmi
->dev
, NULL
, &conn_info
);
2603 mutex_lock(&hdmi
->cec_notifier_mutex
);
2604 hdmi
->cec_notifier
= notifier
;
2605 mutex_unlock(&hdmi
->cec_notifier_mutex
);
2610 /* -----------------------------------------------------------------------------
2611 * DRM Bridge Operations
2615 * Possible output formats :
2616 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
2617 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
2618 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
2619 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
2620 * - MEDIA_BUS_FMT_YUV16_1X48,
2621 * - MEDIA_BUS_FMT_RGB161616_1X48,
2622 * - MEDIA_BUS_FMT_UYVY12_1X24,
2623 * - MEDIA_BUS_FMT_YUV12_1X36,
2624 * - MEDIA_BUS_FMT_RGB121212_1X36,
2625 * - MEDIA_BUS_FMT_UYVY10_1X20,
2626 * - MEDIA_BUS_FMT_YUV10_1X30,
2627 * - MEDIA_BUS_FMT_RGB101010_1X30,
2628 * - MEDIA_BUS_FMT_UYVY8_1X16,
2629 * - MEDIA_BUS_FMT_YUV8_1X24,
2630 * - MEDIA_BUS_FMT_RGB888_1X24,
2633 /* Can return a maximum of 11 possible output formats for a mode/connector */
2634 #define MAX_OUTPUT_SEL_FORMATS 11
2636 static u32
*dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge
*bridge
,
2637 struct drm_bridge_state
*bridge_state
,
2638 struct drm_crtc_state
*crtc_state
,
2639 struct drm_connector_state
*conn_state
,
2640 unsigned int *num_output_fmts
)
2642 struct drm_connector
*conn
= conn_state
->connector
;
2643 struct drm_display_info
*info
= &conn
->display_info
;
2644 struct drm_display_mode
*mode
= &crtc_state
->mode
;
2645 u8 max_bpc
= conn_state
->max_requested_bpc
;
2646 bool is_hdmi2_sink
= info
->hdmi
.scdc
.supported
||
2647 (info
->color_formats
& DRM_COLOR_FORMAT_YCBCR420
);
2651 *num_output_fmts
= 0;
2653 output_fmts
= kcalloc(MAX_OUTPUT_SEL_FORMATS
, sizeof(*output_fmts
),
2658 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
2659 if (list_is_singular(&bridge
->encoder
->bridge_chain
) ||
2660 list_is_first(&bridge
->chain_node
, &bridge
->encoder
->bridge_chain
)) {
2661 *num_output_fmts
= 1;
2662 output_fmts
[0] = MEDIA_BUS_FMT_FIXED
;
2668 * If the current mode enforces 4:2:0, force the output but format
2669 * to 4:2:0 and do not add the YUV422/444/RGB formats
2671 if (conn
->ycbcr_420_allowed
&&
2672 (drm_mode_is_420_only(info
, mode
) ||
2673 (is_hdmi2_sink
&& drm_mode_is_420_also(info
, mode
)))) {
2675 /* Order bus formats from 16bit to 8bit if supported */
2676 if (max_bpc
>= 16 && info
->bpc
== 16 &&
2677 (info
->hdmi
.y420_dc_modes
& DRM_EDID_YCBCR420_DC_48
))
2678 output_fmts
[i
++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48
;
2680 if (max_bpc
>= 12 && info
->bpc
>= 12 &&
2681 (info
->hdmi
.y420_dc_modes
& DRM_EDID_YCBCR420_DC_36
))
2682 output_fmts
[i
++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36
;
2684 if (max_bpc
>= 10 && info
->bpc
>= 10 &&
2685 (info
->hdmi
.y420_dc_modes
& DRM_EDID_YCBCR420_DC_30
))
2686 output_fmts
[i
++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30
;
2688 /* Default 8bit fallback */
2689 output_fmts
[i
++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24
;
2691 if (drm_mode_is_420_only(info
, mode
)) {
2692 *num_output_fmts
= i
;
2698 * Order bus formats from 16bit to 8bit and from YUV422 to RGB
2699 * if supported. In any case the default RGB888 format is added
2702 /* Default 8bit RGB fallback */
2703 output_fmts
[i
++] = MEDIA_BUS_FMT_RGB888_1X24
;
2705 if (max_bpc
>= 16 && info
->bpc
== 16) {
2706 if (info
->color_formats
& DRM_COLOR_FORMAT_YCBCR444
)
2707 output_fmts
[i
++] = MEDIA_BUS_FMT_YUV16_1X48
;
2709 output_fmts
[i
++] = MEDIA_BUS_FMT_RGB161616_1X48
;
2712 if (max_bpc
>= 12 && info
->bpc
>= 12) {
2713 if (info
->color_formats
& DRM_COLOR_FORMAT_YCBCR422
)
2714 output_fmts
[i
++] = MEDIA_BUS_FMT_UYVY12_1X24
;
2716 if (info
->color_formats
& DRM_COLOR_FORMAT_YCBCR444
)
2717 output_fmts
[i
++] = MEDIA_BUS_FMT_YUV12_1X36
;
2719 output_fmts
[i
++] = MEDIA_BUS_FMT_RGB121212_1X36
;
2722 if (max_bpc
>= 10 && info
->bpc
>= 10) {
2723 if (info
->color_formats
& DRM_COLOR_FORMAT_YCBCR422
)
2724 output_fmts
[i
++] = MEDIA_BUS_FMT_UYVY10_1X20
;
2726 if (info
->color_formats
& DRM_COLOR_FORMAT_YCBCR444
)
2727 output_fmts
[i
++] = MEDIA_BUS_FMT_YUV10_1X30
;
2729 output_fmts
[i
++] = MEDIA_BUS_FMT_RGB101010_1X30
;
2732 if (info
->color_formats
& DRM_COLOR_FORMAT_YCBCR422
)
2733 output_fmts
[i
++] = MEDIA_BUS_FMT_UYVY8_1X16
;
2735 if (info
->color_formats
& DRM_COLOR_FORMAT_YCBCR444
)
2736 output_fmts
[i
++] = MEDIA_BUS_FMT_YUV8_1X24
;
2738 *num_output_fmts
= i
;
2744 * Possible input formats :
2745 * - MEDIA_BUS_FMT_RGB888_1X24
2746 * - MEDIA_BUS_FMT_YUV8_1X24
2747 * - MEDIA_BUS_FMT_UYVY8_1X16
2748 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
2749 * - MEDIA_BUS_FMT_RGB101010_1X30
2750 * - MEDIA_BUS_FMT_YUV10_1X30
2751 * - MEDIA_BUS_FMT_UYVY10_1X20
2752 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
2753 * - MEDIA_BUS_FMT_RGB121212_1X36
2754 * - MEDIA_BUS_FMT_YUV12_1X36
2755 * - MEDIA_BUS_FMT_UYVY12_1X24
2756 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
2757 * - MEDIA_BUS_FMT_RGB161616_1X48
2758 * - MEDIA_BUS_FMT_YUV16_1X48
2759 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
2762 /* Can return a maximum of 3 possible input formats for an output format */
2763 #define MAX_INPUT_SEL_FORMATS 3
2765 static u32
*dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge
*bridge
,
2766 struct drm_bridge_state
*bridge_state
,
2767 struct drm_crtc_state
*crtc_state
,
2768 struct drm_connector_state
*conn_state
,
2770 unsigned int *num_input_fmts
)
2775 *num_input_fmts
= 0;
2777 input_fmts
= kcalloc(MAX_INPUT_SEL_FORMATS
, sizeof(*input_fmts
),
2782 switch (output_fmt
) {
2783 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
2784 case MEDIA_BUS_FMT_FIXED
:
2785 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB888_1X24
;
2788 case MEDIA_BUS_FMT_RGB888_1X24
:
2789 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB888_1X24
;
2790 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV8_1X24
;
2791 input_fmts
[i
++] = MEDIA_BUS_FMT_UYVY8_1X16
;
2793 case MEDIA_BUS_FMT_YUV8_1X24
:
2794 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV8_1X24
;
2795 input_fmts
[i
++] = MEDIA_BUS_FMT_UYVY8_1X16
;
2796 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB888_1X24
;
2798 case MEDIA_BUS_FMT_UYVY8_1X16
:
2799 input_fmts
[i
++] = MEDIA_BUS_FMT_UYVY8_1X16
;
2800 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV8_1X24
;
2801 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB888_1X24
;
2805 case MEDIA_BUS_FMT_RGB101010_1X30
:
2806 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB101010_1X30
;
2807 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV10_1X30
;
2808 input_fmts
[i
++] = MEDIA_BUS_FMT_UYVY10_1X20
;
2810 case MEDIA_BUS_FMT_YUV10_1X30
:
2811 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV10_1X30
;
2812 input_fmts
[i
++] = MEDIA_BUS_FMT_UYVY10_1X20
;
2813 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB101010_1X30
;
2815 case MEDIA_BUS_FMT_UYVY10_1X20
:
2816 input_fmts
[i
++] = MEDIA_BUS_FMT_UYVY10_1X20
;
2817 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV10_1X30
;
2818 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB101010_1X30
;
2822 case MEDIA_BUS_FMT_RGB121212_1X36
:
2823 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB121212_1X36
;
2824 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV12_1X36
;
2825 input_fmts
[i
++] = MEDIA_BUS_FMT_UYVY12_1X24
;
2827 case MEDIA_BUS_FMT_YUV12_1X36
:
2828 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV12_1X36
;
2829 input_fmts
[i
++] = MEDIA_BUS_FMT_UYVY12_1X24
;
2830 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB121212_1X36
;
2832 case MEDIA_BUS_FMT_UYVY12_1X24
:
2833 input_fmts
[i
++] = MEDIA_BUS_FMT_UYVY12_1X24
;
2834 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV12_1X36
;
2835 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB121212_1X36
;
2839 case MEDIA_BUS_FMT_RGB161616_1X48
:
2840 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB161616_1X48
;
2841 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV16_1X48
;
2843 case MEDIA_BUS_FMT_YUV16_1X48
:
2844 input_fmts
[i
++] = MEDIA_BUS_FMT_YUV16_1X48
;
2845 input_fmts
[i
++] = MEDIA_BUS_FMT_RGB161616_1X48
;
2849 case MEDIA_BUS_FMT_UYYVYY8_0_5X24
:
2850 case MEDIA_BUS_FMT_UYYVYY10_0_5X30
:
2851 case MEDIA_BUS_FMT_UYYVYY12_0_5X36
:
2852 case MEDIA_BUS_FMT_UYYVYY16_0_5X48
:
2853 input_fmts
[i
++] = output_fmt
;
2857 *num_input_fmts
= i
;
2859 if (*num_input_fmts
== 0) {
2867 static int dw_hdmi_bridge_atomic_check(struct drm_bridge
*bridge
,
2868 struct drm_bridge_state
*bridge_state
,
2869 struct drm_crtc_state
*crtc_state
,
2870 struct drm_connector_state
*conn_state
)
2872 struct dw_hdmi
*hdmi
= bridge
->driver_private
;
2874 hdmi
->hdmi_data
.enc_out_bus_format
=
2875 bridge_state
->output_bus_cfg
.format
;
2877 hdmi
->hdmi_data
.enc_in_bus_format
=
2878 bridge_state
->input_bus_cfg
.format
;
2880 dev_dbg(hdmi
->dev
, "input format 0x%04x, output format 0x%04x\n",
2881 bridge_state
->input_bus_cfg
.format
,
2882 bridge_state
->output_bus_cfg
.format
);
2887 static int dw_hdmi_bridge_attach(struct drm_bridge
*bridge
,
2888 enum drm_bridge_attach_flags flags
)
2890 struct dw_hdmi
*hdmi
= bridge
->driver_private
;
2892 if (flags
& DRM_BRIDGE_ATTACH_NO_CONNECTOR
)
2893 return drm_bridge_attach(bridge
->encoder
, hdmi
->next_bridge
,
2896 return dw_hdmi_connector_create(hdmi
);
2899 static void dw_hdmi_bridge_detach(struct drm_bridge
*bridge
)
2901 struct dw_hdmi
*hdmi
= bridge
->driver_private
;
2903 mutex_lock(&hdmi
->cec_notifier_mutex
);
2904 cec_notifier_conn_unregister(hdmi
->cec_notifier
);
2905 hdmi
->cec_notifier
= NULL
;
2906 mutex_unlock(&hdmi
->cec_notifier_mutex
);
2909 static enum drm_mode_status
2910 dw_hdmi_bridge_mode_valid(struct drm_bridge
*bridge
,
2911 const struct drm_display_info
*info
,
2912 const struct drm_display_mode
*mode
)
2914 struct dw_hdmi
*hdmi
= bridge
->driver_private
;
2915 const struct dw_hdmi_plat_data
*pdata
= hdmi
->plat_data
;
2916 enum drm_mode_status mode_status
= MODE_OK
;
2918 /* We don't support double-clocked modes */
2919 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
2922 if (pdata
->mode_valid
)
2923 mode_status
= pdata
->mode_valid(hdmi
, pdata
->priv_data
, info
,
2929 static void dw_hdmi_bridge_mode_set(struct drm_bridge
*bridge
,
2930 const struct drm_display_mode
*orig_mode
,
2931 const struct drm_display_mode
*mode
)
2933 struct dw_hdmi
*hdmi
= bridge
->driver_private
;
2935 mutex_lock(&hdmi
->mutex
);
2937 /* Store the display mode for plugin/DKMS poweron events */
2938 drm_mode_copy(&hdmi
->previous_mode
, mode
);
2940 mutex_unlock(&hdmi
->mutex
);
2943 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge
*bridge
,
2944 struct drm_bridge_state
*old_state
)
2946 struct dw_hdmi
*hdmi
= bridge
->driver_private
;
2948 mutex_lock(&hdmi
->mutex
);
2949 hdmi
->disabled
= true;
2950 hdmi
->curr_conn
= NULL
;
2951 dw_hdmi_update_power(hdmi
);
2952 dw_hdmi_update_phy_mask(hdmi
);
2953 handle_plugged_change(hdmi
, false);
2954 mutex_unlock(&hdmi
->mutex
);
2957 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge
*bridge
,
2958 struct drm_bridge_state
*old_state
)
2960 struct dw_hdmi
*hdmi
= bridge
->driver_private
;
2961 struct drm_atomic_state
*state
= old_state
->base
.state
;
2962 struct drm_connector
*connector
;
2964 connector
= drm_atomic_get_new_connector_for_encoder(state
,
2967 mutex_lock(&hdmi
->mutex
);
2968 hdmi
->disabled
= false;
2969 hdmi
->curr_conn
= connector
;
2970 dw_hdmi_update_power(hdmi
);
2971 dw_hdmi_update_phy_mask(hdmi
);
2972 handle_plugged_change(hdmi
, true);
2973 mutex_unlock(&hdmi
->mutex
);
2976 static enum drm_connector_status
dw_hdmi_bridge_detect(struct drm_bridge
*bridge
)
2978 struct dw_hdmi
*hdmi
= bridge
->driver_private
;
2980 return dw_hdmi_detect(hdmi
);
2983 static struct edid
*dw_hdmi_bridge_get_edid(struct drm_bridge
*bridge
,
2984 struct drm_connector
*connector
)
2986 struct dw_hdmi
*hdmi
= bridge
->driver_private
;
2988 return dw_hdmi_get_edid(hdmi
, connector
);
2991 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs
= {
2992 .atomic_duplicate_state
= drm_atomic_helper_bridge_duplicate_state
,
2993 .atomic_destroy_state
= drm_atomic_helper_bridge_destroy_state
,
2994 .atomic_reset
= drm_atomic_helper_bridge_reset
,
2995 .attach
= dw_hdmi_bridge_attach
,
2996 .detach
= dw_hdmi_bridge_detach
,
2997 .atomic_check
= dw_hdmi_bridge_atomic_check
,
2998 .atomic_get_output_bus_fmts
= dw_hdmi_bridge_atomic_get_output_bus_fmts
,
2999 .atomic_get_input_bus_fmts
= dw_hdmi_bridge_atomic_get_input_bus_fmts
,
3000 .atomic_enable
= dw_hdmi_bridge_atomic_enable
,
3001 .atomic_disable
= dw_hdmi_bridge_atomic_disable
,
3002 .mode_set
= dw_hdmi_bridge_mode_set
,
3003 .mode_valid
= dw_hdmi_bridge_mode_valid
,
3004 .detect
= dw_hdmi_bridge_detect
,
3005 .get_edid
= dw_hdmi_bridge_get_edid
,
3008 /* -----------------------------------------------------------------------------
3012 static irqreturn_t
dw_hdmi_i2c_irq(struct dw_hdmi
*hdmi
)
3014 struct dw_hdmi_i2c
*i2c
= hdmi
->i2c
;
3017 stat
= hdmi_readb(hdmi
, HDMI_IH_I2CM_STAT0
);
3021 hdmi_writeb(hdmi
, stat
, HDMI_IH_I2CM_STAT0
);
3025 complete(&i2c
->cmp
);
3030 static irqreturn_t
dw_hdmi_hardirq(int irq
, void *dev_id
)
3032 struct dw_hdmi
*hdmi
= dev_id
;
3034 irqreturn_t ret
= IRQ_NONE
;
3037 ret
= dw_hdmi_i2c_irq(hdmi
);
3039 intr_stat
= hdmi_readb(hdmi
, HDMI_IH_PHY_STAT0
);
3041 hdmi_writeb(hdmi
, ~0, HDMI_IH_MUTE_PHY_STAT0
);
3042 return IRQ_WAKE_THREAD
;
3048 void dw_hdmi_setup_rx_sense(struct dw_hdmi
*hdmi
, bool hpd
, bool rx_sense
)
3050 mutex_lock(&hdmi
->mutex
);
3054 * If the RX sense status indicates we're disconnected,
3055 * clear the software rxsense status.
3058 hdmi
->rxsense
= false;
3061 * Only set the software rxsense status when both
3062 * rxsense and hpd indicates we're connected.
3063 * This avoids what seems to be bad behaviour in
3064 * at least iMX6S versions of the phy.
3067 hdmi
->rxsense
= true;
3069 dw_hdmi_update_power(hdmi
);
3070 dw_hdmi_update_phy_mask(hdmi
);
3072 mutex_unlock(&hdmi
->mutex
);
3074 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense
);
3076 static irqreturn_t
dw_hdmi_irq(int irq
, void *dev_id
)
3078 struct dw_hdmi
*hdmi
= dev_id
;
3079 u8 intr_stat
, phy_int_pol
, phy_pol_mask
, phy_stat
;
3080 enum drm_connector_status status
= connector_status_unknown
;
3082 intr_stat
= hdmi_readb(hdmi
, HDMI_IH_PHY_STAT0
);
3083 phy_int_pol
= hdmi_readb(hdmi
, HDMI_PHY_POL0
);
3084 phy_stat
= hdmi_readb(hdmi
, HDMI_PHY_STAT0
);
3087 if (intr_stat
& HDMI_IH_PHY_STAT0_HPD
)
3088 phy_pol_mask
|= HDMI_PHY_HPD
;
3089 if (intr_stat
& HDMI_IH_PHY_STAT0_RX_SENSE0
)
3090 phy_pol_mask
|= HDMI_PHY_RX_SENSE0
;
3091 if (intr_stat
& HDMI_IH_PHY_STAT0_RX_SENSE1
)
3092 phy_pol_mask
|= HDMI_PHY_RX_SENSE1
;
3093 if (intr_stat
& HDMI_IH_PHY_STAT0_RX_SENSE2
)
3094 phy_pol_mask
|= HDMI_PHY_RX_SENSE2
;
3095 if (intr_stat
& HDMI_IH_PHY_STAT0_RX_SENSE3
)
3096 phy_pol_mask
|= HDMI_PHY_RX_SENSE3
;
3099 hdmi_modb(hdmi
, ~phy_int_pol
, phy_pol_mask
, HDMI_PHY_POL0
);
3102 * RX sense tells us whether the TDMS transmitters are detecting
3103 * load - in other words, there's something listening on the
3104 * other end of the link. Use this to decide whether we should
3105 * power on the phy as HPD may be toggled by the sink to merely
3106 * ask the source to re-read the EDID.
3109 (HDMI_IH_PHY_STAT0_RX_SENSE
| HDMI_IH_PHY_STAT0_HPD
)) {
3110 dw_hdmi_setup_rx_sense(hdmi
,
3111 phy_stat
& HDMI_PHY_HPD
,
3112 phy_stat
& HDMI_PHY_RX_SENSE
);
3114 if ((phy_stat
& (HDMI_PHY_RX_SENSE
| HDMI_PHY_HPD
)) == 0) {
3115 mutex_lock(&hdmi
->cec_notifier_mutex
);
3116 cec_notifier_phys_addr_invalidate(hdmi
->cec_notifier
);
3117 mutex_unlock(&hdmi
->cec_notifier_mutex
);
3120 if (phy_stat
& HDMI_PHY_HPD
)
3121 status
= connector_status_connected
;
3123 if (!(phy_stat
& (HDMI_PHY_HPD
| HDMI_PHY_RX_SENSE
)))
3124 status
= connector_status_disconnected
;
3127 if (status
!= connector_status_unknown
) {
3128 dev_dbg(hdmi
->dev
, "EVENT=%s\n",
3129 status
== connector_status_connected
?
3130 "plugin" : "plugout");
3132 if (hdmi
->bridge
.dev
) {
3133 drm_helper_hpd_irq_event(hdmi
->bridge
.dev
);
3134 drm_bridge_hpd_notify(&hdmi
->bridge
, status
);
3138 hdmi_writeb(hdmi
, intr_stat
, HDMI_IH_PHY_STAT0
);
3139 hdmi_writeb(hdmi
, ~(HDMI_IH_PHY_STAT0_HPD
| HDMI_IH_PHY_STAT0_RX_SENSE
),
3140 HDMI_IH_MUTE_PHY_STAT0
);
3145 static const struct dw_hdmi_phy_data dw_hdmi_phys
[] = {
3147 .type
= DW_HDMI_PHY_DWC_HDMI_TX_PHY
,
3148 .name
= "DWC HDMI TX PHY",
3151 .type
= DW_HDMI_PHY_DWC_MHL_PHY_HEAC
,
3152 .name
= "DWC MHL PHY + HEAC PHY",
3155 .configure
= hdmi_phy_configure_dwc_hdmi_3d_tx
,
3157 .type
= DW_HDMI_PHY_DWC_MHL_PHY
,
3158 .name
= "DWC MHL PHY",
3161 .configure
= hdmi_phy_configure_dwc_hdmi_3d_tx
,
3163 .type
= DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC
,
3164 .name
= "DWC HDMI 3D TX PHY + HEAC PHY",
3166 .configure
= hdmi_phy_configure_dwc_hdmi_3d_tx
,
3168 .type
= DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY
,
3169 .name
= "DWC HDMI 3D TX PHY",
3171 .configure
= hdmi_phy_configure_dwc_hdmi_3d_tx
,
3173 .type
= DW_HDMI_PHY_DWC_HDMI20_TX_PHY
,
3174 .name
= "DWC HDMI 2.0 TX PHY",
3177 .configure
= hdmi_phy_configure_dwc_hdmi_3d_tx
,
3179 .type
= DW_HDMI_PHY_VENDOR_PHY
,
3180 .name
= "Vendor PHY",
3184 static int dw_hdmi_detect_phy(struct dw_hdmi
*hdmi
)
3189 phy_type
= hdmi
->plat_data
->phy_force_vendor
?
3190 DW_HDMI_PHY_VENDOR_PHY
:
3191 hdmi_readb(hdmi
, HDMI_CONFIG2_ID
);
3193 if (phy_type
== DW_HDMI_PHY_VENDOR_PHY
) {
3194 /* Vendor PHYs require support from the glue layer. */
3195 if (!hdmi
->plat_data
->phy_ops
|| !hdmi
->plat_data
->phy_name
) {
3197 "Vendor HDMI PHY not supported by glue layer\n");
3201 hdmi
->phy
.ops
= hdmi
->plat_data
->phy_ops
;
3202 hdmi
->phy
.data
= hdmi
->plat_data
->phy_data
;
3203 hdmi
->phy
.name
= hdmi
->plat_data
->phy_name
;
3207 /* Synopsys PHYs are handled internally. */
3208 for (i
= 0; i
< ARRAY_SIZE(dw_hdmi_phys
); ++i
) {
3209 if (dw_hdmi_phys
[i
].type
== phy_type
) {
3210 hdmi
->phy
.ops
= &dw_hdmi_synopsys_phy_ops
;
3211 hdmi
->phy
.name
= dw_hdmi_phys
[i
].name
;
3212 hdmi
->phy
.data
= (void *)&dw_hdmi_phys
[i
];
3214 if (!dw_hdmi_phys
[i
].configure
&&
3215 !hdmi
->plat_data
->configure_phy
) {
3216 dev_err(hdmi
->dev
, "%s requires platform support\n",
3225 dev_err(hdmi
->dev
, "Unsupported HDMI PHY type (%02x)\n", phy_type
);
3229 static void dw_hdmi_cec_enable(struct dw_hdmi
*hdmi
)
3231 mutex_lock(&hdmi
->mutex
);
3232 hdmi
->mc_clkdis
&= ~HDMI_MC_CLKDIS_CECCLK_DISABLE
;
3233 hdmi_writeb(hdmi
, hdmi
->mc_clkdis
, HDMI_MC_CLKDIS
);
3234 mutex_unlock(&hdmi
->mutex
);
3237 static void dw_hdmi_cec_disable(struct dw_hdmi
*hdmi
)
3239 mutex_lock(&hdmi
->mutex
);
3240 hdmi
->mc_clkdis
|= HDMI_MC_CLKDIS_CECCLK_DISABLE
;
3241 hdmi_writeb(hdmi
, hdmi
->mc_clkdis
, HDMI_MC_CLKDIS
);
3242 mutex_unlock(&hdmi
->mutex
);
3245 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops
= {
3246 .write
= hdmi_writeb
,
3248 .enable
= dw_hdmi_cec_enable
,
3249 .disable
= dw_hdmi_cec_disable
,
3252 static const struct regmap_config hdmi_regmap_8bit_config
= {
3256 .max_register
= HDMI_I2CM_FS_SCL_LCNT_0_ADDR
,
3259 static const struct regmap_config hdmi_regmap_32bit_config
= {
3263 .max_register
= HDMI_I2CM_FS_SCL_LCNT_0_ADDR
<< 2,
3266 static void dw_hdmi_init_hw(struct dw_hdmi
*hdmi
)
3268 initialize_hdmi_ih_mutes(hdmi
);
3271 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
3272 * Even if we are using a separate i2c adapter doing this doesn't
3275 dw_hdmi_i2c_init(hdmi
);
3277 if (hdmi
->phy
.ops
->setup_hpd
)
3278 hdmi
->phy
.ops
->setup_hpd(hdmi
, hdmi
->phy
.data
);
3281 /* -----------------------------------------------------------------------------
3282 * Probe/remove API, used from platforms based on the DRM bridge API.
3285 static int dw_hdmi_parse_dt(struct dw_hdmi
*hdmi
)
3287 struct device_node
*endpoint
;
3288 struct device_node
*remote
;
3290 if (!hdmi
->plat_data
->output_port
)
3293 endpoint
= of_graph_get_endpoint_by_regs(hdmi
->dev
->of_node
,
3294 hdmi
->plat_data
->output_port
,
3298 * On platforms whose bindings don't make the output port
3299 * mandatory (such as Rockchip) the plat_data->output_port
3300 * field isn't set, so it's safe to make this a fatal error.
3302 dev_err(hdmi
->dev
, "Missing endpoint in port@%u\n",
3303 hdmi
->plat_data
->output_port
);
3307 remote
= of_graph_get_remote_port_parent(endpoint
);
3308 of_node_put(endpoint
);
3310 dev_err(hdmi
->dev
, "Endpoint in port@%u unconnected\n",
3311 hdmi
->plat_data
->output_port
);
3315 if (!of_device_is_available(remote
)) {
3316 dev_err(hdmi
->dev
, "port@%u remote device is disabled\n",
3317 hdmi
->plat_data
->output_port
);
3318 of_node_put(remote
);
3322 hdmi
->next_bridge
= of_drm_find_bridge(remote
);
3323 of_node_put(remote
);
3324 if (!hdmi
->next_bridge
)
3325 return -EPROBE_DEFER
;
3330 bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi
*hdmi
)
3332 return hdmi_bus_fmt_is_yuv420(hdmi
->hdmi_data
.enc_out_bus_format
);
3334 EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420
);
3336 struct dw_hdmi
*dw_hdmi_probe(struct platform_device
*pdev
,
3337 const struct dw_hdmi_plat_data
*plat_data
)
3339 struct device
*dev
= &pdev
->dev
;
3340 struct device_node
*np
= dev
->of_node
;
3341 struct platform_device_info pdevinfo
;
3342 struct device_node
*ddc_node
;
3343 struct dw_hdmi_cec_data cec
;
3344 struct dw_hdmi
*hdmi
;
3345 struct resource
*iores
= NULL
;
3354 hdmi
= devm_kzalloc(dev
, sizeof(*hdmi
), GFP_KERNEL
);
3356 return ERR_PTR(-ENOMEM
);
3358 hdmi
->plat_data
= plat_data
;
3360 hdmi
->sample_rate
= 48000;
3362 hdmi
->disabled
= true;
3363 hdmi
->rxsense
= true;
3364 hdmi
->phy_mask
= (u8
)~(HDMI_PHY_HPD
| HDMI_PHY_RX_SENSE
);
3365 hdmi
->mc_clkdis
= 0x7f;
3366 hdmi
->last_connector_result
= connector_status_disconnected
;
3368 mutex_init(&hdmi
->mutex
);
3369 mutex_init(&hdmi
->audio_mutex
);
3370 mutex_init(&hdmi
->cec_notifier_mutex
);
3371 spin_lock_init(&hdmi
->audio_lock
);
3373 ret
= dw_hdmi_parse_dt(hdmi
);
3375 return ERR_PTR(ret
);
3377 ddc_node
= of_parse_phandle(np
, "ddc-i2c-bus", 0);
3379 hdmi
->ddc
= of_get_i2c_adapter_by_node(ddc_node
);
3380 of_node_put(ddc_node
);
3382 dev_dbg(hdmi
->dev
, "failed to read ddc node\n");
3383 return ERR_PTR(-EPROBE_DEFER
);
3387 dev_dbg(hdmi
->dev
, "no ddc property found\n");
3390 if (!plat_data
->regm
) {
3391 const struct regmap_config
*reg_config
;
3393 of_property_read_u32(np
, "reg-io-width", &val
);
3396 reg_config
= &hdmi_regmap_32bit_config
;
3397 hdmi
->reg_shift
= 2;
3400 reg_config
= &hdmi_regmap_8bit_config
;
3403 dev_err(dev
, "reg-io-width must be 1 or 4\n");
3404 return ERR_PTR(-EINVAL
);
3407 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3408 hdmi
->regs
= devm_ioremap_resource(dev
, iores
);
3409 if (IS_ERR(hdmi
->regs
)) {
3410 ret
= PTR_ERR(hdmi
->regs
);
3414 hdmi
->regm
= devm_regmap_init_mmio(dev
, hdmi
->regs
, reg_config
);
3415 if (IS_ERR(hdmi
->regm
)) {
3416 dev_err(dev
, "Failed to configure regmap\n");
3417 ret
= PTR_ERR(hdmi
->regm
);
3421 hdmi
->regm
= plat_data
->regm
;
3424 hdmi
->isfr_clk
= devm_clk_get(hdmi
->dev
, "isfr");
3425 if (IS_ERR(hdmi
->isfr_clk
)) {
3426 ret
= PTR_ERR(hdmi
->isfr_clk
);
3427 dev_err(hdmi
->dev
, "Unable to get HDMI isfr clk: %d\n", ret
);
3431 ret
= clk_prepare_enable(hdmi
->isfr_clk
);
3433 dev_err(hdmi
->dev
, "Cannot enable HDMI isfr clock: %d\n", ret
);
3437 hdmi
->iahb_clk
= devm_clk_get(hdmi
->dev
, "iahb");
3438 if (IS_ERR(hdmi
->iahb_clk
)) {
3439 ret
= PTR_ERR(hdmi
->iahb_clk
);
3440 dev_err(hdmi
->dev
, "Unable to get HDMI iahb clk: %d\n", ret
);
3444 ret
= clk_prepare_enable(hdmi
->iahb_clk
);
3446 dev_err(hdmi
->dev
, "Cannot enable HDMI iahb clock: %d\n", ret
);
3450 hdmi
->cec_clk
= devm_clk_get(hdmi
->dev
, "cec");
3451 if (PTR_ERR(hdmi
->cec_clk
) == -ENOENT
) {
3452 hdmi
->cec_clk
= NULL
;
3453 } else if (IS_ERR(hdmi
->cec_clk
)) {
3454 ret
= PTR_ERR(hdmi
->cec_clk
);
3455 if (ret
!= -EPROBE_DEFER
)
3456 dev_err(hdmi
->dev
, "Cannot get HDMI cec clock: %d\n",
3459 hdmi
->cec_clk
= NULL
;
3462 ret
= clk_prepare_enable(hdmi
->cec_clk
);
3464 dev_err(hdmi
->dev
, "Cannot enable HDMI cec clock: %d\n",
3470 /* Product and revision IDs */
3471 hdmi
->version
= (hdmi_readb(hdmi
, HDMI_DESIGN_ID
) << 8)
3472 | (hdmi_readb(hdmi
, HDMI_REVISION_ID
) << 0);
3473 prod_id0
= hdmi_readb(hdmi
, HDMI_PRODUCT_ID0
);
3474 prod_id1
= hdmi_readb(hdmi
, HDMI_PRODUCT_ID1
);
3476 if (prod_id0
!= HDMI_PRODUCT_ID0_HDMI_TX
||
3477 (prod_id1
& ~HDMI_PRODUCT_ID1_HDCP
) != HDMI_PRODUCT_ID1_HDMI_TX
) {
3478 dev_err(dev
, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
3479 hdmi
->version
, prod_id0
, prod_id1
);
3484 ret
= dw_hdmi_detect_phy(hdmi
);
3488 dev_info(dev
, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3489 hdmi
->version
>> 12, hdmi
->version
& 0xfff,
3490 prod_id1
& HDMI_PRODUCT_ID1_HDCP
? "with" : "without",
3493 dw_hdmi_init_hw(hdmi
);
3495 irq
= platform_get_irq(pdev
, 0);
3501 ret
= devm_request_threaded_irq(dev
, irq
, dw_hdmi_hardirq
,
3502 dw_hdmi_irq
, IRQF_SHARED
,
3503 dev_name(dev
), hdmi
);
3508 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
3509 * N and cts values before enabling phy
3511 hdmi_init_clk_regenerator(hdmi
);
3513 /* If DDC bus is not specified, try to register HDMI I2C bus */
3515 /* Look for (optional) stuff related to unwedging */
3516 hdmi
->pinctrl
= devm_pinctrl_get(dev
);
3517 if (!IS_ERR(hdmi
->pinctrl
)) {
3518 hdmi
->unwedge_state
=
3519 pinctrl_lookup_state(hdmi
->pinctrl
, "unwedge");
3520 hdmi
->default_state
=
3521 pinctrl_lookup_state(hdmi
->pinctrl
, "default");
3523 if (IS_ERR(hdmi
->default_state
) ||
3524 IS_ERR(hdmi
->unwedge_state
)) {
3525 if (!IS_ERR(hdmi
->unwedge_state
))
3527 "Unwedge requires default pinctrl\n");
3528 hdmi
->default_state
= NULL
;
3529 hdmi
->unwedge_state
= NULL
;
3533 hdmi
->ddc
= dw_hdmi_i2c_adapter(hdmi
);
3534 if (IS_ERR(hdmi
->ddc
))
3538 hdmi
->bridge
.driver_private
= hdmi
;
3539 hdmi
->bridge
.funcs
= &dw_hdmi_bridge_funcs
;
3540 hdmi
->bridge
.ops
= DRM_BRIDGE_OP_DETECT
| DRM_BRIDGE_OP_EDID
3541 | DRM_BRIDGE_OP_HPD
;
3542 hdmi
->bridge
.interlace_allowed
= true;
3543 hdmi
->bridge
.ddc
= hdmi
->ddc
;
3544 hdmi
->bridge
.of_node
= pdev
->dev
.of_node
;
3546 memset(&pdevinfo
, 0, sizeof(pdevinfo
));
3547 pdevinfo
.parent
= dev
;
3548 pdevinfo
.id
= PLATFORM_DEVID_AUTO
;
3550 config0
= hdmi_readb(hdmi
, HDMI_CONFIG0_ID
);
3551 config3
= hdmi_readb(hdmi
, HDMI_CONFIG3_ID
);
3553 if (iores
&& config3
& HDMI_CONFIG3_AHBAUDDMA
) {
3554 struct dw_hdmi_audio_data audio
;
3556 audio
.phys
= iores
->start
;
3557 audio
.base
= hdmi
->regs
;
3560 audio
.get_eld
= hdmi_audio_get_eld
;
3561 hdmi
->enable_audio
= dw_hdmi_ahb_audio_enable
;
3562 hdmi
->disable_audio
= dw_hdmi_ahb_audio_disable
;
3564 pdevinfo
.name
= "dw-hdmi-ahb-audio";
3565 pdevinfo
.data
= &audio
;
3566 pdevinfo
.size_data
= sizeof(audio
);
3567 pdevinfo
.dma_mask
= DMA_BIT_MASK(32);
3568 hdmi
->audio
= platform_device_register_full(&pdevinfo
);
3569 } else if (config0
& HDMI_CONFIG0_I2S
) {
3570 struct dw_hdmi_i2s_audio_data audio
;
3573 audio
.get_eld
= hdmi_audio_get_eld
;
3574 audio
.write
= hdmi_writeb
;
3575 audio
.read
= hdmi_readb
;
3576 hdmi
->enable_audio
= dw_hdmi_i2s_audio_enable
;
3577 hdmi
->disable_audio
= dw_hdmi_i2s_audio_disable
;
3579 pdevinfo
.name
= "dw-hdmi-i2s-audio";
3580 pdevinfo
.data
= &audio
;
3581 pdevinfo
.size_data
= sizeof(audio
);
3582 pdevinfo
.dma_mask
= DMA_BIT_MASK(32);
3583 hdmi
->audio
= platform_device_register_full(&pdevinfo
);
3584 } else if (iores
&& config3
& HDMI_CONFIG3_GPAUD
) {
3585 struct dw_hdmi_audio_data audio
;
3587 audio
.phys
= iores
->start
;
3588 audio
.base
= hdmi
->regs
;
3591 audio
.get_eld
= hdmi_audio_get_eld
;
3593 hdmi
->enable_audio
= dw_hdmi_gp_audio_enable
;
3594 hdmi
->disable_audio
= dw_hdmi_gp_audio_disable
;
3596 pdevinfo
.name
= "dw-hdmi-gp-audio";
3597 pdevinfo
.id
= PLATFORM_DEVID_NONE
;
3598 pdevinfo
.data
= &audio
;
3599 pdevinfo
.size_data
= sizeof(audio
);
3600 pdevinfo
.dma_mask
= DMA_BIT_MASK(32);
3601 hdmi
->audio
= platform_device_register_full(&pdevinfo
);
3604 if (!plat_data
->disable_cec
&& (config0
& HDMI_CONFIG0_CEC
)) {
3606 cec
.ops
= &dw_hdmi_cec_ops
;
3609 pdevinfo
.name
= "dw-hdmi-cec";
3610 pdevinfo
.data
= &cec
;
3611 pdevinfo
.size_data
= sizeof(cec
);
3612 pdevinfo
.dma_mask
= 0;
3614 hdmi
->cec
= platform_device_register_full(&pdevinfo
);
3617 drm_bridge_add(&hdmi
->bridge
);
3622 clk_disable_unprepare(hdmi
->iahb_clk
);
3623 clk_disable_unprepare(hdmi
->cec_clk
);
3625 clk_disable_unprepare(hdmi
->isfr_clk
);
3627 i2c_put_adapter(hdmi
->ddc
);
3629 return ERR_PTR(ret
);
3631 EXPORT_SYMBOL_GPL(dw_hdmi_probe
);
3633 void dw_hdmi_remove(struct dw_hdmi
*hdmi
)
3635 drm_bridge_remove(&hdmi
->bridge
);
3637 if (hdmi
->audio
&& !IS_ERR(hdmi
->audio
))
3638 platform_device_unregister(hdmi
->audio
);
3639 if (!IS_ERR(hdmi
->cec
))
3640 platform_device_unregister(hdmi
->cec
);
3642 /* Disable all interrupts */
3643 hdmi_writeb(hdmi
, ~0, HDMI_IH_MUTE_PHY_STAT0
);
3645 clk_disable_unprepare(hdmi
->iahb_clk
);
3646 clk_disable_unprepare(hdmi
->isfr_clk
);
3647 clk_disable_unprepare(hdmi
->cec_clk
);
3650 i2c_del_adapter(&hdmi
->i2c
->adap
);
3652 i2c_put_adapter(hdmi
->ddc
);
3654 EXPORT_SYMBOL_GPL(dw_hdmi_remove
);
3656 /* -----------------------------------------------------------------------------
3657 * Bind/unbind API, used from platforms based on the component framework.
3659 struct dw_hdmi
*dw_hdmi_bind(struct platform_device
*pdev
,
3660 struct drm_encoder
*encoder
,
3661 const struct dw_hdmi_plat_data
*plat_data
)
3663 struct dw_hdmi
*hdmi
;
3666 hdmi
= dw_hdmi_probe(pdev
, plat_data
);
3670 ret
= drm_bridge_attach(encoder
, &hdmi
->bridge
, NULL
, 0);
3672 dw_hdmi_remove(hdmi
);
3673 return ERR_PTR(ret
);
3678 EXPORT_SYMBOL_GPL(dw_hdmi_bind
);
3680 void dw_hdmi_unbind(struct dw_hdmi
*hdmi
)
3682 dw_hdmi_remove(hdmi
);
3684 EXPORT_SYMBOL_GPL(dw_hdmi_unbind
);
3686 void dw_hdmi_resume(struct dw_hdmi
*hdmi
)
3688 dw_hdmi_init_hw(hdmi
);
3690 EXPORT_SYMBOL_GPL(dw_hdmi_resume
);
3692 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3693 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3694 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3695 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
3696 MODULE_DESCRIPTION("DW HDMI transmitter driver");
3697 MODULE_LICENSE("GPL");
3698 MODULE_ALIAS("platform:dw-hdmi");