drivers/gpu/drm/cirrus/cirrus_mode.c

   1
   2 /*
   3  * Copyright 2012 Red Hat
   4  *
   5  * This file is subject to the terms and conditions of the GNU General
   6  * Public License version 2. See the file COPYING in the main
   7  * directory of this archive for more details.
   8  *
   9  * Authors: Matthew Garrett
  10  *          Dave Airlie
  11  *
  12  * Portions of this code derived from cirrusfb.c:
  13  * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
  14  *
  15  * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
  16  */
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20 #include <drm/drm_probe_helper.h>
  21
  22 #include <video/cirrus.h>
  23
  24 #include "cirrus_drv.h"
  25
  26 #define CIRRUS_LUT_SIZE 256
  27
  28 #define PALETTE_INDEX 0x8
  29 #define PALETTE_DATA 0x9
  30
  31 /*
  32  * This file contains setup code for the CRTC.
  33  */
  34
  35 /*
  36  * The DRM core requires DPMS functions, but they make little sense in our
  37  * case and so are just stubs
  38  */
  39
  40 static void cirrus_crtc_dpms(struct drm_crtc *crtc, int mode)
  41 {
  42         struct drm_device *dev = crtc->dev;
  43         struct cirrus_device *cdev = dev->dev_private;
  44         u8 sr01, gr0e;
  45
  46         switch (mode) {
  47         case DRM_MODE_DPMS_ON:
  48                 sr01 = 0x00;
  49                 gr0e = 0x00;
  50                 break;
  51         case DRM_MODE_DPMS_STANDBY:
  52                 sr01 = 0x20;
  53                 gr0e = 0x02;
  54                 break;
  55         case DRM_MODE_DPMS_SUSPEND:
  56                 sr01 = 0x20;
  57                 gr0e = 0x04;
  58                 break;
  59         case DRM_MODE_DPMS_OFF:
  60                 sr01 = 0x20;
  61                 gr0e = 0x06;
  62                 break;
  63         default:
  64                 return;
  65         }
  66
  67         WREG8(SEQ_INDEX, 0x1);
  68         sr01 |= RREG8(SEQ_DATA) & ~0x20;
  69         WREG_SEQ(0x1, sr01);
  70
  71         WREG8(GFX_INDEX, 0xe);
  72         gr0e |= RREG8(GFX_DATA) & ~0x06;
  73         WREG_GFX(0xe, gr0e);
  74 }
  75
  76 static void cirrus_set_start_address(struct drm_crtc *crtc, unsigned offset)
  77 {
  78         struct cirrus_device *cdev = crtc->dev->dev_private;
  79         u32 addr;
  80         u8 tmp;
  81
  82         addr = offset >> 2;
  83         WREG_CRT(0x0c, (u8)((addr >> 8) & 0xff));
  84         WREG_CRT(0x0d, (u8)(addr & 0xff));
  85
  86         WREG8(CRT_INDEX, 0x1b);
  87         tmp = RREG8(CRT_DATA);
  88         tmp &= 0xf2;
  89         tmp |= (addr >> 16) & 0x01;
  90         tmp |= (addr >> 15) & 0x0c;
  91         WREG_CRT(0x1b, tmp);
  92         WREG8(CRT_INDEX, 0x1d);
  93         tmp = RREG8(CRT_DATA);
  94         tmp &= 0x7f;
  95         tmp |= (addr >> 12) & 0x80;
  96         WREG_CRT(0x1d, tmp);
  97 }
  98
  99 /* cirrus is different - we will force move buffers out of VRAM */
 100 static int cirrus_crtc_do_set_base(struct drm_crtc *crtc,
 101                                 struct drm_framebuffer *fb,
 102                                 int x, int y, int atomic)
 103 {
 104         struct cirrus_device *cdev = crtc->dev->dev_private;
 105         struct cirrus_bo *bo;
 106         int ret;
 107         u64 gpu_addr;
 108
 109         /* push the previous fb to system ram */
 110         if (!atomic && fb) {
 111                 bo = gem_to_cirrus_bo(fb->obj[0]);
 112                 ret = cirrus_bo_reserve(bo, false);
 113                 if (ret)
 114                         return ret;
 115                 cirrus_bo_push_sysram(bo);
 116                 cirrus_bo_unreserve(bo);
 117         }
 118
 119         bo = gem_to_cirrus_bo(crtc->primary->fb->obj[0]);
 120
 121         ret = cirrus_bo_reserve(bo, false);
 122         if (ret)
 123                 return ret;
 124
 125         ret = cirrus_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
 126         if (ret) {
 127                 cirrus_bo_unreserve(bo);
 128                 return ret;
 129         }
 130
 131         if (cdev->mode_info.gfbdev->gfb == crtc->primary->fb) {
 132                 /* if pushing console in kmap it */
 133                 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
 134                 if (ret)
 135                         DRM_ERROR("failed to kmap fbcon\n");
 136         }
 137         cirrus_bo_unreserve(bo);
 138
 139         cirrus_set_start_address(crtc, (u32)gpu_addr);
 140         return 0;
 141 }
 142
 143 static int cirrus_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 144                              struct drm_framebuffer *old_fb)
 145 {
 146         return cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
 147 }
 148
 149 /*
 150  * The meat of this driver. The core passes us a mode and we have to program
 151  * it. The modesetting here is the bare minimum required to satisfy the qemu
 152  * emulation of this hardware, and running this against a real device is
 153  * likely to result in an inadequately programmed mode. We've already had
 154  * the opportunity to modify the mode, so whatever we receive here should
 155  * be something that can be correctly programmed and displayed
 156  */
 157 static int cirrus_crtc_mode_set(struct drm_crtc *crtc,
 158                                 struct drm_display_mode *mode,
 159                                 struct drm_display_mode *adjusted_mode,
 160                                 int x, int y, struct drm_framebuffer *old_fb)
 161 {
 162         struct drm_device *dev = crtc->dev;
 163         struct cirrus_device *cdev = dev->dev_private;
 164         const struct drm_framebuffer *fb = crtc->primary->fb;
 165         int hsyncstart, hsyncend, htotal, hdispend;
 166         int vtotal, vdispend;
 167         int tmp;
 168         int sr07 = 0, hdr = 0;
 169
 170         htotal = mode->htotal / 8;
 171         hsyncend = mode->hsync_end / 8;
 172         hsyncstart = mode->hsync_start / 8;
 173         hdispend = mode->hdisplay / 8;
 174
 175         vtotal = mode->vtotal;
 176         vdispend = mode->vdisplay;
 177
 178         vdispend -= 1;
 179         vtotal -= 2;
 180
 181         htotal -= 5;
 182         hdispend -= 1;
 183         hsyncstart += 1;
 184         hsyncend += 1;
 185
 186         WREG_CRT(VGA_CRTC_V_SYNC_END, 0x20);
 187         WREG_CRT(VGA_CRTC_H_TOTAL, htotal);
 188         WREG_CRT(VGA_CRTC_H_DISP, hdispend);
 189         WREG_CRT(VGA_CRTC_H_SYNC_START, hsyncstart);
 190         WREG_CRT(VGA_CRTC_H_SYNC_END, hsyncend);
 191         WREG_CRT(VGA_CRTC_V_TOTAL, vtotal & 0xff);
 192         WREG_CRT(VGA_CRTC_V_DISP_END, vdispend & 0xff);
 193
 194         tmp = 0x40;
 195         if ((vdispend + 1) & 512)
 196                 tmp |= 0x20;
 197         WREG_CRT(VGA_CRTC_MAX_SCAN, tmp);
 198
 199         /*
 200          * Overflow bits for values that don't fit in the standard registers
 201          */
 202         tmp = 16;
 203         if (vtotal & 256)
 204                 tmp |= 1;
 205         if (vdispend & 256)
 206                 tmp |= 2;
 207         if ((vdispend + 1) & 256)
 208                 tmp |= 8;
 209         if (vtotal & 512)
 210                 tmp |= 32;
 211         if (vdispend & 512)
 212                 tmp |= 64;
 213         WREG_CRT(VGA_CRTC_OVERFLOW, tmp);
 214
 215         tmp = 0;
 216
 217         /* More overflow bits */
 218
 219         if ((htotal + 5) & 64)
 220                 tmp |= 16;
 221         if ((htotal + 5) & 128)
 222                 tmp |= 32;
 223         if (vtotal & 256)
 224                 tmp |= 64;
 225         if (vtotal & 512)
 226                 tmp |= 128;
 227
 228         WREG_CRT(CL_CRT1A, tmp);
 229
 230         /* Disable Hercules/CGA compatibility */
 231         WREG_CRT(VGA_CRTC_MODE, 0x03);
 232
 233         WREG8(SEQ_INDEX, 0x7);
 234         sr07 = RREG8(SEQ_DATA);
 235         sr07 &= 0xe0;
 236         hdr = 0;
 237         switch (fb->format->cpp[0] * 8) {
 238         case 8:
 239                 sr07 |= 0x11;
 240                 break;
 241         case 16:
 242                 sr07 |= 0x17;
 243                 hdr = 0xc1;
 244                 break;
 245         case 24:
 246                 sr07 |= 0x15;
 247                 hdr = 0xc5;
 248                 break;
 249         case 32:
 250                 sr07 |= 0x19;
 251                 hdr = 0xc5;
 252                 break;
 253         default:
 254                 return -1;
 255         }
 256
 257         WREG_SEQ(0x7, sr07);
 258
 259         /* Program the pitch */
 260         tmp = fb->pitches[0] / 8;
 261         WREG_CRT(VGA_CRTC_OFFSET, tmp);
 262
 263         /* Enable extended blanking and pitch bits, and enable full memory */
 264         tmp = 0x22;
 265         tmp |= (fb->pitches[0] >> 7) & 0x10;
 266         tmp |= (fb->pitches[0] >> 6) & 0x40;
 267         WREG_CRT(0x1b, tmp);
 268
 269         /* Enable high-colour modes */
 270         WREG_GFX(VGA_GFX_MODE, 0x40);
 271
 272         /* And set graphics mode */
 273         WREG_GFX(VGA_GFX_MISC, 0x01);
 274
 275         WREG_HDR(hdr);
 276         cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
 277
 278         /* Unblank (needed on S3 resume, vgabios doesn't do it then) */
 279         outb(0x20, 0x3c0);
 280         return 0;
 281 }
 282
 283 /*
 284  * This is called before a mode is programmed. A typical use might be to
 285  * enable DPMS during the programming to avoid seeing intermediate stages,
 286  * but that's not relevant to us
 287  */
 288 static void cirrus_crtc_prepare(struct drm_crtc *crtc)
 289 {
 290 }
 291
 292 static void cirrus_crtc_load_lut(struct drm_crtc *crtc)
 293 {
 294         struct drm_device *dev = crtc->dev;
 295         struct cirrus_device *cdev = dev->dev_private;
 296         u16 *r, *g, *b;
 297         int i;
 298
 299         if (!crtc->enabled)
 300                 return;
 301
 302         r = crtc->gamma_store;
 303         g = r + crtc->gamma_size;
 304         b = g + crtc->gamma_size;
 305
 306         for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
 307                 /* VGA registers */
 308                 WREG8(PALETTE_INDEX, i);
 309                 WREG8(PALETTE_DATA, *r++ >> 8);
 310                 WREG8(PALETTE_DATA, *g++ >> 8);
 311                 WREG8(PALETTE_DATA, *b++ >> 8);
 312         }
 313 }
 314
 315 /*
 316  * This is called after a mode is programmed. It should reverse anything done
 317  * by the prepare function
 318  */
 319 static void cirrus_crtc_commit(struct drm_crtc *crtc)
 320 {
 321         cirrus_crtc_load_lut(crtc);
 322 }
 323
 324 /*
 325  * The core can pass us a set of gamma values to program. We actually only
 326  * use this for 8-bit mode so can't perform smooth fades on deeper modes,
 327  * but it's a requirement that we provide the function
 328  */
 329 static int cirrus_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 330                                  u16 *blue, uint32_t size,
 331                                  struct drm_modeset_acquire_ctx *ctx)
 332 {
 333         cirrus_crtc_load_lut(crtc);
 334
 335         return 0;
 336 }
 337
 338 /* Simple cleanup function */
 339 static void cirrus_crtc_destroy(struct drm_crtc *crtc)
 340 {
 341         struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
 342
 343         drm_crtc_cleanup(crtc);
 344         kfree(cirrus_crtc);
 345 }
 346
 347 /* These provide the minimum set of functions required to handle a CRTC */
 348 static const struct drm_crtc_funcs cirrus_crtc_funcs = {
 349         .gamma_set = cirrus_crtc_gamma_set,
 350         .set_config = drm_crtc_helper_set_config,
 351         .destroy = cirrus_crtc_destroy,
 352 };
 353
 354 static const struct drm_crtc_helper_funcs cirrus_helper_funcs = {
 355         .dpms = cirrus_crtc_dpms,
 356         .mode_set = cirrus_crtc_mode_set,
 357         .mode_set_base = cirrus_crtc_mode_set_base,
 358         .prepare = cirrus_crtc_prepare,
 359         .commit = cirrus_crtc_commit,
 360 };
 361
 362 /* CRTC setup */
 363 static void cirrus_crtc_init(struct drm_device *dev)
 364 {
 365         struct cirrus_device *cdev = dev->dev_private;
 366         struct cirrus_crtc *cirrus_crtc;
 367
 368         cirrus_crtc = kzalloc(sizeof(struct cirrus_crtc) +
 369                               (CIRRUSFB_CONN_LIMIT * sizeof(struct drm_connector *)),
 370                               GFP_KERNEL);
 371
 372         if (cirrus_crtc == NULL)
 373                 return;
 374
 375         drm_crtc_init(dev, &cirrus_crtc->base, &cirrus_crtc_funcs);
 376
 377         drm_mode_crtc_set_gamma_size(&cirrus_crtc->base, CIRRUS_LUT_SIZE);
 378         cdev->mode_info.crtc = cirrus_crtc;
 379
 380         drm_crtc_helper_add(&cirrus_crtc->base, &cirrus_helper_funcs);
 381 }
 382
 383 static void cirrus_encoder_mode_set(struct drm_encoder *encoder,
 384                                 struct drm_display_mode *mode,
 385                                 struct drm_display_mode *adjusted_mode)
 386 {
 387 }
 388
 389 static void cirrus_encoder_dpms(struct drm_encoder *encoder, int state)
 390 {
 391         return;
 392 }
 393
 394 static void cirrus_encoder_prepare(struct drm_encoder *encoder)
 395 {
 396 }
 397
 398 static void cirrus_encoder_commit(struct drm_encoder *encoder)
 399 {
 400 }
 401
 402 static void cirrus_encoder_destroy(struct drm_encoder *encoder)
 403 {
 404         struct cirrus_encoder *cirrus_encoder = to_cirrus_encoder(encoder);
 405         drm_encoder_cleanup(encoder);
 406         kfree(cirrus_encoder);
 407 }
 408
 409 static const struct drm_encoder_helper_funcs cirrus_encoder_helper_funcs = {
 410         .dpms = cirrus_encoder_dpms,
 411         .mode_set = cirrus_encoder_mode_set,
 412         .prepare = cirrus_encoder_prepare,
 413         .commit = cirrus_encoder_commit,
 414 };
 415
 416 static const struct drm_encoder_funcs cirrus_encoder_encoder_funcs = {
 417         .destroy = cirrus_encoder_destroy,
 418 };
 419
 420 static struct drm_encoder *cirrus_encoder_init(struct drm_device *dev)
 421 {
 422         struct drm_encoder *encoder;
 423         struct cirrus_encoder *cirrus_encoder;
 424
 425         cirrus_encoder = kzalloc(sizeof(struct cirrus_encoder), GFP_KERNEL);
 426         if (!cirrus_encoder)
 427                 return NULL;
 428
 429         encoder = &cirrus_encoder->base;
 430         encoder->possible_crtcs = 0x1;
 431
 432         drm_encoder_init(dev, encoder, &cirrus_encoder_encoder_funcs,
 433                          DRM_MODE_ENCODER_DAC, NULL);
 434         drm_encoder_helper_add(encoder, &cirrus_encoder_helper_funcs);
 435
 436         return encoder;
 437 }
 438
 439
 440 static int cirrus_vga_get_modes(struct drm_connector *connector)
 441 {
 442         int count;
 443
 444         /* Just add a static list of modes */
 445         if (cirrus_bpp <= 24) {
 446                 count = drm_add_modes_noedid(connector, 1280, 1024);
 447                 drm_set_preferred_mode(connector, 1024, 768);
 448         } else {
 449                 count = drm_add_modes_noedid(connector, 800, 600);
 450                 drm_set_preferred_mode(connector, 800, 600);
 451         }
 452         return count;
 453 }
 454
 455 static struct drm_encoder *cirrus_connector_best_encoder(struct drm_connector
 456                                                   *connector)
 457 {
 458         int enc_id = connector->encoder_ids[0];
 459         /* pick the encoder ids */
 460         if (enc_id)
 461                 return drm_encoder_find(connector->dev, NULL, enc_id);
 462         return NULL;
 463 }
 464
 465 static void cirrus_connector_destroy(struct drm_connector *connector)
 466 {
 467         drm_connector_cleanup(connector);
 468         kfree(connector);
 469 }
 470
 471 static const struct drm_connector_helper_funcs cirrus_vga_connector_helper_funcs = {
 472         .get_modes = cirrus_vga_get_modes,
 473         .best_encoder = cirrus_connector_best_encoder,
 474 };
 475
 476 static const struct drm_connector_funcs cirrus_vga_connector_funcs = {
 477         .dpms = drm_helper_connector_dpms,
 478         .fill_modes = drm_helper_probe_single_connector_modes,
 479         .destroy = cirrus_connector_destroy,
 480 };
 481
 482 static struct drm_connector *cirrus_vga_init(struct drm_device *dev)
 483 {
 484         struct drm_connector *connector;
 485         struct cirrus_connector *cirrus_connector;
 486
 487         cirrus_connector = kzalloc(sizeof(struct cirrus_connector), GFP_KERNEL);
 488         if (!cirrus_connector)
 489                 return NULL;
 490
 491         connector = &cirrus_connector->base;
 492
 493         drm_connector_init(dev, connector,
 494                            &cirrus_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 495
 496         drm_connector_helper_add(connector, &cirrus_vga_connector_helper_funcs);
 497
 498         drm_connector_register(connector);
 499         return connector;
 500 }
 501
 502
 503 int cirrus_modeset_init(struct cirrus_device *cdev)
 504 {
 505         struct drm_encoder *encoder;
 506         struct drm_connector *connector;
 507         int ret;
 508
 509         drm_mode_config_init(cdev->dev);
 510         cdev->mode_info.mode_config_initialized = true;
 511
 512         cdev->dev->mode_config.max_width = CIRRUS_MAX_FB_WIDTH;
 513         cdev->dev->mode_config.max_height = CIRRUS_MAX_FB_HEIGHT;
 514
 515         cdev->dev->mode_config.fb_base = cdev->mc.vram_base;
 516         cdev->dev->mode_config.preferred_depth = cirrus_bpp;
 517         /* don't prefer a shadow on virt GPU */
 518         cdev->dev->mode_config.prefer_shadow = 0;
 519
 520         cirrus_crtc_init(cdev->dev);
 521
 522         encoder = cirrus_encoder_init(cdev->dev);
 523         if (!encoder) {
 524                 DRM_ERROR("cirrus_encoder_init failed\n");
 525                 return -1;
 526         }
 527
 528         connector = cirrus_vga_init(cdev->dev);
 529         if (!connector) {
 530                 DRM_ERROR("cirrus_vga_init failed\n");
 531                 return -1;
 532         }
 533
 534         drm_connector_attach_encoder(connector, encoder);
 535
 536         ret = cirrus_fbdev_init(cdev);
 537         if (ret) {
 538                 DRM_ERROR("cirrus_fbdev_init failed\n");
 539                 return ret;
 540         }
 541
 542         return 0;
 543 }
 544
 545 void cirrus_modeset_fini(struct cirrus_device *cdev)
 546 {
 547         cirrus_fbdev_fini(cdev);
 548
 549         if (cdev->mode_info.mode_config_initialized) {
 550                 drm_mode_config_cleanup(cdev->dev);
 551                 cdev->mode_info.mode_config_initialized = false;
 552         }
 553 }