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Merge tag 'tegra-for-5.2-arm64-soc-fixes' of git://git.kernel.org/pub/scm/linux/kerne...
[thirdparty/linux.git] / drivers / gpu / drm / drm_edid.c
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
36 #include <drm/drmP.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
41
42 #include "drm_crtc_internal.h"
43
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
47
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
51
52 /*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* use +hsync +vsync for detailed mode */
72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
73 /* Force reduced-blanking timings for detailed modes */
74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
75 /* Force 8bpc */
76 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
77 /* Force 12bpc */
78 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
79 /* Force 6bpc */
80 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
81 /* Force 10bpc */
82 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
83 /* Non desktop display (i.e. HMD) */
84 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
85
86 struct detailed_mode_closure {
87 struct drm_connector *connector;
88 struct edid *edid;
89 bool preferred;
90 u32 quirks;
91 int modes;
92 };
93
94 #define LEVEL_DMT 0
95 #define LEVEL_GTF 1
96 #define LEVEL_GTF2 2
97 #define LEVEL_CVT 3
98
99 static const struct edid_quirk {
100 char vendor[4];
101 int product_id;
102 u32 quirks;
103 } edid_quirk_list[] = {
104 /* Acer AL1706 */
105 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
106 /* Acer F51 */
107 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
108
109 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
110 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
111
112 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
113 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
114
115 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
116 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
117
118 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
119 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
120
121 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
122 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
123
124 /* Belinea 10 15 55 */
125 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
126 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
127
128 /* Envision Peripherals, Inc. EN-7100e */
129 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
130 /* Envision EN2028 */
131 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
132
133 /* Funai Electronics PM36B */
134 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
135 EDID_QUIRK_DETAILED_IN_CM },
136
137 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
138 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
139
140 /* LG Philips LCD LP154W01-A5 */
141 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
142 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
143
144 /* Samsung SyncMaster 205BW. Note: irony */
145 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
146 /* Samsung SyncMaster 22[5-6]BW */
147 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
148 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
149
150 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
151 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
152
153 /* ViewSonic VA2026w */
154 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
155
156 /* Medion MD 30217 PG */
157 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
158
159 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
160 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
161
162 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
163 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
164
165 /* Valve Index Headset */
166 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
167 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
168 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
169 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
170 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
171 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
172 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
183
184 /* HTC Vive and Vive Pro VR Headsets */
185 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
186 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
187
188 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
189 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
190 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
191 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
192
193 /* Windows Mixed Reality Headsets */
194 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
195 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
196 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
197 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
198 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
199 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
200 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
201 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
202
203 /* Sony PlayStation VR Headset */
204 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
205
206 /* Sensics VR Headsets */
207 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
208
209 /* OSVR HDK and HDK2 VR Headsets */
210 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
211 };
212
213 /*
214 * Autogenerated from the DMT spec.
215 * This table is copied from xfree86/modes/xf86EdidModes.c.
216 */
217 static const struct drm_display_mode drm_dmt_modes[] = {
218 /* 0x01 - 640x350@85Hz */
219 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
220 736, 832, 0, 350, 382, 385, 445, 0,
221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
222 /* 0x02 - 640x400@85Hz */
223 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
224 736, 832, 0, 400, 401, 404, 445, 0,
225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
226 /* 0x03 - 720x400@85Hz */
227 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
228 828, 936, 0, 400, 401, 404, 446, 0,
229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
230 /* 0x04 - 640x480@60Hz */
231 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
232 752, 800, 0, 480, 490, 492, 525, 0,
233 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
234 /* 0x05 - 640x480@72Hz */
235 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
236 704, 832, 0, 480, 489, 492, 520, 0,
237 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
238 /* 0x06 - 640x480@75Hz */
239 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
240 720, 840, 0, 480, 481, 484, 500, 0,
241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
242 /* 0x07 - 640x480@85Hz */
243 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
244 752, 832, 0, 480, 481, 484, 509, 0,
245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
246 /* 0x08 - 800x600@56Hz */
247 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
248 896, 1024, 0, 600, 601, 603, 625, 0,
249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 0x09 - 800x600@60Hz */
251 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
252 968, 1056, 0, 600, 601, 605, 628, 0,
253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
254 /* 0x0a - 800x600@72Hz */
255 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
256 976, 1040, 0, 600, 637, 643, 666, 0,
257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
258 /* 0x0b - 800x600@75Hz */
259 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
260 896, 1056, 0, 600, 601, 604, 625, 0,
261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
262 /* 0x0c - 800x600@85Hz */
263 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
264 896, 1048, 0, 600, 601, 604, 631, 0,
265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
266 /* 0x0d - 800x600@120Hz RB */
267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
268 880, 960, 0, 600, 603, 607, 636, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
270 /* 0x0e - 848x480@60Hz */
271 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
272 976, 1088, 0, 480, 486, 494, 517, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
274 /* 0x0f - 1024x768@43Hz, interlace */
275 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
276 1208, 1264, 0, 768, 768, 776, 817, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
278 DRM_MODE_FLAG_INTERLACE) },
279 /* 0x10 - 1024x768@60Hz */
280 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
281 1184, 1344, 0, 768, 771, 777, 806, 0,
282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
283 /* 0x11 - 1024x768@70Hz */
284 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
285 1184, 1328, 0, 768, 771, 777, 806, 0,
286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
287 /* 0x12 - 1024x768@75Hz */
288 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
289 1136, 1312, 0, 768, 769, 772, 800, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
291 /* 0x13 - 1024x768@85Hz */
292 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
293 1168, 1376, 0, 768, 769, 772, 808, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
295 /* 0x14 - 1024x768@120Hz RB */
296 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
297 1104, 1184, 0, 768, 771, 775, 813, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
299 /* 0x15 - 1152x864@75Hz */
300 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
301 1344, 1600, 0, 864, 865, 868, 900, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x55 - 1280x720@60Hz */
304 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
305 1430, 1650, 0, 720, 725, 730, 750, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
307 /* 0x16 - 1280x768@60Hz RB */
308 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
309 1360, 1440, 0, 768, 771, 778, 790, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
311 /* 0x17 - 1280x768@60Hz */
312 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
313 1472, 1664, 0, 768, 771, 778, 798, 0,
314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x18 - 1280x768@75Hz */
316 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
317 1488, 1696, 0, 768, 771, 778, 805, 0,
318 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
319 /* 0x19 - 1280x768@85Hz */
320 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
321 1496, 1712, 0, 768, 771, 778, 809, 0,
322 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
323 /* 0x1a - 1280x768@120Hz RB */
324 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
325 1360, 1440, 0, 768, 771, 778, 813, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
327 /* 0x1b - 1280x800@60Hz RB */
328 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
329 1360, 1440, 0, 800, 803, 809, 823, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
331 /* 0x1c - 1280x800@60Hz */
332 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
333 1480, 1680, 0, 800, 803, 809, 831, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x1d - 1280x800@75Hz */
336 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
337 1488, 1696, 0, 800, 803, 809, 838, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
339 /* 0x1e - 1280x800@85Hz */
340 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
341 1496, 1712, 0, 800, 803, 809, 843, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x1f - 1280x800@120Hz RB */
344 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
345 1360, 1440, 0, 800, 803, 809, 847, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
347 /* 0x20 - 1280x960@60Hz */
348 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
349 1488, 1800, 0, 960, 961, 964, 1000, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
351 /* 0x21 - 1280x960@85Hz */
352 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
353 1504, 1728, 0, 960, 961, 964, 1011, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
355 /* 0x22 - 1280x960@120Hz RB */
356 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
357 1360, 1440, 0, 960, 963, 967, 1017, 0,
358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
359 /* 0x23 - 1280x1024@60Hz */
360 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
361 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x24 - 1280x1024@75Hz */
364 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
365 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x25 - 1280x1024@85Hz */
368 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
369 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x26 - 1280x1024@120Hz RB */
372 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
373 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
375 /* 0x27 - 1360x768@60Hz */
376 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
377 1536, 1792, 0, 768, 771, 777, 795, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
379 /* 0x28 - 1360x768@120Hz RB */
380 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
381 1440, 1520, 0, 768, 771, 776, 813, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
383 /* 0x51 - 1366x768@60Hz */
384 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
385 1579, 1792, 0, 768, 771, 774, 798, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x56 - 1366x768@60Hz */
388 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
389 1436, 1500, 0, 768, 769, 772, 800, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x29 - 1400x1050@60Hz RB */
392 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
393 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
395 /* 0x2a - 1400x1050@60Hz */
396 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
397 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
398 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
399 /* 0x2b - 1400x1050@75Hz */
400 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
401 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
402 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
403 /* 0x2c - 1400x1050@85Hz */
404 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
405 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x2d - 1400x1050@120Hz RB */
408 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
409 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
411 /* 0x2e - 1440x900@60Hz RB */
412 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
413 1520, 1600, 0, 900, 903, 909, 926, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
415 /* 0x2f - 1440x900@60Hz */
416 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
417 1672, 1904, 0, 900, 903, 909, 934, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x30 - 1440x900@75Hz */
420 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
421 1688, 1936, 0, 900, 903, 909, 942, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
423 /* 0x31 - 1440x900@85Hz */
424 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
425 1696, 1952, 0, 900, 903, 909, 948, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x32 - 1440x900@120Hz RB */
428 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
429 1520, 1600, 0, 900, 903, 909, 953, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
431 /* 0x53 - 1600x900@60Hz */
432 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
433 1704, 1800, 0, 900, 901, 904, 1000, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
435 /* 0x33 - 1600x1200@60Hz */
436 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
437 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 0x34 - 1600x1200@65Hz */
440 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
441 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 0x35 - 1600x1200@70Hz */
444 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
445 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
447 /* 0x36 - 1600x1200@75Hz */
448 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
449 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
451 /* 0x37 - 1600x1200@85Hz */
452 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
453 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
455 /* 0x38 - 1600x1200@120Hz RB */
456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
457 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
459 /* 0x39 - 1680x1050@60Hz RB */
460 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
461 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
463 /* 0x3a - 1680x1050@60Hz */
464 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
465 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
466 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x3b - 1680x1050@75Hz */
468 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
469 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 0x3c - 1680x1050@85Hz */
472 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
473 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x3d - 1680x1050@120Hz RB */
476 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
477 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
479 /* 0x3e - 1792x1344@60Hz */
480 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
481 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
483 /* 0x3f - 1792x1344@75Hz */
484 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
485 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x40 - 1792x1344@120Hz RB */
488 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
489 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
491 /* 0x41 - 1856x1392@60Hz */
492 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
493 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x42 - 1856x1392@75Hz */
496 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
497 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
499 /* 0x43 - 1856x1392@120Hz RB */
500 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
501 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
503 /* 0x52 - 1920x1080@60Hz */
504 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
505 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
507 /* 0x44 - 1920x1200@60Hz RB */
508 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
509 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
511 /* 0x45 - 1920x1200@60Hz */
512 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
513 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
515 /* 0x46 - 1920x1200@75Hz */
516 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
517 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
519 /* 0x47 - 1920x1200@85Hz */
520 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
521 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
523 /* 0x48 - 1920x1200@120Hz RB */
524 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
525 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
527 /* 0x49 - 1920x1440@60Hz */
528 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
529 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
531 /* 0x4a - 1920x1440@75Hz */
532 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
533 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
535 /* 0x4b - 1920x1440@120Hz RB */
536 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
537 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
538 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
539 /* 0x54 - 2048x1152@60Hz */
540 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
541 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
543 /* 0x4c - 2560x1600@60Hz RB */
544 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
545 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
547 /* 0x4d - 2560x1600@60Hz */
548 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
549 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
551 /* 0x4e - 2560x1600@75Hz */
552 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
553 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
555 /* 0x4f - 2560x1600@85Hz */
556 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
557 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
559 /* 0x50 - 2560x1600@120Hz RB */
560 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
561 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
563 /* 0x57 - 4096x2160@60Hz RB */
564 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
565 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
567 /* 0x58 - 4096x2160@59.94Hz RB */
568 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
569 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
571 };
572
573 /*
574 * These more or less come from the DMT spec. The 720x400 modes are
575 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
576 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
577 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
578 * mode.
579 *
580 * The DMT modes have been fact-checked; the rest are mild guesses.
581 */
582 static const struct drm_display_mode edid_est_modes[] = {
583 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
584 968, 1056, 0, 600, 601, 605, 628, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
586 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
587 896, 1024, 0, 600, 601, 603, 625, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
589 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
590 720, 840, 0, 480, 481, 484, 500, 0,
591 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
592 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
593 704, 832, 0, 480, 489, 492, 520, 0,
594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
596 768, 864, 0, 480, 483, 486, 525, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
599 752, 800, 0, 480, 490, 492, 525, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
601 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
602 846, 900, 0, 400, 421, 423, 449, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
604 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
605 846, 900, 0, 400, 412, 414, 449, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
607 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
608 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
610 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
611 1136, 1312, 0, 768, 769, 772, 800, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
613 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
614 1184, 1328, 0, 768, 771, 777, 806, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
617 1184, 1344, 0, 768, 771, 777, 806, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
619 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
620 1208, 1264, 0, 768, 768, 776, 817, 0,
621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
622 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
623 928, 1152, 0, 624, 625, 628, 667, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
625 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
626 896, 1056, 0, 600, 601, 604, 625, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
628 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
629 976, 1040, 0, 600, 637, 643, 666, 0,
630 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
631 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
632 1344, 1600, 0, 864, 865, 868, 900, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
634 };
635
636 struct minimode {
637 short w;
638 short h;
639 short r;
640 short rb;
641 };
642
643 static const struct minimode est3_modes[] = {
644 /* byte 6 */
645 { 640, 350, 85, 0 },
646 { 640, 400, 85, 0 },
647 { 720, 400, 85, 0 },
648 { 640, 480, 85, 0 },
649 { 848, 480, 60, 0 },
650 { 800, 600, 85, 0 },
651 { 1024, 768, 85, 0 },
652 { 1152, 864, 75, 0 },
653 /* byte 7 */
654 { 1280, 768, 60, 1 },
655 { 1280, 768, 60, 0 },
656 { 1280, 768, 75, 0 },
657 { 1280, 768, 85, 0 },
658 { 1280, 960, 60, 0 },
659 { 1280, 960, 85, 0 },
660 { 1280, 1024, 60, 0 },
661 { 1280, 1024, 85, 0 },
662 /* byte 8 */
663 { 1360, 768, 60, 0 },
664 { 1440, 900, 60, 1 },
665 { 1440, 900, 60, 0 },
666 { 1440, 900, 75, 0 },
667 { 1440, 900, 85, 0 },
668 { 1400, 1050, 60, 1 },
669 { 1400, 1050, 60, 0 },
670 { 1400, 1050, 75, 0 },
671 /* byte 9 */
672 { 1400, 1050, 85, 0 },
673 { 1680, 1050, 60, 1 },
674 { 1680, 1050, 60, 0 },
675 { 1680, 1050, 75, 0 },
676 { 1680, 1050, 85, 0 },
677 { 1600, 1200, 60, 0 },
678 { 1600, 1200, 65, 0 },
679 { 1600, 1200, 70, 0 },
680 /* byte 10 */
681 { 1600, 1200, 75, 0 },
682 { 1600, 1200, 85, 0 },
683 { 1792, 1344, 60, 0 },
684 { 1792, 1344, 75, 0 },
685 { 1856, 1392, 60, 0 },
686 { 1856, 1392, 75, 0 },
687 { 1920, 1200, 60, 1 },
688 { 1920, 1200, 60, 0 },
689 /* byte 11 */
690 { 1920, 1200, 75, 0 },
691 { 1920, 1200, 85, 0 },
692 { 1920, 1440, 60, 0 },
693 { 1920, 1440, 75, 0 },
694 };
695
696 static const struct minimode extra_modes[] = {
697 { 1024, 576, 60, 0 },
698 { 1366, 768, 60, 0 },
699 { 1600, 900, 60, 0 },
700 { 1680, 945, 60, 0 },
701 { 1920, 1080, 60, 0 },
702 { 2048, 1152, 60, 0 },
703 { 2048, 1536, 60, 0 },
704 };
705
706 /*
707 * Probably taken from CEA-861 spec.
708 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
709 *
710 * Index using the VIC.
711 */
712 static const struct drm_display_mode edid_cea_modes[] = {
713 /* 0 - dummy, VICs start at 1 */
714 { },
715 /* 1 - 640x480@60Hz 4:3 */
716 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
717 752, 800, 0, 480, 490, 492, 525, 0,
718 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
720 /* 2 - 720x480@60Hz 4:3 */
721 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
722 798, 858, 0, 480, 489, 495, 525, 0,
723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
724 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
725 /* 3 - 720x480@60Hz 16:9 */
726 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
727 798, 858, 0, 480, 489, 495, 525, 0,
728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
729 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
730 /* 4 - 1280x720@60Hz 16:9 */
731 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
732 1430, 1650, 0, 720, 725, 730, 750, 0,
733 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
735 /* 5 - 1920x1080i@60Hz 16:9 */
736 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
737 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
738 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
739 DRM_MODE_FLAG_INTERLACE),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741 /* 6 - 720(1440)x480i@60Hz 4:3 */
742 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
743 801, 858, 0, 480, 488, 494, 525, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
745 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
747 /* 7 - 720(1440)x480i@60Hz 16:9 */
748 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
749 801, 858, 0, 480, 488, 494, 525, 0,
750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
751 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
752 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 8 - 720(1440)x240@60Hz 4:3 */
754 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
755 801, 858, 0, 240, 244, 247, 262, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
757 DRM_MODE_FLAG_DBLCLK),
758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
759 /* 9 - 720(1440)x240@60Hz 16:9 */
760 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
761 801, 858, 0, 240, 244, 247, 262, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
763 DRM_MODE_FLAG_DBLCLK),
764 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 10 - 2880x480i@60Hz 4:3 */
766 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
767 3204, 3432, 0, 480, 488, 494, 525, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_INTERLACE),
770 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 11 - 2880x480i@60Hz 16:9 */
772 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
773 3204, 3432, 0, 480, 488, 494, 525, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_INTERLACE),
776 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 12 - 2880x240@60Hz 4:3 */
778 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
779 3204, 3432, 0, 240, 244, 247, 262, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
781 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782 /* 13 - 2880x240@60Hz 16:9 */
783 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 240, 244, 247, 262, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
786 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
787 /* 14 - 1440x480@60Hz 4:3 */
788 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
789 1596, 1716, 0, 480, 489, 495, 525, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
791 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
792 /* 15 - 1440x480@60Hz 16:9 */
793 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
794 1596, 1716, 0, 480, 489, 495, 525, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
796 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
797 /* 16 - 1920x1080@60Hz 16:9 */
798 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
799 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
800 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
801 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
802 /* 17 - 720x576@50Hz 4:3 */
803 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
804 796, 864, 0, 576, 581, 586, 625, 0,
805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
806 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
807 /* 18 - 720x576@50Hz 16:9 */
808 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
809 796, 864, 0, 576, 581, 586, 625, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
811 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
812 /* 19 - 1280x720@50Hz 16:9 */
813 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
814 1760, 1980, 0, 720, 725, 730, 750, 0,
815 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
817 /* 20 - 1920x1080i@50Hz 16:9 */
818 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
819 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
821 DRM_MODE_FLAG_INTERLACE),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 21 - 720(1440)x576i@50Hz 4:3 */
824 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
825 795, 864, 0, 576, 580, 586, 625, 0,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
827 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
829 /* 22 - 720(1440)x576i@50Hz 16:9 */
830 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
831 795, 864, 0, 576, 580, 586, 625, 0,
832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
833 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
834 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 23 - 720(1440)x288@50Hz 4:3 */
836 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
837 795, 864, 0, 288, 290, 293, 312, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
839 DRM_MODE_FLAG_DBLCLK),
840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
841 /* 24 - 720(1440)x288@50Hz 16:9 */
842 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
843 795, 864, 0, 288, 290, 293, 312, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
845 DRM_MODE_FLAG_DBLCLK),
846 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 25 - 2880x576i@50Hz 4:3 */
848 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
849 3180, 3456, 0, 576, 580, 586, 625, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_INTERLACE),
852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 26 - 2880x576i@50Hz 16:9 */
854 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
855 3180, 3456, 0, 576, 580, 586, 625, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_INTERLACE),
858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 27 - 2880x288@50Hz 4:3 */
860 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
861 3180, 3456, 0, 288, 290, 293, 312, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
864 /* 28 - 2880x288@50Hz 16:9 */
865 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 288, 290, 293, 312, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
869 /* 29 - 1440x576@50Hz 4:3 */
870 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
871 1592, 1728, 0, 576, 581, 586, 625, 0,
872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
873 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
874 /* 30 - 1440x576@50Hz 16:9 */
875 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
876 1592, 1728, 0, 576, 581, 586, 625, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
878 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
879 /* 31 - 1920x1080@50Hz 16:9 */
880 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
881 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
883 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
884 /* 32 - 1920x1080@24Hz 16:9 */
885 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
886 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
888 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
889 /* 33 - 1920x1080@25Hz 16:9 */
890 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
891 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
893 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 34 - 1920x1080@30Hz 16:9 */
895 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
896 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
898 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
899 /* 35 - 2880x480@60Hz 4:3 */
900 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
901 3192, 3432, 0, 480, 489, 495, 525, 0,
902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
903 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
904 /* 36 - 2880x480@60Hz 16:9 */
905 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
906 3192, 3432, 0, 480, 489, 495, 525, 0,
907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
908 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
909 /* 37 - 2880x576@50Hz 4:3 */
910 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
911 3184, 3456, 0, 576, 581, 586, 625, 0,
912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
913 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
914 /* 38 - 2880x576@50Hz 16:9 */
915 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
916 3184, 3456, 0, 576, 581, 586, 625, 0,
917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
918 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
919 /* 39 - 1920x1080i@50Hz 16:9 */
920 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
921 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
923 DRM_MODE_FLAG_INTERLACE),
924 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925 /* 40 - 1920x1080i@100Hz 16:9 */
926 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
927 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
929 DRM_MODE_FLAG_INTERLACE),
930 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 41 - 1280x720@100Hz 16:9 */
932 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
933 1760, 1980, 0, 720, 725, 730, 750, 0,
934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
935 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
936 /* 42 - 720x576@100Hz 4:3 */
937 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
938 796, 864, 0, 576, 581, 586, 625, 0,
939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
940 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
941 /* 43 - 720x576@100Hz 16:9 */
942 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
943 796, 864, 0, 576, 581, 586, 625, 0,
944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
945 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
946 /* 44 - 720(1440)x576i@100Hz 4:3 */
947 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
948 795, 864, 0, 576, 580, 586, 625, 0,
949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
950 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
951 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
952 /* 45 - 720(1440)x576i@100Hz 16:9 */
953 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
954 795, 864, 0, 576, 580, 586, 625, 0,
955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
956 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
957 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
958 /* 46 - 1920x1080i@120Hz 16:9 */
959 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
960 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
961 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
962 DRM_MODE_FLAG_INTERLACE),
963 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
964 /* 47 - 1280x720@120Hz 16:9 */
965 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
966 1430, 1650, 0, 720, 725, 730, 750, 0,
967 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
968 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
969 /* 48 - 720x480@120Hz 4:3 */
970 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
971 798, 858, 0, 480, 489, 495, 525, 0,
972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
973 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
974 /* 49 - 720x480@120Hz 16:9 */
975 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
976 798, 858, 0, 480, 489, 495, 525, 0,
977 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
978 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
979 /* 50 - 720(1440)x480i@120Hz 4:3 */
980 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
981 801, 858, 0, 480, 488, 494, 525, 0,
982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
983 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
984 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
985 /* 51 - 720(1440)x480i@120Hz 16:9 */
986 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
987 801, 858, 0, 480, 488, 494, 525, 0,
988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
989 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
990 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
991 /* 52 - 720x576@200Hz 4:3 */
992 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
993 796, 864, 0, 576, 581, 586, 625, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
995 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
996 /* 53 - 720x576@200Hz 16:9 */
997 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
998 796, 864, 0, 576, 581, 586, 625, 0,
999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1000 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1001 /* 54 - 720(1440)x576i@200Hz 4:3 */
1002 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1003 795, 864, 0, 576, 580, 586, 625, 0,
1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1005 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1006 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1007 /* 55 - 720(1440)x576i@200Hz 16:9 */
1008 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1009 795, 864, 0, 576, 580, 586, 625, 0,
1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1011 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1012 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1013 /* 56 - 720x480@240Hz 4:3 */
1014 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1015 798, 858, 0, 480, 489, 495, 525, 0,
1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1017 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1018 /* 57 - 720x480@240Hz 16:9 */
1019 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1020 798, 858, 0, 480, 489, 495, 525, 0,
1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1022 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1023 /* 58 - 720(1440)x480i@240Hz 4:3 */
1024 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1025 801, 858, 0, 480, 488, 494, 525, 0,
1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1027 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1028 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1029 /* 59 - 720(1440)x480i@240Hz 16:9 */
1030 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1031 801, 858, 0, 480, 488, 494, 525, 0,
1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1033 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1034 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1035 /* 60 - 1280x720@24Hz 16:9 */
1036 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1037 3080, 3300, 0, 720, 725, 730, 750, 0,
1038 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1039 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1040 /* 61 - 1280x720@25Hz 16:9 */
1041 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1042 3740, 3960, 0, 720, 725, 730, 750, 0,
1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1044 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1045 /* 62 - 1280x720@30Hz 16:9 */
1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1047 3080, 3300, 0, 720, 725, 730, 750, 0,
1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1049 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1050 /* 63 - 1920x1080@120Hz 16:9 */
1051 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1052 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1055 /* 64 - 1920x1080@100Hz 16:9 */
1056 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1057 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1060 /* 65 - 1280x720@24Hz 64:27 */
1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1062 3080, 3300, 0, 720, 725, 730, 750, 0,
1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1065 /* 66 - 1280x720@25Hz 64:27 */
1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1067 3740, 3960, 0, 720, 725, 730, 750, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1070 /* 67 - 1280x720@30Hz 64:27 */
1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1072 3080, 3300, 0, 720, 725, 730, 750, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1075 /* 68 - 1280x720@50Hz 64:27 */
1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1077 1760, 1980, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1080 /* 69 - 1280x720@60Hz 64:27 */
1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1082 1430, 1650, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085 /* 70 - 1280x720@100Hz 64:27 */
1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1087 1760, 1980, 0, 720, 725, 730, 750, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090 /* 71 - 1280x720@120Hz 64:27 */
1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1092 1430, 1650, 0, 720, 725, 730, 750, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095 /* 72 - 1920x1080@24Hz 64:27 */
1096 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1097 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 73 - 1920x1080@25Hz 64:27 */
1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1102 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 74 - 1920x1080@30Hz 64:27 */
1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1107 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 75 - 1920x1080@50Hz 64:27 */
1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1112 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 76 - 1920x1080@60Hz 64:27 */
1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1117 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 77 - 1920x1080@100Hz 64:27 */
1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 78 - 1920x1080@120Hz 64:27 */
1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 79 - 1680x720@24Hz 64:27 */
1131 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1132 3080, 3300, 0, 720, 725, 730, 750, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 80 - 1680x720@25Hz 64:27 */
1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1137 2948, 3168, 0, 720, 725, 730, 750, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 81 - 1680x720@30Hz 64:27 */
1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1142 2420, 2640, 0, 720, 725, 730, 750, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 82 - 1680x720@50Hz 64:27 */
1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1147 1980, 2200, 0, 720, 725, 730, 750, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 83 - 1680x720@60Hz 64:27 */
1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1152 1980, 2200, 0, 720, 725, 730, 750, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 84 - 1680x720@100Hz 64:27 */
1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1157 1780, 2000, 0, 720, 725, 730, 825, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 85 - 1680x720@120Hz 64:27 */
1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1162 1780, 2000, 0, 720, 725, 730, 825, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 86 - 2560x1080@24Hz 64:27 */
1166 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1167 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 87 - 2560x1080@25Hz 64:27 */
1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1172 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 88 - 2560x1080@30Hz 64:27 */
1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1177 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 89 - 2560x1080@50Hz 64:27 */
1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1182 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 90 - 2560x1080@60Hz 64:27 */
1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1187 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190 /* 91 - 2560x1080@100Hz 64:27 */
1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1192 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195 /* 92 - 2560x1080@120Hz 64:27 */
1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1197 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200 /* 93 - 3840x2160@24Hz 16:9 */
1201 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1202 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1205 /* 94 - 3840x2160@25Hz 16:9 */
1206 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1207 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1210 /* 95 - 3840x2160@30Hz 16:9 */
1211 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1212 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1215 /* 96 - 3840x2160@50Hz 16:9 */
1216 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1217 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1220 /* 97 - 3840x2160@60Hz 16:9 */
1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1222 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1225 /* 98 - 4096x2160@24Hz 256:135 */
1226 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1227 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1230 /* 99 - 4096x2160@25Hz 256:135 */
1231 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1232 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1235 /* 100 - 4096x2160@30Hz 256:135 */
1236 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1237 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1240 /* 101 - 4096x2160@50Hz 256:135 */
1241 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1242 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1245 /* 102 - 4096x2160@60Hz 256:135 */
1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1247 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1250 /* 103 - 3840x2160@24Hz 64:27 */
1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1252 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1255 /* 104 - 3840x2160@25Hz 64:27 */
1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1257 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1260 /* 105 - 3840x2160@30Hz 64:27 */
1261 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1262 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1265 /* 106 - 3840x2160@50Hz 64:27 */
1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1267 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1270 /* 107 - 3840x2160@60Hz 64:27 */
1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1272 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1275 };
1276
1277 /*
1278 * HDMI 1.4 4k modes. Index using the VIC.
1279 */
1280 static const struct drm_display_mode edid_4k_modes[] = {
1281 /* 0 - dummy, VICs start at 1 */
1282 { },
1283 /* 1 - 3840x2160@30Hz */
1284 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1285 3840, 4016, 4104, 4400, 0,
1286 2160, 2168, 2178, 2250, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .vrefresh = 30, },
1289 /* 2 - 3840x2160@25Hz */
1290 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1291 3840, 4896, 4984, 5280, 0,
1292 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 .vrefresh = 25, },
1295 /* 3 - 3840x2160@24Hz */
1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1297 3840, 5116, 5204, 5500, 0,
1298 2160, 2168, 2178, 2250, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300 .vrefresh = 24, },
1301 /* 4 - 4096x2160@24Hz (SMPTE) */
1302 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1303 4096, 5116, 5204, 5500, 0,
1304 2160, 2168, 2178, 2250, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1306 .vrefresh = 24, },
1307 };
1308
1309 /*** DDC fetch and block validation ***/
1310
1311 static const u8 edid_header[] = {
1312 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1313 };
1314
1315 /**
1316 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1317 * @raw_edid: pointer to raw base EDID block
1318 *
1319 * Sanity check the header of the base EDID block.
1320 *
1321 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1322 */
1323 int drm_edid_header_is_valid(const u8 *raw_edid)
1324 {
1325 int i, score = 0;
1326
1327 for (i = 0; i < sizeof(edid_header); i++)
1328 if (raw_edid[i] == edid_header[i])
1329 score++;
1330
1331 return score;
1332 }
1333 EXPORT_SYMBOL(drm_edid_header_is_valid);
1334
1335 static int edid_fixup __read_mostly = 6;
1336 module_param_named(edid_fixup, edid_fixup, int, 0400);
1337 MODULE_PARM_DESC(edid_fixup,
1338 "Minimum number of valid EDID header bytes (0-8, default 6)");
1339
1340 static void drm_get_displayid(struct drm_connector *connector,
1341 struct edid *edid);
1342
1343 static int drm_edid_block_checksum(const u8 *raw_edid)
1344 {
1345 int i;
1346 u8 csum = 0;
1347 for (i = 0; i < EDID_LENGTH; i++)
1348 csum += raw_edid[i];
1349
1350 return csum;
1351 }
1352
1353 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1354 {
1355 if (memchr_inv(in_edid, 0, length))
1356 return false;
1357
1358 return true;
1359 }
1360
1361 /**
1362 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1363 * @raw_edid: pointer to raw EDID block
1364 * @block: type of block to validate (0 for base, extension otherwise)
1365 * @print_bad_edid: if true, dump bad EDID blocks to the console
1366 * @edid_corrupt: if true, the header or checksum is invalid
1367 *
1368 * Validate a base or extension EDID block and optionally dump bad blocks to
1369 * the console.
1370 *
1371 * Return: True if the block is valid, false otherwise.
1372 */
1373 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1374 bool *edid_corrupt)
1375 {
1376 u8 csum;
1377 struct edid *edid = (struct edid *)raw_edid;
1378
1379 if (WARN_ON(!raw_edid))
1380 return false;
1381
1382 if (edid_fixup > 8 || edid_fixup < 0)
1383 edid_fixup = 6;
1384
1385 if (block == 0) {
1386 int score = drm_edid_header_is_valid(raw_edid);
1387 if (score == 8) {
1388 if (edid_corrupt)
1389 *edid_corrupt = false;
1390 } else if (score >= edid_fixup) {
1391 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1392 * The corrupt flag needs to be set here otherwise, the
1393 * fix-up code here will correct the problem, the
1394 * checksum is correct and the test fails
1395 */
1396 if (edid_corrupt)
1397 *edid_corrupt = true;
1398 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1399 memcpy(raw_edid, edid_header, sizeof(edid_header));
1400 } else {
1401 if (edid_corrupt)
1402 *edid_corrupt = true;
1403 goto bad;
1404 }
1405 }
1406
1407 csum = drm_edid_block_checksum(raw_edid);
1408 if (csum) {
1409 if (edid_corrupt)
1410 *edid_corrupt = true;
1411
1412 /* allow CEA to slide through, switches mangle this */
1413 if (raw_edid[0] == CEA_EXT) {
1414 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1415 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1416 } else {
1417 if (print_bad_edid)
1418 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1419
1420 goto bad;
1421 }
1422 }
1423
1424 /* per-block-type checks */
1425 switch (raw_edid[0]) {
1426 case 0: /* base */
1427 if (edid->version != 1) {
1428 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1429 goto bad;
1430 }
1431
1432 if (edid->revision > 4)
1433 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1434 break;
1435
1436 default:
1437 break;
1438 }
1439
1440 return true;
1441
1442 bad:
1443 if (print_bad_edid) {
1444 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1445 pr_notice("EDID block is all zeroes\n");
1446 } else {
1447 pr_notice("Raw EDID:\n");
1448 print_hex_dump(KERN_NOTICE,
1449 " \t", DUMP_PREFIX_NONE, 16, 1,
1450 raw_edid, EDID_LENGTH, false);
1451 }
1452 }
1453 return false;
1454 }
1455 EXPORT_SYMBOL(drm_edid_block_valid);
1456
1457 /**
1458 * drm_edid_is_valid - sanity check EDID data
1459 * @edid: EDID data
1460 *
1461 * Sanity-check an entire EDID record (including extensions)
1462 *
1463 * Return: True if the EDID data is valid, false otherwise.
1464 */
1465 bool drm_edid_is_valid(struct edid *edid)
1466 {
1467 int i;
1468 u8 *raw = (u8 *)edid;
1469
1470 if (!edid)
1471 return false;
1472
1473 for (i = 0; i <= edid->extensions; i++)
1474 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1475 return false;
1476
1477 return true;
1478 }
1479 EXPORT_SYMBOL(drm_edid_is_valid);
1480
1481 #define DDC_SEGMENT_ADDR 0x30
1482 /**
1483 * drm_do_probe_ddc_edid() - get EDID information via I2C
1484 * @data: I2C device adapter
1485 * @buf: EDID data buffer to be filled
1486 * @block: 128 byte EDID block to start fetching from
1487 * @len: EDID data buffer length to fetch
1488 *
1489 * Try to fetch EDID information by calling I2C driver functions.
1490 *
1491 * Return: 0 on success or -1 on failure.
1492 */
1493 static int
1494 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1495 {
1496 struct i2c_adapter *adapter = data;
1497 unsigned char start = block * EDID_LENGTH;
1498 unsigned char segment = block >> 1;
1499 unsigned char xfers = segment ? 3 : 2;
1500 int ret, retries = 5;
1501
1502 /*
1503 * The core I2C driver will automatically retry the transfer if the
1504 * adapter reports EAGAIN. However, we find that bit-banging transfers
1505 * are susceptible to errors under a heavily loaded machine and
1506 * generate spurious NAKs and timeouts. Retrying the transfer
1507 * of the individual block a few times seems to overcome this.
1508 */
1509 do {
1510 struct i2c_msg msgs[] = {
1511 {
1512 .addr = DDC_SEGMENT_ADDR,
1513 .flags = 0,
1514 .len = 1,
1515 .buf = &segment,
1516 }, {
1517 .addr = DDC_ADDR,
1518 .flags = 0,
1519 .len = 1,
1520 .buf = &start,
1521 }, {
1522 .addr = DDC_ADDR,
1523 .flags = I2C_M_RD,
1524 .len = len,
1525 .buf = buf,
1526 }
1527 };
1528
1529 /*
1530 * Avoid sending the segment addr to not upset non-compliant
1531 * DDC monitors.
1532 */
1533 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1534
1535 if (ret == -ENXIO) {
1536 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1537 adapter->name);
1538 break;
1539 }
1540 } while (ret != xfers && --retries);
1541
1542 return ret == xfers ? 0 : -1;
1543 }
1544
1545 static void connector_bad_edid(struct drm_connector *connector,
1546 u8 *edid, int num_blocks)
1547 {
1548 int i;
1549
1550 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1551 return;
1552
1553 dev_warn(connector->dev->dev,
1554 "%s: EDID is invalid:\n",
1555 connector->name);
1556 for (i = 0; i < num_blocks; i++) {
1557 u8 *block = edid + i * EDID_LENGTH;
1558 char prefix[20];
1559
1560 if (drm_edid_is_zero(block, EDID_LENGTH))
1561 sprintf(prefix, "\t[%02x] ZERO ", i);
1562 else if (!drm_edid_block_valid(block, i, false, NULL))
1563 sprintf(prefix, "\t[%02x] BAD ", i);
1564 else
1565 sprintf(prefix, "\t[%02x] GOOD ", i);
1566
1567 print_hex_dump(KERN_WARNING,
1568 prefix, DUMP_PREFIX_NONE, 16, 1,
1569 block, EDID_LENGTH, false);
1570 }
1571 }
1572
1573 /**
1574 * drm_do_get_edid - get EDID data using a custom EDID block read function
1575 * @connector: connector we're probing
1576 * @get_edid_block: EDID block read function
1577 * @data: private data passed to the block read function
1578 *
1579 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1580 * exposes a different interface to read EDID blocks this function can be used
1581 * to get EDID data using a custom block read function.
1582 *
1583 * As in the general case the DDC bus is accessible by the kernel at the I2C
1584 * level, drivers must make all reasonable efforts to expose it as an I2C
1585 * adapter and use drm_get_edid() instead of abusing this function.
1586 *
1587 * The EDID may be overridden using debugfs override_edid or firmare EDID
1588 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1589 * order. Having either of them bypasses actual EDID reads.
1590 *
1591 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1592 */
1593 struct edid *drm_do_get_edid(struct drm_connector *connector,
1594 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1595 size_t len),
1596 void *data)
1597 {
1598 int i, j = 0, valid_extensions = 0;
1599 u8 *edid, *new;
1600 struct edid *override = NULL;
1601
1602 if (connector->override_edid)
1603 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1604
1605 if (!override)
1606 override = drm_load_edid_firmware(connector);
1607
1608 if (!IS_ERR_OR_NULL(override))
1609 return override;
1610
1611 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1612 return NULL;
1613
1614 /* base block fetch */
1615 for (i = 0; i < 4; i++) {
1616 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1617 goto out;
1618 if (drm_edid_block_valid(edid, 0, false,
1619 &connector->edid_corrupt))
1620 break;
1621 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1622 connector->null_edid_counter++;
1623 goto carp;
1624 }
1625 }
1626 if (i == 4)
1627 goto carp;
1628
1629 /* if there's no extensions, we're done */
1630 valid_extensions = edid[0x7e];
1631 if (valid_extensions == 0)
1632 return (struct edid *)edid;
1633
1634 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1635 if (!new)
1636 goto out;
1637 edid = new;
1638
1639 for (j = 1; j <= edid[0x7e]; j++) {
1640 u8 *block = edid + j * EDID_LENGTH;
1641
1642 for (i = 0; i < 4; i++) {
1643 if (get_edid_block(data, block, j, EDID_LENGTH))
1644 goto out;
1645 if (drm_edid_block_valid(block, j, false, NULL))
1646 break;
1647 }
1648
1649 if (i == 4)
1650 valid_extensions--;
1651 }
1652
1653 if (valid_extensions != edid[0x7e]) {
1654 u8 *base;
1655
1656 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1657
1658 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1659 edid[0x7e] = valid_extensions;
1660
1661 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1662 GFP_KERNEL);
1663 if (!new)
1664 goto out;
1665
1666 base = new;
1667 for (i = 0; i <= edid[0x7e]; i++) {
1668 u8 *block = edid + i * EDID_LENGTH;
1669
1670 if (!drm_edid_block_valid(block, i, false, NULL))
1671 continue;
1672
1673 memcpy(base, block, EDID_LENGTH);
1674 base += EDID_LENGTH;
1675 }
1676
1677 kfree(edid);
1678 edid = new;
1679 }
1680
1681 return (struct edid *)edid;
1682
1683 carp:
1684 connector_bad_edid(connector, edid, 1);
1685 out:
1686 kfree(edid);
1687 return NULL;
1688 }
1689 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1690
1691 /**
1692 * drm_probe_ddc() - probe DDC presence
1693 * @adapter: I2C adapter to probe
1694 *
1695 * Return: True on success, false on failure.
1696 */
1697 bool
1698 drm_probe_ddc(struct i2c_adapter *adapter)
1699 {
1700 unsigned char out;
1701
1702 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1703 }
1704 EXPORT_SYMBOL(drm_probe_ddc);
1705
1706 /**
1707 * drm_get_edid - get EDID data, if available
1708 * @connector: connector we're probing
1709 * @adapter: I2C adapter to use for DDC
1710 *
1711 * Poke the given I2C channel to grab EDID data if possible. If found,
1712 * attach it to the connector.
1713 *
1714 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1715 */
1716 struct edid *drm_get_edid(struct drm_connector *connector,
1717 struct i2c_adapter *adapter)
1718 {
1719 struct edid *edid;
1720
1721 if (connector->force == DRM_FORCE_OFF)
1722 return NULL;
1723
1724 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1725 return NULL;
1726
1727 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1728 if (edid)
1729 drm_get_displayid(connector, edid);
1730 return edid;
1731 }
1732 EXPORT_SYMBOL(drm_get_edid);
1733
1734 /**
1735 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1736 * @connector: connector we're probing
1737 * @adapter: I2C adapter to use for DDC
1738 *
1739 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1740 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1741 * switch DDC to the GPU which is retrieving EDID.
1742 *
1743 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1744 */
1745 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1746 struct i2c_adapter *adapter)
1747 {
1748 struct pci_dev *pdev = connector->dev->pdev;
1749 struct edid *edid;
1750
1751 vga_switcheroo_lock_ddc(pdev);
1752 edid = drm_get_edid(connector, adapter);
1753 vga_switcheroo_unlock_ddc(pdev);
1754
1755 return edid;
1756 }
1757 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1758
1759 /**
1760 * drm_edid_duplicate - duplicate an EDID and the extensions
1761 * @edid: EDID to duplicate
1762 *
1763 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1764 */
1765 struct edid *drm_edid_duplicate(const struct edid *edid)
1766 {
1767 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1768 }
1769 EXPORT_SYMBOL(drm_edid_duplicate);
1770
1771 /*** EDID parsing ***/
1772
1773 /**
1774 * edid_vendor - match a string against EDID's obfuscated vendor field
1775 * @edid: EDID to match
1776 * @vendor: vendor string
1777 *
1778 * Returns true if @vendor is in @edid, false otherwise
1779 */
1780 static bool edid_vendor(const struct edid *edid, const char *vendor)
1781 {
1782 char edid_vendor[3];
1783
1784 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1785 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1786 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1787 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1788
1789 return !strncmp(edid_vendor, vendor, 3);
1790 }
1791
1792 /**
1793 * edid_get_quirks - return quirk flags for a given EDID
1794 * @edid: EDID to process
1795 *
1796 * This tells subsequent routines what fixes they need to apply.
1797 */
1798 static u32 edid_get_quirks(const struct edid *edid)
1799 {
1800 const struct edid_quirk *quirk;
1801 int i;
1802
1803 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1804 quirk = &edid_quirk_list[i];
1805
1806 if (edid_vendor(edid, quirk->vendor) &&
1807 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1808 return quirk->quirks;
1809 }
1810
1811 return 0;
1812 }
1813
1814 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1815 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1816
1817 /**
1818 * edid_fixup_preferred - set preferred modes based on quirk list
1819 * @connector: has mode list to fix up
1820 * @quirks: quirks list
1821 *
1822 * Walk the mode list for @connector, clearing the preferred status
1823 * on existing modes and setting it anew for the right mode ala @quirks.
1824 */
1825 static void edid_fixup_preferred(struct drm_connector *connector,
1826 u32 quirks)
1827 {
1828 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1829 int target_refresh = 0;
1830 int cur_vrefresh, preferred_vrefresh;
1831
1832 if (list_empty(&connector->probed_modes))
1833 return;
1834
1835 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1836 target_refresh = 60;
1837 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1838 target_refresh = 75;
1839
1840 preferred_mode = list_first_entry(&connector->probed_modes,
1841 struct drm_display_mode, head);
1842
1843 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1844 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1845
1846 if (cur_mode == preferred_mode)
1847 continue;
1848
1849 /* Largest mode is preferred */
1850 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1851 preferred_mode = cur_mode;
1852
1853 cur_vrefresh = cur_mode->vrefresh ?
1854 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1855 preferred_vrefresh = preferred_mode->vrefresh ?
1856 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1857 /* At a given size, try to get closest to target refresh */
1858 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1859 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1860 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1861 preferred_mode = cur_mode;
1862 }
1863 }
1864
1865 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1866 }
1867
1868 static bool
1869 mode_is_rb(const struct drm_display_mode *mode)
1870 {
1871 return (mode->htotal - mode->hdisplay == 160) &&
1872 (mode->hsync_end - mode->hdisplay == 80) &&
1873 (mode->hsync_end - mode->hsync_start == 32) &&
1874 (mode->vsync_start - mode->vdisplay == 3);
1875 }
1876
1877 /*
1878 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1879 * @dev: Device to duplicate against
1880 * @hsize: Mode width
1881 * @vsize: Mode height
1882 * @fresh: Mode refresh rate
1883 * @rb: Mode reduced-blanking-ness
1884 *
1885 * Walk the DMT mode list looking for a match for the given parameters.
1886 *
1887 * Return: A newly allocated copy of the mode, or NULL if not found.
1888 */
1889 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1890 int hsize, int vsize, int fresh,
1891 bool rb)
1892 {
1893 int i;
1894
1895 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1896 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1897 if (hsize != ptr->hdisplay)
1898 continue;
1899 if (vsize != ptr->vdisplay)
1900 continue;
1901 if (fresh != drm_mode_vrefresh(ptr))
1902 continue;
1903 if (rb != mode_is_rb(ptr))
1904 continue;
1905
1906 return drm_mode_duplicate(dev, ptr);
1907 }
1908
1909 return NULL;
1910 }
1911 EXPORT_SYMBOL(drm_mode_find_dmt);
1912
1913 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1914
1915 static void
1916 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1917 {
1918 int i, n = 0;
1919 u8 d = ext[0x02];
1920 u8 *det_base = ext + d;
1921
1922 n = (127 - d) / 18;
1923 for (i = 0; i < n; i++)
1924 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1925 }
1926
1927 static void
1928 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1929 {
1930 unsigned int i, n = min((int)ext[0x02], 6);
1931 u8 *det_base = ext + 5;
1932
1933 if (ext[0x01] != 1)
1934 return; /* unknown version */
1935
1936 for (i = 0; i < n; i++)
1937 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1938 }
1939
1940 static void
1941 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1942 {
1943 int i;
1944 struct edid *edid = (struct edid *)raw_edid;
1945
1946 if (edid == NULL)
1947 return;
1948
1949 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1950 cb(&(edid->detailed_timings[i]), closure);
1951
1952 for (i = 1; i <= raw_edid[0x7e]; i++) {
1953 u8 *ext = raw_edid + (i * EDID_LENGTH);
1954 switch (*ext) {
1955 case CEA_EXT:
1956 cea_for_each_detailed_block(ext, cb, closure);
1957 break;
1958 case VTB_EXT:
1959 vtb_for_each_detailed_block(ext, cb, closure);
1960 break;
1961 default:
1962 break;
1963 }
1964 }
1965 }
1966
1967 static void
1968 is_rb(struct detailed_timing *t, void *data)
1969 {
1970 u8 *r = (u8 *)t;
1971 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1972 if (r[15] & 0x10)
1973 *(bool *)data = true;
1974 }
1975
1976 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1977 static bool
1978 drm_monitor_supports_rb(struct edid *edid)
1979 {
1980 if (edid->revision >= 4) {
1981 bool ret = false;
1982 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1983 return ret;
1984 }
1985
1986 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1987 }
1988
1989 static void
1990 find_gtf2(struct detailed_timing *t, void *data)
1991 {
1992 u8 *r = (u8 *)t;
1993 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1994 *(u8 **)data = r;
1995 }
1996
1997 /* Secondary GTF curve kicks in above some break frequency */
1998 static int
1999 drm_gtf2_hbreak(struct edid *edid)
2000 {
2001 u8 *r = NULL;
2002 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2003 return r ? (r[12] * 2) : 0;
2004 }
2005
2006 static int
2007 drm_gtf2_2c(struct edid *edid)
2008 {
2009 u8 *r = NULL;
2010 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2011 return r ? r[13] : 0;
2012 }
2013
2014 static int
2015 drm_gtf2_m(struct edid *edid)
2016 {
2017 u8 *r = NULL;
2018 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2019 return r ? (r[15] << 8) + r[14] : 0;
2020 }
2021
2022 static int
2023 drm_gtf2_k(struct edid *edid)
2024 {
2025 u8 *r = NULL;
2026 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2027 return r ? r[16] : 0;
2028 }
2029
2030 static int
2031 drm_gtf2_2j(struct edid *edid)
2032 {
2033 u8 *r = NULL;
2034 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2035 return r ? r[17] : 0;
2036 }
2037
2038 /**
2039 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2040 * @edid: EDID block to scan
2041 */
2042 static int standard_timing_level(struct edid *edid)
2043 {
2044 if (edid->revision >= 2) {
2045 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2046 return LEVEL_CVT;
2047 if (drm_gtf2_hbreak(edid))
2048 return LEVEL_GTF2;
2049 return LEVEL_GTF;
2050 }
2051 return LEVEL_DMT;
2052 }
2053
2054 /*
2055 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2056 * monitors fill with ascii space (0x20) instead.
2057 */
2058 static int
2059 bad_std_timing(u8 a, u8 b)
2060 {
2061 return (a == 0x00 && b == 0x00) ||
2062 (a == 0x01 && b == 0x01) ||
2063 (a == 0x20 && b == 0x20);
2064 }
2065
2066 /**
2067 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2068 * @connector: connector of for the EDID block
2069 * @edid: EDID block to scan
2070 * @t: standard timing params
2071 *
2072 * Take the standard timing params (in this case width, aspect, and refresh)
2073 * and convert them into a real mode using CVT/GTF/DMT.
2074 */
2075 static struct drm_display_mode *
2076 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2077 struct std_timing *t)
2078 {
2079 struct drm_device *dev = connector->dev;
2080 struct drm_display_mode *m, *mode = NULL;
2081 int hsize, vsize;
2082 int vrefresh_rate;
2083 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2084 >> EDID_TIMING_ASPECT_SHIFT;
2085 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2086 >> EDID_TIMING_VFREQ_SHIFT;
2087 int timing_level = standard_timing_level(edid);
2088
2089 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2090 return NULL;
2091
2092 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2093 hsize = t->hsize * 8 + 248;
2094 /* vrefresh_rate = vfreq + 60 */
2095 vrefresh_rate = vfreq + 60;
2096 /* the vdisplay is calculated based on the aspect ratio */
2097 if (aspect_ratio == 0) {
2098 if (edid->revision < 3)
2099 vsize = hsize;
2100 else
2101 vsize = (hsize * 10) / 16;
2102 } else if (aspect_ratio == 1)
2103 vsize = (hsize * 3) / 4;
2104 else if (aspect_ratio == 2)
2105 vsize = (hsize * 4) / 5;
2106 else
2107 vsize = (hsize * 9) / 16;
2108
2109 /* HDTV hack, part 1 */
2110 if (vrefresh_rate == 60 &&
2111 ((hsize == 1360 && vsize == 765) ||
2112 (hsize == 1368 && vsize == 769))) {
2113 hsize = 1366;
2114 vsize = 768;
2115 }
2116
2117 /*
2118 * If this connector already has a mode for this size and refresh
2119 * rate (because it came from detailed or CVT info), use that
2120 * instead. This way we don't have to guess at interlace or
2121 * reduced blanking.
2122 */
2123 list_for_each_entry(m, &connector->probed_modes, head)
2124 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2125 drm_mode_vrefresh(m) == vrefresh_rate)
2126 return NULL;
2127
2128 /* HDTV hack, part 2 */
2129 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2130 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2131 false);
2132 if (!mode)
2133 return NULL;
2134 mode->hdisplay = 1366;
2135 mode->hsync_start = mode->hsync_start - 1;
2136 mode->hsync_end = mode->hsync_end - 1;
2137 return mode;
2138 }
2139
2140 /* check whether it can be found in default mode table */
2141 if (drm_monitor_supports_rb(edid)) {
2142 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2143 true);
2144 if (mode)
2145 return mode;
2146 }
2147 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2148 if (mode)
2149 return mode;
2150
2151 /* okay, generate it */
2152 switch (timing_level) {
2153 case LEVEL_DMT:
2154 break;
2155 case LEVEL_GTF:
2156 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2157 break;
2158 case LEVEL_GTF2:
2159 /*
2160 * This is potentially wrong if there's ever a monitor with
2161 * more than one ranges section, each claiming a different
2162 * secondary GTF curve. Please don't do that.
2163 */
2164 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2165 if (!mode)
2166 return NULL;
2167 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2168 drm_mode_destroy(dev, mode);
2169 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2170 vrefresh_rate, 0, 0,
2171 drm_gtf2_m(edid),
2172 drm_gtf2_2c(edid),
2173 drm_gtf2_k(edid),
2174 drm_gtf2_2j(edid));
2175 }
2176 break;
2177 case LEVEL_CVT:
2178 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2179 false);
2180 break;
2181 }
2182 return mode;
2183 }
2184
2185 /*
2186 * EDID is delightfully ambiguous about how interlaced modes are to be
2187 * encoded. Our internal representation is of frame height, but some
2188 * HDTV detailed timings are encoded as field height.
2189 *
2190 * The format list here is from CEA, in frame size. Technically we
2191 * should be checking refresh rate too. Whatever.
2192 */
2193 static void
2194 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2195 struct detailed_pixel_timing *pt)
2196 {
2197 int i;
2198 static const struct {
2199 int w, h;
2200 } cea_interlaced[] = {
2201 { 1920, 1080 },
2202 { 720, 480 },
2203 { 1440, 480 },
2204 { 2880, 480 },
2205 { 720, 576 },
2206 { 1440, 576 },
2207 { 2880, 576 },
2208 };
2209
2210 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2211 return;
2212
2213 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2214 if ((mode->hdisplay == cea_interlaced[i].w) &&
2215 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2216 mode->vdisplay *= 2;
2217 mode->vsync_start *= 2;
2218 mode->vsync_end *= 2;
2219 mode->vtotal *= 2;
2220 mode->vtotal |= 1;
2221 }
2222 }
2223
2224 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2225 }
2226
2227 /**
2228 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2229 * @dev: DRM device (needed to create new mode)
2230 * @edid: EDID block
2231 * @timing: EDID detailed timing info
2232 * @quirks: quirks to apply
2233 *
2234 * An EDID detailed timing block contains enough info for us to create and
2235 * return a new struct drm_display_mode.
2236 */
2237 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2238 struct edid *edid,
2239 struct detailed_timing *timing,
2240 u32 quirks)
2241 {
2242 struct drm_display_mode *mode;
2243 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2244 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2245 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2246 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2247 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2248 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2249 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2250 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2251 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2252
2253 /* ignore tiny modes */
2254 if (hactive < 64 || vactive < 64)
2255 return NULL;
2256
2257 if (pt->misc & DRM_EDID_PT_STEREO) {
2258 DRM_DEBUG_KMS("stereo mode not supported\n");
2259 return NULL;
2260 }
2261 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2262 DRM_DEBUG_KMS("composite sync not supported\n");
2263 }
2264
2265 /* it is incorrect if hsync/vsync width is zero */
2266 if (!hsync_pulse_width || !vsync_pulse_width) {
2267 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2268 "Wrong Hsync/Vsync pulse width\n");
2269 return NULL;
2270 }
2271
2272 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2273 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2274 if (!mode)
2275 return NULL;
2276
2277 goto set_size;
2278 }
2279
2280 mode = drm_mode_create(dev);
2281 if (!mode)
2282 return NULL;
2283
2284 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2285 timing->pixel_clock = cpu_to_le16(1088);
2286
2287 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2288
2289 mode->hdisplay = hactive;
2290 mode->hsync_start = mode->hdisplay + hsync_offset;
2291 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2292 mode->htotal = mode->hdisplay + hblank;
2293
2294 mode->vdisplay = vactive;
2295 mode->vsync_start = mode->vdisplay + vsync_offset;
2296 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2297 mode->vtotal = mode->vdisplay + vblank;
2298
2299 /* Some EDIDs have bogus h/vtotal values */
2300 if (mode->hsync_end > mode->htotal)
2301 mode->htotal = mode->hsync_end + 1;
2302 if (mode->vsync_end > mode->vtotal)
2303 mode->vtotal = mode->vsync_end + 1;
2304
2305 drm_mode_do_interlace_quirk(mode, pt);
2306
2307 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2308 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2309 }
2310
2311 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2312 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2313 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2314 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2315
2316 set_size:
2317 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2318 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2319
2320 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2321 mode->width_mm *= 10;
2322 mode->height_mm *= 10;
2323 }
2324
2325 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2326 mode->width_mm = edid->width_cm * 10;
2327 mode->height_mm = edid->height_cm * 10;
2328 }
2329
2330 mode->type = DRM_MODE_TYPE_DRIVER;
2331 mode->vrefresh = drm_mode_vrefresh(mode);
2332 drm_mode_set_name(mode);
2333
2334 return mode;
2335 }
2336
2337 static bool
2338 mode_in_hsync_range(const struct drm_display_mode *mode,
2339 struct edid *edid, u8 *t)
2340 {
2341 int hsync, hmin, hmax;
2342
2343 hmin = t[7];
2344 if (edid->revision >= 4)
2345 hmin += ((t[4] & 0x04) ? 255 : 0);
2346 hmax = t[8];
2347 if (edid->revision >= 4)
2348 hmax += ((t[4] & 0x08) ? 255 : 0);
2349 hsync = drm_mode_hsync(mode);
2350
2351 return (hsync <= hmax && hsync >= hmin);
2352 }
2353
2354 static bool
2355 mode_in_vsync_range(const struct drm_display_mode *mode,
2356 struct edid *edid, u8 *t)
2357 {
2358 int vsync, vmin, vmax;
2359
2360 vmin = t[5];
2361 if (edid->revision >= 4)
2362 vmin += ((t[4] & 0x01) ? 255 : 0);
2363 vmax = t[6];
2364 if (edid->revision >= 4)
2365 vmax += ((t[4] & 0x02) ? 255 : 0);
2366 vsync = drm_mode_vrefresh(mode);
2367
2368 return (vsync <= vmax && vsync >= vmin);
2369 }
2370
2371 static u32
2372 range_pixel_clock(struct edid *edid, u8 *t)
2373 {
2374 /* unspecified */
2375 if (t[9] == 0 || t[9] == 255)
2376 return 0;
2377
2378 /* 1.4 with CVT support gives us real precision, yay */
2379 if (edid->revision >= 4 && t[10] == 0x04)
2380 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2381
2382 /* 1.3 is pathetic, so fuzz up a bit */
2383 return t[9] * 10000 + 5001;
2384 }
2385
2386 static bool
2387 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2388 struct detailed_timing *timing)
2389 {
2390 u32 max_clock;
2391 u8 *t = (u8 *)timing;
2392
2393 if (!mode_in_hsync_range(mode, edid, t))
2394 return false;
2395
2396 if (!mode_in_vsync_range(mode, edid, t))
2397 return false;
2398
2399 if ((max_clock = range_pixel_clock(edid, t)))
2400 if (mode->clock > max_clock)
2401 return false;
2402
2403 /* 1.4 max horizontal check */
2404 if (edid->revision >= 4 && t[10] == 0x04)
2405 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2406 return false;
2407
2408 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2409 return false;
2410
2411 return true;
2412 }
2413
2414 static bool valid_inferred_mode(const struct drm_connector *connector,
2415 const struct drm_display_mode *mode)
2416 {
2417 const struct drm_display_mode *m;
2418 bool ok = false;
2419
2420 list_for_each_entry(m, &connector->probed_modes, head) {
2421 if (mode->hdisplay == m->hdisplay &&
2422 mode->vdisplay == m->vdisplay &&
2423 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2424 return false; /* duplicated */
2425 if (mode->hdisplay <= m->hdisplay &&
2426 mode->vdisplay <= m->vdisplay)
2427 ok = true;
2428 }
2429 return ok;
2430 }
2431
2432 static int
2433 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2434 struct detailed_timing *timing)
2435 {
2436 int i, modes = 0;
2437 struct drm_display_mode *newmode;
2438 struct drm_device *dev = connector->dev;
2439
2440 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2441 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2442 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2443 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2444 if (newmode) {
2445 drm_mode_probed_add(connector, newmode);
2446 modes++;
2447 }
2448 }
2449 }
2450
2451 return modes;
2452 }
2453
2454 /* fix up 1366x768 mode from 1368x768;
2455 * GFT/CVT can't express 1366 width which isn't dividable by 8
2456 */
2457 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2458 {
2459 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2460 mode->hdisplay = 1366;
2461 mode->hsync_start--;
2462 mode->hsync_end--;
2463 drm_mode_set_name(mode);
2464 }
2465 }
2466
2467 static int
2468 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2469 struct detailed_timing *timing)
2470 {
2471 int i, modes = 0;
2472 struct drm_display_mode *newmode;
2473 struct drm_device *dev = connector->dev;
2474
2475 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2476 const struct minimode *m = &extra_modes[i];
2477 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2478 if (!newmode)
2479 return modes;
2480
2481 drm_mode_fixup_1366x768(newmode);
2482 if (!mode_in_range(newmode, edid, timing) ||
2483 !valid_inferred_mode(connector, newmode)) {
2484 drm_mode_destroy(dev, newmode);
2485 continue;
2486 }
2487
2488 drm_mode_probed_add(connector, newmode);
2489 modes++;
2490 }
2491
2492 return modes;
2493 }
2494
2495 static int
2496 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2497 struct detailed_timing *timing)
2498 {
2499 int i, modes = 0;
2500 struct drm_display_mode *newmode;
2501 struct drm_device *dev = connector->dev;
2502 bool rb = drm_monitor_supports_rb(edid);
2503
2504 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2505 const struct minimode *m = &extra_modes[i];
2506 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2507 if (!newmode)
2508 return modes;
2509
2510 drm_mode_fixup_1366x768(newmode);
2511 if (!mode_in_range(newmode, edid, timing) ||
2512 !valid_inferred_mode(connector, newmode)) {
2513 drm_mode_destroy(dev, newmode);
2514 continue;
2515 }
2516
2517 drm_mode_probed_add(connector, newmode);
2518 modes++;
2519 }
2520
2521 return modes;
2522 }
2523
2524 static void
2525 do_inferred_modes(struct detailed_timing *timing, void *c)
2526 {
2527 struct detailed_mode_closure *closure = c;
2528 struct detailed_non_pixel *data = &timing->data.other_data;
2529 struct detailed_data_monitor_range *range = &data->data.range;
2530
2531 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2532 return;
2533
2534 closure->modes += drm_dmt_modes_for_range(closure->connector,
2535 closure->edid,
2536 timing);
2537
2538 if (!version_greater(closure->edid, 1, 1))
2539 return; /* GTF not defined yet */
2540
2541 switch (range->flags) {
2542 case 0x02: /* secondary gtf, XXX could do more */
2543 case 0x00: /* default gtf */
2544 closure->modes += drm_gtf_modes_for_range(closure->connector,
2545 closure->edid,
2546 timing);
2547 break;
2548 case 0x04: /* cvt, only in 1.4+ */
2549 if (!version_greater(closure->edid, 1, 3))
2550 break;
2551
2552 closure->modes += drm_cvt_modes_for_range(closure->connector,
2553 closure->edid,
2554 timing);
2555 break;
2556 case 0x01: /* just the ranges, no formula */
2557 default:
2558 break;
2559 }
2560 }
2561
2562 static int
2563 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2564 {
2565 struct detailed_mode_closure closure = {
2566 .connector = connector,
2567 .edid = edid,
2568 };
2569
2570 if (version_greater(edid, 1, 0))
2571 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2572 &closure);
2573
2574 return closure.modes;
2575 }
2576
2577 static int
2578 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2579 {
2580 int i, j, m, modes = 0;
2581 struct drm_display_mode *mode;
2582 u8 *est = ((u8 *)timing) + 6;
2583
2584 for (i = 0; i < 6; i++) {
2585 for (j = 7; j >= 0; j--) {
2586 m = (i * 8) + (7 - j);
2587 if (m >= ARRAY_SIZE(est3_modes))
2588 break;
2589 if (est[i] & (1 << j)) {
2590 mode = drm_mode_find_dmt(connector->dev,
2591 est3_modes[m].w,
2592 est3_modes[m].h,
2593 est3_modes[m].r,
2594 est3_modes[m].rb);
2595 if (mode) {
2596 drm_mode_probed_add(connector, mode);
2597 modes++;
2598 }
2599 }
2600 }
2601 }
2602
2603 return modes;
2604 }
2605
2606 static void
2607 do_established_modes(struct detailed_timing *timing, void *c)
2608 {
2609 struct detailed_mode_closure *closure = c;
2610 struct detailed_non_pixel *data = &timing->data.other_data;
2611
2612 if (data->type == EDID_DETAIL_EST_TIMINGS)
2613 closure->modes += drm_est3_modes(closure->connector, timing);
2614 }
2615
2616 /**
2617 * add_established_modes - get est. modes from EDID and add them
2618 * @connector: connector to add mode(s) to
2619 * @edid: EDID block to scan
2620 *
2621 * Each EDID block contains a bitmap of the supported "established modes" list
2622 * (defined above). Tease them out and add them to the global modes list.
2623 */
2624 static int
2625 add_established_modes(struct drm_connector *connector, struct edid *edid)
2626 {
2627 struct drm_device *dev = connector->dev;
2628 unsigned long est_bits = edid->established_timings.t1 |
2629 (edid->established_timings.t2 << 8) |
2630 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2631 int i, modes = 0;
2632 struct detailed_mode_closure closure = {
2633 .connector = connector,
2634 .edid = edid,
2635 };
2636
2637 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2638 if (est_bits & (1<<i)) {
2639 struct drm_display_mode *newmode;
2640 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2641 if (newmode) {
2642 drm_mode_probed_add(connector, newmode);
2643 modes++;
2644 }
2645 }
2646 }
2647
2648 if (version_greater(edid, 1, 0))
2649 drm_for_each_detailed_block((u8 *)edid,
2650 do_established_modes, &closure);
2651
2652 return modes + closure.modes;
2653 }
2654
2655 static void
2656 do_standard_modes(struct detailed_timing *timing, void *c)
2657 {
2658 struct detailed_mode_closure *closure = c;
2659 struct detailed_non_pixel *data = &timing->data.other_data;
2660 struct drm_connector *connector = closure->connector;
2661 struct edid *edid = closure->edid;
2662
2663 if (data->type == EDID_DETAIL_STD_MODES) {
2664 int i;
2665 for (i = 0; i < 6; i++) {
2666 struct std_timing *std;
2667 struct drm_display_mode *newmode;
2668
2669 std = &data->data.timings[i];
2670 newmode = drm_mode_std(connector, edid, std);
2671 if (newmode) {
2672 drm_mode_probed_add(connector, newmode);
2673 closure->modes++;
2674 }
2675 }
2676 }
2677 }
2678
2679 /**
2680 * add_standard_modes - get std. modes from EDID and add them
2681 * @connector: connector to add mode(s) to
2682 * @edid: EDID block to scan
2683 *
2684 * Standard modes can be calculated using the appropriate standard (DMT,
2685 * GTF or CVT. Grab them from @edid and add them to the list.
2686 */
2687 static int
2688 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2689 {
2690 int i, modes = 0;
2691 struct detailed_mode_closure closure = {
2692 .connector = connector,
2693 .edid = edid,
2694 };
2695
2696 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2697 struct drm_display_mode *newmode;
2698
2699 newmode = drm_mode_std(connector, edid,
2700 &edid->standard_timings[i]);
2701 if (newmode) {
2702 drm_mode_probed_add(connector, newmode);
2703 modes++;
2704 }
2705 }
2706
2707 if (version_greater(edid, 1, 0))
2708 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2709 &closure);
2710
2711 /* XXX should also look for standard codes in VTB blocks */
2712
2713 return modes + closure.modes;
2714 }
2715
2716 static int drm_cvt_modes(struct drm_connector *connector,
2717 struct detailed_timing *timing)
2718 {
2719 int i, j, modes = 0;
2720 struct drm_display_mode *newmode;
2721 struct drm_device *dev = connector->dev;
2722 struct cvt_timing *cvt;
2723 const int rates[] = { 60, 85, 75, 60, 50 };
2724 const u8 empty[3] = { 0, 0, 0 };
2725
2726 for (i = 0; i < 4; i++) {
2727 int uninitialized_var(width), height;
2728 cvt = &(timing->data.other_data.data.cvt[i]);
2729
2730 if (!memcmp(cvt->code, empty, 3))
2731 continue;
2732
2733 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2734 switch (cvt->code[1] & 0x0c) {
2735 case 0x00:
2736 width = height * 4 / 3;
2737 break;
2738 case 0x04:
2739 width = height * 16 / 9;
2740 break;
2741 case 0x08:
2742 width = height * 16 / 10;
2743 break;
2744 case 0x0c:
2745 width = height * 15 / 9;
2746 break;
2747 }
2748
2749 for (j = 1; j < 5; j++) {
2750 if (cvt->code[2] & (1 << j)) {
2751 newmode = drm_cvt_mode(dev, width, height,
2752 rates[j], j == 0,
2753 false, false);
2754 if (newmode) {
2755 drm_mode_probed_add(connector, newmode);
2756 modes++;
2757 }
2758 }
2759 }
2760 }
2761
2762 return modes;
2763 }
2764
2765 static void
2766 do_cvt_mode(struct detailed_timing *timing, void *c)
2767 {
2768 struct detailed_mode_closure *closure = c;
2769 struct detailed_non_pixel *data = &timing->data.other_data;
2770
2771 if (data->type == EDID_DETAIL_CVT_3BYTE)
2772 closure->modes += drm_cvt_modes(closure->connector, timing);
2773 }
2774
2775 static int
2776 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2777 {
2778 struct detailed_mode_closure closure = {
2779 .connector = connector,
2780 .edid = edid,
2781 };
2782
2783 if (version_greater(edid, 1, 2))
2784 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2785
2786 /* XXX should also look for CVT codes in VTB blocks */
2787
2788 return closure.modes;
2789 }
2790
2791 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2792
2793 static void
2794 do_detailed_mode(struct detailed_timing *timing, void *c)
2795 {
2796 struct detailed_mode_closure *closure = c;
2797 struct drm_display_mode *newmode;
2798
2799 if (timing->pixel_clock) {
2800 newmode = drm_mode_detailed(closure->connector->dev,
2801 closure->edid, timing,
2802 closure->quirks);
2803 if (!newmode)
2804 return;
2805
2806 if (closure->preferred)
2807 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2808
2809 /*
2810 * Detailed modes are limited to 10kHz pixel clock resolution,
2811 * so fix up anything that looks like CEA/HDMI mode, but the clock
2812 * is just slightly off.
2813 */
2814 fixup_detailed_cea_mode_clock(newmode);
2815
2816 drm_mode_probed_add(closure->connector, newmode);
2817 closure->modes++;
2818 closure->preferred = false;
2819 }
2820 }
2821
2822 /*
2823 * add_detailed_modes - Add modes from detailed timings
2824 * @connector: attached connector
2825 * @edid: EDID block to scan
2826 * @quirks: quirks to apply
2827 */
2828 static int
2829 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2830 u32 quirks)
2831 {
2832 struct detailed_mode_closure closure = {
2833 .connector = connector,
2834 .edid = edid,
2835 .preferred = true,
2836 .quirks = quirks,
2837 };
2838
2839 if (closure.preferred && !version_greater(edid, 1, 3))
2840 closure.preferred =
2841 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2842
2843 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2844
2845 return closure.modes;
2846 }
2847
2848 #define AUDIO_BLOCK 0x01
2849 #define VIDEO_BLOCK 0x02
2850 #define VENDOR_BLOCK 0x03
2851 #define SPEAKER_BLOCK 0x04
2852 #define USE_EXTENDED_TAG 0x07
2853 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2854 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2855 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2856 #define EDID_BASIC_AUDIO (1 << 6)
2857 #define EDID_CEA_YCRCB444 (1 << 5)
2858 #define EDID_CEA_YCRCB422 (1 << 4)
2859 #define EDID_CEA_VCDB_QS (1 << 6)
2860
2861 /*
2862 * Search EDID for CEA extension block.
2863 */
2864 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2865 {
2866 u8 *edid_ext = NULL;
2867 int i;
2868
2869 /* No EDID or EDID extensions */
2870 if (edid == NULL || edid->extensions == 0)
2871 return NULL;
2872
2873 /* Find CEA extension */
2874 for (i = 0; i < edid->extensions; i++) {
2875 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2876 if (edid_ext[0] == ext_id)
2877 break;
2878 }
2879
2880 if (i == edid->extensions)
2881 return NULL;
2882
2883 return edid_ext;
2884 }
2885
2886 static u8 *drm_find_cea_extension(const struct edid *edid)
2887 {
2888 return drm_find_edid_extension(edid, CEA_EXT);
2889 }
2890
2891 static u8 *drm_find_displayid_extension(const struct edid *edid)
2892 {
2893 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2894 }
2895
2896 /*
2897 * Calculate the alternate clock for the CEA mode
2898 * (60Hz vs. 59.94Hz etc.)
2899 */
2900 static unsigned int
2901 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2902 {
2903 unsigned int clock = cea_mode->clock;
2904
2905 if (cea_mode->vrefresh % 6 != 0)
2906 return clock;
2907
2908 /*
2909 * edid_cea_modes contains the 59.94Hz
2910 * variant for 240 and 480 line modes,
2911 * and the 60Hz variant otherwise.
2912 */
2913 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2914 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2915 else
2916 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2917
2918 return clock;
2919 }
2920
2921 static bool
2922 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2923 {
2924 /*
2925 * For certain VICs the spec allows the vertical
2926 * front porch to vary by one or two lines.
2927 *
2928 * cea_modes[] stores the variant with the shortest
2929 * vertical front porch. We can adjust the mode to
2930 * get the other variants by simply increasing the
2931 * vertical front porch length.
2932 */
2933 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2934 edid_cea_modes[9].vtotal != 262 ||
2935 edid_cea_modes[12].vtotal != 262 ||
2936 edid_cea_modes[13].vtotal != 262 ||
2937 edid_cea_modes[23].vtotal != 312 ||
2938 edid_cea_modes[24].vtotal != 312 ||
2939 edid_cea_modes[27].vtotal != 312 ||
2940 edid_cea_modes[28].vtotal != 312);
2941
2942 if (((vic == 8 || vic == 9 ||
2943 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2944 ((vic == 23 || vic == 24 ||
2945 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2946 mode->vsync_start++;
2947 mode->vsync_end++;
2948 mode->vtotal++;
2949
2950 return true;
2951 }
2952
2953 return false;
2954 }
2955
2956 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2957 unsigned int clock_tolerance)
2958 {
2959 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2960 u8 vic;
2961
2962 if (!to_match->clock)
2963 return 0;
2964
2965 if (to_match->picture_aspect_ratio)
2966 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2967
2968 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2969 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2970 unsigned int clock1, clock2;
2971
2972 /* Check both 60Hz and 59.94Hz */
2973 clock1 = cea_mode.clock;
2974 clock2 = cea_mode_alternate_clock(&cea_mode);
2975
2976 if (abs(to_match->clock - clock1) > clock_tolerance &&
2977 abs(to_match->clock - clock2) > clock_tolerance)
2978 continue;
2979
2980 do {
2981 if (drm_mode_match(to_match, &cea_mode, match_flags))
2982 return vic;
2983 } while (cea_mode_alternate_timings(vic, &cea_mode));
2984 }
2985
2986 return 0;
2987 }
2988
2989 /**
2990 * drm_match_cea_mode - look for a CEA mode matching given mode
2991 * @to_match: display mode
2992 *
2993 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2994 * mode.
2995 */
2996 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2997 {
2998 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2999 u8 vic;
3000
3001 if (!to_match->clock)
3002 return 0;
3003
3004 if (to_match->picture_aspect_ratio)
3005 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3006
3007 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3008 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3009 unsigned int clock1, clock2;
3010
3011 /* Check both 60Hz and 59.94Hz */
3012 clock1 = cea_mode.clock;
3013 clock2 = cea_mode_alternate_clock(&cea_mode);
3014
3015 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3016 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3017 continue;
3018
3019 do {
3020 if (drm_mode_match(to_match, &cea_mode, match_flags))
3021 return vic;
3022 } while (cea_mode_alternate_timings(vic, &cea_mode));
3023 }
3024
3025 return 0;
3026 }
3027 EXPORT_SYMBOL(drm_match_cea_mode);
3028
3029 static bool drm_valid_cea_vic(u8 vic)
3030 {
3031 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3032 }
3033
3034 /**
3035 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3036 * the input VIC from the CEA mode list
3037 * @video_code: ID given to each of the CEA modes
3038 *
3039 * Returns picture aspect ratio
3040 */
3041 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3042 {
3043 return edid_cea_modes[video_code].picture_aspect_ratio;
3044 }
3045 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3046
3047 /*
3048 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3049 * specific block).
3050 *
3051 * It's almost like cea_mode_alternate_clock(), we just need to add an
3052 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3053 * one.
3054 */
3055 static unsigned int
3056 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3057 {
3058 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3059 return hdmi_mode->clock;
3060
3061 return cea_mode_alternate_clock(hdmi_mode);
3062 }
3063
3064 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3065 unsigned int clock_tolerance)
3066 {
3067 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3068 u8 vic;
3069
3070 if (!to_match->clock)
3071 return 0;
3072
3073 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3074 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3075 unsigned int clock1, clock2;
3076
3077 /* Make sure to also match alternate clocks */
3078 clock1 = hdmi_mode->clock;
3079 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3080
3081 if (abs(to_match->clock - clock1) > clock_tolerance &&
3082 abs(to_match->clock - clock2) > clock_tolerance)
3083 continue;
3084
3085 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3086 return vic;
3087 }
3088
3089 return 0;
3090 }
3091
3092 /*
3093 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3094 * @to_match: display mode
3095 *
3096 * An HDMI mode is one defined in the HDMI vendor specific block.
3097 *
3098 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3099 */
3100 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3101 {
3102 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3103 u8 vic;
3104
3105 if (!to_match->clock)
3106 return 0;
3107
3108 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3109 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3110 unsigned int clock1, clock2;
3111
3112 /* Make sure to also match alternate clocks */
3113 clock1 = hdmi_mode->clock;
3114 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3115
3116 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3117 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3118 drm_mode_match(to_match, hdmi_mode, match_flags))
3119 return vic;
3120 }
3121 return 0;
3122 }
3123
3124 static bool drm_valid_hdmi_vic(u8 vic)
3125 {
3126 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3127 }
3128
3129 static int
3130 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3131 {
3132 struct drm_device *dev = connector->dev;
3133 struct drm_display_mode *mode, *tmp;
3134 LIST_HEAD(list);
3135 int modes = 0;
3136
3137 /* Don't add CEA modes if the CEA extension block is missing */
3138 if (!drm_find_cea_extension(edid))
3139 return 0;
3140
3141 /*
3142 * Go through all probed modes and create a new mode
3143 * with the alternate clock for certain CEA modes.
3144 */
3145 list_for_each_entry(mode, &connector->probed_modes, head) {
3146 const struct drm_display_mode *cea_mode = NULL;
3147 struct drm_display_mode *newmode;
3148 u8 vic = drm_match_cea_mode(mode);
3149 unsigned int clock1, clock2;
3150
3151 if (drm_valid_cea_vic(vic)) {
3152 cea_mode = &edid_cea_modes[vic];
3153 clock2 = cea_mode_alternate_clock(cea_mode);
3154 } else {
3155 vic = drm_match_hdmi_mode(mode);
3156 if (drm_valid_hdmi_vic(vic)) {
3157 cea_mode = &edid_4k_modes[vic];
3158 clock2 = hdmi_mode_alternate_clock(cea_mode);
3159 }
3160 }
3161
3162 if (!cea_mode)
3163 continue;
3164
3165 clock1 = cea_mode->clock;
3166
3167 if (clock1 == clock2)
3168 continue;
3169
3170 if (mode->clock != clock1 && mode->clock != clock2)
3171 continue;
3172
3173 newmode = drm_mode_duplicate(dev, cea_mode);
3174 if (!newmode)
3175 continue;
3176
3177 /* Carry over the stereo flags */
3178 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3179
3180 /*
3181 * The current mode could be either variant. Make
3182 * sure to pick the "other" clock for the new mode.
3183 */
3184 if (mode->clock != clock1)
3185 newmode->clock = clock1;
3186 else
3187 newmode->clock = clock2;
3188
3189 list_add_tail(&newmode->head, &list);
3190 }
3191
3192 list_for_each_entry_safe(mode, tmp, &list, head) {
3193 list_del(&mode->head);
3194 drm_mode_probed_add(connector, mode);
3195 modes++;
3196 }
3197
3198 return modes;
3199 }
3200
3201 static u8 svd_to_vic(u8 svd)
3202 {
3203 /* 0-6 bit vic, 7th bit native mode indicator */
3204 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3205 return svd & 127;
3206
3207 return svd;
3208 }
3209
3210 static struct drm_display_mode *
3211 drm_display_mode_from_vic_index(struct drm_connector *connector,
3212 const u8 *video_db, u8 video_len,
3213 u8 video_index)
3214 {
3215 struct drm_device *dev = connector->dev;
3216 struct drm_display_mode *newmode;
3217 u8 vic;
3218
3219 if (video_db == NULL || video_index >= video_len)
3220 return NULL;
3221
3222 /* CEA modes are numbered 1..127 */
3223 vic = svd_to_vic(video_db[video_index]);
3224 if (!drm_valid_cea_vic(vic))
3225 return NULL;
3226
3227 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3228 if (!newmode)
3229 return NULL;
3230
3231 newmode->vrefresh = 0;
3232
3233 return newmode;
3234 }
3235
3236 /*
3237 * do_y420vdb_modes - Parse YCBCR 420 only modes
3238 * @connector: connector corresponding to the HDMI sink
3239 * @svds: start of the data block of CEA YCBCR 420 VDB
3240 * @len: length of the CEA YCBCR 420 VDB
3241 *
3242 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3243 * which contains modes which can be supported in YCBCR 420
3244 * output format only.
3245 */
3246 static int do_y420vdb_modes(struct drm_connector *connector,
3247 const u8 *svds, u8 svds_len)
3248 {
3249 int modes = 0, i;
3250 struct drm_device *dev = connector->dev;
3251 struct drm_display_info *info = &connector->display_info;
3252 struct drm_hdmi_info *hdmi = &info->hdmi;
3253
3254 for (i = 0; i < svds_len; i++) {
3255 u8 vic = svd_to_vic(svds[i]);
3256 struct drm_display_mode *newmode;
3257
3258 if (!drm_valid_cea_vic(vic))
3259 continue;
3260
3261 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3262 if (!newmode)
3263 break;
3264 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3265 drm_mode_probed_add(connector, newmode);
3266 modes++;
3267 }
3268
3269 if (modes > 0)
3270 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3271 return modes;
3272 }
3273
3274 /*
3275 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3276 * @connector: connector corresponding to the HDMI sink
3277 * @vic: CEA vic for the video mode to be added in the map
3278 *
3279 * Makes an entry for a videomode in the YCBCR 420 bitmap
3280 */
3281 static void
3282 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3283 {
3284 u8 vic = svd_to_vic(svd);
3285 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3286
3287 if (!drm_valid_cea_vic(vic))
3288 return;
3289
3290 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3291 }
3292
3293 static int
3294 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3295 {
3296 int i, modes = 0;
3297 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3298
3299 for (i = 0; i < len; i++) {
3300 struct drm_display_mode *mode;
3301 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3302 if (mode) {
3303 /*
3304 * YCBCR420 capability block contains a bitmap which
3305 * gives the index of CEA modes from CEA VDB, which
3306 * can support YCBCR 420 sampling output also (apart
3307 * from RGB/YCBCR444 etc).
3308 * For example, if the bit 0 in bitmap is set,
3309 * first mode in VDB can support YCBCR420 output too.
3310 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3311 */
3312 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3313 drm_add_cmdb_modes(connector, db[i]);
3314
3315 drm_mode_probed_add(connector, mode);
3316 modes++;
3317 }
3318 }
3319
3320 return modes;
3321 }
3322
3323 struct stereo_mandatory_mode {
3324 int width, height, vrefresh;
3325 unsigned int flags;
3326 };
3327
3328 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3329 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3330 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3331 { 1920, 1080, 50,
3332 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3333 { 1920, 1080, 60,
3334 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3335 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3336 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3337 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3338 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3339 };
3340
3341 static bool
3342 stereo_match_mandatory(const struct drm_display_mode *mode,
3343 const struct stereo_mandatory_mode *stereo_mode)
3344 {
3345 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3346
3347 return mode->hdisplay == stereo_mode->width &&
3348 mode->vdisplay == stereo_mode->height &&
3349 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3350 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3351 }
3352
3353 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3354 {
3355 struct drm_device *dev = connector->dev;
3356 const struct drm_display_mode *mode;
3357 struct list_head stereo_modes;
3358 int modes = 0, i;
3359
3360 INIT_LIST_HEAD(&stereo_modes);
3361
3362 list_for_each_entry(mode, &connector->probed_modes, head) {
3363 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3364 const struct stereo_mandatory_mode *mandatory;
3365 struct drm_display_mode *new_mode;
3366
3367 if (!stereo_match_mandatory(mode,
3368 &stereo_mandatory_modes[i]))
3369 continue;
3370
3371 mandatory = &stereo_mandatory_modes[i];
3372 new_mode = drm_mode_duplicate(dev, mode);
3373 if (!new_mode)
3374 continue;
3375
3376 new_mode->flags |= mandatory->flags;
3377 list_add_tail(&new_mode->head, &stereo_modes);
3378 modes++;
3379 }
3380 }
3381
3382 list_splice_tail(&stereo_modes, &connector->probed_modes);
3383
3384 return modes;
3385 }
3386
3387 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3388 {
3389 struct drm_device *dev = connector->dev;
3390 struct drm_display_mode *newmode;
3391
3392 if (!drm_valid_hdmi_vic(vic)) {
3393 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3394 return 0;
3395 }
3396
3397 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3398 if (!newmode)
3399 return 0;
3400
3401 drm_mode_probed_add(connector, newmode);
3402
3403 return 1;
3404 }
3405
3406 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3407 const u8 *video_db, u8 video_len, u8 video_index)
3408 {
3409 struct drm_display_mode *newmode;
3410 int modes = 0;
3411
3412 if (structure & (1 << 0)) {
3413 newmode = drm_display_mode_from_vic_index(connector, video_db,
3414 video_len,
3415 video_index);
3416 if (newmode) {
3417 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3418 drm_mode_probed_add(connector, newmode);
3419 modes++;
3420 }
3421 }
3422 if (structure & (1 << 6)) {
3423 newmode = drm_display_mode_from_vic_index(connector, video_db,
3424 video_len,
3425 video_index);
3426 if (newmode) {
3427 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3428 drm_mode_probed_add(connector, newmode);
3429 modes++;
3430 }
3431 }
3432 if (structure & (1 << 8)) {
3433 newmode = drm_display_mode_from_vic_index(connector, video_db,
3434 video_len,
3435 video_index);
3436 if (newmode) {
3437 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3438 drm_mode_probed_add(connector, newmode);
3439 modes++;
3440 }
3441 }
3442
3443 return modes;
3444 }
3445
3446 /*
3447 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3448 * @connector: connector corresponding to the HDMI sink
3449 * @db: start of the CEA vendor specific block
3450 * @len: length of the CEA block payload, ie. one can access up to db[len]
3451 *
3452 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3453 * also adds the stereo 3d modes when applicable.
3454 */
3455 static int
3456 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3457 const u8 *video_db, u8 video_len)
3458 {
3459 struct drm_display_info *info = &connector->display_info;
3460 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3461 u8 vic_len, hdmi_3d_len = 0;
3462 u16 mask;
3463 u16 structure_all;
3464
3465 if (len < 8)
3466 goto out;
3467
3468 /* no HDMI_Video_Present */
3469 if (!(db[8] & (1 << 5)))
3470 goto out;
3471
3472 /* Latency_Fields_Present */
3473 if (db[8] & (1 << 7))
3474 offset += 2;
3475
3476 /* I_Latency_Fields_Present */
3477 if (db[8] & (1 << 6))
3478 offset += 2;
3479
3480 /* the declared length is not long enough for the 2 first bytes
3481 * of additional video format capabilities */
3482 if (len < (8 + offset + 2))
3483 goto out;
3484
3485 /* 3D_Present */
3486 offset++;
3487 if (db[8 + offset] & (1 << 7)) {
3488 modes += add_hdmi_mandatory_stereo_modes(connector);
3489
3490 /* 3D_Multi_present */
3491 multi_present = (db[8 + offset] & 0x60) >> 5;
3492 }
3493
3494 offset++;
3495 vic_len = db[8 + offset] >> 5;
3496 hdmi_3d_len = db[8 + offset] & 0x1f;
3497
3498 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3499 u8 vic;
3500
3501 vic = db[9 + offset + i];
3502 modes += add_hdmi_mode(connector, vic);
3503 }
3504 offset += 1 + vic_len;
3505
3506 if (multi_present == 1)
3507 multi_len = 2;
3508 else if (multi_present == 2)
3509 multi_len = 4;
3510 else
3511 multi_len = 0;
3512
3513 if (len < (8 + offset + hdmi_3d_len - 1))
3514 goto out;
3515
3516 if (hdmi_3d_len < multi_len)
3517 goto out;
3518
3519 if (multi_present == 1 || multi_present == 2) {
3520 /* 3D_Structure_ALL */
3521 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3522
3523 /* check if 3D_MASK is present */
3524 if (multi_present == 2)
3525 mask = (db[10 + offset] << 8) | db[11 + offset];
3526 else
3527 mask = 0xffff;
3528
3529 for (i = 0; i < 16; i++) {
3530 if (mask & (1 << i))
3531 modes += add_3d_struct_modes(connector,
3532 structure_all,
3533 video_db,
3534 video_len, i);
3535 }
3536 }
3537
3538 offset += multi_len;
3539
3540 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3541 int vic_index;
3542 struct drm_display_mode *newmode = NULL;
3543 unsigned int newflag = 0;
3544 bool detail_present;
3545
3546 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3547
3548 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3549 break;
3550
3551 /* 2D_VIC_order_X */
3552 vic_index = db[8 + offset + i] >> 4;
3553
3554 /* 3D_Structure_X */
3555 switch (db[8 + offset + i] & 0x0f) {
3556 case 0:
3557 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3558 break;
3559 case 6:
3560 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3561 break;
3562 case 8:
3563 /* 3D_Detail_X */
3564 if ((db[9 + offset + i] >> 4) == 1)
3565 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3566 break;
3567 }
3568
3569 if (newflag != 0) {
3570 newmode = drm_display_mode_from_vic_index(connector,
3571 video_db,
3572 video_len,
3573 vic_index);
3574
3575 if (newmode) {
3576 newmode->flags |= newflag;
3577 drm_mode_probed_add(connector, newmode);
3578 modes++;
3579 }
3580 }
3581
3582 if (detail_present)
3583 i++;
3584 }
3585
3586 out:
3587 if (modes > 0)
3588 info->has_hdmi_infoframe = true;
3589 return modes;
3590 }
3591
3592 static int
3593 cea_db_payload_len(const u8 *db)
3594 {
3595 return db[0] & 0x1f;
3596 }
3597
3598 static int
3599 cea_db_extended_tag(const u8 *db)
3600 {
3601 return db[1];
3602 }
3603
3604 static int
3605 cea_db_tag(const u8 *db)
3606 {
3607 return db[0] >> 5;
3608 }
3609
3610 static int
3611 cea_revision(const u8 *cea)
3612 {
3613 return cea[1];
3614 }
3615
3616 static int
3617 cea_db_offsets(const u8 *cea, int *start, int *end)
3618 {
3619 /* Data block offset in CEA extension block */
3620 *start = 4;
3621 *end = cea[2];
3622 if (*end == 0)
3623 *end = 127;
3624 if (*end < 4 || *end > 127)
3625 return -ERANGE;
3626 return 0;
3627 }
3628
3629 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3630 {
3631 int hdmi_id;
3632
3633 if (cea_db_tag(db) != VENDOR_BLOCK)
3634 return false;
3635
3636 if (cea_db_payload_len(db) < 5)
3637 return false;
3638
3639 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3640
3641 return hdmi_id == HDMI_IEEE_OUI;
3642 }
3643
3644 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3645 {
3646 unsigned int oui;
3647
3648 if (cea_db_tag(db) != VENDOR_BLOCK)
3649 return false;
3650
3651 if (cea_db_payload_len(db) < 7)
3652 return false;
3653
3654 oui = db[3] << 16 | db[2] << 8 | db[1];
3655
3656 return oui == HDMI_FORUM_IEEE_OUI;
3657 }
3658
3659 static bool cea_db_is_vcdb(const u8 *db)
3660 {
3661 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3662 return false;
3663
3664 if (cea_db_payload_len(db) != 2)
3665 return false;
3666
3667 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
3668 return false;
3669
3670 return true;
3671 }
3672
3673 static bool cea_db_is_y420cmdb(const u8 *db)
3674 {
3675 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3676 return false;
3677
3678 if (!cea_db_payload_len(db))
3679 return false;
3680
3681 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3682 return false;
3683
3684 return true;
3685 }
3686
3687 static bool cea_db_is_y420vdb(const u8 *db)
3688 {
3689 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3690 return false;
3691
3692 if (!cea_db_payload_len(db))
3693 return false;
3694
3695 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3696 return false;
3697
3698 return true;
3699 }
3700
3701 #define for_each_cea_db(cea, i, start, end) \
3702 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3703
3704 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3705 const u8 *db)
3706 {
3707 struct drm_display_info *info = &connector->display_info;
3708 struct drm_hdmi_info *hdmi = &info->hdmi;
3709 u8 map_len = cea_db_payload_len(db) - 1;
3710 u8 count;
3711 u64 map = 0;
3712
3713 if (map_len == 0) {
3714 /* All CEA modes support ycbcr420 sampling also.*/
3715 hdmi->y420_cmdb_map = U64_MAX;
3716 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3717 return;
3718 }
3719
3720 /*
3721 * This map indicates which of the existing CEA block modes
3722 * from VDB can support YCBCR420 output too. So if bit=0 is
3723 * set, first mode from VDB can support YCBCR420 output too.
3724 * We will parse and keep this map, before parsing VDB itself
3725 * to avoid going through the same block again and again.
3726 *
3727 * Spec is not clear about max possible size of this block.
3728 * Clamping max bitmap block size at 8 bytes. Every byte can
3729 * address 8 CEA modes, in this way this map can address
3730 * 8*8 = first 64 SVDs.
3731 */
3732 if (WARN_ON_ONCE(map_len > 8))
3733 map_len = 8;
3734
3735 for (count = 0; count < map_len; count++)
3736 map |= (u64)db[2 + count] << (8 * count);
3737
3738 if (map)
3739 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3740
3741 hdmi->y420_cmdb_map = map;
3742 }
3743
3744 static int
3745 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3746 {
3747 const u8 *cea = drm_find_cea_extension(edid);
3748 const u8 *db, *hdmi = NULL, *video = NULL;
3749 u8 dbl, hdmi_len, video_len = 0;
3750 int modes = 0;
3751
3752 if (cea && cea_revision(cea) >= 3) {
3753 int i, start, end;
3754
3755 if (cea_db_offsets(cea, &start, &end))
3756 return 0;
3757
3758 for_each_cea_db(cea, i, start, end) {
3759 db = &cea[i];
3760 dbl = cea_db_payload_len(db);
3761
3762 if (cea_db_tag(db) == VIDEO_BLOCK) {
3763 video = db + 1;
3764 video_len = dbl;
3765 modes += do_cea_modes(connector, video, dbl);
3766 } else if (cea_db_is_hdmi_vsdb(db)) {
3767 hdmi = db;
3768 hdmi_len = dbl;
3769 } else if (cea_db_is_y420vdb(db)) {
3770 const u8 *vdb420 = &db[2];
3771
3772 /* Add 4:2:0(only) modes present in EDID */
3773 modes += do_y420vdb_modes(connector,
3774 vdb420,
3775 dbl - 1);
3776 }
3777 }
3778 }
3779
3780 /*
3781 * We parse the HDMI VSDB after having added the cea modes as we will
3782 * be patching their flags when the sink supports stereo 3D.
3783 */
3784 if (hdmi)
3785 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3786 video_len);
3787
3788 return modes;
3789 }
3790
3791 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3792 {
3793 const struct drm_display_mode *cea_mode;
3794 int clock1, clock2, clock;
3795 u8 vic;
3796 const char *type;
3797
3798 /*
3799 * allow 5kHz clock difference either way to account for
3800 * the 10kHz clock resolution limit of detailed timings.
3801 */
3802 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3803 if (drm_valid_cea_vic(vic)) {
3804 type = "CEA";
3805 cea_mode = &edid_cea_modes[vic];
3806 clock1 = cea_mode->clock;
3807 clock2 = cea_mode_alternate_clock(cea_mode);
3808 } else {
3809 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3810 if (drm_valid_hdmi_vic(vic)) {
3811 type = "HDMI";
3812 cea_mode = &edid_4k_modes[vic];
3813 clock1 = cea_mode->clock;
3814 clock2 = hdmi_mode_alternate_clock(cea_mode);
3815 } else {
3816 return;
3817 }
3818 }
3819
3820 /* pick whichever is closest */
3821 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3822 clock = clock1;
3823 else
3824 clock = clock2;
3825
3826 if (mode->clock == clock)
3827 return;
3828
3829 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3830 type, vic, mode->clock, clock);
3831 mode->clock = clock;
3832 }
3833
3834 static void
3835 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3836 {
3837 u8 len = cea_db_payload_len(db);
3838
3839 if (len >= 6 && (db[6] & (1 << 7)))
3840 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3841 if (len >= 8) {
3842 connector->latency_present[0] = db[8] >> 7;
3843 connector->latency_present[1] = (db[8] >> 6) & 1;
3844 }
3845 if (len >= 9)
3846 connector->video_latency[0] = db[9];
3847 if (len >= 10)
3848 connector->audio_latency[0] = db[10];
3849 if (len >= 11)
3850 connector->video_latency[1] = db[11];
3851 if (len >= 12)
3852 connector->audio_latency[1] = db[12];
3853
3854 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3855 "video latency %d %d, "
3856 "audio latency %d %d\n",
3857 connector->latency_present[0],
3858 connector->latency_present[1],
3859 connector->video_latency[0],
3860 connector->video_latency[1],
3861 connector->audio_latency[0],
3862 connector->audio_latency[1]);
3863 }
3864
3865 static void
3866 monitor_name(struct detailed_timing *t, void *data)
3867 {
3868 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3869 *(u8 **)data = t->data.other_data.data.str.str;
3870 }
3871
3872 static int get_monitor_name(struct edid *edid, char name[13])
3873 {
3874 char *edid_name = NULL;
3875 int mnl;
3876
3877 if (!edid || !name)
3878 return 0;
3879
3880 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3881 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3882 if (edid_name[mnl] == 0x0a)
3883 break;
3884
3885 name[mnl] = edid_name[mnl];
3886 }
3887
3888 return mnl;
3889 }
3890
3891 /**
3892 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3893 * @edid: monitor EDID information
3894 * @name: pointer to a character array to hold the name of the monitor
3895 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3896 *
3897 */
3898 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3899 {
3900 int name_length;
3901 char buf[13];
3902
3903 if (bufsize <= 0)
3904 return;
3905
3906 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3907 memcpy(name, buf, name_length);
3908 name[name_length] = '\0';
3909 }
3910 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3911
3912 static void clear_eld(struct drm_connector *connector)
3913 {
3914 memset(connector->eld, 0, sizeof(connector->eld));
3915
3916 connector->latency_present[0] = false;
3917 connector->latency_present[1] = false;
3918 connector->video_latency[0] = 0;
3919 connector->audio_latency[0] = 0;
3920 connector->video_latency[1] = 0;
3921 connector->audio_latency[1] = 0;
3922 }
3923
3924 /*
3925 * drm_edid_to_eld - build ELD from EDID
3926 * @connector: connector corresponding to the HDMI/DP sink
3927 * @edid: EDID to parse
3928 *
3929 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3930 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3931 */
3932 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3933 {
3934 uint8_t *eld = connector->eld;
3935 u8 *cea;
3936 u8 *db;
3937 int total_sad_count = 0;
3938 int mnl;
3939 int dbl;
3940
3941 clear_eld(connector);
3942
3943 if (!edid)
3944 return;
3945
3946 cea = drm_find_cea_extension(edid);
3947 if (!cea) {
3948 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3949 return;
3950 }
3951
3952 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3953 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
3954
3955 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3956 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
3957
3958 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
3959
3960 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
3961 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
3962 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
3963 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
3964
3965 if (cea_revision(cea) >= 3) {
3966 int i, start, end;
3967
3968 if (cea_db_offsets(cea, &start, &end)) {
3969 start = 0;
3970 end = 0;
3971 }
3972
3973 for_each_cea_db(cea, i, start, end) {
3974 db = &cea[i];
3975 dbl = cea_db_payload_len(db);
3976
3977 switch (cea_db_tag(db)) {
3978 int sad_count;
3979
3980 case AUDIO_BLOCK:
3981 /* Audio Data Block, contains SADs */
3982 sad_count = min(dbl / 3, 15 - total_sad_count);
3983 if (sad_count >= 1)
3984 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
3985 &db[1], sad_count * 3);
3986 total_sad_count += sad_count;
3987 break;
3988 case SPEAKER_BLOCK:
3989 /* Speaker Allocation Data Block */
3990 if (dbl >= 1)
3991 eld[DRM_ELD_SPEAKER] = db[1];
3992 break;
3993 case VENDOR_BLOCK:
3994 /* HDMI Vendor-Specific Data Block */
3995 if (cea_db_is_hdmi_vsdb(db))
3996 drm_parse_hdmi_vsdb_audio(connector, db);
3997 break;
3998 default:
3999 break;
4000 }
4001 }
4002 }
4003 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4004
4005 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4006 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4007 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4008 else
4009 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4010
4011 eld[DRM_ELD_BASELINE_ELD_LEN] =
4012 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4013
4014 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4015 drm_eld_size(eld), total_sad_count);
4016 }
4017
4018 /**
4019 * drm_edid_to_sad - extracts SADs from EDID
4020 * @edid: EDID to parse
4021 * @sads: pointer that will be set to the extracted SADs
4022 *
4023 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4024 *
4025 * Note: The returned pointer needs to be freed using kfree().
4026 *
4027 * Return: The number of found SADs or negative number on error.
4028 */
4029 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4030 {
4031 int count = 0;
4032 int i, start, end, dbl;
4033 u8 *cea;
4034
4035 cea = drm_find_cea_extension(edid);
4036 if (!cea) {
4037 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4038 return -ENOENT;
4039 }
4040
4041 if (cea_revision(cea) < 3) {
4042 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4043 return -ENOTSUPP;
4044 }
4045
4046 if (cea_db_offsets(cea, &start, &end)) {
4047 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4048 return -EPROTO;
4049 }
4050
4051 for_each_cea_db(cea, i, start, end) {
4052 u8 *db = &cea[i];
4053
4054 if (cea_db_tag(db) == AUDIO_BLOCK) {
4055 int j;
4056 dbl = cea_db_payload_len(db);
4057
4058 count = dbl / 3; /* SAD is 3B */
4059 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4060 if (!*sads)
4061 return -ENOMEM;
4062 for (j = 0; j < count; j++) {
4063 u8 *sad = &db[1 + j * 3];
4064
4065 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4066 (*sads)[j].channels = sad[0] & 0x7;
4067 (*sads)[j].freq = sad[1] & 0x7F;
4068 (*sads)[j].byte2 = sad[2];
4069 }
4070 break;
4071 }
4072 }
4073
4074 return count;
4075 }
4076 EXPORT_SYMBOL(drm_edid_to_sad);
4077
4078 /**
4079 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4080 * @edid: EDID to parse
4081 * @sadb: pointer to the speaker block
4082 *
4083 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4084 *
4085 * Note: The returned pointer needs to be freed using kfree().
4086 *
4087 * Return: The number of found Speaker Allocation Blocks or negative number on
4088 * error.
4089 */
4090 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4091 {
4092 int count = 0;
4093 int i, start, end, dbl;
4094 const u8 *cea;
4095
4096 cea = drm_find_cea_extension(edid);
4097 if (!cea) {
4098 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4099 return -ENOENT;
4100 }
4101
4102 if (cea_revision(cea) < 3) {
4103 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4104 return -ENOTSUPP;
4105 }
4106
4107 if (cea_db_offsets(cea, &start, &end)) {
4108 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4109 return -EPROTO;
4110 }
4111
4112 for_each_cea_db(cea, i, start, end) {
4113 const u8 *db = &cea[i];
4114
4115 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4116 dbl = cea_db_payload_len(db);
4117
4118 /* Speaker Allocation Data Block */
4119 if (dbl == 3) {
4120 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4121 if (!*sadb)
4122 return -ENOMEM;
4123 count = dbl;
4124 break;
4125 }
4126 }
4127 }
4128
4129 return count;
4130 }
4131 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4132
4133 /**
4134 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4135 * @connector: connector associated with the HDMI/DP sink
4136 * @mode: the display mode
4137 *
4138 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4139 * the sink doesn't support audio or video.
4140 */
4141 int drm_av_sync_delay(struct drm_connector *connector,
4142 const struct drm_display_mode *mode)
4143 {
4144 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4145 int a, v;
4146
4147 if (!connector->latency_present[0])
4148 return 0;
4149 if (!connector->latency_present[1])
4150 i = 0;
4151
4152 a = connector->audio_latency[i];
4153 v = connector->video_latency[i];
4154
4155 /*
4156 * HDMI/DP sink doesn't support audio or video?
4157 */
4158 if (a == 255 || v == 255)
4159 return 0;
4160
4161 /*
4162 * Convert raw EDID values to millisecond.
4163 * Treat unknown latency as 0ms.
4164 */
4165 if (a)
4166 a = min(2 * (a - 1), 500);
4167 if (v)
4168 v = min(2 * (v - 1), 500);
4169
4170 return max(v - a, 0);
4171 }
4172 EXPORT_SYMBOL(drm_av_sync_delay);
4173
4174 /**
4175 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4176 * @edid: monitor EDID information
4177 *
4178 * Parse the CEA extension according to CEA-861-B.
4179 *
4180 * Return: True if the monitor is HDMI, false if not or unknown.
4181 */
4182 bool drm_detect_hdmi_monitor(struct edid *edid)
4183 {
4184 u8 *edid_ext;
4185 int i;
4186 int start_offset, end_offset;
4187
4188 edid_ext = drm_find_cea_extension(edid);
4189 if (!edid_ext)
4190 return false;
4191
4192 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4193 return false;
4194
4195 /*
4196 * Because HDMI identifier is in Vendor Specific Block,
4197 * search it from all data blocks of CEA extension.
4198 */
4199 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4200 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4201 return true;
4202 }
4203
4204 return false;
4205 }
4206 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4207
4208 /**
4209 * drm_detect_monitor_audio - check monitor audio capability
4210 * @edid: EDID block to scan
4211 *
4212 * Monitor should have CEA extension block.
4213 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4214 * audio' only. If there is any audio extension block and supported
4215 * audio format, assume at least 'basic audio' support, even if 'basic
4216 * audio' is not defined in EDID.
4217 *
4218 * Return: True if the monitor supports audio, false otherwise.
4219 */
4220 bool drm_detect_monitor_audio(struct edid *edid)
4221 {
4222 u8 *edid_ext;
4223 int i, j;
4224 bool has_audio = false;
4225 int start_offset, end_offset;
4226
4227 edid_ext = drm_find_cea_extension(edid);
4228 if (!edid_ext)
4229 goto end;
4230
4231 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4232
4233 if (has_audio) {
4234 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4235 goto end;
4236 }
4237
4238 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4239 goto end;
4240
4241 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4242 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4243 has_audio = true;
4244 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4245 DRM_DEBUG_KMS("CEA audio format %d\n",
4246 (edid_ext[i + j] >> 3) & 0xf);
4247 goto end;
4248 }
4249 }
4250 end:
4251 return has_audio;
4252 }
4253 EXPORT_SYMBOL(drm_detect_monitor_audio);
4254
4255
4256 /**
4257 * drm_default_rgb_quant_range - default RGB quantization range
4258 * @mode: display mode
4259 *
4260 * Determine the default RGB quantization range for the mode,
4261 * as specified in CEA-861.
4262 *
4263 * Return: The default RGB quantization range for the mode
4264 */
4265 enum hdmi_quantization_range
4266 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4267 {
4268 /* All CEA modes other than VIC 1 use limited quantization range. */
4269 return drm_match_cea_mode(mode) > 1 ?
4270 HDMI_QUANTIZATION_RANGE_LIMITED :
4271 HDMI_QUANTIZATION_RANGE_FULL;
4272 }
4273 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4274
4275 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4276 {
4277 struct drm_display_info *info = &connector->display_info;
4278
4279 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4280
4281 if (db[2] & EDID_CEA_VCDB_QS)
4282 info->rgb_quant_range_selectable = true;
4283 }
4284
4285 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4286 const u8 *db)
4287 {
4288 u8 dc_mask;
4289 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4290
4291 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4292 hdmi->y420_dc_modes = dc_mask;
4293 }
4294
4295 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4296 const u8 *hf_vsdb)
4297 {
4298 struct drm_display_info *display = &connector->display_info;
4299 struct drm_hdmi_info *hdmi = &display->hdmi;
4300
4301 display->has_hdmi_infoframe = true;
4302
4303 if (hf_vsdb[6] & 0x80) {
4304 hdmi->scdc.supported = true;
4305 if (hf_vsdb[6] & 0x40)
4306 hdmi->scdc.read_request = true;
4307 }
4308
4309 /*
4310 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4311 * And as per the spec, three factors confirm this:
4312 * * Availability of a HF-VSDB block in EDID (check)
4313 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4314 * * SCDC support available (let's check)
4315 * Lets check it out.
4316 */
4317
4318 if (hf_vsdb[5]) {
4319 /* max clock is 5000 KHz times block value */
4320 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4321 struct drm_scdc *scdc = &hdmi->scdc;
4322
4323 if (max_tmds_clock > 340000) {
4324 display->max_tmds_clock = max_tmds_clock;
4325 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4326 display->max_tmds_clock);
4327 }
4328
4329 if (scdc->supported) {
4330 scdc->scrambling.supported = true;
4331
4332 /* Few sinks support scrambling for cloks < 340M */
4333 if ((hf_vsdb[6] & 0x8))
4334 scdc->scrambling.low_rates = true;
4335 }
4336 }
4337
4338 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4339 }
4340
4341 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4342 const u8 *hdmi)
4343 {
4344 struct drm_display_info *info = &connector->display_info;
4345 unsigned int dc_bpc = 0;
4346
4347 /* HDMI supports at least 8 bpc */
4348 info->bpc = 8;
4349
4350 if (cea_db_payload_len(hdmi) < 6)
4351 return;
4352
4353 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4354 dc_bpc = 10;
4355 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4356 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4357 connector->name);
4358 }
4359
4360 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4361 dc_bpc = 12;
4362 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4363 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4364 connector->name);
4365 }
4366
4367 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4368 dc_bpc = 16;
4369 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4370 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4371 connector->name);
4372 }
4373
4374 if (dc_bpc == 0) {
4375 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4376 connector->name);
4377 return;
4378 }
4379
4380 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4381 connector->name, dc_bpc);
4382 info->bpc = dc_bpc;
4383
4384 /*
4385 * Deep color support mandates RGB444 support for all video
4386 * modes and forbids YCRCB422 support for all video modes per
4387 * HDMI 1.3 spec.
4388 */
4389 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4390
4391 /* YCRCB444 is optional according to spec. */
4392 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4393 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4394 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4395 connector->name);
4396 }
4397
4398 /*
4399 * Spec says that if any deep color mode is supported at all,
4400 * then deep color 36 bit must be supported.
4401 */
4402 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4403 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4404 connector->name);
4405 }
4406 }
4407
4408 static void
4409 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4410 {
4411 struct drm_display_info *info = &connector->display_info;
4412 u8 len = cea_db_payload_len(db);
4413
4414 if (len >= 6)
4415 info->dvi_dual = db[6] & 1;
4416 if (len >= 7)
4417 info->max_tmds_clock = db[7] * 5000;
4418
4419 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4420 "max TMDS clock %d kHz\n",
4421 info->dvi_dual,
4422 info->max_tmds_clock);
4423
4424 drm_parse_hdmi_deep_color_info(connector, db);
4425 }
4426
4427 static void drm_parse_cea_ext(struct drm_connector *connector,
4428 const struct edid *edid)
4429 {
4430 struct drm_display_info *info = &connector->display_info;
4431 const u8 *edid_ext;
4432 int i, start, end;
4433
4434 edid_ext = drm_find_cea_extension(edid);
4435 if (!edid_ext)
4436 return;
4437
4438 info->cea_rev = edid_ext[1];
4439
4440 /* The existence of a CEA block should imply RGB support */
4441 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4442 if (edid_ext[3] & EDID_CEA_YCRCB444)
4443 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4444 if (edid_ext[3] & EDID_CEA_YCRCB422)
4445 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4446
4447 if (cea_db_offsets(edid_ext, &start, &end))
4448 return;
4449
4450 for_each_cea_db(edid_ext, i, start, end) {
4451 const u8 *db = &edid_ext[i];
4452
4453 if (cea_db_is_hdmi_vsdb(db))
4454 drm_parse_hdmi_vsdb_video(connector, db);
4455 if (cea_db_is_hdmi_forum_vsdb(db))
4456 drm_parse_hdmi_forum_vsdb(connector, db);
4457 if (cea_db_is_y420cmdb(db))
4458 drm_parse_y420cmdb_bitmap(connector, db);
4459 if (cea_db_is_vcdb(db))
4460 drm_parse_vcdb(connector, db);
4461 }
4462 }
4463
4464 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4465 * all of the values which would have been set from EDID
4466 */
4467 void
4468 drm_reset_display_info(struct drm_connector *connector)
4469 {
4470 struct drm_display_info *info = &connector->display_info;
4471
4472 info->width_mm = 0;
4473 info->height_mm = 0;
4474
4475 info->bpc = 0;
4476 info->color_formats = 0;
4477 info->cea_rev = 0;
4478 info->max_tmds_clock = 0;
4479 info->dvi_dual = false;
4480 info->has_hdmi_infoframe = false;
4481 info->rgb_quant_range_selectable = false;
4482 memset(&info->hdmi, 0, sizeof(info->hdmi));
4483
4484 info->non_desktop = 0;
4485 }
4486
4487 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4488 {
4489 struct drm_display_info *info = &connector->display_info;
4490
4491 u32 quirks = edid_get_quirks(edid);
4492
4493 drm_reset_display_info(connector);
4494
4495 info->width_mm = edid->width_cm * 10;
4496 info->height_mm = edid->height_cm * 10;
4497
4498 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4499
4500 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4501
4502 if (edid->revision < 3)
4503 return quirks;
4504
4505 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4506 return quirks;
4507
4508 drm_parse_cea_ext(connector, edid);
4509
4510 /*
4511 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4512 *
4513 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4514 * tells us to assume 8 bpc color depth if the EDID doesn't have
4515 * extensions which tell otherwise.
4516 */
4517 if ((info->bpc == 0) && (edid->revision < 4) &&
4518 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4519 info->bpc = 8;
4520 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4521 connector->name, info->bpc);
4522 }
4523
4524 /* Only defined for 1.4 with digital displays */
4525 if (edid->revision < 4)
4526 return quirks;
4527
4528 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4529 case DRM_EDID_DIGITAL_DEPTH_6:
4530 info->bpc = 6;
4531 break;
4532 case DRM_EDID_DIGITAL_DEPTH_8:
4533 info->bpc = 8;
4534 break;
4535 case DRM_EDID_DIGITAL_DEPTH_10:
4536 info->bpc = 10;
4537 break;
4538 case DRM_EDID_DIGITAL_DEPTH_12:
4539 info->bpc = 12;
4540 break;
4541 case DRM_EDID_DIGITAL_DEPTH_14:
4542 info->bpc = 14;
4543 break;
4544 case DRM_EDID_DIGITAL_DEPTH_16:
4545 info->bpc = 16;
4546 break;
4547 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4548 default:
4549 info->bpc = 0;
4550 break;
4551 }
4552
4553 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4554 connector->name, info->bpc);
4555
4556 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4557 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4558 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4559 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4560 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4561 return quirks;
4562 }
4563
4564 static int validate_displayid(u8 *displayid, int length, int idx)
4565 {
4566 int i;
4567 u8 csum = 0;
4568 struct displayid_hdr *base;
4569
4570 base = (struct displayid_hdr *)&displayid[idx];
4571
4572 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4573 base->rev, base->bytes, base->prod_id, base->ext_count);
4574
4575 if (base->bytes + 5 > length - idx)
4576 return -EINVAL;
4577 for (i = idx; i <= base->bytes + 5; i++) {
4578 csum += displayid[i];
4579 }
4580 if (csum) {
4581 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4582 return -EINVAL;
4583 }
4584 return 0;
4585 }
4586
4587 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4588 struct displayid_detailed_timings_1 *timings)
4589 {
4590 struct drm_display_mode *mode;
4591 unsigned pixel_clock = (timings->pixel_clock[0] |
4592 (timings->pixel_clock[1] << 8) |
4593 (timings->pixel_clock[2] << 16));
4594 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4595 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4596 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4597 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4598 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4599 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4600 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4601 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4602 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4603 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4604 mode = drm_mode_create(dev);
4605 if (!mode)
4606 return NULL;
4607
4608 mode->clock = pixel_clock * 10;
4609 mode->hdisplay = hactive;
4610 mode->hsync_start = mode->hdisplay + hsync;
4611 mode->hsync_end = mode->hsync_start + hsync_width;
4612 mode->htotal = mode->hdisplay + hblank;
4613
4614 mode->vdisplay = vactive;
4615 mode->vsync_start = mode->vdisplay + vsync;
4616 mode->vsync_end = mode->vsync_start + vsync_width;
4617 mode->vtotal = mode->vdisplay + vblank;
4618
4619 mode->flags = 0;
4620 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4621 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4622 mode->type = DRM_MODE_TYPE_DRIVER;
4623
4624 if (timings->flags & 0x80)
4625 mode->type |= DRM_MODE_TYPE_PREFERRED;
4626 mode->vrefresh = drm_mode_vrefresh(mode);
4627 drm_mode_set_name(mode);
4628
4629 return mode;
4630 }
4631
4632 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4633 struct displayid_block *block)
4634 {
4635 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4636 int i;
4637 int num_timings;
4638 struct drm_display_mode *newmode;
4639 int num_modes = 0;
4640 /* blocks must be multiple of 20 bytes length */
4641 if (block->num_bytes % 20)
4642 return 0;
4643
4644 num_timings = block->num_bytes / 20;
4645 for (i = 0; i < num_timings; i++) {
4646 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4647
4648 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4649 if (!newmode)
4650 continue;
4651
4652 drm_mode_probed_add(connector, newmode);
4653 num_modes++;
4654 }
4655 return num_modes;
4656 }
4657
4658 static int add_displayid_detailed_modes(struct drm_connector *connector,
4659 struct edid *edid)
4660 {
4661 u8 *displayid;
4662 int ret;
4663 int idx = 1;
4664 int length = EDID_LENGTH;
4665 struct displayid_block *block;
4666 int num_modes = 0;
4667
4668 displayid = drm_find_displayid_extension(edid);
4669 if (!displayid)
4670 return 0;
4671
4672 ret = validate_displayid(displayid, length, idx);
4673 if (ret)
4674 return 0;
4675
4676 idx += sizeof(struct displayid_hdr);
4677 while (block = (struct displayid_block *)&displayid[idx],
4678 idx + sizeof(struct displayid_block) <= length &&
4679 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4680 block->num_bytes > 0) {
4681 idx += block->num_bytes + sizeof(struct displayid_block);
4682 switch (block->tag) {
4683 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4684 num_modes += add_displayid_detailed_1_modes(connector, block);
4685 break;
4686 }
4687 }
4688 return num_modes;
4689 }
4690
4691 /**
4692 * drm_add_edid_modes - add modes from EDID data, if available
4693 * @connector: connector we're probing
4694 * @edid: EDID data
4695 *
4696 * Add the specified modes to the connector's mode list. Also fills out the
4697 * &drm_display_info structure and ELD in @connector with any information which
4698 * can be derived from the edid.
4699 *
4700 * Return: The number of modes added or 0 if we couldn't find any.
4701 */
4702 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4703 {
4704 int num_modes = 0;
4705 u32 quirks;
4706
4707 if (edid == NULL) {
4708 clear_eld(connector);
4709 return 0;
4710 }
4711 if (!drm_edid_is_valid(edid)) {
4712 clear_eld(connector);
4713 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4714 connector->name);
4715 return 0;
4716 }
4717
4718 drm_edid_to_eld(connector, edid);
4719
4720 /*
4721 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4722 * To avoid multiple parsing of same block, lets parse that map
4723 * from sink info, before parsing CEA modes.
4724 */
4725 quirks = drm_add_display_info(connector, edid);
4726
4727 /*
4728 * EDID spec says modes should be preferred in this order:
4729 * - preferred detailed mode
4730 * - other detailed modes from base block
4731 * - detailed modes from extension blocks
4732 * - CVT 3-byte code modes
4733 * - standard timing codes
4734 * - established timing codes
4735 * - modes inferred from GTF or CVT range information
4736 *
4737 * We get this pretty much right.
4738 *
4739 * XXX order for additional mode types in extension blocks?
4740 */
4741 num_modes += add_detailed_modes(connector, edid, quirks);
4742 num_modes += add_cvt_modes(connector, edid);
4743 num_modes += add_standard_modes(connector, edid);
4744 num_modes += add_established_modes(connector, edid);
4745 num_modes += add_cea_modes(connector, edid);
4746 num_modes += add_alternate_cea_modes(connector, edid);
4747 num_modes += add_displayid_detailed_modes(connector, edid);
4748 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4749 num_modes += add_inferred_modes(connector, edid);
4750
4751 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4752 edid_fixup_preferred(connector, quirks);
4753
4754 if (quirks & EDID_QUIRK_FORCE_6BPC)
4755 connector->display_info.bpc = 6;
4756
4757 if (quirks & EDID_QUIRK_FORCE_8BPC)
4758 connector->display_info.bpc = 8;
4759
4760 if (quirks & EDID_QUIRK_FORCE_10BPC)
4761 connector->display_info.bpc = 10;
4762
4763 if (quirks & EDID_QUIRK_FORCE_12BPC)
4764 connector->display_info.bpc = 12;
4765
4766 return num_modes;
4767 }
4768 EXPORT_SYMBOL(drm_add_edid_modes);
4769
4770 /**
4771 * drm_add_modes_noedid - add modes for the connectors without EDID
4772 * @connector: connector we're probing
4773 * @hdisplay: the horizontal display limit
4774 * @vdisplay: the vertical display limit
4775 *
4776 * Add the specified modes to the connector's mode list. Only when the
4777 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4778 *
4779 * Return: The number of modes added or 0 if we couldn't find any.
4780 */
4781 int drm_add_modes_noedid(struct drm_connector *connector,
4782 int hdisplay, int vdisplay)
4783 {
4784 int i, count, num_modes = 0;
4785 struct drm_display_mode *mode;
4786 struct drm_device *dev = connector->dev;
4787
4788 count = ARRAY_SIZE(drm_dmt_modes);
4789 if (hdisplay < 0)
4790 hdisplay = 0;
4791 if (vdisplay < 0)
4792 vdisplay = 0;
4793
4794 for (i = 0; i < count; i++) {
4795 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4796 if (hdisplay && vdisplay) {
4797 /*
4798 * Only when two are valid, they will be used to check
4799 * whether the mode should be added to the mode list of
4800 * the connector.
4801 */
4802 if (ptr->hdisplay > hdisplay ||
4803 ptr->vdisplay > vdisplay)
4804 continue;
4805 }
4806 if (drm_mode_vrefresh(ptr) > 61)
4807 continue;
4808 mode = drm_mode_duplicate(dev, ptr);
4809 if (mode) {
4810 drm_mode_probed_add(connector, mode);
4811 num_modes++;
4812 }
4813 }
4814 return num_modes;
4815 }
4816 EXPORT_SYMBOL(drm_add_modes_noedid);
4817
4818 /**
4819 * drm_set_preferred_mode - Sets the preferred mode of a connector
4820 * @connector: connector whose mode list should be processed
4821 * @hpref: horizontal resolution of preferred mode
4822 * @vpref: vertical resolution of preferred mode
4823 *
4824 * Marks a mode as preferred if it matches the resolution specified by @hpref
4825 * and @vpref.
4826 */
4827 void drm_set_preferred_mode(struct drm_connector *connector,
4828 int hpref, int vpref)
4829 {
4830 struct drm_display_mode *mode;
4831
4832 list_for_each_entry(mode, &connector->probed_modes, head) {
4833 if (mode->hdisplay == hpref &&
4834 mode->vdisplay == vpref)
4835 mode->type |= DRM_MODE_TYPE_PREFERRED;
4836 }
4837 }
4838 EXPORT_SYMBOL(drm_set_preferred_mode);
4839
4840 static bool is_hdmi2_sink(struct drm_connector *connector)
4841 {
4842 /*
4843 * FIXME: sil-sii8620 doesn't have a connector around when
4844 * we need one, so we have to be prepared for a NULL connector.
4845 */
4846 if (!connector)
4847 return true;
4848
4849 return connector->display_info.hdmi.scdc.supported ||
4850 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
4851 }
4852
4853 /**
4854 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4855 * data from a DRM display mode
4856 * @frame: HDMI AVI infoframe
4857 * @connector: the connector
4858 * @mode: DRM display mode
4859 *
4860 * Return: 0 on success or a negative error code on failure.
4861 */
4862 int
4863 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4864 struct drm_connector *connector,
4865 const struct drm_display_mode *mode)
4866 {
4867 enum hdmi_picture_aspect picture_aspect;
4868 int err;
4869
4870 if (!frame || !mode)
4871 return -EINVAL;
4872
4873 err = hdmi_avi_infoframe_init(frame);
4874 if (err < 0)
4875 return err;
4876
4877 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4878 frame->pixel_repeat = 1;
4879
4880 frame->video_code = drm_match_cea_mode(mode);
4881
4882 /*
4883 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4884 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4885 * have to make sure we dont break HDMI 1.4 sinks.
4886 */
4887 if (!is_hdmi2_sink(connector) && frame->video_code > 64)
4888 frame->video_code = 0;
4889
4890 /*
4891 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4892 * we should send its VIC in vendor infoframes, else send the
4893 * VIC in AVI infoframes. Lets check if this mode is present in
4894 * HDMI 1.4b 4K modes
4895 */
4896 if (frame->video_code) {
4897 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4898 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4899
4900 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4901 frame->video_code = 0;
4902 }
4903
4904 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4905
4906 /*
4907 * As some drivers don't support atomic, we can't use connector state.
4908 * So just initialize the frame with default values, just the same way
4909 * as it's done with other properties here.
4910 */
4911 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
4912 frame->itc = 0;
4913
4914 /*
4915 * Populate picture aspect ratio from either
4916 * user input (if specified) or from the CEA mode list.
4917 */
4918 picture_aspect = mode->picture_aspect_ratio;
4919 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
4920 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
4921
4922 /*
4923 * The infoframe can't convey anything but none, 4:3
4924 * and 16:9, so if the user has asked for anything else
4925 * we can only satisfy it by specifying the right VIC.
4926 */
4927 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
4928 if (picture_aspect !=
4929 drm_get_cea_aspect_ratio(frame->video_code))
4930 return -EINVAL;
4931 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4932 }
4933
4934 frame->picture_aspect = picture_aspect;
4935 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4936 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4937
4938 return 0;
4939 }
4940 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4941
4942 /* HDMI Colorspace Spec Definitions */
4943 #define FULL_COLORIMETRY_MASK 0x1FF
4944 #define NORMAL_COLORIMETRY_MASK 0x3
4945 #define EXTENDED_COLORIMETRY_MASK 0x7
4946 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
4947
4948 #define C(x) ((x) << 0)
4949 #define EC(x) ((x) << 2)
4950 #define ACE(x) ((x) << 5)
4951
4952 #define HDMI_COLORIMETRY_NO_DATA 0x0
4953 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
4954 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
4955 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
4956 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
4957 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
4958 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
4959 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
4960 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
4961 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
4962 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
4963 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
4964 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
4965
4966 static const u32 hdmi_colorimetry_val[] = {
4967 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
4968 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
4969 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
4970 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
4971 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
4972 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
4973 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
4974 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
4975 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
4976 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
4977 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
4978 };
4979
4980 #undef C
4981 #undef EC
4982 #undef ACE
4983
4984 /**
4985 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
4986 * colorspace information
4987 * @frame: HDMI AVI infoframe
4988 * @conn_state: connector state
4989 */
4990 void
4991 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
4992 const struct drm_connector_state *conn_state)
4993 {
4994 u32 colorimetry_val;
4995 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
4996
4997 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
4998 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
4999 else
5000 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5001
5002 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5003 /*
5004 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5005 * structure and extend it in drivers/video/hdmi
5006 */
5007 frame->extended_colorimetry = (colorimetry_val >> 2) &
5008 EXTENDED_COLORIMETRY_MASK;
5009 }
5010 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5011
5012 /**
5013 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5014 * quantization range information
5015 * @frame: HDMI AVI infoframe
5016 * @connector: the connector
5017 * @mode: DRM display mode
5018 * @rgb_quant_range: RGB quantization range (Q)
5019 */
5020 void
5021 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5022 struct drm_connector *connector,
5023 const struct drm_display_mode *mode,
5024 enum hdmi_quantization_range rgb_quant_range)
5025 {
5026 const struct drm_display_info *info = &connector->display_info;
5027
5028 /*
5029 * CEA-861:
5030 * "A Source shall not send a non-zero Q value that does not correspond
5031 * to the default RGB Quantization Range for the transmitted Picture
5032 * unless the Sink indicates support for the Q bit in a Video
5033 * Capabilities Data Block."
5034 *
5035 * HDMI 2.0 recommends sending non-zero Q when it does match the
5036 * default RGB quantization range for the mode, even when QS=0.
5037 */
5038 if (info->rgb_quant_range_selectable ||
5039 rgb_quant_range == drm_default_rgb_quant_range(mode))
5040 frame->quantization_range = rgb_quant_range;
5041 else
5042 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5043
5044 /*
5045 * CEA-861-F:
5046 * "When transmitting any RGB colorimetry, the Source should set the
5047 * YQ-field to match the RGB Quantization Range being transmitted
5048 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5049 * set YQ=1) and the Sink shall ignore the YQ-field."
5050 *
5051 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5052 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5053 * good way to tell which version of CEA-861 the sink supports, so
5054 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5055 * on on CEA-861-F.
5056 */
5057 if (!is_hdmi2_sink(connector) ||
5058 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5059 frame->ycc_quantization_range =
5060 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5061 else
5062 frame->ycc_quantization_range =
5063 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5064 }
5065 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5066
5067 static enum hdmi_3d_structure
5068 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5069 {
5070 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5071
5072 switch (layout) {
5073 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5074 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5075 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5076 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5077 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5078 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5079 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5080 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5081 case DRM_MODE_FLAG_3D_L_DEPTH:
5082 return HDMI_3D_STRUCTURE_L_DEPTH;
5083 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5084 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5085 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5086 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5087 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5088 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5089 default:
5090 return HDMI_3D_STRUCTURE_INVALID;
5091 }
5092 }
5093
5094 /**
5095 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5096 * data from a DRM display mode
5097 * @frame: HDMI vendor infoframe
5098 * @connector: the connector
5099 * @mode: DRM display mode
5100 *
5101 * Note that there's is a need to send HDMI vendor infoframes only when using a
5102 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5103 * function will return -EINVAL, error that can be safely ignored.
5104 *
5105 * Return: 0 on success or a negative error code on failure.
5106 */
5107 int
5108 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5109 struct drm_connector *connector,
5110 const struct drm_display_mode *mode)
5111 {
5112 /*
5113 * FIXME: sil-sii8620 doesn't have a connector around when
5114 * we need one, so we have to be prepared for a NULL connector.
5115 */
5116 bool has_hdmi_infoframe = connector ?
5117 connector->display_info.has_hdmi_infoframe : false;
5118 int err;
5119 u32 s3d_flags;
5120 u8 vic;
5121
5122 if (!frame || !mode)
5123 return -EINVAL;
5124
5125 if (!has_hdmi_infoframe)
5126 return -EINVAL;
5127
5128 vic = drm_match_hdmi_mode(mode);
5129 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5130
5131 /*
5132 * Even if it's not absolutely necessary to send the infoframe
5133 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5134 * know that the sink can handle it. This is based on a
5135 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5136 * have trouble realizing that they shuld switch from 3D to 2D
5137 * mode if the source simply stops sending the infoframe when
5138 * it wants to switch from 3D to 2D.
5139 */
5140
5141 if (vic && s3d_flags)
5142 return -EINVAL;
5143
5144 err = hdmi_vendor_infoframe_init(frame);
5145 if (err < 0)
5146 return err;
5147
5148 frame->vic = vic;
5149 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5150
5151 return 0;
5152 }
5153 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5154
5155 static int drm_parse_tiled_block(struct drm_connector *connector,
5156 struct displayid_block *block)
5157 {
5158 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5159 u16 w, h;
5160 u8 tile_v_loc, tile_h_loc;
5161 u8 num_v_tile, num_h_tile;
5162 struct drm_tile_group *tg;
5163
5164 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5165 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5166
5167 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5168 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5169 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5170 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5171
5172 connector->has_tile = true;
5173 if (tile->tile_cap & 0x80)
5174 connector->tile_is_single_monitor = true;
5175
5176 connector->num_h_tile = num_h_tile + 1;
5177 connector->num_v_tile = num_v_tile + 1;
5178 connector->tile_h_loc = tile_h_loc;
5179 connector->tile_v_loc = tile_v_loc;
5180 connector->tile_h_size = w + 1;
5181 connector->tile_v_size = h + 1;
5182
5183 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5184 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5185 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5186 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5187 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5188
5189 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5190 if (!tg) {
5191 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5192 }
5193 if (!tg)
5194 return -ENOMEM;
5195
5196 if (connector->tile_group != tg) {
5197 /* if we haven't got a pointer,
5198 take the reference, drop ref to old tile group */
5199 if (connector->tile_group) {
5200 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5201 }
5202 connector->tile_group = tg;
5203 } else
5204 /* if same tile group, then release the ref we just took. */
5205 drm_mode_put_tile_group(connector->dev, tg);
5206 return 0;
5207 }
5208
5209 static int drm_parse_display_id(struct drm_connector *connector,
5210 u8 *displayid, int length,
5211 bool is_edid_extension)
5212 {
5213 /* if this is an EDID extension the first byte will be 0x70 */
5214 int idx = 0;
5215 struct displayid_block *block;
5216 int ret;
5217
5218 if (is_edid_extension)
5219 idx = 1;
5220
5221 ret = validate_displayid(displayid, length, idx);
5222 if (ret)
5223 return ret;
5224
5225 idx += sizeof(struct displayid_hdr);
5226 while (block = (struct displayid_block *)&displayid[idx],
5227 idx + sizeof(struct displayid_block) <= length &&
5228 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5229 block->num_bytes > 0) {
5230 idx += block->num_bytes + sizeof(struct displayid_block);
5231 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5232 block->tag, block->rev, block->num_bytes);
5233
5234 switch (block->tag) {
5235 case DATA_BLOCK_TILED_DISPLAY:
5236 ret = drm_parse_tiled_block(connector, block);
5237 if (ret)
5238 return ret;
5239 break;
5240 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5241 /* handled in mode gathering code. */
5242 break;
5243 default:
5244 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5245 break;
5246 }
5247 }
5248 return 0;
5249 }
5250
5251 static void drm_get_displayid(struct drm_connector *connector,
5252 struct edid *edid)
5253 {
5254 void *displayid = NULL;
5255 int ret;
5256 connector->has_tile = false;
5257 displayid = drm_find_displayid_extension(edid);
5258 if (!displayid) {
5259 /* drop reference to any tile group we had */
5260 goto out_drop_ref;
5261 }
5262
5263 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5264 if (ret < 0)
5265 goto out_drop_ref;
5266 if (!connector->has_tile)
5267 goto out_drop_ref;
5268 return;
5269 out_drop_ref:
5270 if (connector->tile_group) {
5271 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5272 connector->tile_group = NULL;
5273 }
5274 return;
5275 }
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