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Merge tag 'drm-fixes-2019-06-14' of git://anongit.freedesktop.org/drm/drm
[thirdparty/linux.git] / drivers / gpu / drm / drm_edid.c
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
36 #include <drm/drmP.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
41
42 #include "drm_crtc_internal.h"
43
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
47
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
51
52 /*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* use +hsync +vsync for detailed mode */
72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
73 /* Force reduced-blanking timings for detailed modes */
74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
75 /* Force 8bpc */
76 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
77 /* Force 12bpc */
78 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
79 /* Force 6bpc */
80 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
81 /* Force 10bpc */
82 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
83 /* Non desktop display (i.e. HMD) */
84 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
85
86 struct detailed_mode_closure {
87 struct drm_connector *connector;
88 struct edid *edid;
89 bool preferred;
90 u32 quirks;
91 int modes;
92 };
93
94 #define LEVEL_DMT 0
95 #define LEVEL_GTF 1
96 #define LEVEL_GTF2 2
97 #define LEVEL_CVT 3
98
99 static const struct edid_quirk {
100 char vendor[4];
101 int product_id;
102 u32 quirks;
103 } edid_quirk_list[] = {
104 /* Acer AL1706 */
105 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
106 /* Acer F51 */
107 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
108
109 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
110 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
111
112 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
113 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
114
115 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
116 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
117
118 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
119 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
120
121 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
122 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
123
124 /* Belinea 10 15 55 */
125 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
126 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
127
128 /* Envision Peripherals, Inc. EN-7100e */
129 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
130 /* Envision EN2028 */
131 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
132
133 /* Funai Electronics PM36B */
134 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
135 EDID_QUIRK_DETAILED_IN_CM },
136
137 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
138 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
139
140 /* LG Philips LCD LP154W01-A5 */
141 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
142 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
143
144 /* Samsung SyncMaster 205BW. Note: irony */
145 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
146 /* Samsung SyncMaster 22[5-6]BW */
147 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
148 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
149
150 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
151 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
152
153 /* ViewSonic VA2026w */
154 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
155
156 /* Medion MD 30217 PG */
157 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
158
159 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
160 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
161
162 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
163 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
164
165 /* Valve Index Headset */
166 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
167 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
168 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
169 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
170 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
171 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
172 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
183
184 /* HTC Vive and Vive Pro VR Headsets */
185 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
186 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
187
188 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
189 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
190 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
191 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
192
193 /* Windows Mixed Reality Headsets */
194 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
195 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
196 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
197 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
198 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
199 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
200 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
201 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
202
203 /* Sony PlayStation VR Headset */
204 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
205
206 /* Sensics VR Headsets */
207 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
208
209 /* OSVR HDK and HDK2 VR Headsets */
210 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
211 };
212
213 /*
214 * Autogenerated from the DMT spec.
215 * This table is copied from xfree86/modes/xf86EdidModes.c.
216 */
217 static const struct drm_display_mode drm_dmt_modes[] = {
218 /* 0x01 - 640x350@85Hz */
219 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
220 736, 832, 0, 350, 382, 385, 445, 0,
221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
222 /* 0x02 - 640x400@85Hz */
223 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
224 736, 832, 0, 400, 401, 404, 445, 0,
225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
226 /* 0x03 - 720x400@85Hz */
227 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
228 828, 936, 0, 400, 401, 404, 446, 0,
229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
230 /* 0x04 - 640x480@60Hz */
231 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
232 752, 800, 0, 480, 490, 492, 525, 0,
233 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
234 /* 0x05 - 640x480@72Hz */
235 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
236 704, 832, 0, 480, 489, 492, 520, 0,
237 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
238 /* 0x06 - 640x480@75Hz */
239 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
240 720, 840, 0, 480, 481, 484, 500, 0,
241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
242 /* 0x07 - 640x480@85Hz */
243 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
244 752, 832, 0, 480, 481, 484, 509, 0,
245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
246 /* 0x08 - 800x600@56Hz */
247 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
248 896, 1024, 0, 600, 601, 603, 625, 0,
249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 0x09 - 800x600@60Hz */
251 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
252 968, 1056, 0, 600, 601, 605, 628, 0,
253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
254 /* 0x0a - 800x600@72Hz */
255 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
256 976, 1040, 0, 600, 637, 643, 666, 0,
257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
258 /* 0x0b - 800x600@75Hz */
259 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
260 896, 1056, 0, 600, 601, 604, 625, 0,
261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
262 /* 0x0c - 800x600@85Hz */
263 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
264 896, 1048, 0, 600, 601, 604, 631, 0,
265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
266 /* 0x0d - 800x600@120Hz RB */
267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
268 880, 960, 0, 600, 603, 607, 636, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
270 /* 0x0e - 848x480@60Hz */
271 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
272 976, 1088, 0, 480, 486, 494, 517, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
274 /* 0x0f - 1024x768@43Hz, interlace */
275 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
276 1208, 1264, 0, 768, 768, 776, 817, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
278 DRM_MODE_FLAG_INTERLACE) },
279 /* 0x10 - 1024x768@60Hz */
280 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
281 1184, 1344, 0, 768, 771, 777, 806, 0,
282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
283 /* 0x11 - 1024x768@70Hz */
284 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
285 1184, 1328, 0, 768, 771, 777, 806, 0,
286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
287 /* 0x12 - 1024x768@75Hz */
288 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
289 1136, 1312, 0, 768, 769, 772, 800, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
291 /* 0x13 - 1024x768@85Hz */
292 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
293 1168, 1376, 0, 768, 769, 772, 808, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
295 /* 0x14 - 1024x768@120Hz RB */
296 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
297 1104, 1184, 0, 768, 771, 775, 813, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
299 /* 0x15 - 1152x864@75Hz */
300 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
301 1344, 1600, 0, 864, 865, 868, 900, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x55 - 1280x720@60Hz */
304 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
305 1430, 1650, 0, 720, 725, 730, 750, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
307 /* 0x16 - 1280x768@60Hz RB */
308 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
309 1360, 1440, 0, 768, 771, 778, 790, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
311 /* 0x17 - 1280x768@60Hz */
312 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
313 1472, 1664, 0, 768, 771, 778, 798, 0,
314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x18 - 1280x768@75Hz */
316 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
317 1488, 1696, 0, 768, 771, 778, 805, 0,
318 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
319 /* 0x19 - 1280x768@85Hz */
320 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
321 1496, 1712, 0, 768, 771, 778, 809, 0,
322 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
323 /* 0x1a - 1280x768@120Hz RB */
324 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
325 1360, 1440, 0, 768, 771, 778, 813, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
327 /* 0x1b - 1280x800@60Hz RB */
328 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
329 1360, 1440, 0, 800, 803, 809, 823, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
331 /* 0x1c - 1280x800@60Hz */
332 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
333 1480, 1680, 0, 800, 803, 809, 831, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x1d - 1280x800@75Hz */
336 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
337 1488, 1696, 0, 800, 803, 809, 838, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
339 /* 0x1e - 1280x800@85Hz */
340 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
341 1496, 1712, 0, 800, 803, 809, 843, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x1f - 1280x800@120Hz RB */
344 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
345 1360, 1440, 0, 800, 803, 809, 847, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
347 /* 0x20 - 1280x960@60Hz */
348 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
349 1488, 1800, 0, 960, 961, 964, 1000, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
351 /* 0x21 - 1280x960@85Hz */
352 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
353 1504, 1728, 0, 960, 961, 964, 1011, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
355 /* 0x22 - 1280x960@120Hz RB */
356 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
357 1360, 1440, 0, 960, 963, 967, 1017, 0,
358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
359 /* 0x23 - 1280x1024@60Hz */
360 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
361 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x24 - 1280x1024@75Hz */
364 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
365 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x25 - 1280x1024@85Hz */
368 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
369 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x26 - 1280x1024@120Hz RB */
372 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
373 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
375 /* 0x27 - 1360x768@60Hz */
376 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
377 1536, 1792, 0, 768, 771, 777, 795, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
379 /* 0x28 - 1360x768@120Hz RB */
380 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
381 1440, 1520, 0, 768, 771, 776, 813, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
383 /* 0x51 - 1366x768@60Hz */
384 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
385 1579, 1792, 0, 768, 771, 774, 798, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x56 - 1366x768@60Hz */
388 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
389 1436, 1500, 0, 768, 769, 772, 800, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x29 - 1400x1050@60Hz RB */
392 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
393 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
395 /* 0x2a - 1400x1050@60Hz */
396 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
397 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
398 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
399 /* 0x2b - 1400x1050@75Hz */
400 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
401 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
402 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
403 /* 0x2c - 1400x1050@85Hz */
404 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
405 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x2d - 1400x1050@120Hz RB */
408 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
409 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
411 /* 0x2e - 1440x900@60Hz RB */
412 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
413 1520, 1600, 0, 900, 903, 909, 926, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
415 /* 0x2f - 1440x900@60Hz */
416 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
417 1672, 1904, 0, 900, 903, 909, 934, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x30 - 1440x900@75Hz */
420 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
421 1688, 1936, 0, 900, 903, 909, 942, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
423 /* 0x31 - 1440x900@85Hz */
424 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
425 1696, 1952, 0, 900, 903, 909, 948, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x32 - 1440x900@120Hz RB */
428 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
429 1520, 1600, 0, 900, 903, 909, 953, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
431 /* 0x53 - 1600x900@60Hz */
432 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
433 1704, 1800, 0, 900, 901, 904, 1000, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
435 /* 0x33 - 1600x1200@60Hz */
436 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
437 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 0x34 - 1600x1200@65Hz */
440 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
441 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 0x35 - 1600x1200@70Hz */
444 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
445 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
447 /* 0x36 - 1600x1200@75Hz */
448 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
449 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
451 /* 0x37 - 1600x1200@85Hz */
452 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
453 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
455 /* 0x38 - 1600x1200@120Hz RB */
456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
457 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
459 /* 0x39 - 1680x1050@60Hz RB */
460 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
461 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
463 /* 0x3a - 1680x1050@60Hz */
464 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
465 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
466 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x3b - 1680x1050@75Hz */
468 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
469 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 0x3c - 1680x1050@85Hz */
472 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
473 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x3d - 1680x1050@120Hz RB */
476 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
477 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
479 /* 0x3e - 1792x1344@60Hz */
480 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
481 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
483 /* 0x3f - 1792x1344@75Hz */
484 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
485 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x40 - 1792x1344@120Hz RB */
488 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
489 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
491 /* 0x41 - 1856x1392@60Hz */
492 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
493 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x42 - 1856x1392@75Hz */
496 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
497 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
499 /* 0x43 - 1856x1392@120Hz RB */
500 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
501 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
503 /* 0x52 - 1920x1080@60Hz */
504 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
505 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
507 /* 0x44 - 1920x1200@60Hz RB */
508 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
509 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
511 /* 0x45 - 1920x1200@60Hz */
512 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
513 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
515 /* 0x46 - 1920x1200@75Hz */
516 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
517 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
519 /* 0x47 - 1920x1200@85Hz */
520 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
521 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
523 /* 0x48 - 1920x1200@120Hz RB */
524 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
525 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
527 /* 0x49 - 1920x1440@60Hz */
528 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
529 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
531 /* 0x4a - 1920x1440@75Hz */
532 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
533 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
535 /* 0x4b - 1920x1440@120Hz RB */
536 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
537 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
538 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
539 /* 0x54 - 2048x1152@60Hz */
540 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
541 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
543 /* 0x4c - 2560x1600@60Hz RB */
544 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
545 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
547 /* 0x4d - 2560x1600@60Hz */
548 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
549 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
551 /* 0x4e - 2560x1600@75Hz */
552 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
553 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
555 /* 0x4f - 2560x1600@85Hz */
556 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
557 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
559 /* 0x50 - 2560x1600@120Hz RB */
560 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
561 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
563 /* 0x57 - 4096x2160@60Hz RB */
564 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
565 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
567 /* 0x58 - 4096x2160@59.94Hz RB */
568 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
569 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
571 };
572
573 /*
574 * These more or less come from the DMT spec. The 720x400 modes are
575 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
576 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
577 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
578 * mode.
579 *
580 * The DMT modes have been fact-checked; the rest are mild guesses.
581 */
582 static const struct drm_display_mode edid_est_modes[] = {
583 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
584 968, 1056, 0, 600, 601, 605, 628, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
586 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
587 896, 1024, 0, 600, 601, 603, 625, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
589 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
590 720, 840, 0, 480, 481, 484, 500, 0,
591 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
592 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
593 704, 832, 0, 480, 489, 492, 520, 0,
594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
596 768, 864, 0, 480, 483, 486, 525, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
599 752, 800, 0, 480, 490, 492, 525, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
601 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
602 846, 900, 0, 400, 421, 423, 449, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
604 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
605 846, 900, 0, 400, 412, 414, 449, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
607 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
608 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
610 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
611 1136, 1312, 0, 768, 769, 772, 800, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
613 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
614 1184, 1328, 0, 768, 771, 777, 806, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
617 1184, 1344, 0, 768, 771, 777, 806, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
619 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
620 1208, 1264, 0, 768, 768, 776, 817, 0,
621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
622 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
623 928, 1152, 0, 624, 625, 628, 667, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
625 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
626 896, 1056, 0, 600, 601, 604, 625, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
628 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
629 976, 1040, 0, 600, 637, 643, 666, 0,
630 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
631 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
632 1344, 1600, 0, 864, 865, 868, 900, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
634 };
635
636 struct minimode {
637 short w;
638 short h;
639 short r;
640 short rb;
641 };
642
643 static const struct minimode est3_modes[] = {
644 /* byte 6 */
645 { 640, 350, 85, 0 },
646 { 640, 400, 85, 0 },
647 { 720, 400, 85, 0 },
648 { 640, 480, 85, 0 },
649 { 848, 480, 60, 0 },
650 { 800, 600, 85, 0 },
651 { 1024, 768, 85, 0 },
652 { 1152, 864, 75, 0 },
653 /* byte 7 */
654 { 1280, 768, 60, 1 },
655 { 1280, 768, 60, 0 },
656 { 1280, 768, 75, 0 },
657 { 1280, 768, 85, 0 },
658 { 1280, 960, 60, 0 },
659 { 1280, 960, 85, 0 },
660 { 1280, 1024, 60, 0 },
661 { 1280, 1024, 85, 0 },
662 /* byte 8 */
663 { 1360, 768, 60, 0 },
664 { 1440, 900, 60, 1 },
665 { 1440, 900, 60, 0 },
666 { 1440, 900, 75, 0 },
667 { 1440, 900, 85, 0 },
668 { 1400, 1050, 60, 1 },
669 { 1400, 1050, 60, 0 },
670 { 1400, 1050, 75, 0 },
671 /* byte 9 */
672 { 1400, 1050, 85, 0 },
673 { 1680, 1050, 60, 1 },
674 { 1680, 1050, 60, 0 },
675 { 1680, 1050, 75, 0 },
676 { 1680, 1050, 85, 0 },
677 { 1600, 1200, 60, 0 },
678 { 1600, 1200, 65, 0 },
679 { 1600, 1200, 70, 0 },
680 /* byte 10 */
681 { 1600, 1200, 75, 0 },
682 { 1600, 1200, 85, 0 },
683 { 1792, 1344, 60, 0 },
684 { 1792, 1344, 75, 0 },
685 { 1856, 1392, 60, 0 },
686 { 1856, 1392, 75, 0 },
687 { 1920, 1200, 60, 1 },
688 { 1920, 1200, 60, 0 },
689 /* byte 11 */
690 { 1920, 1200, 75, 0 },
691 { 1920, 1200, 85, 0 },
692 { 1920, 1440, 60, 0 },
693 { 1920, 1440, 75, 0 },
694 };
695
696 static const struct minimode extra_modes[] = {
697 { 1024, 576, 60, 0 },
698 { 1366, 768, 60, 0 },
699 { 1600, 900, 60, 0 },
700 { 1680, 945, 60, 0 },
701 { 1920, 1080, 60, 0 },
702 { 2048, 1152, 60, 0 },
703 { 2048, 1536, 60, 0 },
704 };
705
706 /*
707 * Probably taken from CEA-861 spec.
708 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
709 *
710 * Index using the VIC.
711 */
712 static const struct drm_display_mode edid_cea_modes[] = {
713 /* 0 - dummy, VICs start at 1 */
714 { },
715 /* 1 - 640x480@60Hz 4:3 */
716 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
717 752, 800, 0, 480, 490, 492, 525, 0,
718 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
720 /* 2 - 720x480@60Hz 4:3 */
721 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
722 798, 858, 0, 480, 489, 495, 525, 0,
723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
724 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
725 /* 3 - 720x480@60Hz 16:9 */
726 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
727 798, 858, 0, 480, 489, 495, 525, 0,
728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
729 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
730 /* 4 - 1280x720@60Hz 16:9 */
731 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
732 1430, 1650, 0, 720, 725, 730, 750, 0,
733 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
735 /* 5 - 1920x1080i@60Hz 16:9 */
736 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
737 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
738 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
739 DRM_MODE_FLAG_INTERLACE),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741 /* 6 - 720(1440)x480i@60Hz 4:3 */
742 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
743 801, 858, 0, 480, 488, 494, 525, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
745 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
747 /* 7 - 720(1440)x480i@60Hz 16:9 */
748 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
749 801, 858, 0, 480, 488, 494, 525, 0,
750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
751 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
752 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 8 - 720(1440)x240@60Hz 4:3 */
754 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
755 801, 858, 0, 240, 244, 247, 262, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
757 DRM_MODE_FLAG_DBLCLK),
758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
759 /* 9 - 720(1440)x240@60Hz 16:9 */
760 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
761 801, 858, 0, 240, 244, 247, 262, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
763 DRM_MODE_FLAG_DBLCLK),
764 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 10 - 2880x480i@60Hz 4:3 */
766 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
767 3204, 3432, 0, 480, 488, 494, 525, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_INTERLACE),
770 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 11 - 2880x480i@60Hz 16:9 */
772 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
773 3204, 3432, 0, 480, 488, 494, 525, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_INTERLACE),
776 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 12 - 2880x240@60Hz 4:3 */
778 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
779 3204, 3432, 0, 240, 244, 247, 262, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
781 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782 /* 13 - 2880x240@60Hz 16:9 */
783 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 240, 244, 247, 262, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
786 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
787 /* 14 - 1440x480@60Hz 4:3 */
788 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
789 1596, 1716, 0, 480, 489, 495, 525, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
791 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
792 /* 15 - 1440x480@60Hz 16:9 */
793 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
794 1596, 1716, 0, 480, 489, 495, 525, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
796 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
797 /* 16 - 1920x1080@60Hz 16:9 */
798 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
799 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
800 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
801 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
802 /* 17 - 720x576@50Hz 4:3 */
803 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
804 796, 864, 0, 576, 581, 586, 625, 0,
805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
806 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
807 /* 18 - 720x576@50Hz 16:9 */
808 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
809 796, 864, 0, 576, 581, 586, 625, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
811 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
812 /* 19 - 1280x720@50Hz 16:9 */
813 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
814 1760, 1980, 0, 720, 725, 730, 750, 0,
815 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
817 /* 20 - 1920x1080i@50Hz 16:9 */
818 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
819 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
821 DRM_MODE_FLAG_INTERLACE),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 21 - 720(1440)x576i@50Hz 4:3 */
824 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
825 795, 864, 0, 576, 580, 586, 625, 0,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
827 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
829 /* 22 - 720(1440)x576i@50Hz 16:9 */
830 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
831 795, 864, 0, 576, 580, 586, 625, 0,
832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
833 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
834 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 23 - 720(1440)x288@50Hz 4:3 */
836 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
837 795, 864, 0, 288, 290, 293, 312, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
839 DRM_MODE_FLAG_DBLCLK),
840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
841 /* 24 - 720(1440)x288@50Hz 16:9 */
842 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
843 795, 864, 0, 288, 290, 293, 312, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
845 DRM_MODE_FLAG_DBLCLK),
846 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 25 - 2880x576i@50Hz 4:3 */
848 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
849 3180, 3456, 0, 576, 580, 586, 625, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_INTERLACE),
852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 26 - 2880x576i@50Hz 16:9 */
854 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
855 3180, 3456, 0, 576, 580, 586, 625, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_INTERLACE),
858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 27 - 2880x288@50Hz 4:3 */
860 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
861 3180, 3456, 0, 288, 290, 293, 312, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
864 /* 28 - 2880x288@50Hz 16:9 */
865 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 288, 290, 293, 312, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
869 /* 29 - 1440x576@50Hz 4:3 */
870 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
871 1592, 1728, 0, 576, 581, 586, 625, 0,
872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
873 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
874 /* 30 - 1440x576@50Hz 16:9 */
875 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
876 1592, 1728, 0, 576, 581, 586, 625, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
878 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
879 /* 31 - 1920x1080@50Hz 16:9 */
880 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
881 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
883 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
884 /* 32 - 1920x1080@24Hz 16:9 */
885 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
886 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
888 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
889 /* 33 - 1920x1080@25Hz 16:9 */
890 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
891 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
893 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 34 - 1920x1080@30Hz 16:9 */
895 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
896 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
898 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
899 /* 35 - 2880x480@60Hz 4:3 */
900 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
901 3192, 3432, 0, 480, 489, 495, 525, 0,
902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
903 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
904 /* 36 - 2880x480@60Hz 16:9 */
905 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
906 3192, 3432, 0, 480, 489, 495, 525, 0,
907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
908 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
909 /* 37 - 2880x576@50Hz 4:3 */
910 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
911 3184, 3456, 0, 576, 581, 586, 625, 0,
912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
913 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
914 /* 38 - 2880x576@50Hz 16:9 */
915 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
916 3184, 3456, 0, 576, 581, 586, 625, 0,
917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
918 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
919 /* 39 - 1920x1080i@50Hz 16:9 */
920 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
921 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
923 DRM_MODE_FLAG_INTERLACE),
924 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925 /* 40 - 1920x1080i@100Hz 16:9 */
926 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
927 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
929 DRM_MODE_FLAG_INTERLACE),
930 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 41 - 1280x720@100Hz 16:9 */
932 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
933 1760, 1980, 0, 720, 725, 730, 750, 0,
934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
935 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
936 /* 42 - 720x576@100Hz 4:3 */
937 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
938 796, 864, 0, 576, 581, 586, 625, 0,
939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
940 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
941 /* 43 - 720x576@100Hz 16:9 */
942 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
943 796, 864, 0, 576, 581, 586, 625, 0,
944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
945 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
946 /* 44 - 720(1440)x576i@100Hz 4:3 */
947 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
948 795, 864, 0, 576, 580, 586, 625, 0,
949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
950 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
951 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
952 /* 45 - 720(1440)x576i@100Hz 16:9 */
953 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
954 795, 864, 0, 576, 580, 586, 625, 0,
955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
956 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
957 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
958 /* 46 - 1920x1080i@120Hz 16:9 */
959 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
960 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
961 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
962 DRM_MODE_FLAG_INTERLACE),
963 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
964 /* 47 - 1280x720@120Hz 16:9 */
965 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
966 1430, 1650, 0, 720, 725, 730, 750, 0,
967 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
968 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
969 /* 48 - 720x480@120Hz 4:3 */
970 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
971 798, 858, 0, 480, 489, 495, 525, 0,
972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
973 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
974 /* 49 - 720x480@120Hz 16:9 */
975 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
976 798, 858, 0, 480, 489, 495, 525, 0,
977 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
978 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
979 /* 50 - 720(1440)x480i@120Hz 4:3 */
980 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
981 801, 858, 0, 480, 488, 494, 525, 0,
982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
983 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
984 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
985 /* 51 - 720(1440)x480i@120Hz 16:9 */
986 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
987 801, 858, 0, 480, 488, 494, 525, 0,
988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
989 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
990 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
991 /* 52 - 720x576@200Hz 4:3 */
992 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
993 796, 864, 0, 576, 581, 586, 625, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
995 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
996 /* 53 - 720x576@200Hz 16:9 */
997 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
998 796, 864, 0, 576, 581, 586, 625, 0,
999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1000 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1001 /* 54 - 720(1440)x576i@200Hz 4:3 */
1002 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1003 795, 864, 0, 576, 580, 586, 625, 0,
1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1005 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1006 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1007 /* 55 - 720(1440)x576i@200Hz 16:9 */
1008 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1009 795, 864, 0, 576, 580, 586, 625, 0,
1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1011 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1012 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1013 /* 56 - 720x480@240Hz 4:3 */
1014 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1015 798, 858, 0, 480, 489, 495, 525, 0,
1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1017 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1018 /* 57 - 720x480@240Hz 16:9 */
1019 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1020 798, 858, 0, 480, 489, 495, 525, 0,
1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1022 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1023 /* 58 - 720(1440)x480i@240Hz 4:3 */
1024 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1025 801, 858, 0, 480, 488, 494, 525, 0,
1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1027 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1028 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1029 /* 59 - 720(1440)x480i@240Hz 16:9 */
1030 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1031 801, 858, 0, 480, 488, 494, 525, 0,
1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1033 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1034 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1035 /* 60 - 1280x720@24Hz 16:9 */
1036 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1037 3080, 3300, 0, 720, 725, 730, 750, 0,
1038 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1039 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1040 /* 61 - 1280x720@25Hz 16:9 */
1041 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1042 3740, 3960, 0, 720, 725, 730, 750, 0,
1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1044 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1045 /* 62 - 1280x720@30Hz 16:9 */
1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1047 3080, 3300, 0, 720, 725, 730, 750, 0,
1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1049 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1050 /* 63 - 1920x1080@120Hz 16:9 */
1051 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1052 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1055 /* 64 - 1920x1080@100Hz 16:9 */
1056 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1057 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1060 /* 65 - 1280x720@24Hz 64:27 */
1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1062 3080, 3300, 0, 720, 725, 730, 750, 0,
1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1065 /* 66 - 1280x720@25Hz 64:27 */
1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1067 3740, 3960, 0, 720, 725, 730, 750, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1070 /* 67 - 1280x720@30Hz 64:27 */
1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1072 3080, 3300, 0, 720, 725, 730, 750, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1075 /* 68 - 1280x720@50Hz 64:27 */
1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1077 1760, 1980, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1080 /* 69 - 1280x720@60Hz 64:27 */
1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1082 1430, 1650, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085 /* 70 - 1280x720@100Hz 64:27 */
1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1087 1760, 1980, 0, 720, 725, 730, 750, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090 /* 71 - 1280x720@120Hz 64:27 */
1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1092 1430, 1650, 0, 720, 725, 730, 750, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095 /* 72 - 1920x1080@24Hz 64:27 */
1096 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1097 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 73 - 1920x1080@25Hz 64:27 */
1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1102 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 74 - 1920x1080@30Hz 64:27 */
1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1107 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 75 - 1920x1080@50Hz 64:27 */
1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1112 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 76 - 1920x1080@60Hz 64:27 */
1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1117 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 77 - 1920x1080@100Hz 64:27 */
1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 78 - 1920x1080@120Hz 64:27 */
1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 79 - 1680x720@24Hz 64:27 */
1131 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1132 3080, 3300, 0, 720, 725, 730, 750, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 80 - 1680x720@25Hz 64:27 */
1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1137 2948, 3168, 0, 720, 725, 730, 750, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 81 - 1680x720@30Hz 64:27 */
1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1142 2420, 2640, 0, 720, 725, 730, 750, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 82 - 1680x720@50Hz 64:27 */
1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1147 1980, 2200, 0, 720, 725, 730, 750, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 83 - 1680x720@60Hz 64:27 */
1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1152 1980, 2200, 0, 720, 725, 730, 750, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 84 - 1680x720@100Hz 64:27 */
1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1157 1780, 2000, 0, 720, 725, 730, 825, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 85 - 1680x720@120Hz 64:27 */
1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1162 1780, 2000, 0, 720, 725, 730, 825, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 86 - 2560x1080@24Hz 64:27 */
1166 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1167 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 87 - 2560x1080@25Hz 64:27 */
1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1172 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 88 - 2560x1080@30Hz 64:27 */
1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1177 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 89 - 2560x1080@50Hz 64:27 */
1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1182 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 90 - 2560x1080@60Hz 64:27 */
1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1187 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190 /* 91 - 2560x1080@100Hz 64:27 */
1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1192 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195 /* 92 - 2560x1080@120Hz 64:27 */
1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1197 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200 /* 93 - 3840x2160@24Hz 16:9 */
1201 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1202 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1205 /* 94 - 3840x2160@25Hz 16:9 */
1206 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1207 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1210 /* 95 - 3840x2160@30Hz 16:9 */
1211 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1212 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1215 /* 96 - 3840x2160@50Hz 16:9 */
1216 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1217 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1220 /* 97 - 3840x2160@60Hz 16:9 */
1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1222 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1225 /* 98 - 4096x2160@24Hz 256:135 */
1226 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1227 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1230 /* 99 - 4096x2160@25Hz 256:135 */
1231 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1232 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1235 /* 100 - 4096x2160@30Hz 256:135 */
1236 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1237 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1240 /* 101 - 4096x2160@50Hz 256:135 */
1241 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1242 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1245 /* 102 - 4096x2160@60Hz 256:135 */
1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1247 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1250 /* 103 - 3840x2160@24Hz 64:27 */
1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1252 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1255 /* 104 - 3840x2160@25Hz 64:27 */
1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1257 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1260 /* 105 - 3840x2160@30Hz 64:27 */
1261 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1262 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1265 /* 106 - 3840x2160@50Hz 64:27 */
1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1267 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1270 /* 107 - 3840x2160@60Hz 64:27 */
1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1272 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1275 };
1276
1277 /*
1278 * HDMI 1.4 4k modes. Index using the VIC.
1279 */
1280 static const struct drm_display_mode edid_4k_modes[] = {
1281 /* 0 - dummy, VICs start at 1 */
1282 { },
1283 /* 1 - 3840x2160@30Hz */
1284 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1285 3840, 4016, 4104, 4400, 0,
1286 2160, 2168, 2178, 2250, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .vrefresh = 30, },
1289 /* 2 - 3840x2160@25Hz */
1290 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1291 3840, 4896, 4984, 5280, 0,
1292 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 .vrefresh = 25, },
1295 /* 3 - 3840x2160@24Hz */
1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1297 3840, 5116, 5204, 5500, 0,
1298 2160, 2168, 2178, 2250, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300 .vrefresh = 24, },
1301 /* 4 - 4096x2160@24Hz (SMPTE) */
1302 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1303 4096, 5116, 5204, 5500, 0,
1304 2160, 2168, 2178, 2250, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1306 .vrefresh = 24, },
1307 };
1308
1309 /*** DDC fetch and block validation ***/
1310
1311 static const u8 edid_header[] = {
1312 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1313 };
1314
1315 /**
1316 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1317 * @raw_edid: pointer to raw base EDID block
1318 *
1319 * Sanity check the header of the base EDID block.
1320 *
1321 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1322 */
1323 int drm_edid_header_is_valid(const u8 *raw_edid)
1324 {
1325 int i, score = 0;
1326
1327 for (i = 0; i < sizeof(edid_header); i++)
1328 if (raw_edid[i] == edid_header[i])
1329 score++;
1330
1331 return score;
1332 }
1333 EXPORT_SYMBOL(drm_edid_header_is_valid);
1334
1335 static int edid_fixup __read_mostly = 6;
1336 module_param_named(edid_fixup, edid_fixup, int, 0400);
1337 MODULE_PARM_DESC(edid_fixup,
1338 "Minimum number of valid EDID header bytes (0-8, default 6)");
1339
1340 static void drm_get_displayid(struct drm_connector *connector,
1341 struct edid *edid);
1342
1343 static int drm_edid_block_checksum(const u8 *raw_edid)
1344 {
1345 int i;
1346 u8 csum = 0;
1347 for (i = 0; i < EDID_LENGTH; i++)
1348 csum += raw_edid[i];
1349
1350 return csum;
1351 }
1352
1353 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1354 {
1355 if (memchr_inv(in_edid, 0, length))
1356 return false;
1357
1358 return true;
1359 }
1360
1361 /**
1362 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1363 * @raw_edid: pointer to raw EDID block
1364 * @block: type of block to validate (0 for base, extension otherwise)
1365 * @print_bad_edid: if true, dump bad EDID blocks to the console
1366 * @edid_corrupt: if true, the header or checksum is invalid
1367 *
1368 * Validate a base or extension EDID block and optionally dump bad blocks to
1369 * the console.
1370 *
1371 * Return: True if the block is valid, false otherwise.
1372 */
1373 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1374 bool *edid_corrupt)
1375 {
1376 u8 csum;
1377 struct edid *edid = (struct edid *)raw_edid;
1378
1379 if (WARN_ON(!raw_edid))
1380 return false;
1381
1382 if (edid_fixup > 8 || edid_fixup < 0)
1383 edid_fixup = 6;
1384
1385 if (block == 0) {
1386 int score = drm_edid_header_is_valid(raw_edid);
1387 if (score == 8) {
1388 if (edid_corrupt)
1389 *edid_corrupt = false;
1390 } else if (score >= edid_fixup) {
1391 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1392 * The corrupt flag needs to be set here otherwise, the
1393 * fix-up code here will correct the problem, the
1394 * checksum is correct and the test fails
1395 */
1396 if (edid_corrupt)
1397 *edid_corrupt = true;
1398 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1399 memcpy(raw_edid, edid_header, sizeof(edid_header));
1400 } else {
1401 if (edid_corrupt)
1402 *edid_corrupt = true;
1403 goto bad;
1404 }
1405 }
1406
1407 csum = drm_edid_block_checksum(raw_edid);
1408 if (csum) {
1409 if (edid_corrupt)
1410 *edid_corrupt = true;
1411
1412 /* allow CEA to slide through, switches mangle this */
1413 if (raw_edid[0] == CEA_EXT) {
1414 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1415 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1416 } else {
1417 if (print_bad_edid)
1418 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1419
1420 goto bad;
1421 }
1422 }
1423
1424 /* per-block-type checks */
1425 switch (raw_edid[0]) {
1426 case 0: /* base */
1427 if (edid->version != 1) {
1428 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1429 goto bad;
1430 }
1431
1432 if (edid->revision > 4)
1433 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1434 break;
1435
1436 default:
1437 break;
1438 }
1439
1440 return true;
1441
1442 bad:
1443 if (print_bad_edid) {
1444 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1445 pr_notice("EDID block is all zeroes\n");
1446 } else {
1447 pr_notice("Raw EDID:\n");
1448 print_hex_dump(KERN_NOTICE,
1449 " \t", DUMP_PREFIX_NONE, 16, 1,
1450 raw_edid, EDID_LENGTH, false);
1451 }
1452 }
1453 return false;
1454 }
1455 EXPORT_SYMBOL(drm_edid_block_valid);
1456
1457 /**
1458 * drm_edid_is_valid - sanity check EDID data
1459 * @edid: EDID data
1460 *
1461 * Sanity-check an entire EDID record (including extensions)
1462 *
1463 * Return: True if the EDID data is valid, false otherwise.
1464 */
1465 bool drm_edid_is_valid(struct edid *edid)
1466 {
1467 int i;
1468 u8 *raw = (u8 *)edid;
1469
1470 if (!edid)
1471 return false;
1472
1473 for (i = 0; i <= edid->extensions; i++)
1474 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1475 return false;
1476
1477 return true;
1478 }
1479 EXPORT_SYMBOL(drm_edid_is_valid);
1480
1481 #define DDC_SEGMENT_ADDR 0x30
1482 /**
1483 * drm_do_probe_ddc_edid() - get EDID information via I2C
1484 * @data: I2C device adapter
1485 * @buf: EDID data buffer to be filled
1486 * @block: 128 byte EDID block to start fetching from
1487 * @len: EDID data buffer length to fetch
1488 *
1489 * Try to fetch EDID information by calling I2C driver functions.
1490 *
1491 * Return: 0 on success or -1 on failure.
1492 */
1493 static int
1494 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1495 {
1496 struct i2c_adapter *adapter = data;
1497 unsigned char start = block * EDID_LENGTH;
1498 unsigned char segment = block >> 1;
1499 unsigned char xfers = segment ? 3 : 2;
1500 int ret, retries = 5;
1501
1502 /*
1503 * The core I2C driver will automatically retry the transfer if the
1504 * adapter reports EAGAIN. However, we find that bit-banging transfers
1505 * are susceptible to errors under a heavily loaded machine and
1506 * generate spurious NAKs and timeouts. Retrying the transfer
1507 * of the individual block a few times seems to overcome this.
1508 */
1509 do {
1510 struct i2c_msg msgs[] = {
1511 {
1512 .addr = DDC_SEGMENT_ADDR,
1513 .flags = 0,
1514 .len = 1,
1515 .buf = &segment,
1516 }, {
1517 .addr = DDC_ADDR,
1518 .flags = 0,
1519 .len = 1,
1520 .buf = &start,
1521 }, {
1522 .addr = DDC_ADDR,
1523 .flags = I2C_M_RD,
1524 .len = len,
1525 .buf = buf,
1526 }
1527 };
1528
1529 /*
1530 * Avoid sending the segment addr to not upset non-compliant
1531 * DDC monitors.
1532 */
1533 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1534
1535 if (ret == -ENXIO) {
1536 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1537 adapter->name);
1538 break;
1539 }
1540 } while (ret != xfers && --retries);
1541
1542 return ret == xfers ? 0 : -1;
1543 }
1544
1545 static void connector_bad_edid(struct drm_connector *connector,
1546 u8 *edid, int num_blocks)
1547 {
1548 int i;
1549
1550 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1551 return;
1552
1553 dev_warn(connector->dev->dev,
1554 "%s: EDID is invalid:\n",
1555 connector->name);
1556 for (i = 0; i < num_blocks; i++) {
1557 u8 *block = edid + i * EDID_LENGTH;
1558 char prefix[20];
1559
1560 if (drm_edid_is_zero(block, EDID_LENGTH))
1561 sprintf(prefix, "\t[%02x] ZERO ", i);
1562 else if (!drm_edid_block_valid(block, i, false, NULL))
1563 sprintf(prefix, "\t[%02x] BAD ", i);
1564 else
1565 sprintf(prefix, "\t[%02x] GOOD ", i);
1566
1567 print_hex_dump(KERN_WARNING,
1568 prefix, DUMP_PREFIX_NONE, 16, 1,
1569 block, EDID_LENGTH, false);
1570 }
1571 }
1572
1573 /* Get override or firmware EDID */
1574 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1575 {
1576 struct edid *override = NULL;
1577
1578 if (connector->override_edid)
1579 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1580
1581 if (!override)
1582 override = drm_load_edid_firmware(connector);
1583
1584 return IS_ERR(override) ? NULL : override;
1585 }
1586
1587 /**
1588 * drm_add_override_edid_modes - add modes from override/firmware EDID
1589 * @connector: connector we're probing
1590 *
1591 * Add modes from the override/firmware EDID, if available. Only to be used from
1592 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1593 * failed during drm_get_edid() and caused the override/firmware EDID to be
1594 * skipped.
1595 *
1596 * Return: The number of modes added or 0 if we couldn't find any.
1597 */
1598 int drm_add_override_edid_modes(struct drm_connector *connector)
1599 {
1600 struct edid *override;
1601 int num_modes = 0;
1602
1603 override = drm_get_override_edid(connector);
1604 if (override) {
1605 drm_connector_update_edid_property(connector, override);
1606 num_modes = drm_add_edid_modes(connector, override);
1607 kfree(override);
1608
1609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1610 connector->base.id, connector->name, num_modes);
1611 }
1612
1613 return num_modes;
1614 }
1615 EXPORT_SYMBOL(drm_add_override_edid_modes);
1616
1617 /**
1618 * drm_do_get_edid - get EDID data using a custom EDID block read function
1619 * @connector: connector we're probing
1620 * @get_edid_block: EDID block read function
1621 * @data: private data passed to the block read function
1622 *
1623 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1624 * exposes a different interface to read EDID blocks this function can be used
1625 * to get EDID data using a custom block read function.
1626 *
1627 * As in the general case the DDC bus is accessible by the kernel at the I2C
1628 * level, drivers must make all reasonable efforts to expose it as an I2C
1629 * adapter and use drm_get_edid() instead of abusing this function.
1630 *
1631 * The EDID may be overridden using debugfs override_edid or firmare EDID
1632 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1633 * order. Having either of them bypasses actual EDID reads.
1634 *
1635 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1636 */
1637 struct edid *drm_do_get_edid(struct drm_connector *connector,
1638 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1639 size_t len),
1640 void *data)
1641 {
1642 int i, j = 0, valid_extensions = 0;
1643 u8 *edid, *new;
1644 struct edid *override;
1645
1646 override = drm_get_override_edid(connector);
1647 if (override)
1648 return override;
1649
1650 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1651 return NULL;
1652
1653 /* base block fetch */
1654 for (i = 0; i < 4; i++) {
1655 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1656 goto out;
1657 if (drm_edid_block_valid(edid, 0, false,
1658 &connector->edid_corrupt))
1659 break;
1660 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1661 connector->null_edid_counter++;
1662 goto carp;
1663 }
1664 }
1665 if (i == 4)
1666 goto carp;
1667
1668 /* if there's no extensions, we're done */
1669 valid_extensions = edid[0x7e];
1670 if (valid_extensions == 0)
1671 return (struct edid *)edid;
1672
1673 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1674 if (!new)
1675 goto out;
1676 edid = new;
1677
1678 for (j = 1; j <= edid[0x7e]; j++) {
1679 u8 *block = edid + j * EDID_LENGTH;
1680
1681 for (i = 0; i < 4; i++) {
1682 if (get_edid_block(data, block, j, EDID_LENGTH))
1683 goto out;
1684 if (drm_edid_block_valid(block, j, false, NULL))
1685 break;
1686 }
1687
1688 if (i == 4)
1689 valid_extensions--;
1690 }
1691
1692 if (valid_extensions != edid[0x7e]) {
1693 u8 *base;
1694
1695 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1696
1697 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1698 edid[0x7e] = valid_extensions;
1699
1700 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1701 GFP_KERNEL);
1702 if (!new)
1703 goto out;
1704
1705 base = new;
1706 for (i = 0; i <= edid[0x7e]; i++) {
1707 u8 *block = edid + i * EDID_LENGTH;
1708
1709 if (!drm_edid_block_valid(block, i, false, NULL))
1710 continue;
1711
1712 memcpy(base, block, EDID_LENGTH);
1713 base += EDID_LENGTH;
1714 }
1715
1716 kfree(edid);
1717 edid = new;
1718 }
1719
1720 return (struct edid *)edid;
1721
1722 carp:
1723 connector_bad_edid(connector, edid, 1);
1724 out:
1725 kfree(edid);
1726 return NULL;
1727 }
1728 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1729
1730 /**
1731 * drm_probe_ddc() - probe DDC presence
1732 * @adapter: I2C adapter to probe
1733 *
1734 * Return: True on success, false on failure.
1735 */
1736 bool
1737 drm_probe_ddc(struct i2c_adapter *adapter)
1738 {
1739 unsigned char out;
1740
1741 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1742 }
1743 EXPORT_SYMBOL(drm_probe_ddc);
1744
1745 /**
1746 * drm_get_edid - get EDID data, if available
1747 * @connector: connector we're probing
1748 * @adapter: I2C adapter to use for DDC
1749 *
1750 * Poke the given I2C channel to grab EDID data if possible. If found,
1751 * attach it to the connector.
1752 *
1753 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1754 */
1755 struct edid *drm_get_edid(struct drm_connector *connector,
1756 struct i2c_adapter *adapter)
1757 {
1758 struct edid *edid;
1759
1760 if (connector->force == DRM_FORCE_OFF)
1761 return NULL;
1762
1763 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1764 return NULL;
1765
1766 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1767 if (edid)
1768 drm_get_displayid(connector, edid);
1769 return edid;
1770 }
1771 EXPORT_SYMBOL(drm_get_edid);
1772
1773 /**
1774 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1775 * @connector: connector we're probing
1776 * @adapter: I2C adapter to use for DDC
1777 *
1778 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1779 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1780 * switch DDC to the GPU which is retrieving EDID.
1781 *
1782 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1783 */
1784 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1785 struct i2c_adapter *adapter)
1786 {
1787 struct pci_dev *pdev = connector->dev->pdev;
1788 struct edid *edid;
1789
1790 vga_switcheroo_lock_ddc(pdev);
1791 edid = drm_get_edid(connector, adapter);
1792 vga_switcheroo_unlock_ddc(pdev);
1793
1794 return edid;
1795 }
1796 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1797
1798 /**
1799 * drm_edid_duplicate - duplicate an EDID and the extensions
1800 * @edid: EDID to duplicate
1801 *
1802 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1803 */
1804 struct edid *drm_edid_duplicate(const struct edid *edid)
1805 {
1806 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1807 }
1808 EXPORT_SYMBOL(drm_edid_duplicate);
1809
1810 /*** EDID parsing ***/
1811
1812 /**
1813 * edid_vendor - match a string against EDID's obfuscated vendor field
1814 * @edid: EDID to match
1815 * @vendor: vendor string
1816 *
1817 * Returns true if @vendor is in @edid, false otherwise
1818 */
1819 static bool edid_vendor(const struct edid *edid, const char *vendor)
1820 {
1821 char edid_vendor[3];
1822
1823 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1824 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1825 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1826 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1827
1828 return !strncmp(edid_vendor, vendor, 3);
1829 }
1830
1831 /**
1832 * edid_get_quirks - return quirk flags for a given EDID
1833 * @edid: EDID to process
1834 *
1835 * This tells subsequent routines what fixes they need to apply.
1836 */
1837 static u32 edid_get_quirks(const struct edid *edid)
1838 {
1839 const struct edid_quirk *quirk;
1840 int i;
1841
1842 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1843 quirk = &edid_quirk_list[i];
1844
1845 if (edid_vendor(edid, quirk->vendor) &&
1846 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1847 return quirk->quirks;
1848 }
1849
1850 return 0;
1851 }
1852
1853 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1854 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1855
1856 /**
1857 * edid_fixup_preferred - set preferred modes based on quirk list
1858 * @connector: has mode list to fix up
1859 * @quirks: quirks list
1860 *
1861 * Walk the mode list for @connector, clearing the preferred status
1862 * on existing modes and setting it anew for the right mode ala @quirks.
1863 */
1864 static void edid_fixup_preferred(struct drm_connector *connector,
1865 u32 quirks)
1866 {
1867 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1868 int target_refresh = 0;
1869 int cur_vrefresh, preferred_vrefresh;
1870
1871 if (list_empty(&connector->probed_modes))
1872 return;
1873
1874 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1875 target_refresh = 60;
1876 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1877 target_refresh = 75;
1878
1879 preferred_mode = list_first_entry(&connector->probed_modes,
1880 struct drm_display_mode, head);
1881
1882 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1883 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1884
1885 if (cur_mode == preferred_mode)
1886 continue;
1887
1888 /* Largest mode is preferred */
1889 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1890 preferred_mode = cur_mode;
1891
1892 cur_vrefresh = cur_mode->vrefresh ?
1893 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1894 preferred_vrefresh = preferred_mode->vrefresh ?
1895 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1896 /* At a given size, try to get closest to target refresh */
1897 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1898 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1899 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1900 preferred_mode = cur_mode;
1901 }
1902 }
1903
1904 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1905 }
1906
1907 static bool
1908 mode_is_rb(const struct drm_display_mode *mode)
1909 {
1910 return (mode->htotal - mode->hdisplay == 160) &&
1911 (mode->hsync_end - mode->hdisplay == 80) &&
1912 (mode->hsync_end - mode->hsync_start == 32) &&
1913 (mode->vsync_start - mode->vdisplay == 3);
1914 }
1915
1916 /*
1917 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1918 * @dev: Device to duplicate against
1919 * @hsize: Mode width
1920 * @vsize: Mode height
1921 * @fresh: Mode refresh rate
1922 * @rb: Mode reduced-blanking-ness
1923 *
1924 * Walk the DMT mode list looking for a match for the given parameters.
1925 *
1926 * Return: A newly allocated copy of the mode, or NULL if not found.
1927 */
1928 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1929 int hsize, int vsize, int fresh,
1930 bool rb)
1931 {
1932 int i;
1933
1934 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1935 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1936 if (hsize != ptr->hdisplay)
1937 continue;
1938 if (vsize != ptr->vdisplay)
1939 continue;
1940 if (fresh != drm_mode_vrefresh(ptr))
1941 continue;
1942 if (rb != mode_is_rb(ptr))
1943 continue;
1944
1945 return drm_mode_duplicate(dev, ptr);
1946 }
1947
1948 return NULL;
1949 }
1950 EXPORT_SYMBOL(drm_mode_find_dmt);
1951
1952 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1953
1954 static void
1955 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1956 {
1957 int i, n = 0;
1958 u8 d = ext[0x02];
1959 u8 *det_base = ext + d;
1960
1961 n = (127 - d) / 18;
1962 for (i = 0; i < n; i++)
1963 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1964 }
1965
1966 static void
1967 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1968 {
1969 unsigned int i, n = min((int)ext[0x02], 6);
1970 u8 *det_base = ext + 5;
1971
1972 if (ext[0x01] != 1)
1973 return; /* unknown version */
1974
1975 for (i = 0; i < n; i++)
1976 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1977 }
1978
1979 static void
1980 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1981 {
1982 int i;
1983 struct edid *edid = (struct edid *)raw_edid;
1984
1985 if (edid == NULL)
1986 return;
1987
1988 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1989 cb(&(edid->detailed_timings[i]), closure);
1990
1991 for (i = 1; i <= raw_edid[0x7e]; i++) {
1992 u8 *ext = raw_edid + (i * EDID_LENGTH);
1993 switch (*ext) {
1994 case CEA_EXT:
1995 cea_for_each_detailed_block(ext, cb, closure);
1996 break;
1997 case VTB_EXT:
1998 vtb_for_each_detailed_block(ext, cb, closure);
1999 break;
2000 default:
2001 break;
2002 }
2003 }
2004 }
2005
2006 static void
2007 is_rb(struct detailed_timing *t, void *data)
2008 {
2009 u8 *r = (u8 *)t;
2010 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
2011 if (r[15] & 0x10)
2012 *(bool *)data = true;
2013 }
2014
2015 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2016 static bool
2017 drm_monitor_supports_rb(struct edid *edid)
2018 {
2019 if (edid->revision >= 4) {
2020 bool ret = false;
2021 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2022 return ret;
2023 }
2024
2025 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2026 }
2027
2028 static void
2029 find_gtf2(struct detailed_timing *t, void *data)
2030 {
2031 u8 *r = (u8 *)t;
2032 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
2033 *(u8 **)data = r;
2034 }
2035
2036 /* Secondary GTF curve kicks in above some break frequency */
2037 static int
2038 drm_gtf2_hbreak(struct edid *edid)
2039 {
2040 u8 *r = NULL;
2041 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2042 return r ? (r[12] * 2) : 0;
2043 }
2044
2045 static int
2046 drm_gtf2_2c(struct edid *edid)
2047 {
2048 u8 *r = NULL;
2049 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2050 return r ? r[13] : 0;
2051 }
2052
2053 static int
2054 drm_gtf2_m(struct edid *edid)
2055 {
2056 u8 *r = NULL;
2057 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2058 return r ? (r[15] << 8) + r[14] : 0;
2059 }
2060
2061 static int
2062 drm_gtf2_k(struct edid *edid)
2063 {
2064 u8 *r = NULL;
2065 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2066 return r ? r[16] : 0;
2067 }
2068
2069 static int
2070 drm_gtf2_2j(struct edid *edid)
2071 {
2072 u8 *r = NULL;
2073 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2074 return r ? r[17] : 0;
2075 }
2076
2077 /**
2078 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2079 * @edid: EDID block to scan
2080 */
2081 static int standard_timing_level(struct edid *edid)
2082 {
2083 if (edid->revision >= 2) {
2084 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2085 return LEVEL_CVT;
2086 if (drm_gtf2_hbreak(edid))
2087 return LEVEL_GTF2;
2088 return LEVEL_GTF;
2089 }
2090 return LEVEL_DMT;
2091 }
2092
2093 /*
2094 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2095 * monitors fill with ascii space (0x20) instead.
2096 */
2097 static int
2098 bad_std_timing(u8 a, u8 b)
2099 {
2100 return (a == 0x00 && b == 0x00) ||
2101 (a == 0x01 && b == 0x01) ||
2102 (a == 0x20 && b == 0x20);
2103 }
2104
2105 /**
2106 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2107 * @connector: connector of for the EDID block
2108 * @edid: EDID block to scan
2109 * @t: standard timing params
2110 *
2111 * Take the standard timing params (in this case width, aspect, and refresh)
2112 * and convert them into a real mode using CVT/GTF/DMT.
2113 */
2114 static struct drm_display_mode *
2115 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2116 struct std_timing *t)
2117 {
2118 struct drm_device *dev = connector->dev;
2119 struct drm_display_mode *m, *mode = NULL;
2120 int hsize, vsize;
2121 int vrefresh_rate;
2122 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2123 >> EDID_TIMING_ASPECT_SHIFT;
2124 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2125 >> EDID_TIMING_VFREQ_SHIFT;
2126 int timing_level = standard_timing_level(edid);
2127
2128 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2129 return NULL;
2130
2131 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2132 hsize = t->hsize * 8 + 248;
2133 /* vrefresh_rate = vfreq + 60 */
2134 vrefresh_rate = vfreq + 60;
2135 /* the vdisplay is calculated based on the aspect ratio */
2136 if (aspect_ratio == 0) {
2137 if (edid->revision < 3)
2138 vsize = hsize;
2139 else
2140 vsize = (hsize * 10) / 16;
2141 } else if (aspect_ratio == 1)
2142 vsize = (hsize * 3) / 4;
2143 else if (aspect_ratio == 2)
2144 vsize = (hsize * 4) / 5;
2145 else
2146 vsize = (hsize * 9) / 16;
2147
2148 /* HDTV hack, part 1 */
2149 if (vrefresh_rate == 60 &&
2150 ((hsize == 1360 && vsize == 765) ||
2151 (hsize == 1368 && vsize == 769))) {
2152 hsize = 1366;
2153 vsize = 768;
2154 }
2155
2156 /*
2157 * If this connector already has a mode for this size and refresh
2158 * rate (because it came from detailed or CVT info), use that
2159 * instead. This way we don't have to guess at interlace or
2160 * reduced blanking.
2161 */
2162 list_for_each_entry(m, &connector->probed_modes, head)
2163 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2164 drm_mode_vrefresh(m) == vrefresh_rate)
2165 return NULL;
2166
2167 /* HDTV hack, part 2 */
2168 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2169 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2170 false);
2171 if (!mode)
2172 return NULL;
2173 mode->hdisplay = 1366;
2174 mode->hsync_start = mode->hsync_start - 1;
2175 mode->hsync_end = mode->hsync_end - 1;
2176 return mode;
2177 }
2178
2179 /* check whether it can be found in default mode table */
2180 if (drm_monitor_supports_rb(edid)) {
2181 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2182 true);
2183 if (mode)
2184 return mode;
2185 }
2186 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2187 if (mode)
2188 return mode;
2189
2190 /* okay, generate it */
2191 switch (timing_level) {
2192 case LEVEL_DMT:
2193 break;
2194 case LEVEL_GTF:
2195 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2196 break;
2197 case LEVEL_GTF2:
2198 /*
2199 * This is potentially wrong if there's ever a monitor with
2200 * more than one ranges section, each claiming a different
2201 * secondary GTF curve. Please don't do that.
2202 */
2203 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2204 if (!mode)
2205 return NULL;
2206 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2207 drm_mode_destroy(dev, mode);
2208 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2209 vrefresh_rate, 0, 0,
2210 drm_gtf2_m(edid),
2211 drm_gtf2_2c(edid),
2212 drm_gtf2_k(edid),
2213 drm_gtf2_2j(edid));
2214 }
2215 break;
2216 case LEVEL_CVT:
2217 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2218 false);
2219 break;
2220 }
2221 return mode;
2222 }
2223
2224 /*
2225 * EDID is delightfully ambiguous about how interlaced modes are to be
2226 * encoded. Our internal representation is of frame height, but some
2227 * HDTV detailed timings are encoded as field height.
2228 *
2229 * The format list here is from CEA, in frame size. Technically we
2230 * should be checking refresh rate too. Whatever.
2231 */
2232 static void
2233 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2234 struct detailed_pixel_timing *pt)
2235 {
2236 int i;
2237 static const struct {
2238 int w, h;
2239 } cea_interlaced[] = {
2240 { 1920, 1080 },
2241 { 720, 480 },
2242 { 1440, 480 },
2243 { 2880, 480 },
2244 { 720, 576 },
2245 { 1440, 576 },
2246 { 2880, 576 },
2247 };
2248
2249 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2250 return;
2251
2252 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2253 if ((mode->hdisplay == cea_interlaced[i].w) &&
2254 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2255 mode->vdisplay *= 2;
2256 mode->vsync_start *= 2;
2257 mode->vsync_end *= 2;
2258 mode->vtotal *= 2;
2259 mode->vtotal |= 1;
2260 }
2261 }
2262
2263 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2264 }
2265
2266 /**
2267 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2268 * @dev: DRM device (needed to create new mode)
2269 * @edid: EDID block
2270 * @timing: EDID detailed timing info
2271 * @quirks: quirks to apply
2272 *
2273 * An EDID detailed timing block contains enough info for us to create and
2274 * return a new struct drm_display_mode.
2275 */
2276 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2277 struct edid *edid,
2278 struct detailed_timing *timing,
2279 u32 quirks)
2280 {
2281 struct drm_display_mode *mode;
2282 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2283 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2284 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2285 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2286 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2287 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2288 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2289 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2290 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2291
2292 /* ignore tiny modes */
2293 if (hactive < 64 || vactive < 64)
2294 return NULL;
2295
2296 if (pt->misc & DRM_EDID_PT_STEREO) {
2297 DRM_DEBUG_KMS("stereo mode not supported\n");
2298 return NULL;
2299 }
2300 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2301 DRM_DEBUG_KMS("composite sync not supported\n");
2302 }
2303
2304 /* it is incorrect if hsync/vsync width is zero */
2305 if (!hsync_pulse_width || !vsync_pulse_width) {
2306 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2307 "Wrong Hsync/Vsync pulse width\n");
2308 return NULL;
2309 }
2310
2311 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2312 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2313 if (!mode)
2314 return NULL;
2315
2316 goto set_size;
2317 }
2318
2319 mode = drm_mode_create(dev);
2320 if (!mode)
2321 return NULL;
2322
2323 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2324 timing->pixel_clock = cpu_to_le16(1088);
2325
2326 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2327
2328 mode->hdisplay = hactive;
2329 mode->hsync_start = mode->hdisplay + hsync_offset;
2330 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2331 mode->htotal = mode->hdisplay + hblank;
2332
2333 mode->vdisplay = vactive;
2334 mode->vsync_start = mode->vdisplay + vsync_offset;
2335 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2336 mode->vtotal = mode->vdisplay + vblank;
2337
2338 /* Some EDIDs have bogus h/vtotal values */
2339 if (mode->hsync_end > mode->htotal)
2340 mode->htotal = mode->hsync_end + 1;
2341 if (mode->vsync_end > mode->vtotal)
2342 mode->vtotal = mode->vsync_end + 1;
2343
2344 drm_mode_do_interlace_quirk(mode, pt);
2345
2346 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2347 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2348 }
2349
2350 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2351 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2352 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2353 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2354
2355 set_size:
2356 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2357 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2358
2359 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2360 mode->width_mm *= 10;
2361 mode->height_mm *= 10;
2362 }
2363
2364 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2365 mode->width_mm = edid->width_cm * 10;
2366 mode->height_mm = edid->height_cm * 10;
2367 }
2368
2369 mode->type = DRM_MODE_TYPE_DRIVER;
2370 mode->vrefresh = drm_mode_vrefresh(mode);
2371 drm_mode_set_name(mode);
2372
2373 return mode;
2374 }
2375
2376 static bool
2377 mode_in_hsync_range(const struct drm_display_mode *mode,
2378 struct edid *edid, u8 *t)
2379 {
2380 int hsync, hmin, hmax;
2381
2382 hmin = t[7];
2383 if (edid->revision >= 4)
2384 hmin += ((t[4] & 0x04) ? 255 : 0);
2385 hmax = t[8];
2386 if (edid->revision >= 4)
2387 hmax += ((t[4] & 0x08) ? 255 : 0);
2388 hsync = drm_mode_hsync(mode);
2389
2390 return (hsync <= hmax && hsync >= hmin);
2391 }
2392
2393 static bool
2394 mode_in_vsync_range(const struct drm_display_mode *mode,
2395 struct edid *edid, u8 *t)
2396 {
2397 int vsync, vmin, vmax;
2398
2399 vmin = t[5];
2400 if (edid->revision >= 4)
2401 vmin += ((t[4] & 0x01) ? 255 : 0);
2402 vmax = t[6];
2403 if (edid->revision >= 4)
2404 vmax += ((t[4] & 0x02) ? 255 : 0);
2405 vsync = drm_mode_vrefresh(mode);
2406
2407 return (vsync <= vmax && vsync >= vmin);
2408 }
2409
2410 static u32
2411 range_pixel_clock(struct edid *edid, u8 *t)
2412 {
2413 /* unspecified */
2414 if (t[9] == 0 || t[9] == 255)
2415 return 0;
2416
2417 /* 1.4 with CVT support gives us real precision, yay */
2418 if (edid->revision >= 4 && t[10] == 0x04)
2419 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2420
2421 /* 1.3 is pathetic, so fuzz up a bit */
2422 return t[9] * 10000 + 5001;
2423 }
2424
2425 static bool
2426 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2427 struct detailed_timing *timing)
2428 {
2429 u32 max_clock;
2430 u8 *t = (u8 *)timing;
2431
2432 if (!mode_in_hsync_range(mode, edid, t))
2433 return false;
2434
2435 if (!mode_in_vsync_range(mode, edid, t))
2436 return false;
2437
2438 if ((max_clock = range_pixel_clock(edid, t)))
2439 if (mode->clock > max_clock)
2440 return false;
2441
2442 /* 1.4 max horizontal check */
2443 if (edid->revision >= 4 && t[10] == 0x04)
2444 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2445 return false;
2446
2447 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2448 return false;
2449
2450 return true;
2451 }
2452
2453 static bool valid_inferred_mode(const struct drm_connector *connector,
2454 const struct drm_display_mode *mode)
2455 {
2456 const struct drm_display_mode *m;
2457 bool ok = false;
2458
2459 list_for_each_entry(m, &connector->probed_modes, head) {
2460 if (mode->hdisplay == m->hdisplay &&
2461 mode->vdisplay == m->vdisplay &&
2462 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2463 return false; /* duplicated */
2464 if (mode->hdisplay <= m->hdisplay &&
2465 mode->vdisplay <= m->vdisplay)
2466 ok = true;
2467 }
2468 return ok;
2469 }
2470
2471 static int
2472 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2473 struct detailed_timing *timing)
2474 {
2475 int i, modes = 0;
2476 struct drm_display_mode *newmode;
2477 struct drm_device *dev = connector->dev;
2478
2479 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2480 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2481 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2482 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2483 if (newmode) {
2484 drm_mode_probed_add(connector, newmode);
2485 modes++;
2486 }
2487 }
2488 }
2489
2490 return modes;
2491 }
2492
2493 /* fix up 1366x768 mode from 1368x768;
2494 * GFT/CVT can't express 1366 width which isn't dividable by 8
2495 */
2496 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2497 {
2498 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2499 mode->hdisplay = 1366;
2500 mode->hsync_start--;
2501 mode->hsync_end--;
2502 drm_mode_set_name(mode);
2503 }
2504 }
2505
2506 static int
2507 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2508 struct detailed_timing *timing)
2509 {
2510 int i, modes = 0;
2511 struct drm_display_mode *newmode;
2512 struct drm_device *dev = connector->dev;
2513
2514 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2515 const struct minimode *m = &extra_modes[i];
2516 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2517 if (!newmode)
2518 return modes;
2519
2520 drm_mode_fixup_1366x768(newmode);
2521 if (!mode_in_range(newmode, edid, timing) ||
2522 !valid_inferred_mode(connector, newmode)) {
2523 drm_mode_destroy(dev, newmode);
2524 continue;
2525 }
2526
2527 drm_mode_probed_add(connector, newmode);
2528 modes++;
2529 }
2530
2531 return modes;
2532 }
2533
2534 static int
2535 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2536 struct detailed_timing *timing)
2537 {
2538 int i, modes = 0;
2539 struct drm_display_mode *newmode;
2540 struct drm_device *dev = connector->dev;
2541 bool rb = drm_monitor_supports_rb(edid);
2542
2543 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2544 const struct minimode *m = &extra_modes[i];
2545 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2546 if (!newmode)
2547 return modes;
2548
2549 drm_mode_fixup_1366x768(newmode);
2550 if (!mode_in_range(newmode, edid, timing) ||
2551 !valid_inferred_mode(connector, newmode)) {
2552 drm_mode_destroy(dev, newmode);
2553 continue;
2554 }
2555
2556 drm_mode_probed_add(connector, newmode);
2557 modes++;
2558 }
2559
2560 return modes;
2561 }
2562
2563 static void
2564 do_inferred_modes(struct detailed_timing *timing, void *c)
2565 {
2566 struct detailed_mode_closure *closure = c;
2567 struct detailed_non_pixel *data = &timing->data.other_data;
2568 struct detailed_data_monitor_range *range = &data->data.range;
2569
2570 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2571 return;
2572
2573 closure->modes += drm_dmt_modes_for_range(closure->connector,
2574 closure->edid,
2575 timing);
2576
2577 if (!version_greater(closure->edid, 1, 1))
2578 return; /* GTF not defined yet */
2579
2580 switch (range->flags) {
2581 case 0x02: /* secondary gtf, XXX could do more */
2582 case 0x00: /* default gtf */
2583 closure->modes += drm_gtf_modes_for_range(closure->connector,
2584 closure->edid,
2585 timing);
2586 break;
2587 case 0x04: /* cvt, only in 1.4+ */
2588 if (!version_greater(closure->edid, 1, 3))
2589 break;
2590
2591 closure->modes += drm_cvt_modes_for_range(closure->connector,
2592 closure->edid,
2593 timing);
2594 break;
2595 case 0x01: /* just the ranges, no formula */
2596 default:
2597 break;
2598 }
2599 }
2600
2601 static int
2602 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2603 {
2604 struct detailed_mode_closure closure = {
2605 .connector = connector,
2606 .edid = edid,
2607 };
2608
2609 if (version_greater(edid, 1, 0))
2610 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2611 &closure);
2612
2613 return closure.modes;
2614 }
2615
2616 static int
2617 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2618 {
2619 int i, j, m, modes = 0;
2620 struct drm_display_mode *mode;
2621 u8 *est = ((u8 *)timing) + 6;
2622
2623 for (i = 0; i < 6; i++) {
2624 for (j = 7; j >= 0; j--) {
2625 m = (i * 8) + (7 - j);
2626 if (m >= ARRAY_SIZE(est3_modes))
2627 break;
2628 if (est[i] & (1 << j)) {
2629 mode = drm_mode_find_dmt(connector->dev,
2630 est3_modes[m].w,
2631 est3_modes[m].h,
2632 est3_modes[m].r,
2633 est3_modes[m].rb);
2634 if (mode) {
2635 drm_mode_probed_add(connector, mode);
2636 modes++;
2637 }
2638 }
2639 }
2640 }
2641
2642 return modes;
2643 }
2644
2645 static void
2646 do_established_modes(struct detailed_timing *timing, void *c)
2647 {
2648 struct detailed_mode_closure *closure = c;
2649 struct detailed_non_pixel *data = &timing->data.other_data;
2650
2651 if (data->type == EDID_DETAIL_EST_TIMINGS)
2652 closure->modes += drm_est3_modes(closure->connector, timing);
2653 }
2654
2655 /**
2656 * add_established_modes - get est. modes from EDID and add them
2657 * @connector: connector to add mode(s) to
2658 * @edid: EDID block to scan
2659 *
2660 * Each EDID block contains a bitmap of the supported "established modes" list
2661 * (defined above). Tease them out and add them to the global modes list.
2662 */
2663 static int
2664 add_established_modes(struct drm_connector *connector, struct edid *edid)
2665 {
2666 struct drm_device *dev = connector->dev;
2667 unsigned long est_bits = edid->established_timings.t1 |
2668 (edid->established_timings.t2 << 8) |
2669 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2670 int i, modes = 0;
2671 struct detailed_mode_closure closure = {
2672 .connector = connector,
2673 .edid = edid,
2674 };
2675
2676 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2677 if (est_bits & (1<<i)) {
2678 struct drm_display_mode *newmode;
2679 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2680 if (newmode) {
2681 drm_mode_probed_add(connector, newmode);
2682 modes++;
2683 }
2684 }
2685 }
2686
2687 if (version_greater(edid, 1, 0))
2688 drm_for_each_detailed_block((u8 *)edid,
2689 do_established_modes, &closure);
2690
2691 return modes + closure.modes;
2692 }
2693
2694 static void
2695 do_standard_modes(struct detailed_timing *timing, void *c)
2696 {
2697 struct detailed_mode_closure *closure = c;
2698 struct detailed_non_pixel *data = &timing->data.other_data;
2699 struct drm_connector *connector = closure->connector;
2700 struct edid *edid = closure->edid;
2701
2702 if (data->type == EDID_DETAIL_STD_MODES) {
2703 int i;
2704 for (i = 0; i < 6; i++) {
2705 struct std_timing *std;
2706 struct drm_display_mode *newmode;
2707
2708 std = &data->data.timings[i];
2709 newmode = drm_mode_std(connector, edid, std);
2710 if (newmode) {
2711 drm_mode_probed_add(connector, newmode);
2712 closure->modes++;
2713 }
2714 }
2715 }
2716 }
2717
2718 /**
2719 * add_standard_modes - get std. modes from EDID and add them
2720 * @connector: connector to add mode(s) to
2721 * @edid: EDID block to scan
2722 *
2723 * Standard modes can be calculated using the appropriate standard (DMT,
2724 * GTF or CVT. Grab them from @edid and add them to the list.
2725 */
2726 static int
2727 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2728 {
2729 int i, modes = 0;
2730 struct detailed_mode_closure closure = {
2731 .connector = connector,
2732 .edid = edid,
2733 };
2734
2735 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2736 struct drm_display_mode *newmode;
2737
2738 newmode = drm_mode_std(connector, edid,
2739 &edid->standard_timings[i]);
2740 if (newmode) {
2741 drm_mode_probed_add(connector, newmode);
2742 modes++;
2743 }
2744 }
2745
2746 if (version_greater(edid, 1, 0))
2747 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2748 &closure);
2749
2750 /* XXX should also look for standard codes in VTB blocks */
2751
2752 return modes + closure.modes;
2753 }
2754
2755 static int drm_cvt_modes(struct drm_connector *connector,
2756 struct detailed_timing *timing)
2757 {
2758 int i, j, modes = 0;
2759 struct drm_display_mode *newmode;
2760 struct drm_device *dev = connector->dev;
2761 struct cvt_timing *cvt;
2762 const int rates[] = { 60, 85, 75, 60, 50 };
2763 const u8 empty[3] = { 0, 0, 0 };
2764
2765 for (i = 0; i < 4; i++) {
2766 int uninitialized_var(width), height;
2767 cvt = &(timing->data.other_data.data.cvt[i]);
2768
2769 if (!memcmp(cvt->code, empty, 3))
2770 continue;
2771
2772 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2773 switch (cvt->code[1] & 0x0c) {
2774 case 0x00:
2775 width = height * 4 / 3;
2776 break;
2777 case 0x04:
2778 width = height * 16 / 9;
2779 break;
2780 case 0x08:
2781 width = height * 16 / 10;
2782 break;
2783 case 0x0c:
2784 width = height * 15 / 9;
2785 break;
2786 }
2787
2788 for (j = 1; j < 5; j++) {
2789 if (cvt->code[2] & (1 << j)) {
2790 newmode = drm_cvt_mode(dev, width, height,
2791 rates[j], j == 0,
2792 false, false);
2793 if (newmode) {
2794 drm_mode_probed_add(connector, newmode);
2795 modes++;
2796 }
2797 }
2798 }
2799 }
2800
2801 return modes;
2802 }
2803
2804 static void
2805 do_cvt_mode(struct detailed_timing *timing, void *c)
2806 {
2807 struct detailed_mode_closure *closure = c;
2808 struct detailed_non_pixel *data = &timing->data.other_data;
2809
2810 if (data->type == EDID_DETAIL_CVT_3BYTE)
2811 closure->modes += drm_cvt_modes(closure->connector, timing);
2812 }
2813
2814 static int
2815 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2816 {
2817 struct detailed_mode_closure closure = {
2818 .connector = connector,
2819 .edid = edid,
2820 };
2821
2822 if (version_greater(edid, 1, 2))
2823 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2824
2825 /* XXX should also look for CVT codes in VTB blocks */
2826
2827 return closure.modes;
2828 }
2829
2830 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2831
2832 static void
2833 do_detailed_mode(struct detailed_timing *timing, void *c)
2834 {
2835 struct detailed_mode_closure *closure = c;
2836 struct drm_display_mode *newmode;
2837
2838 if (timing->pixel_clock) {
2839 newmode = drm_mode_detailed(closure->connector->dev,
2840 closure->edid, timing,
2841 closure->quirks);
2842 if (!newmode)
2843 return;
2844
2845 if (closure->preferred)
2846 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2847
2848 /*
2849 * Detailed modes are limited to 10kHz pixel clock resolution,
2850 * so fix up anything that looks like CEA/HDMI mode, but the clock
2851 * is just slightly off.
2852 */
2853 fixup_detailed_cea_mode_clock(newmode);
2854
2855 drm_mode_probed_add(closure->connector, newmode);
2856 closure->modes++;
2857 closure->preferred = false;
2858 }
2859 }
2860
2861 /*
2862 * add_detailed_modes - Add modes from detailed timings
2863 * @connector: attached connector
2864 * @edid: EDID block to scan
2865 * @quirks: quirks to apply
2866 */
2867 static int
2868 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2869 u32 quirks)
2870 {
2871 struct detailed_mode_closure closure = {
2872 .connector = connector,
2873 .edid = edid,
2874 .preferred = true,
2875 .quirks = quirks,
2876 };
2877
2878 if (closure.preferred && !version_greater(edid, 1, 3))
2879 closure.preferred =
2880 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2881
2882 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2883
2884 return closure.modes;
2885 }
2886
2887 #define AUDIO_BLOCK 0x01
2888 #define VIDEO_BLOCK 0x02
2889 #define VENDOR_BLOCK 0x03
2890 #define SPEAKER_BLOCK 0x04
2891 #define USE_EXTENDED_TAG 0x07
2892 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2893 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2894 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2895 #define EDID_BASIC_AUDIO (1 << 6)
2896 #define EDID_CEA_YCRCB444 (1 << 5)
2897 #define EDID_CEA_YCRCB422 (1 << 4)
2898 #define EDID_CEA_VCDB_QS (1 << 6)
2899
2900 /*
2901 * Search EDID for CEA extension block.
2902 */
2903 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2904 {
2905 u8 *edid_ext = NULL;
2906 int i;
2907
2908 /* No EDID or EDID extensions */
2909 if (edid == NULL || edid->extensions == 0)
2910 return NULL;
2911
2912 /* Find CEA extension */
2913 for (i = 0; i < edid->extensions; i++) {
2914 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2915 if (edid_ext[0] == ext_id)
2916 break;
2917 }
2918
2919 if (i == edid->extensions)
2920 return NULL;
2921
2922 return edid_ext;
2923 }
2924
2925 static u8 *drm_find_cea_extension(const struct edid *edid)
2926 {
2927 return drm_find_edid_extension(edid, CEA_EXT);
2928 }
2929
2930 static u8 *drm_find_displayid_extension(const struct edid *edid)
2931 {
2932 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2933 }
2934
2935 /*
2936 * Calculate the alternate clock for the CEA mode
2937 * (60Hz vs. 59.94Hz etc.)
2938 */
2939 static unsigned int
2940 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2941 {
2942 unsigned int clock = cea_mode->clock;
2943
2944 if (cea_mode->vrefresh % 6 != 0)
2945 return clock;
2946
2947 /*
2948 * edid_cea_modes contains the 59.94Hz
2949 * variant for 240 and 480 line modes,
2950 * and the 60Hz variant otherwise.
2951 */
2952 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2953 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2954 else
2955 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2956
2957 return clock;
2958 }
2959
2960 static bool
2961 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2962 {
2963 /*
2964 * For certain VICs the spec allows the vertical
2965 * front porch to vary by one or two lines.
2966 *
2967 * cea_modes[] stores the variant with the shortest
2968 * vertical front porch. We can adjust the mode to
2969 * get the other variants by simply increasing the
2970 * vertical front porch length.
2971 */
2972 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2973 edid_cea_modes[9].vtotal != 262 ||
2974 edid_cea_modes[12].vtotal != 262 ||
2975 edid_cea_modes[13].vtotal != 262 ||
2976 edid_cea_modes[23].vtotal != 312 ||
2977 edid_cea_modes[24].vtotal != 312 ||
2978 edid_cea_modes[27].vtotal != 312 ||
2979 edid_cea_modes[28].vtotal != 312);
2980
2981 if (((vic == 8 || vic == 9 ||
2982 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2983 ((vic == 23 || vic == 24 ||
2984 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2985 mode->vsync_start++;
2986 mode->vsync_end++;
2987 mode->vtotal++;
2988
2989 return true;
2990 }
2991
2992 return false;
2993 }
2994
2995 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2996 unsigned int clock_tolerance)
2997 {
2998 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2999 u8 vic;
3000
3001 if (!to_match->clock)
3002 return 0;
3003
3004 if (to_match->picture_aspect_ratio)
3005 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3006
3007 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3008 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3009 unsigned int clock1, clock2;
3010
3011 /* Check both 60Hz and 59.94Hz */
3012 clock1 = cea_mode.clock;
3013 clock2 = cea_mode_alternate_clock(&cea_mode);
3014
3015 if (abs(to_match->clock - clock1) > clock_tolerance &&
3016 abs(to_match->clock - clock2) > clock_tolerance)
3017 continue;
3018
3019 do {
3020 if (drm_mode_match(to_match, &cea_mode, match_flags))
3021 return vic;
3022 } while (cea_mode_alternate_timings(vic, &cea_mode));
3023 }
3024
3025 return 0;
3026 }
3027
3028 /**
3029 * drm_match_cea_mode - look for a CEA mode matching given mode
3030 * @to_match: display mode
3031 *
3032 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3033 * mode.
3034 */
3035 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3036 {
3037 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3038 u8 vic;
3039
3040 if (!to_match->clock)
3041 return 0;
3042
3043 if (to_match->picture_aspect_ratio)
3044 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3045
3046 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3047 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3048 unsigned int clock1, clock2;
3049
3050 /* Check both 60Hz and 59.94Hz */
3051 clock1 = cea_mode.clock;
3052 clock2 = cea_mode_alternate_clock(&cea_mode);
3053
3054 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3055 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3056 continue;
3057
3058 do {
3059 if (drm_mode_match(to_match, &cea_mode, match_flags))
3060 return vic;
3061 } while (cea_mode_alternate_timings(vic, &cea_mode));
3062 }
3063
3064 return 0;
3065 }
3066 EXPORT_SYMBOL(drm_match_cea_mode);
3067
3068 static bool drm_valid_cea_vic(u8 vic)
3069 {
3070 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3071 }
3072
3073 /**
3074 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3075 * the input VIC from the CEA mode list
3076 * @video_code: ID given to each of the CEA modes
3077 *
3078 * Returns picture aspect ratio
3079 */
3080 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3081 {
3082 return edid_cea_modes[video_code].picture_aspect_ratio;
3083 }
3084 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3085
3086 /*
3087 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3088 * specific block).
3089 *
3090 * It's almost like cea_mode_alternate_clock(), we just need to add an
3091 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3092 * one.
3093 */
3094 static unsigned int
3095 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3096 {
3097 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3098 return hdmi_mode->clock;
3099
3100 return cea_mode_alternate_clock(hdmi_mode);
3101 }
3102
3103 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3104 unsigned int clock_tolerance)
3105 {
3106 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3107 u8 vic;
3108
3109 if (!to_match->clock)
3110 return 0;
3111
3112 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3113 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3114 unsigned int clock1, clock2;
3115
3116 /* Make sure to also match alternate clocks */
3117 clock1 = hdmi_mode->clock;
3118 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3119
3120 if (abs(to_match->clock - clock1) > clock_tolerance &&
3121 abs(to_match->clock - clock2) > clock_tolerance)
3122 continue;
3123
3124 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3125 return vic;
3126 }
3127
3128 return 0;
3129 }
3130
3131 /*
3132 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3133 * @to_match: display mode
3134 *
3135 * An HDMI mode is one defined in the HDMI vendor specific block.
3136 *
3137 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3138 */
3139 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3140 {
3141 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3142 u8 vic;
3143
3144 if (!to_match->clock)
3145 return 0;
3146
3147 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3148 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3149 unsigned int clock1, clock2;
3150
3151 /* Make sure to also match alternate clocks */
3152 clock1 = hdmi_mode->clock;
3153 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3154
3155 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3156 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3157 drm_mode_match(to_match, hdmi_mode, match_flags))
3158 return vic;
3159 }
3160 return 0;
3161 }
3162
3163 static bool drm_valid_hdmi_vic(u8 vic)
3164 {
3165 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3166 }
3167
3168 static int
3169 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3170 {
3171 struct drm_device *dev = connector->dev;
3172 struct drm_display_mode *mode, *tmp;
3173 LIST_HEAD(list);
3174 int modes = 0;
3175
3176 /* Don't add CEA modes if the CEA extension block is missing */
3177 if (!drm_find_cea_extension(edid))
3178 return 0;
3179
3180 /*
3181 * Go through all probed modes and create a new mode
3182 * with the alternate clock for certain CEA modes.
3183 */
3184 list_for_each_entry(mode, &connector->probed_modes, head) {
3185 const struct drm_display_mode *cea_mode = NULL;
3186 struct drm_display_mode *newmode;
3187 u8 vic = drm_match_cea_mode(mode);
3188 unsigned int clock1, clock2;
3189
3190 if (drm_valid_cea_vic(vic)) {
3191 cea_mode = &edid_cea_modes[vic];
3192 clock2 = cea_mode_alternate_clock(cea_mode);
3193 } else {
3194 vic = drm_match_hdmi_mode(mode);
3195 if (drm_valid_hdmi_vic(vic)) {
3196 cea_mode = &edid_4k_modes[vic];
3197 clock2 = hdmi_mode_alternate_clock(cea_mode);
3198 }
3199 }
3200
3201 if (!cea_mode)
3202 continue;
3203
3204 clock1 = cea_mode->clock;
3205
3206 if (clock1 == clock2)
3207 continue;
3208
3209 if (mode->clock != clock1 && mode->clock != clock2)
3210 continue;
3211
3212 newmode = drm_mode_duplicate(dev, cea_mode);
3213 if (!newmode)
3214 continue;
3215
3216 /* Carry over the stereo flags */
3217 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3218
3219 /*
3220 * The current mode could be either variant. Make
3221 * sure to pick the "other" clock for the new mode.
3222 */
3223 if (mode->clock != clock1)
3224 newmode->clock = clock1;
3225 else
3226 newmode->clock = clock2;
3227
3228 list_add_tail(&newmode->head, &list);
3229 }
3230
3231 list_for_each_entry_safe(mode, tmp, &list, head) {
3232 list_del(&mode->head);
3233 drm_mode_probed_add(connector, mode);
3234 modes++;
3235 }
3236
3237 return modes;
3238 }
3239
3240 static u8 svd_to_vic(u8 svd)
3241 {
3242 /* 0-6 bit vic, 7th bit native mode indicator */
3243 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3244 return svd & 127;
3245
3246 return svd;
3247 }
3248
3249 static struct drm_display_mode *
3250 drm_display_mode_from_vic_index(struct drm_connector *connector,
3251 const u8 *video_db, u8 video_len,
3252 u8 video_index)
3253 {
3254 struct drm_device *dev = connector->dev;
3255 struct drm_display_mode *newmode;
3256 u8 vic;
3257
3258 if (video_db == NULL || video_index >= video_len)
3259 return NULL;
3260
3261 /* CEA modes are numbered 1..127 */
3262 vic = svd_to_vic(video_db[video_index]);
3263 if (!drm_valid_cea_vic(vic))
3264 return NULL;
3265
3266 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3267 if (!newmode)
3268 return NULL;
3269
3270 newmode->vrefresh = 0;
3271
3272 return newmode;
3273 }
3274
3275 /*
3276 * do_y420vdb_modes - Parse YCBCR 420 only modes
3277 * @connector: connector corresponding to the HDMI sink
3278 * @svds: start of the data block of CEA YCBCR 420 VDB
3279 * @len: length of the CEA YCBCR 420 VDB
3280 *
3281 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3282 * which contains modes which can be supported in YCBCR 420
3283 * output format only.
3284 */
3285 static int do_y420vdb_modes(struct drm_connector *connector,
3286 const u8 *svds, u8 svds_len)
3287 {
3288 int modes = 0, i;
3289 struct drm_device *dev = connector->dev;
3290 struct drm_display_info *info = &connector->display_info;
3291 struct drm_hdmi_info *hdmi = &info->hdmi;
3292
3293 for (i = 0; i < svds_len; i++) {
3294 u8 vic = svd_to_vic(svds[i]);
3295 struct drm_display_mode *newmode;
3296
3297 if (!drm_valid_cea_vic(vic))
3298 continue;
3299
3300 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3301 if (!newmode)
3302 break;
3303 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3304 drm_mode_probed_add(connector, newmode);
3305 modes++;
3306 }
3307
3308 if (modes > 0)
3309 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3310 return modes;
3311 }
3312
3313 /*
3314 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3315 * @connector: connector corresponding to the HDMI sink
3316 * @vic: CEA vic for the video mode to be added in the map
3317 *
3318 * Makes an entry for a videomode in the YCBCR 420 bitmap
3319 */
3320 static void
3321 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3322 {
3323 u8 vic = svd_to_vic(svd);
3324 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3325
3326 if (!drm_valid_cea_vic(vic))
3327 return;
3328
3329 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3330 }
3331
3332 static int
3333 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3334 {
3335 int i, modes = 0;
3336 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3337
3338 for (i = 0; i < len; i++) {
3339 struct drm_display_mode *mode;
3340 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3341 if (mode) {
3342 /*
3343 * YCBCR420 capability block contains a bitmap which
3344 * gives the index of CEA modes from CEA VDB, which
3345 * can support YCBCR 420 sampling output also (apart
3346 * from RGB/YCBCR444 etc).
3347 * For example, if the bit 0 in bitmap is set,
3348 * first mode in VDB can support YCBCR420 output too.
3349 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3350 */
3351 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3352 drm_add_cmdb_modes(connector, db[i]);
3353
3354 drm_mode_probed_add(connector, mode);
3355 modes++;
3356 }
3357 }
3358
3359 return modes;
3360 }
3361
3362 struct stereo_mandatory_mode {
3363 int width, height, vrefresh;
3364 unsigned int flags;
3365 };
3366
3367 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3368 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3369 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3370 { 1920, 1080, 50,
3371 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3372 { 1920, 1080, 60,
3373 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3374 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3375 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3376 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3377 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3378 };
3379
3380 static bool
3381 stereo_match_mandatory(const struct drm_display_mode *mode,
3382 const struct stereo_mandatory_mode *stereo_mode)
3383 {
3384 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3385
3386 return mode->hdisplay == stereo_mode->width &&
3387 mode->vdisplay == stereo_mode->height &&
3388 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3389 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3390 }
3391
3392 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3393 {
3394 struct drm_device *dev = connector->dev;
3395 const struct drm_display_mode *mode;
3396 struct list_head stereo_modes;
3397 int modes = 0, i;
3398
3399 INIT_LIST_HEAD(&stereo_modes);
3400
3401 list_for_each_entry(mode, &connector->probed_modes, head) {
3402 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3403 const struct stereo_mandatory_mode *mandatory;
3404 struct drm_display_mode *new_mode;
3405
3406 if (!stereo_match_mandatory(mode,
3407 &stereo_mandatory_modes[i]))
3408 continue;
3409
3410 mandatory = &stereo_mandatory_modes[i];
3411 new_mode = drm_mode_duplicate(dev, mode);
3412 if (!new_mode)
3413 continue;
3414
3415 new_mode->flags |= mandatory->flags;
3416 list_add_tail(&new_mode->head, &stereo_modes);
3417 modes++;
3418 }
3419 }
3420
3421 list_splice_tail(&stereo_modes, &connector->probed_modes);
3422
3423 return modes;
3424 }
3425
3426 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3427 {
3428 struct drm_device *dev = connector->dev;
3429 struct drm_display_mode *newmode;
3430
3431 if (!drm_valid_hdmi_vic(vic)) {
3432 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3433 return 0;
3434 }
3435
3436 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3437 if (!newmode)
3438 return 0;
3439
3440 drm_mode_probed_add(connector, newmode);
3441
3442 return 1;
3443 }
3444
3445 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3446 const u8 *video_db, u8 video_len, u8 video_index)
3447 {
3448 struct drm_display_mode *newmode;
3449 int modes = 0;
3450
3451 if (structure & (1 << 0)) {
3452 newmode = drm_display_mode_from_vic_index(connector, video_db,
3453 video_len,
3454 video_index);
3455 if (newmode) {
3456 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3457 drm_mode_probed_add(connector, newmode);
3458 modes++;
3459 }
3460 }
3461 if (structure & (1 << 6)) {
3462 newmode = drm_display_mode_from_vic_index(connector, video_db,
3463 video_len,
3464 video_index);
3465 if (newmode) {
3466 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3467 drm_mode_probed_add(connector, newmode);
3468 modes++;
3469 }
3470 }
3471 if (structure & (1 << 8)) {
3472 newmode = drm_display_mode_from_vic_index(connector, video_db,
3473 video_len,
3474 video_index);
3475 if (newmode) {
3476 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3477 drm_mode_probed_add(connector, newmode);
3478 modes++;
3479 }
3480 }
3481
3482 return modes;
3483 }
3484
3485 /*
3486 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3487 * @connector: connector corresponding to the HDMI sink
3488 * @db: start of the CEA vendor specific block
3489 * @len: length of the CEA block payload, ie. one can access up to db[len]
3490 *
3491 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3492 * also adds the stereo 3d modes when applicable.
3493 */
3494 static int
3495 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3496 const u8 *video_db, u8 video_len)
3497 {
3498 struct drm_display_info *info = &connector->display_info;
3499 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3500 u8 vic_len, hdmi_3d_len = 0;
3501 u16 mask;
3502 u16 structure_all;
3503
3504 if (len < 8)
3505 goto out;
3506
3507 /* no HDMI_Video_Present */
3508 if (!(db[8] & (1 << 5)))
3509 goto out;
3510
3511 /* Latency_Fields_Present */
3512 if (db[8] & (1 << 7))
3513 offset += 2;
3514
3515 /* I_Latency_Fields_Present */
3516 if (db[8] & (1 << 6))
3517 offset += 2;
3518
3519 /* the declared length is not long enough for the 2 first bytes
3520 * of additional video format capabilities */
3521 if (len < (8 + offset + 2))
3522 goto out;
3523
3524 /* 3D_Present */
3525 offset++;
3526 if (db[8 + offset] & (1 << 7)) {
3527 modes += add_hdmi_mandatory_stereo_modes(connector);
3528
3529 /* 3D_Multi_present */
3530 multi_present = (db[8 + offset] & 0x60) >> 5;
3531 }
3532
3533 offset++;
3534 vic_len = db[8 + offset] >> 5;
3535 hdmi_3d_len = db[8 + offset] & 0x1f;
3536
3537 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3538 u8 vic;
3539
3540 vic = db[9 + offset + i];
3541 modes += add_hdmi_mode(connector, vic);
3542 }
3543 offset += 1 + vic_len;
3544
3545 if (multi_present == 1)
3546 multi_len = 2;
3547 else if (multi_present == 2)
3548 multi_len = 4;
3549 else
3550 multi_len = 0;
3551
3552 if (len < (8 + offset + hdmi_3d_len - 1))
3553 goto out;
3554
3555 if (hdmi_3d_len < multi_len)
3556 goto out;
3557
3558 if (multi_present == 1 || multi_present == 2) {
3559 /* 3D_Structure_ALL */
3560 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3561
3562 /* check if 3D_MASK is present */
3563 if (multi_present == 2)
3564 mask = (db[10 + offset] << 8) | db[11 + offset];
3565 else
3566 mask = 0xffff;
3567
3568 for (i = 0; i < 16; i++) {
3569 if (mask & (1 << i))
3570 modes += add_3d_struct_modes(connector,
3571 structure_all,
3572 video_db,
3573 video_len, i);
3574 }
3575 }
3576
3577 offset += multi_len;
3578
3579 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3580 int vic_index;
3581 struct drm_display_mode *newmode = NULL;
3582 unsigned int newflag = 0;
3583 bool detail_present;
3584
3585 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3586
3587 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3588 break;
3589
3590 /* 2D_VIC_order_X */
3591 vic_index = db[8 + offset + i] >> 4;
3592
3593 /* 3D_Structure_X */
3594 switch (db[8 + offset + i] & 0x0f) {
3595 case 0:
3596 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3597 break;
3598 case 6:
3599 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3600 break;
3601 case 8:
3602 /* 3D_Detail_X */
3603 if ((db[9 + offset + i] >> 4) == 1)
3604 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3605 break;
3606 }
3607
3608 if (newflag != 0) {
3609 newmode = drm_display_mode_from_vic_index(connector,
3610 video_db,
3611 video_len,
3612 vic_index);
3613
3614 if (newmode) {
3615 newmode->flags |= newflag;
3616 drm_mode_probed_add(connector, newmode);
3617 modes++;
3618 }
3619 }
3620
3621 if (detail_present)
3622 i++;
3623 }
3624
3625 out:
3626 if (modes > 0)
3627 info->has_hdmi_infoframe = true;
3628 return modes;
3629 }
3630
3631 static int
3632 cea_db_payload_len(const u8 *db)
3633 {
3634 return db[0] & 0x1f;
3635 }
3636
3637 static int
3638 cea_db_extended_tag(const u8 *db)
3639 {
3640 return db[1];
3641 }
3642
3643 static int
3644 cea_db_tag(const u8 *db)
3645 {
3646 return db[0] >> 5;
3647 }
3648
3649 static int
3650 cea_revision(const u8 *cea)
3651 {
3652 return cea[1];
3653 }
3654
3655 static int
3656 cea_db_offsets(const u8 *cea, int *start, int *end)
3657 {
3658 /* Data block offset in CEA extension block */
3659 *start = 4;
3660 *end = cea[2];
3661 if (*end == 0)
3662 *end = 127;
3663 if (*end < 4 || *end > 127)
3664 return -ERANGE;
3665 return 0;
3666 }
3667
3668 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3669 {
3670 int hdmi_id;
3671
3672 if (cea_db_tag(db) != VENDOR_BLOCK)
3673 return false;
3674
3675 if (cea_db_payload_len(db) < 5)
3676 return false;
3677
3678 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3679
3680 return hdmi_id == HDMI_IEEE_OUI;
3681 }
3682
3683 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3684 {
3685 unsigned int oui;
3686
3687 if (cea_db_tag(db) != VENDOR_BLOCK)
3688 return false;
3689
3690 if (cea_db_payload_len(db) < 7)
3691 return false;
3692
3693 oui = db[3] << 16 | db[2] << 8 | db[1];
3694
3695 return oui == HDMI_FORUM_IEEE_OUI;
3696 }
3697
3698 static bool cea_db_is_vcdb(const u8 *db)
3699 {
3700 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3701 return false;
3702
3703 if (cea_db_payload_len(db) != 2)
3704 return false;
3705
3706 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
3707 return false;
3708
3709 return true;
3710 }
3711
3712 static bool cea_db_is_y420cmdb(const u8 *db)
3713 {
3714 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3715 return false;
3716
3717 if (!cea_db_payload_len(db))
3718 return false;
3719
3720 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3721 return false;
3722
3723 return true;
3724 }
3725
3726 static bool cea_db_is_y420vdb(const u8 *db)
3727 {
3728 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3729 return false;
3730
3731 if (!cea_db_payload_len(db))
3732 return false;
3733
3734 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3735 return false;
3736
3737 return true;
3738 }
3739
3740 #define for_each_cea_db(cea, i, start, end) \
3741 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3742
3743 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3744 const u8 *db)
3745 {
3746 struct drm_display_info *info = &connector->display_info;
3747 struct drm_hdmi_info *hdmi = &info->hdmi;
3748 u8 map_len = cea_db_payload_len(db) - 1;
3749 u8 count;
3750 u64 map = 0;
3751
3752 if (map_len == 0) {
3753 /* All CEA modes support ycbcr420 sampling also.*/
3754 hdmi->y420_cmdb_map = U64_MAX;
3755 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3756 return;
3757 }
3758
3759 /*
3760 * This map indicates which of the existing CEA block modes
3761 * from VDB can support YCBCR420 output too. So if bit=0 is
3762 * set, first mode from VDB can support YCBCR420 output too.
3763 * We will parse and keep this map, before parsing VDB itself
3764 * to avoid going through the same block again and again.
3765 *
3766 * Spec is not clear about max possible size of this block.
3767 * Clamping max bitmap block size at 8 bytes. Every byte can
3768 * address 8 CEA modes, in this way this map can address
3769 * 8*8 = first 64 SVDs.
3770 */
3771 if (WARN_ON_ONCE(map_len > 8))
3772 map_len = 8;
3773
3774 for (count = 0; count < map_len; count++)
3775 map |= (u64)db[2 + count] << (8 * count);
3776
3777 if (map)
3778 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3779
3780 hdmi->y420_cmdb_map = map;
3781 }
3782
3783 static int
3784 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3785 {
3786 const u8 *cea = drm_find_cea_extension(edid);
3787 const u8 *db, *hdmi = NULL, *video = NULL;
3788 u8 dbl, hdmi_len, video_len = 0;
3789 int modes = 0;
3790
3791 if (cea && cea_revision(cea) >= 3) {
3792 int i, start, end;
3793
3794 if (cea_db_offsets(cea, &start, &end))
3795 return 0;
3796
3797 for_each_cea_db(cea, i, start, end) {
3798 db = &cea[i];
3799 dbl = cea_db_payload_len(db);
3800
3801 if (cea_db_tag(db) == VIDEO_BLOCK) {
3802 video = db + 1;
3803 video_len = dbl;
3804 modes += do_cea_modes(connector, video, dbl);
3805 } else if (cea_db_is_hdmi_vsdb(db)) {
3806 hdmi = db;
3807 hdmi_len = dbl;
3808 } else if (cea_db_is_y420vdb(db)) {
3809 const u8 *vdb420 = &db[2];
3810
3811 /* Add 4:2:0(only) modes present in EDID */
3812 modes += do_y420vdb_modes(connector,
3813 vdb420,
3814 dbl - 1);
3815 }
3816 }
3817 }
3818
3819 /*
3820 * We parse the HDMI VSDB after having added the cea modes as we will
3821 * be patching their flags when the sink supports stereo 3D.
3822 */
3823 if (hdmi)
3824 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3825 video_len);
3826
3827 return modes;
3828 }
3829
3830 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3831 {
3832 const struct drm_display_mode *cea_mode;
3833 int clock1, clock2, clock;
3834 u8 vic;
3835 const char *type;
3836
3837 /*
3838 * allow 5kHz clock difference either way to account for
3839 * the 10kHz clock resolution limit of detailed timings.
3840 */
3841 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3842 if (drm_valid_cea_vic(vic)) {
3843 type = "CEA";
3844 cea_mode = &edid_cea_modes[vic];
3845 clock1 = cea_mode->clock;
3846 clock2 = cea_mode_alternate_clock(cea_mode);
3847 } else {
3848 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3849 if (drm_valid_hdmi_vic(vic)) {
3850 type = "HDMI";
3851 cea_mode = &edid_4k_modes[vic];
3852 clock1 = cea_mode->clock;
3853 clock2 = hdmi_mode_alternate_clock(cea_mode);
3854 } else {
3855 return;
3856 }
3857 }
3858
3859 /* pick whichever is closest */
3860 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3861 clock = clock1;
3862 else
3863 clock = clock2;
3864
3865 if (mode->clock == clock)
3866 return;
3867
3868 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3869 type, vic, mode->clock, clock);
3870 mode->clock = clock;
3871 }
3872
3873 static void
3874 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3875 {
3876 u8 len = cea_db_payload_len(db);
3877
3878 if (len >= 6 && (db[6] & (1 << 7)))
3879 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3880 if (len >= 8) {
3881 connector->latency_present[0] = db[8] >> 7;
3882 connector->latency_present[1] = (db[8] >> 6) & 1;
3883 }
3884 if (len >= 9)
3885 connector->video_latency[0] = db[9];
3886 if (len >= 10)
3887 connector->audio_latency[0] = db[10];
3888 if (len >= 11)
3889 connector->video_latency[1] = db[11];
3890 if (len >= 12)
3891 connector->audio_latency[1] = db[12];
3892
3893 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3894 "video latency %d %d, "
3895 "audio latency %d %d\n",
3896 connector->latency_present[0],
3897 connector->latency_present[1],
3898 connector->video_latency[0],
3899 connector->video_latency[1],
3900 connector->audio_latency[0],
3901 connector->audio_latency[1]);
3902 }
3903
3904 static void
3905 monitor_name(struct detailed_timing *t, void *data)
3906 {
3907 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3908 *(u8 **)data = t->data.other_data.data.str.str;
3909 }
3910
3911 static int get_monitor_name(struct edid *edid, char name[13])
3912 {
3913 char *edid_name = NULL;
3914 int mnl;
3915
3916 if (!edid || !name)
3917 return 0;
3918
3919 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3920 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3921 if (edid_name[mnl] == 0x0a)
3922 break;
3923
3924 name[mnl] = edid_name[mnl];
3925 }
3926
3927 return mnl;
3928 }
3929
3930 /**
3931 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3932 * @edid: monitor EDID information
3933 * @name: pointer to a character array to hold the name of the monitor
3934 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3935 *
3936 */
3937 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3938 {
3939 int name_length;
3940 char buf[13];
3941
3942 if (bufsize <= 0)
3943 return;
3944
3945 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3946 memcpy(name, buf, name_length);
3947 name[name_length] = '\0';
3948 }
3949 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3950
3951 static void clear_eld(struct drm_connector *connector)
3952 {
3953 memset(connector->eld, 0, sizeof(connector->eld));
3954
3955 connector->latency_present[0] = false;
3956 connector->latency_present[1] = false;
3957 connector->video_latency[0] = 0;
3958 connector->audio_latency[0] = 0;
3959 connector->video_latency[1] = 0;
3960 connector->audio_latency[1] = 0;
3961 }
3962
3963 /*
3964 * drm_edid_to_eld - build ELD from EDID
3965 * @connector: connector corresponding to the HDMI/DP sink
3966 * @edid: EDID to parse
3967 *
3968 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3969 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3970 */
3971 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3972 {
3973 uint8_t *eld = connector->eld;
3974 u8 *cea;
3975 u8 *db;
3976 int total_sad_count = 0;
3977 int mnl;
3978 int dbl;
3979
3980 clear_eld(connector);
3981
3982 if (!edid)
3983 return;
3984
3985 cea = drm_find_cea_extension(edid);
3986 if (!cea) {
3987 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3988 return;
3989 }
3990
3991 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3992 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
3993
3994 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3995 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
3996
3997 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
3998
3999 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4000 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4001 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4002 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4003
4004 if (cea_revision(cea) >= 3) {
4005 int i, start, end;
4006
4007 if (cea_db_offsets(cea, &start, &end)) {
4008 start = 0;
4009 end = 0;
4010 }
4011
4012 for_each_cea_db(cea, i, start, end) {
4013 db = &cea[i];
4014 dbl = cea_db_payload_len(db);
4015
4016 switch (cea_db_tag(db)) {
4017 int sad_count;
4018
4019 case AUDIO_BLOCK:
4020 /* Audio Data Block, contains SADs */
4021 sad_count = min(dbl / 3, 15 - total_sad_count);
4022 if (sad_count >= 1)
4023 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4024 &db[1], sad_count * 3);
4025 total_sad_count += sad_count;
4026 break;
4027 case SPEAKER_BLOCK:
4028 /* Speaker Allocation Data Block */
4029 if (dbl >= 1)
4030 eld[DRM_ELD_SPEAKER] = db[1];
4031 break;
4032 case VENDOR_BLOCK:
4033 /* HDMI Vendor-Specific Data Block */
4034 if (cea_db_is_hdmi_vsdb(db))
4035 drm_parse_hdmi_vsdb_audio(connector, db);
4036 break;
4037 default:
4038 break;
4039 }
4040 }
4041 }
4042 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4043
4044 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4045 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4046 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4047 else
4048 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4049
4050 eld[DRM_ELD_BASELINE_ELD_LEN] =
4051 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4052
4053 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4054 drm_eld_size(eld), total_sad_count);
4055 }
4056
4057 /**
4058 * drm_edid_to_sad - extracts SADs from EDID
4059 * @edid: EDID to parse
4060 * @sads: pointer that will be set to the extracted SADs
4061 *
4062 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4063 *
4064 * Note: The returned pointer needs to be freed using kfree().
4065 *
4066 * Return: The number of found SADs or negative number on error.
4067 */
4068 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4069 {
4070 int count = 0;
4071 int i, start, end, dbl;
4072 u8 *cea;
4073
4074 cea = drm_find_cea_extension(edid);
4075 if (!cea) {
4076 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4077 return -ENOENT;
4078 }
4079
4080 if (cea_revision(cea) < 3) {
4081 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4082 return -ENOTSUPP;
4083 }
4084
4085 if (cea_db_offsets(cea, &start, &end)) {
4086 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4087 return -EPROTO;
4088 }
4089
4090 for_each_cea_db(cea, i, start, end) {
4091 u8 *db = &cea[i];
4092
4093 if (cea_db_tag(db) == AUDIO_BLOCK) {
4094 int j;
4095 dbl = cea_db_payload_len(db);
4096
4097 count = dbl / 3; /* SAD is 3B */
4098 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4099 if (!*sads)
4100 return -ENOMEM;
4101 for (j = 0; j < count; j++) {
4102 u8 *sad = &db[1 + j * 3];
4103
4104 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4105 (*sads)[j].channels = sad[0] & 0x7;
4106 (*sads)[j].freq = sad[1] & 0x7F;
4107 (*sads)[j].byte2 = sad[2];
4108 }
4109 break;
4110 }
4111 }
4112
4113 return count;
4114 }
4115 EXPORT_SYMBOL(drm_edid_to_sad);
4116
4117 /**
4118 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4119 * @edid: EDID to parse
4120 * @sadb: pointer to the speaker block
4121 *
4122 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4123 *
4124 * Note: The returned pointer needs to be freed using kfree().
4125 *
4126 * Return: The number of found Speaker Allocation Blocks or negative number on
4127 * error.
4128 */
4129 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4130 {
4131 int count = 0;
4132 int i, start, end, dbl;
4133 const u8 *cea;
4134
4135 cea = drm_find_cea_extension(edid);
4136 if (!cea) {
4137 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4138 return -ENOENT;
4139 }
4140
4141 if (cea_revision(cea) < 3) {
4142 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4143 return -ENOTSUPP;
4144 }
4145
4146 if (cea_db_offsets(cea, &start, &end)) {
4147 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4148 return -EPROTO;
4149 }
4150
4151 for_each_cea_db(cea, i, start, end) {
4152 const u8 *db = &cea[i];
4153
4154 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4155 dbl = cea_db_payload_len(db);
4156
4157 /* Speaker Allocation Data Block */
4158 if (dbl == 3) {
4159 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4160 if (!*sadb)
4161 return -ENOMEM;
4162 count = dbl;
4163 break;
4164 }
4165 }
4166 }
4167
4168 return count;
4169 }
4170 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4171
4172 /**
4173 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4174 * @connector: connector associated with the HDMI/DP sink
4175 * @mode: the display mode
4176 *
4177 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4178 * the sink doesn't support audio or video.
4179 */
4180 int drm_av_sync_delay(struct drm_connector *connector,
4181 const struct drm_display_mode *mode)
4182 {
4183 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4184 int a, v;
4185
4186 if (!connector->latency_present[0])
4187 return 0;
4188 if (!connector->latency_present[1])
4189 i = 0;
4190
4191 a = connector->audio_latency[i];
4192 v = connector->video_latency[i];
4193
4194 /*
4195 * HDMI/DP sink doesn't support audio or video?
4196 */
4197 if (a == 255 || v == 255)
4198 return 0;
4199
4200 /*
4201 * Convert raw EDID values to millisecond.
4202 * Treat unknown latency as 0ms.
4203 */
4204 if (a)
4205 a = min(2 * (a - 1), 500);
4206 if (v)
4207 v = min(2 * (v - 1), 500);
4208
4209 return max(v - a, 0);
4210 }
4211 EXPORT_SYMBOL(drm_av_sync_delay);
4212
4213 /**
4214 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4215 * @edid: monitor EDID information
4216 *
4217 * Parse the CEA extension according to CEA-861-B.
4218 *
4219 * Return: True if the monitor is HDMI, false if not or unknown.
4220 */
4221 bool drm_detect_hdmi_monitor(struct edid *edid)
4222 {
4223 u8 *edid_ext;
4224 int i;
4225 int start_offset, end_offset;
4226
4227 edid_ext = drm_find_cea_extension(edid);
4228 if (!edid_ext)
4229 return false;
4230
4231 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4232 return false;
4233
4234 /*
4235 * Because HDMI identifier is in Vendor Specific Block,
4236 * search it from all data blocks of CEA extension.
4237 */
4238 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4239 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4240 return true;
4241 }
4242
4243 return false;
4244 }
4245 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4246
4247 /**
4248 * drm_detect_monitor_audio - check monitor audio capability
4249 * @edid: EDID block to scan
4250 *
4251 * Monitor should have CEA extension block.
4252 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4253 * audio' only. If there is any audio extension block and supported
4254 * audio format, assume at least 'basic audio' support, even if 'basic
4255 * audio' is not defined in EDID.
4256 *
4257 * Return: True if the monitor supports audio, false otherwise.
4258 */
4259 bool drm_detect_monitor_audio(struct edid *edid)
4260 {
4261 u8 *edid_ext;
4262 int i, j;
4263 bool has_audio = false;
4264 int start_offset, end_offset;
4265
4266 edid_ext = drm_find_cea_extension(edid);
4267 if (!edid_ext)
4268 goto end;
4269
4270 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4271
4272 if (has_audio) {
4273 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4274 goto end;
4275 }
4276
4277 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4278 goto end;
4279
4280 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4281 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4282 has_audio = true;
4283 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4284 DRM_DEBUG_KMS("CEA audio format %d\n",
4285 (edid_ext[i + j] >> 3) & 0xf);
4286 goto end;
4287 }
4288 }
4289 end:
4290 return has_audio;
4291 }
4292 EXPORT_SYMBOL(drm_detect_monitor_audio);
4293
4294
4295 /**
4296 * drm_default_rgb_quant_range - default RGB quantization range
4297 * @mode: display mode
4298 *
4299 * Determine the default RGB quantization range for the mode,
4300 * as specified in CEA-861.
4301 *
4302 * Return: The default RGB quantization range for the mode
4303 */
4304 enum hdmi_quantization_range
4305 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4306 {
4307 /* All CEA modes other than VIC 1 use limited quantization range. */
4308 return drm_match_cea_mode(mode) > 1 ?
4309 HDMI_QUANTIZATION_RANGE_LIMITED :
4310 HDMI_QUANTIZATION_RANGE_FULL;
4311 }
4312 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4313
4314 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4315 {
4316 struct drm_display_info *info = &connector->display_info;
4317
4318 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4319
4320 if (db[2] & EDID_CEA_VCDB_QS)
4321 info->rgb_quant_range_selectable = true;
4322 }
4323
4324 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4325 const u8 *db)
4326 {
4327 u8 dc_mask;
4328 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4329
4330 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4331 hdmi->y420_dc_modes = dc_mask;
4332 }
4333
4334 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4335 const u8 *hf_vsdb)
4336 {
4337 struct drm_display_info *display = &connector->display_info;
4338 struct drm_hdmi_info *hdmi = &display->hdmi;
4339
4340 display->has_hdmi_infoframe = true;
4341
4342 if (hf_vsdb[6] & 0x80) {
4343 hdmi->scdc.supported = true;
4344 if (hf_vsdb[6] & 0x40)
4345 hdmi->scdc.read_request = true;
4346 }
4347
4348 /*
4349 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4350 * And as per the spec, three factors confirm this:
4351 * * Availability of a HF-VSDB block in EDID (check)
4352 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4353 * * SCDC support available (let's check)
4354 * Lets check it out.
4355 */
4356
4357 if (hf_vsdb[5]) {
4358 /* max clock is 5000 KHz times block value */
4359 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4360 struct drm_scdc *scdc = &hdmi->scdc;
4361
4362 if (max_tmds_clock > 340000) {
4363 display->max_tmds_clock = max_tmds_clock;
4364 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4365 display->max_tmds_clock);
4366 }
4367
4368 if (scdc->supported) {
4369 scdc->scrambling.supported = true;
4370
4371 /* Few sinks support scrambling for cloks < 340M */
4372 if ((hf_vsdb[6] & 0x8))
4373 scdc->scrambling.low_rates = true;
4374 }
4375 }
4376
4377 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4378 }
4379
4380 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4381 const u8 *hdmi)
4382 {
4383 struct drm_display_info *info = &connector->display_info;
4384 unsigned int dc_bpc = 0;
4385
4386 /* HDMI supports at least 8 bpc */
4387 info->bpc = 8;
4388
4389 if (cea_db_payload_len(hdmi) < 6)
4390 return;
4391
4392 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4393 dc_bpc = 10;
4394 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4395 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4396 connector->name);
4397 }
4398
4399 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4400 dc_bpc = 12;
4401 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4402 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4403 connector->name);
4404 }
4405
4406 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4407 dc_bpc = 16;
4408 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4409 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4410 connector->name);
4411 }
4412
4413 if (dc_bpc == 0) {
4414 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4415 connector->name);
4416 return;
4417 }
4418
4419 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4420 connector->name, dc_bpc);
4421 info->bpc = dc_bpc;
4422
4423 /*
4424 * Deep color support mandates RGB444 support for all video
4425 * modes and forbids YCRCB422 support for all video modes per
4426 * HDMI 1.3 spec.
4427 */
4428 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4429
4430 /* YCRCB444 is optional according to spec. */
4431 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4432 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4433 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4434 connector->name);
4435 }
4436
4437 /*
4438 * Spec says that if any deep color mode is supported at all,
4439 * then deep color 36 bit must be supported.
4440 */
4441 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4442 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4443 connector->name);
4444 }
4445 }
4446
4447 static void
4448 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4449 {
4450 struct drm_display_info *info = &connector->display_info;
4451 u8 len = cea_db_payload_len(db);
4452
4453 if (len >= 6)
4454 info->dvi_dual = db[6] & 1;
4455 if (len >= 7)
4456 info->max_tmds_clock = db[7] * 5000;
4457
4458 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4459 "max TMDS clock %d kHz\n",
4460 info->dvi_dual,
4461 info->max_tmds_clock);
4462
4463 drm_parse_hdmi_deep_color_info(connector, db);
4464 }
4465
4466 static void drm_parse_cea_ext(struct drm_connector *connector,
4467 const struct edid *edid)
4468 {
4469 struct drm_display_info *info = &connector->display_info;
4470 const u8 *edid_ext;
4471 int i, start, end;
4472
4473 edid_ext = drm_find_cea_extension(edid);
4474 if (!edid_ext)
4475 return;
4476
4477 info->cea_rev = edid_ext[1];
4478
4479 /* The existence of a CEA block should imply RGB support */
4480 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4481 if (edid_ext[3] & EDID_CEA_YCRCB444)
4482 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4483 if (edid_ext[3] & EDID_CEA_YCRCB422)
4484 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4485
4486 if (cea_db_offsets(edid_ext, &start, &end))
4487 return;
4488
4489 for_each_cea_db(edid_ext, i, start, end) {
4490 const u8 *db = &edid_ext[i];
4491
4492 if (cea_db_is_hdmi_vsdb(db))
4493 drm_parse_hdmi_vsdb_video(connector, db);
4494 if (cea_db_is_hdmi_forum_vsdb(db))
4495 drm_parse_hdmi_forum_vsdb(connector, db);
4496 if (cea_db_is_y420cmdb(db))
4497 drm_parse_y420cmdb_bitmap(connector, db);
4498 if (cea_db_is_vcdb(db))
4499 drm_parse_vcdb(connector, db);
4500 }
4501 }
4502
4503 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4504 * all of the values which would have been set from EDID
4505 */
4506 void
4507 drm_reset_display_info(struct drm_connector *connector)
4508 {
4509 struct drm_display_info *info = &connector->display_info;
4510
4511 info->width_mm = 0;
4512 info->height_mm = 0;
4513
4514 info->bpc = 0;
4515 info->color_formats = 0;
4516 info->cea_rev = 0;
4517 info->max_tmds_clock = 0;
4518 info->dvi_dual = false;
4519 info->has_hdmi_infoframe = false;
4520 info->rgb_quant_range_selectable = false;
4521 memset(&info->hdmi, 0, sizeof(info->hdmi));
4522
4523 info->non_desktop = 0;
4524 }
4525
4526 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4527 {
4528 struct drm_display_info *info = &connector->display_info;
4529
4530 u32 quirks = edid_get_quirks(edid);
4531
4532 drm_reset_display_info(connector);
4533
4534 info->width_mm = edid->width_cm * 10;
4535 info->height_mm = edid->height_cm * 10;
4536
4537 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4538
4539 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4540
4541 if (edid->revision < 3)
4542 return quirks;
4543
4544 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4545 return quirks;
4546
4547 drm_parse_cea_ext(connector, edid);
4548
4549 /*
4550 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4551 *
4552 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4553 * tells us to assume 8 bpc color depth if the EDID doesn't have
4554 * extensions which tell otherwise.
4555 */
4556 if ((info->bpc == 0) && (edid->revision < 4) &&
4557 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4558 info->bpc = 8;
4559 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4560 connector->name, info->bpc);
4561 }
4562
4563 /* Only defined for 1.4 with digital displays */
4564 if (edid->revision < 4)
4565 return quirks;
4566
4567 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4568 case DRM_EDID_DIGITAL_DEPTH_6:
4569 info->bpc = 6;
4570 break;
4571 case DRM_EDID_DIGITAL_DEPTH_8:
4572 info->bpc = 8;
4573 break;
4574 case DRM_EDID_DIGITAL_DEPTH_10:
4575 info->bpc = 10;
4576 break;
4577 case DRM_EDID_DIGITAL_DEPTH_12:
4578 info->bpc = 12;
4579 break;
4580 case DRM_EDID_DIGITAL_DEPTH_14:
4581 info->bpc = 14;
4582 break;
4583 case DRM_EDID_DIGITAL_DEPTH_16:
4584 info->bpc = 16;
4585 break;
4586 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4587 default:
4588 info->bpc = 0;
4589 break;
4590 }
4591
4592 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4593 connector->name, info->bpc);
4594
4595 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4596 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4597 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4598 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4599 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4600 return quirks;
4601 }
4602
4603 static int validate_displayid(u8 *displayid, int length, int idx)
4604 {
4605 int i;
4606 u8 csum = 0;
4607 struct displayid_hdr *base;
4608
4609 base = (struct displayid_hdr *)&displayid[idx];
4610
4611 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4612 base->rev, base->bytes, base->prod_id, base->ext_count);
4613
4614 if (base->bytes + 5 > length - idx)
4615 return -EINVAL;
4616 for (i = idx; i <= base->bytes + 5; i++) {
4617 csum += displayid[i];
4618 }
4619 if (csum) {
4620 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4621 return -EINVAL;
4622 }
4623 return 0;
4624 }
4625
4626 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4627 struct displayid_detailed_timings_1 *timings)
4628 {
4629 struct drm_display_mode *mode;
4630 unsigned pixel_clock = (timings->pixel_clock[0] |
4631 (timings->pixel_clock[1] << 8) |
4632 (timings->pixel_clock[2] << 16));
4633 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4634 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4635 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4636 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4637 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4638 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4639 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4640 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4641 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4642 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4643 mode = drm_mode_create(dev);
4644 if (!mode)
4645 return NULL;
4646
4647 mode->clock = pixel_clock * 10;
4648 mode->hdisplay = hactive;
4649 mode->hsync_start = mode->hdisplay + hsync;
4650 mode->hsync_end = mode->hsync_start + hsync_width;
4651 mode->htotal = mode->hdisplay + hblank;
4652
4653 mode->vdisplay = vactive;
4654 mode->vsync_start = mode->vdisplay + vsync;
4655 mode->vsync_end = mode->vsync_start + vsync_width;
4656 mode->vtotal = mode->vdisplay + vblank;
4657
4658 mode->flags = 0;
4659 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4660 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4661 mode->type = DRM_MODE_TYPE_DRIVER;
4662
4663 if (timings->flags & 0x80)
4664 mode->type |= DRM_MODE_TYPE_PREFERRED;
4665 mode->vrefresh = drm_mode_vrefresh(mode);
4666 drm_mode_set_name(mode);
4667
4668 return mode;
4669 }
4670
4671 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4672 struct displayid_block *block)
4673 {
4674 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4675 int i;
4676 int num_timings;
4677 struct drm_display_mode *newmode;
4678 int num_modes = 0;
4679 /* blocks must be multiple of 20 bytes length */
4680 if (block->num_bytes % 20)
4681 return 0;
4682
4683 num_timings = block->num_bytes / 20;
4684 for (i = 0; i < num_timings; i++) {
4685 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4686
4687 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4688 if (!newmode)
4689 continue;
4690
4691 drm_mode_probed_add(connector, newmode);
4692 num_modes++;
4693 }
4694 return num_modes;
4695 }
4696
4697 static int add_displayid_detailed_modes(struct drm_connector *connector,
4698 struct edid *edid)
4699 {
4700 u8 *displayid;
4701 int ret;
4702 int idx = 1;
4703 int length = EDID_LENGTH;
4704 struct displayid_block *block;
4705 int num_modes = 0;
4706
4707 displayid = drm_find_displayid_extension(edid);
4708 if (!displayid)
4709 return 0;
4710
4711 ret = validate_displayid(displayid, length, idx);
4712 if (ret)
4713 return 0;
4714
4715 idx += sizeof(struct displayid_hdr);
4716 while (block = (struct displayid_block *)&displayid[idx],
4717 idx + sizeof(struct displayid_block) <= length &&
4718 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4719 block->num_bytes > 0) {
4720 idx += block->num_bytes + sizeof(struct displayid_block);
4721 switch (block->tag) {
4722 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4723 num_modes += add_displayid_detailed_1_modes(connector, block);
4724 break;
4725 }
4726 }
4727 return num_modes;
4728 }
4729
4730 /**
4731 * drm_add_edid_modes - add modes from EDID data, if available
4732 * @connector: connector we're probing
4733 * @edid: EDID data
4734 *
4735 * Add the specified modes to the connector's mode list. Also fills out the
4736 * &drm_display_info structure and ELD in @connector with any information which
4737 * can be derived from the edid.
4738 *
4739 * Return: The number of modes added or 0 if we couldn't find any.
4740 */
4741 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4742 {
4743 int num_modes = 0;
4744 u32 quirks;
4745
4746 if (edid == NULL) {
4747 clear_eld(connector);
4748 return 0;
4749 }
4750 if (!drm_edid_is_valid(edid)) {
4751 clear_eld(connector);
4752 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4753 connector->name);
4754 return 0;
4755 }
4756
4757 drm_edid_to_eld(connector, edid);
4758
4759 /*
4760 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4761 * To avoid multiple parsing of same block, lets parse that map
4762 * from sink info, before parsing CEA modes.
4763 */
4764 quirks = drm_add_display_info(connector, edid);
4765
4766 /*
4767 * EDID spec says modes should be preferred in this order:
4768 * - preferred detailed mode
4769 * - other detailed modes from base block
4770 * - detailed modes from extension blocks
4771 * - CVT 3-byte code modes
4772 * - standard timing codes
4773 * - established timing codes
4774 * - modes inferred from GTF or CVT range information
4775 *
4776 * We get this pretty much right.
4777 *
4778 * XXX order for additional mode types in extension blocks?
4779 */
4780 num_modes += add_detailed_modes(connector, edid, quirks);
4781 num_modes += add_cvt_modes(connector, edid);
4782 num_modes += add_standard_modes(connector, edid);
4783 num_modes += add_established_modes(connector, edid);
4784 num_modes += add_cea_modes(connector, edid);
4785 num_modes += add_alternate_cea_modes(connector, edid);
4786 num_modes += add_displayid_detailed_modes(connector, edid);
4787 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4788 num_modes += add_inferred_modes(connector, edid);
4789
4790 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4791 edid_fixup_preferred(connector, quirks);
4792
4793 if (quirks & EDID_QUIRK_FORCE_6BPC)
4794 connector->display_info.bpc = 6;
4795
4796 if (quirks & EDID_QUIRK_FORCE_8BPC)
4797 connector->display_info.bpc = 8;
4798
4799 if (quirks & EDID_QUIRK_FORCE_10BPC)
4800 connector->display_info.bpc = 10;
4801
4802 if (quirks & EDID_QUIRK_FORCE_12BPC)
4803 connector->display_info.bpc = 12;
4804
4805 return num_modes;
4806 }
4807 EXPORT_SYMBOL(drm_add_edid_modes);
4808
4809 /**
4810 * drm_add_modes_noedid - add modes for the connectors without EDID
4811 * @connector: connector we're probing
4812 * @hdisplay: the horizontal display limit
4813 * @vdisplay: the vertical display limit
4814 *
4815 * Add the specified modes to the connector's mode list. Only when the
4816 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4817 *
4818 * Return: The number of modes added or 0 if we couldn't find any.
4819 */
4820 int drm_add_modes_noedid(struct drm_connector *connector,
4821 int hdisplay, int vdisplay)
4822 {
4823 int i, count, num_modes = 0;
4824 struct drm_display_mode *mode;
4825 struct drm_device *dev = connector->dev;
4826
4827 count = ARRAY_SIZE(drm_dmt_modes);
4828 if (hdisplay < 0)
4829 hdisplay = 0;
4830 if (vdisplay < 0)
4831 vdisplay = 0;
4832
4833 for (i = 0; i < count; i++) {
4834 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4835 if (hdisplay && vdisplay) {
4836 /*
4837 * Only when two are valid, they will be used to check
4838 * whether the mode should be added to the mode list of
4839 * the connector.
4840 */
4841 if (ptr->hdisplay > hdisplay ||
4842 ptr->vdisplay > vdisplay)
4843 continue;
4844 }
4845 if (drm_mode_vrefresh(ptr) > 61)
4846 continue;
4847 mode = drm_mode_duplicate(dev, ptr);
4848 if (mode) {
4849 drm_mode_probed_add(connector, mode);
4850 num_modes++;
4851 }
4852 }
4853 return num_modes;
4854 }
4855 EXPORT_SYMBOL(drm_add_modes_noedid);
4856
4857 /**
4858 * drm_set_preferred_mode - Sets the preferred mode of a connector
4859 * @connector: connector whose mode list should be processed
4860 * @hpref: horizontal resolution of preferred mode
4861 * @vpref: vertical resolution of preferred mode
4862 *
4863 * Marks a mode as preferred if it matches the resolution specified by @hpref
4864 * and @vpref.
4865 */
4866 void drm_set_preferred_mode(struct drm_connector *connector,
4867 int hpref, int vpref)
4868 {
4869 struct drm_display_mode *mode;
4870
4871 list_for_each_entry(mode, &connector->probed_modes, head) {
4872 if (mode->hdisplay == hpref &&
4873 mode->vdisplay == vpref)
4874 mode->type |= DRM_MODE_TYPE_PREFERRED;
4875 }
4876 }
4877 EXPORT_SYMBOL(drm_set_preferred_mode);
4878
4879 static bool is_hdmi2_sink(struct drm_connector *connector)
4880 {
4881 /*
4882 * FIXME: sil-sii8620 doesn't have a connector around when
4883 * we need one, so we have to be prepared for a NULL connector.
4884 */
4885 if (!connector)
4886 return true;
4887
4888 return connector->display_info.hdmi.scdc.supported ||
4889 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
4890 }
4891
4892 /**
4893 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4894 * data from a DRM display mode
4895 * @frame: HDMI AVI infoframe
4896 * @connector: the connector
4897 * @mode: DRM display mode
4898 *
4899 * Return: 0 on success or a negative error code on failure.
4900 */
4901 int
4902 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4903 struct drm_connector *connector,
4904 const struct drm_display_mode *mode)
4905 {
4906 enum hdmi_picture_aspect picture_aspect;
4907 int err;
4908
4909 if (!frame || !mode)
4910 return -EINVAL;
4911
4912 err = hdmi_avi_infoframe_init(frame);
4913 if (err < 0)
4914 return err;
4915
4916 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4917 frame->pixel_repeat = 1;
4918
4919 frame->video_code = drm_match_cea_mode(mode);
4920
4921 /*
4922 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4923 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4924 * have to make sure we dont break HDMI 1.4 sinks.
4925 */
4926 if (!is_hdmi2_sink(connector) && frame->video_code > 64)
4927 frame->video_code = 0;
4928
4929 /*
4930 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4931 * we should send its VIC in vendor infoframes, else send the
4932 * VIC in AVI infoframes. Lets check if this mode is present in
4933 * HDMI 1.4b 4K modes
4934 */
4935 if (frame->video_code) {
4936 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4937 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4938
4939 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4940 frame->video_code = 0;
4941 }
4942
4943 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4944
4945 /*
4946 * As some drivers don't support atomic, we can't use connector state.
4947 * So just initialize the frame with default values, just the same way
4948 * as it's done with other properties here.
4949 */
4950 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
4951 frame->itc = 0;
4952
4953 /*
4954 * Populate picture aspect ratio from either
4955 * user input (if specified) or from the CEA mode list.
4956 */
4957 picture_aspect = mode->picture_aspect_ratio;
4958 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
4959 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
4960
4961 /*
4962 * The infoframe can't convey anything but none, 4:3
4963 * and 16:9, so if the user has asked for anything else
4964 * we can only satisfy it by specifying the right VIC.
4965 */
4966 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
4967 if (picture_aspect !=
4968 drm_get_cea_aspect_ratio(frame->video_code))
4969 return -EINVAL;
4970 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4971 }
4972
4973 frame->picture_aspect = picture_aspect;
4974 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4975 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4976
4977 return 0;
4978 }
4979 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4980
4981 /* HDMI Colorspace Spec Definitions */
4982 #define FULL_COLORIMETRY_MASK 0x1FF
4983 #define NORMAL_COLORIMETRY_MASK 0x3
4984 #define EXTENDED_COLORIMETRY_MASK 0x7
4985 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
4986
4987 #define C(x) ((x) << 0)
4988 #define EC(x) ((x) << 2)
4989 #define ACE(x) ((x) << 5)
4990
4991 #define HDMI_COLORIMETRY_NO_DATA 0x0
4992 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
4993 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
4994 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
4995 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
4996 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
4997 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
4998 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
4999 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5000 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5001 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5002 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5003 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5004
5005 static const u32 hdmi_colorimetry_val[] = {
5006 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5007 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5008 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5009 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5010 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5011 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5012 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5013 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5014 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5015 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5016 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5017 };
5018
5019 #undef C
5020 #undef EC
5021 #undef ACE
5022
5023 /**
5024 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5025 * colorspace information
5026 * @frame: HDMI AVI infoframe
5027 * @conn_state: connector state
5028 */
5029 void
5030 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5031 const struct drm_connector_state *conn_state)
5032 {
5033 u32 colorimetry_val;
5034 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5035
5036 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5037 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5038 else
5039 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5040
5041 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5042 /*
5043 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5044 * structure and extend it in drivers/video/hdmi
5045 */
5046 frame->extended_colorimetry = (colorimetry_val >> 2) &
5047 EXTENDED_COLORIMETRY_MASK;
5048 }
5049 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5050
5051 /**
5052 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5053 * quantization range information
5054 * @frame: HDMI AVI infoframe
5055 * @connector: the connector
5056 * @mode: DRM display mode
5057 * @rgb_quant_range: RGB quantization range (Q)
5058 */
5059 void
5060 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5061 struct drm_connector *connector,
5062 const struct drm_display_mode *mode,
5063 enum hdmi_quantization_range rgb_quant_range)
5064 {
5065 const struct drm_display_info *info = &connector->display_info;
5066
5067 /*
5068 * CEA-861:
5069 * "A Source shall not send a non-zero Q value that does not correspond
5070 * to the default RGB Quantization Range for the transmitted Picture
5071 * unless the Sink indicates support for the Q bit in a Video
5072 * Capabilities Data Block."
5073 *
5074 * HDMI 2.0 recommends sending non-zero Q when it does match the
5075 * default RGB quantization range for the mode, even when QS=0.
5076 */
5077 if (info->rgb_quant_range_selectable ||
5078 rgb_quant_range == drm_default_rgb_quant_range(mode))
5079 frame->quantization_range = rgb_quant_range;
5080 else
5081 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5082
5083 /*
5084 * CEA-861-F:
5085 * "When transmitting any RGB colorimetry, the Source should set the
5086 * YQ-field to match the RGB Quantization Range being transmitted
5087 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5088 * set YQ=1) and the Sink shall ignore the YQ-field."
5089 *
5090 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5091 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5092 * good way to tell which version of CEA-861 the sink supports, so
5093 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5094 * on on CEA-861-F.
5095 */
5096 if (!is_hdmi2_sink(connector) ||
5097 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5098 frame->ycc_quantization_range =
5099 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5100 else
5101 frame->ycc_quantization_range =
5102 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5103 }
5104 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5105
5106 static enum hdmi_3d_structure
5107 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5108 {
5109 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5110
5111 switch (layout) {
5112 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5113 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5114 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5115 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5116 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5117 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5118 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5119 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5120 case DRM_MODE_FLAG_3D_L_DEPTH:
5121 return HDMI_3D_STRUCTURE_L_DEPTH;
5122 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5123 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5124 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5125 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5126 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5127 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5128 default:
5129 return HDMI_3D_STRUCTURE_INVALID;
5130 }
5131 }
5132
5133 /**
5134 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5135 * data from a DRM display mode
5136 * @frame: HDMI vendor infoframe
5137 * @connector: the connector
5138 * @mode: DRM display mode
5139 *
5140 * Note that there's is a need to send HDMI vendor infoframes only when using a
5141 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5142 * function will return -EINVAL, error that can be safely ignored.
5143 *
5144 * Return: 0 on success or a negative error code on failure.
5145 */
5146 int
5147 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5148 struct drm_connector *connector,
5149 const struct drm_display_mode *mode)
5150 {
5151 /*
5152 * FIXME: sil-sii8620 doesn't have a connector around when
5153 * we need one, so we have to be prepared for a NULL connector.
5154 */
5155 bool has_hdmi_infoframe = connector ?
5156 connector->display_info.has_hdmi_infoframe : false;
5157 int err;
5158 u32 s3d_flags;
5159 u8 vic;
5160
5161 if (!frame || !mode)
5162 return -EINVAL;
5163
5164 if (!has_hdmi_infoframe)
5165 return -EINVAL;
5166
5167 vic = drm_match_hdmi_mode(mode);
5168 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5169
5170 /*
5171 * Even if it's not absolutely necessary to send the infoframe
5172 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5173 * know that the sink can handle it. This is based on a
5174 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5175 * have trouble realizing that they shuld switch from 3D to 2D
5176 * mode if the source simply stops sending the infoframe when
5177 * it wants to switch from 3D to 2D.
5178 */
5179
5180 if (vic && s3d_flags)
5181 return -EINVAL;
5182
5183 err = hdmi_vendor_infoframe_init(frame);
5184 if (err < 0)
5185 return err;
5186
5187 frame->vic = vic;
5188 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5189
5190 return 0;
5191 }
5192 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5193
5194 static int drm_parse_tiled_block(struct drm_connector *connector,
5195 struct displayid_block *block)
5196 {
5197 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5198 u16 w, h;
5199 u8 tile_v_loc, tile_h_loc;
5200 u8 num_v_tile, num_h_tile;
5201 struct drm_tile_group *tg;
5202
5203 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5204 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5205
5206 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5207 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5208 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5209 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5210
5211 connector->has_tile = true;
5212 if (tile->tile_cap & 0x80)
5213 connector->tile_is_single_monitor = true;
5214
5215 connector->num_h_tile = num_h_tile + 1;
5216 connector->num_v_tile = num_v_tile + 1;
5217 connector->tile_h_loc = tile_h_loc;
5218 connector->tile_v_loc = tile_v_loc;
5219 connector->tile_h_size = w + 1;
5220 connector->tile_v_size = h + 1;
5221
5222 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5223 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5224 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5225 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5226 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5227
5228 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5229 if (!tg) {
5230 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5231 }
5232 if (!tg)
5233 return -ENOMEM;
5234
5235 if (connector->tile_group != tg) {
5236 /* if we haven't got a pointer,
5237 take the reference, drop ref to old tile group */
5238 if (connector->tile_group) {
5239 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5240 }
5241 connector->tile_group = tg;
5242 } else
5243 /* if same tile group, then release the ref we just took. */
5244 drm_mode_put_tile_group(connector->dev, tg);
5245 return 0;
5246 }
5247
5248 static int drm_parse_display_id(struct drm_connector *connector,
5249 u8 *displayid, int length,
5250 bool is_edid_extension)
5251 {
5252 /* if this is an EDID extension the first byte will be 0x70 */
5253 int idx = 0;
5254 struct displayid_block *block;
5255 int ret;
5256
5257 if (is_edid_extension)
5258 idx = 1;
5259
5260 ret = validate_displayid(displayid, length, idx);
5261 if (ret)
5262 return ret;
5263
5264 idx += sizeof(struct displayid_hdr);
5265 while (block = (struct displayid_block *)&displayid[idx],
5266 idx + sizeof(struct displayid_block) <= length &&
5267 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5268 block->num_bytes > 0) {
5269 idx += block->num_bytes + sizeof(struct displayid_block);
5270 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5271 block->tag, block->rev, block->num_bytes);
5272
5273 switch (block->tag) {
5274 case DATA_BLOCK_TILED_DISPLAY:
5275 ret = drm_parse_tiled_block(connector, block);
5276 if (ret)
5277 return ret;
5278 break;
5279 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5280 /* handled in mode gathering code. */
5281 break;
5282 default:
5283 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5284 break;
5285 }
5286 }
5287 return 0;
5288 }
5289
5290 static void drm_get_displayid(struct drm_connector *connector,
5291 struct edid *edid)
5292 {
5293 void *displayid = NULL;
5294 int ret;
5295 connector->has_tile = false;
5296 displayid = drm_find_displayid_extension(edid);
5297 if (!displayid) {
5298 /* drop reference to any tile group we had */
5299 goto out_drop_ref;
5300 }
5301
5302 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5303 if (ret < 0)
5304 goto out_drop_ref;
5305 if (!connector->has_tile)
5306 goto out_drop_ref;
5307 return;
5308 out_drop_ref:
5309 if (connector->tile_group) {
5310 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5311 connector->tile_group = NULL;
5312 }
5313 return;
5314 }
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